Flash memory test method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a flash memory testing method and device, electronic equipment and a storage medium, and relates to the technical field of flash memory testing. Dividing test data into a plurality of to-be-tested data blocks, sequentially writing the to-be-tested data blocks into the erased to-be-tested flash memory, circularly activating word lines of the to-be-tested flash memory according to preset word line activation time, reading one to-be-tested data block of the to-be-tested flash memory after the word lines are activated each time, and performing data verification on the read to-be-tested data block, and determining whether the to-be-tested flash memory is abnormal or not. The word lines of the flash memory to be tested are activated in a blocking manner, and the blocking data are verified, so that abnormal chips caused by insufficient WL setup time can be successfully screened out.

Description

Technical Field

[0001] The present invention relates to the field of flash memory testing technology, and in particular to a flash memory testing method, device, electronic equipment and storage medium. Background Art

[0002] As a non-volatile storage medium, flash memory has been widely used in embedded systems, mobile devices, and storage solutions. However, the stability of flash memory at high read speeds has always been a technical bottleneck. In particular, when the wordline activation (WL Setup) time is insufficient, the read operation will be unstable, resulting in single-bit errors. Single-bit errors not only affect data integrity, but may also cause system malfunctions and reduce user experience. WL Setup time refers to the time that the wordline needs to be activated before a read or programming operation.

[0003] Currently, the screening test for flash memory mainly focuses on functional testing and basic performance testing under static conditions, and tests the flash memory chip by activating all word lines once. These test methods usually cannot accurately identify the problem of insufficient WL Setup time, resulting in the inability to screen abnormal chips caused by insufficient WL setup time. Summary of the invention

[0004] In view of this, an object of the embodiments of the present invention is to provide a flash memory testing method, device, electronic device and storage medium to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a flash memory testing method, the method comprising:

[0007] Dividing the test data into a plurality of data blocks to be tested, and sequentially writing each of the data blocks to be tested into the erased flash memory to be tested;

[0008] The word lines of the flash memory to be tested are activated cyclically according to the preset word line activation time, and a data block to be tested of the flash memory to be tested is read after each word line activation, and data verification is performed on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

[0009] Optionally, dividing the test data into a plurality of to-be-tested data blocks, and sequentially writing each of the to-be-tested data blocks into the erased to-be-tested flash memory includes:

[0010] Divide the test data into a plurality of test data blocks of preset sizes;

[0011] Generating a check code corresponding to each of the data blocks to be tested according to each of the data blocks to be tested;

[0012] Each of the to-be-tested data blocks and the corresponding verification code are written into the erased to-be-tested flash memory.

[0013] Optionally, the loop activates the word line of the flash memory to be tested according to a preset word line activation time, reads one of the data blocks to be tested of the flash memory to be tested after each word line activation, and performs data verification on the read data block to be tested to confirm whether the flash memory to be tested is abnormal, including:

[0014] Obtaining a storage address of the to-be-tested data block to be read;

[0015] activating the word line corresponding to the storage address according to a preset word line activation time;

[0016] According to the storage address, reading out the data to be verified of the data block to be tested;

[0017] Verifying whether the data to be verified is normal;

[0018] If not, exit the test and determine that the flash memory to be tested is abnormal;

[0019] If so, the step of obtaining a storage address of the to-be-tested data block to be read is performed again until each of the to-be-tested data blocks is verified to be normal or the to-be-tested data is abnormal.

[0020] Optionally, the verifying whether the data to be verified is normal includes:

[0021] Separating the data to be verified to obtain valid data and a first verification code;

[0022] Performing binary division on the valid data and a preset generator polynomial to obtain a second check code;

[0023] Determining whether the second verification code matches the first verification code;

[0024] If yes, the data to be verified is normal;

[0025] If so, the data to be verified is abnormal.

[0026] Optionally, before the step of exiting detection and determining that the flash memory to be tested is abnormal, the step further includes:

[0027] A target spare block is selected from the spare area of ​​the flash memory to be tested, and the bad block of the storage address is replaced.

[0028] Optionally, after the step of verifying that each of the to-be-tested data blocks is normal, the method further includes:

[0029] If the flash memory to be tested is tested normally, the cycle is repeated for a preset number of times to activate the word line of the flash memory to be tested according to the preset word line activation time, and after each word line activation, one of the data blocks to be tested of the flash memory to be tested is read, and data verification is performed on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

[0030] Optionally, before the step of dividing the test data into a plurality of to-be-tested data blocks and sequentially writing the to-be-tested data blocks into the erased to-be-tested flash memory, the step further includes:

[0031] Erasing the entire flash memory to be tested;

[0032] Performing full-chip reading on the flash memory to be tested to obtain results of all storage units of the flash memory to be tested;

[0033] Determine whether any of the results described are not in line with expectations;

[0034] If so, re-erasing the storage cells corresponding to the results that do not meet the expectations;

[0035] If not, the erase is complete.

[0036] In a second aspect, an embodiment of the present invention provides a flash memory testing device, the device comprising:

[0037] A data writing unit, used for dividing the test data into a plurality of data blocks to be tested, and sequentially writing each of the data blocks to be tested into the erased flash memory to be tested;

[0038] A data verification unit is used to cyclically activate the word lines of the flash memory to be tested according to a preset word line activation time, read a data block to be tested of the flash memory to be tested after each word line activation, and perform data verification on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

[0039] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements any of the above-described methods when executing the program.

[0040] In a fourth aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0041] The embodiments of the present invention provide a flash memory testing method, device, electronic device and storage medium. Abnormal chips caused by insufficient WLSetup time can be successfully screened out through block reading verification, thereby ensuring the stability and accuracy of high-speed reading operations. The screening intensity is increased through additional cycles while controlling the test cost. This not only improves the strictness of the test, but also ensures that more potential unstable factors are screened out without increasing excessive costs, thereby ensuring the quality of the final product.

[0042] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic structural block diagram of an electronic device provided by an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of a flash memory testing method provided by an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of a process of step S210 provided in an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of a process flow of step S220 provided in an embodiment of the present invention;

[0048] Figure 5 Another schematic diagram of a flash memory testing method provided by an embodiment of the present invention;

[0049] Figure 6 A schematic structural block diagram of a flash memory testing device provided by an embodiment of the present invention.

[0050] Icons: 100 - electronic device; 101 - memory; 102 - communication interface; 103 - processor; 104 - bus; 300 - flash memory testing device; 310 - data writing unit; 320 - data verification unit. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0054] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0055] As mentioned in the background technology, the stability of flash memory at high read speeds has always been a technical bottleneck. In particular, when the WL Setup time is insufficient, the read operation will be unstable, resulting in single-bit errors. Single-bit errors not only affect data integrity, but may also cause system malfunctions and reduce user experience.

[0056] The wordline activation time refers to the time that the wordline needs to be activated before performing a read or program operation. This parameter directly affects the operating efficiency and stability of the flash memory. If the WL Setup time is not set properly, when the WL Setup time is insufficient, the wordline may not be fully activated, resulting in reduced reliability of the read operation.

[0057] Currently, the screening tests for flash memory mainly focus on functional tests and basic performance tests under static conditions. These test methods usually evaluate the overall performance of flash memory chips by activating all word lines. However, traditional test methods mainly focus on the overall performance indicators of flash memory chips, such as the number of erase times, read and write speeds, etc., while ignoring the key parameter of WLSetup time. This results in many problem chips not being discovered in time due to insufficient WLSetup time.

[0058] Based on the above situation, an embodiment of the present invention provides a flash memory testing method, device, electronic device and storage medium. Through the block reading verification method, the word line of each data block is activated separately and then the data is read to verify the accuracy of the data, so that abnormal chips caused by insufficient WL Setup time can be successfully screened out, thereby ensuring the stability and accuracy of high-speed reading operations.

[0059] To implement the process steps and functions of each example of the present invention, please refer to Figure 1 , Figure 1 A schematic structural block diagram of an electronic device provided by an embodiment of the present invention. The electronic device 100 includes a memory 101 and a processor 103, and the memory 101 and the processor 103 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses 104 or signal lines. The memory 101 can be used to store software programs and modules, and the processor 103 executes the software programs and modules stored in the memory 101 to perform various functional applications and data processing.

[0060] The electronic device 100 may be, but is not limited to, a personal computer (PC), a server, a distributed computer, etc. It is understandable that the electronic device 100 is not limited to a physical server, but may also be a virtual machine on a physical server, a virtual machine built on a cloud platform, etc., which can provide the same functions as the server or virtual machine. The operating system of the electronic device 100 may be, but is not limited to, a Windows system, a Linux system, etc.

[0061] Among them, the memory 101 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc.

[0062] The communication connection between the electronic device 100 and an external device is achieved through at least one communication interface 102 (which can be wired or wireless).

[0063] The processor 103 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the embodiment of the present invention can be completed by the hardware integrated logic circuit in the processor 103 or the instructions in the form of software. The processor 103 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0064] Understandably, Figure 1 The structure shown is for illustration only. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0065] The following is an exemplary description of the flash memory testing method provided by the present invention. Figure 2 , Figure 2 A schematic diagram of a flash memory testing method provided by an embodiment of the present invention, the method execution body can be the above Figure 1 The electronic device 100 shown in FIG. 1 includes: Figure 2 The following steps are described:

[0066] S210: Divide the test data into a plurality of data blocks to be tested, and write each data block to be tested into the erased flash memory to be tested in sequence.

[0067] The erasing-completed flash memory to be tested indicates that the state of the storage unit of the flash memory to be tested has been reset to a certain default value, and new data can be written.

[0068] The test data can be text data, such as plain text files, CSV files, XML files, JSON files, etc., binary data, such as JPEG pictures, MP3 audio files, MP4 video files, RAW data, etc.

[0069] The test data is divided into a plurality of data blocks to be tested, which may be divided according to a preset size, for example, 4 bytes may be one data block to be tested, and each divided data block to be tested is written into the flash memory to be tested.

[0070] S220: cyclically activating the word lines of the flash memory to be tested according to the preset word line activation time, reading a data block to be tested of the flash memory to be tested after each word line activation, and performing data verification on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

[0071] Each time before reading a data block to be tested, the word line of the flash memory to be tested is activated once, the data block to be tested is read and verified, and when the next data block to be tested is read and verified, the word line of the flash memory to be tested is activated again. For example, a data block to be tested is 4 bytes, which means that each time the verification of 4 bytes of data is completed, a new address needs to be sent to perform a new WL setup in order to know the position of the next byte and read 4 bytes of data again for verification. If the 4-byte data verification fails, the flash memory to be tested is abnormal.

[0072] This method reads and verifies the test data in blocks, which is equivalent to testing the WL setup time for each test data block, and can successfully screen out abnormal chips caused by insufficient WL setup time.

[0073] In a possible implementation, in order to quickly verify the test data block, refer to Figure 3 , the above step S210 may include the following steps:

[0074] S211: Divide the test data into a plurality of to-be-tested data blocks of preset sizes.

[0075] The preset size can be 2 bytes, 4 bytes, 8 bytes, etc. This embodiment adopts 4-byte block division and testing, that is, the original test data is divided into multiple 4-byte test data blocks, and each test data block will be written, read and verified separately.

[0076] S212: Generate a check code corresponding to each data block to be tested according to each data block to be tested.

[0077] A check code is a code used to verify data integrity. There are many ways to generate a check code. For each data to be tested, a check code is generated.

[0078] S213: writing each to-be-tested data block and its corresponding check code into the erased to-be-tested flash memory.

[0079] There are many ways to write each test data block and its corresponding verification code into the test flash memory. After establishing a mapping relationship between the test data block and the verification code, they can be stored in the flash memory at different locations respectively, or the test data block and the verification code can be spliced ​​and then stored in the test flash memory.

[0080] For the sake of convenience, it is assumed that the original test data is 16 bytes and the preset data block size is 4 bytes. Four data blocks are divided. If the check code of each data block is 0xAABBCCDD, 0x11223344, 0x55667788, and 0x99AABBCC, the data block to be tested and the verification code are spliced ​​and stored in the flash memory to be tested. When writing to the flash memory to be tested, the data block occupies 4 bytes and the mask occupies 4 bytes. The specific location of writing is: writing data block 1 and its check code: address `0x0000` to `0x0003`: writing the content of data block 1; address `0x0004` to `0x0007`: writing the check code `0xAABBCCDD` of data block 1. Write data block 2 and its checksum: Address `0x0008` to `0x000B`: Write the content of data block 2; Address `0x000C` to `0x000F`: Write the checksum of data block 2 `0x11223344`; Write data block 3 and its checksum: `0x0010` to `0x0013`: Write the content of data block 3; `0x0014` to `0x0017`: Write the checksum of data block 3 `0x55667788`. Data block 4 and its checksum: `0x0018` to `0x001B`: Write the content of data block 4; `0x001C` to `0x001F`: Write the checksum of data block 4 `0x99AABBCC`.

[0081] In a possible implementation, the data block to be tested and the verification code are concatenated and stored in the flash memory to be tested for verification. Figure 4 , the above step S220 may include the following steps:

[0082] S221: Obtain a storage address of a test data block to be read.

[0083] Determine the specific location of the test data block to be read in the flash memory. The initial address of the first test data block may be `0x0000`.

[0084] S222: Activate the word line corresponding to the storage address according to the preset word line activation time.

[0085] In the flash memory, the word line is activated, and data is read after a preset word line activation time. According to the preset word line activation time (eg, 10 nanoseconds), the word line corresponding to the storage address is activated.

[0086] S223: Read out the data to be verified of the data block to be tested according to the storage address.

[0087] According to the storage address, the data to be verified is read, and the data to be verified includes the original test data and the verification code.

[0088] S224: Check whether the data to be checked is normal. If not, execute step S226; if so, execute step S221.

[0089] S226: Exit the test and determine that the flash memory to be tested is abnormal.

[0090] As in the above example, an initial address, such as `0x0000`, is sent to the flash memory. It is necessary to read data blocks `0x0000` to `0x0007`, which include test data and verification codes. The word line at that position is activated, and then the address is read to obtain the data to be verified. The data to be verified is verified. If the data verification passes, step S221 is re-executed, such as updating the address to `0x0008`. If the data verification fails, the test is exited to determine that there is an abnormality in the flash memory to be tested.

[0091] There are many ways to verify whether the data to be verified is normal. Optionally, the above step S224 may include the following steps:

[0092] S2241: Separate the data to be verified to obtain valid data and a first verification code.

[0093] S2242: Perform binary division on the valid data and a preset generator polynomial to obtain a second check code.

[0094] S2243: Determine whether the second verification code matches the first verification code.

[0095] S2244: If yes, the data to be verified is normal.

[0096] S2245: If yes, the data to be verified is abnormal.

[0097] Assume that the data block read is 8 bytes, of which the first 4 bytes are valid data and the last 4 bytes are the first check code. For example, the data block read is `0x123456789ABCDEF0`, of which `0x12345678` is valid data and `0x9ABCDEF0` is the first check code.

[0098] For example, if the preset generator polynomial is `0x1EDC6F41`, perform binary division on the valid data `0x12345678` and the generator polynomial `0x1EDC6F41` to obtain the second check code. Compare the generated second check code with the read first check code. If the two are the same, the data check passes; otherwise, the data check fails.

[0099] Similarly, the same verification code generation method is adopted when writing data, and the same generating polynomial is used.

[0100] In order to enable the abnormal flash memory to be tested to work normally, after step S224 and before step S226, that is, when the data to be verified is abnormal, the storage unit corresponding to the data to be verified may be processed, which may include the following steps:

[0101] S225: Select a target spare block from the spare area of ​​the flash memory to be tested, and replace the bad block of the storage address.

[0102] When the data verification of a database to be tested fails, the test does not exit directly, but a target spare block is selected from the spare area of ​​the flash memory for replacement. The spare area is usually a set of reserved storage units for replacing bad blocks. Read a data block from the flash memory to be tested, such as the address `0x0000` to `0x0003`, verify the data, and if the verification passes, continue to detect the next data block. If the verification fails, select a target spare block from the spare area of ​​the flash memory. The spare area usually has a set of reserved storage units, such as `0x1000` to `0x10FF`. Assuming that the selected target spare block address is `0x1000` to `0x1003`, use the storage units of `0x1000` to `0x1003` to replace the storage units of `0x0000` to `0x0003`.

[0103] In order to increase the screening efforts on the basis of testing cost control, the method may optionally further include:

[0104] S230: If the flash memory to be tested is normal, repeat a preset number of cycles to activate the word lines of the flash memory to be tested according to the preset word line activation time, read a data block to be tested of the flash memory to be tested after each word line activation, and perform data verification on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

[0105] If all the databases to be tested pass verification in the first test, retesting can improve the test coverage and double the WL setup time. On the basis of test cost control, the screening efforts can be increased to more accurately screen out abnormal flash memories.

[0106] In order to make the test more accurate, the flash memory to be tested needs to be erased before writing data. In a possible implementation, before step S210, the method may further include:

[0107] S201: Erase the entire flash memory to be tested.

[0108] Execute the chip erase command to restore all the memory cells of the flash memory to the erased state. Usually, the erase operation will change the value of the memory cell to all 1 (high state).

[0109] S202: Perform full-chip reading on the flash memory to be tested to obtain results of all storage units of the flash memory to be tested.

[0110] Execute the full chip read command to read the data of each storage unit in the flash memory. Record the read result of each storage unit.

[0111] S203: Determine whether any result does not meet expectations. If so, execute step S204; if not, the erasure is completed.

[0112] If the reading results of all storage cells are in line with expectations, erasing is completed and the process proceeds to the next step, executing step S210.

[0113] If the read result of a storage unit does not meet expectations, step S204 is executed.

[0114] S204: Re-erasing the storage units corresponding to the results that do not meet the expectations.

[0115] Re-erase the memory cells that were not erased properly to ensure that they return to normal.

[0116] The following is an overall description of the embodiments of the present invention. Figure 5 For the flash memory to be tested, first erase the entire chip and then verify whether it is completely erased. After the erasure is completed, write the test data into the flash memory to be tested. After the input is written, verify each data block by block. If the verification passes, verify it again in a cycle.

[0117] Furthermore, the embodiment of the present invention also provides a flash memory testing device, referring to Figure 6 , the flash memory testing device 300 comprises:

[0118] The data writing unit 310 is used to divide the test data into a plurality of to-be-tested data blocks, and sequentially write each to-be-tested data block into the erased to-be-tested flash memory;

[0119] The data verification unit 320 is used to activate the word lines of the flash memory to be tested cyclically according to the preset word line activation time, read a data block to be tested of the flash memory to be tested after each word line activation, and perform data verification on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

[0120] In summary, the flash memory testing method, device, electronic device and storage medium provided by the embodiments of the present invention can effectively screen out abnormal chips caused by insufficient word line activation time by adopting block reading and verification, thereby ensuring the stability and accuracy of high-speed reading operations. In addition, by adding additional cycle tests, the screening effort is further increased, while the testing cost is effectively controlled. This method not only improves the rigor of the test, but also screens out more potential unstable factors without increasing excessive costs, thereby ensuring the quality of the final product.

[0121] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a module, a program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0122] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0123] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a computer-readable storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0124] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0125] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A flash memory testing method, characterized in that: The method comprises: Dividing the test data into a plurality of data blocks to be tested, and sequentially writing each of the data blocks to be tested into the erased flash memory to be tested; The word lines of the flash memory to be tested are activated cyclically according to the preset word line activation time, and a data block to be tested of the flash memory to be tested is read after each word line activation, and data verification is performed on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

2. The method according to claim 1, characterized in that The step of dividing the test data into a plurality of data blocks to be tested, and sequentially writing each of the data blocks to be tested into the erased flash memory to be tested comprises: Divide the test data into a plurality of test data blocks of preset sizes; Generating a check code corresponding to each of the data blocks to be tested according to each of the data blocks to be tested; Each of the to-be-tested data blocks and the corresponding verification code are written into the erased to-be-tested flash memory.

3. The method according to claim 1, characterized in that: The loop activates the word line of the flash memory to be tested according to the preset word line activation time, reads one of the data blocks to be tested of the flash memory to be tested after each word line activation, and performs data verification on the read data block to be tested to confirm whether the flash memory to be tested is abnormal, including: Obtaining a storage address of the to-be-tested data block to be read; activating the word line corresponding to the storage address according to a preset word line activation time; According to the storage address, reading out the data to be verified of the data block to be tested; Verifying whether the data to be verified is normal; If not, exit the test and determine that the flash memory to be tested is abnormal; If so, the step of obtaining a storage address of the to-be-tested data block to be read is performed again until each of the to-be-tested data blocks is verified to be normal or the to-be-tested data is abnormal.

4. The method according to claim 3, characterized in that The verifying whether the data to be verified is normal includes: Separating the data to be verified to obtain valid data and a first verification code; Performing binary division on the valid data and a preset generator polynomial to obtain a second check code; Determining whether the second verification code matches the first verification code; If yes, the data to be verified is normal; If so, the data to be verified is abnormal.

5. The method according to claim 3, characterized in that: Before the step of exiting the detection and determining that the flash memory to be tested is abnormal, the step further includes: A target spare block is selected from the spare area of ​​the flash memory to be tested, and the bad block of the storage address is replaced.

6. The method according to claim 1, characterized in that The method further comprises: If the flash memory to be tested is tested normally, the cycle is repeated for a preset number of times to activate the word line of the flash memory to be tested according to the preset word line activation time, and after each word line activation, one of the data blocks to be tested of the flash memory to be tested is read, and data verification is performed on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

7. The method according to claim 1, characterized in that Before the step of dividing the test data into a plurality of data blocks to be tested and sequentially writing each of the data blocks to be tested into the erased flash memory to be tested, the step further includes: Erasing the entire flash memory to be tested; Performing full-chip reading on the flash memory to be tested to obtain results of all storage units of the flash memory to be tested; Determine whether any of the results described are not in line with expectations; If so, re-erasing the storage cells corresponding to the results that do not meet the expectations; If not, the erase is complete.

8. A flash memory testing device, characterized in that: The device comprises: A data writing unit, used for dividing the test data into a plurality of data blocks to be tested, and sequentially writing each of the data blocks to be tested into the erased flash memory to be tested; A data verification unit is used to cyclically activate the word lines of the flash memory to be tested according to a preset word line activation time, read a data block to be tested of the flash memory to be tested after each word line activation, and perform data verification on the read data block to be tested to confirm whether the flash memory to be tested is abnormal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 7 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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