Method for preparing semiconductor structure and a semiconductor structure

Abstract

A method for manufacturing a semiconductor structure and a semiconductor structure, belonging to the technical field of semiconductor processing, particularly relating to the pixel fabrication of a CMOS image sensor; it solves the problem that in the existing CIS process, due to the spin coating of thick photoresist, isolated photoresist patterns with a high aspect ratio (aspect ratio > 3:1) are prone to collapse and lateral displacement under the action of centrifugal force during the drying process; the processing method of the isolated photoresist patterns in the method for manufacturing the semiconductor structure includes the following steps: exposing and developing a photoresist coating to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is an exposed position, and a given thickness of photoresist is reserved at the bottom of the exposed position, so that the bottoms of the plurality of initial isolated photoresist patterns are connected as a whole. The method for manufacturing the semiconductor structure is applicable to the fabrication of a CMOS image sensor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to the processing technology of CMOS image sensors. Background Art

[0002] With the widespread use of CMOS image sensors in consumer electronics and the rapid iteration of these products, demands for CMOS image sensor performance, such as pixel size and full well capacity (FWC), are increasing. For example, professional photography and video require both high resolution and high dynamic range (HDR), requiring individual pixels to maintain improved charge storage capacity through deep photodiodes or backside illumination (BSI) structures while miniaturizing. Autonomous driving LiDAR and machine vision applications, for example, require sensors to operate in extreme lighting conditions (such as strong backlight and at night), requiring ultra-high FWC to avoid saturation while relying on small pixels to achieve high spatial resolution (e.g., identifying distant objects).

[0003] As pixel size continues to shrink, deeper P-wells are required to achieve electrical isolation between adjacent pixels. This inevitably leads to the use of thicker photoresist (photoresist coating) combined with high-energy ion implantation in the pixel manufacturing process of CMOS image sensors to produce deep P-wells. Specifically:

[0004] Smaller pixel sizes require deeper P-wells: When pixel sizes shrink to submicron levels (e.g., below 0.8μm), the depletion regions of adjacent pixels may overlap, leading to leakage current and charge crosstalk. Deep P-wells extend the depletion region width and junction depth to form a thicker space charge region, inhibiting carriers (e.g., electrons) from diffusing or drifting across the isolation region.

[0005] Deeper P-wells require thicker photoresist: High-energy ions (such as boron ions at 500 keV) can travel up to several microns through the photoresist. If the photoresist thickness is insufficient, the ions can penetrate the photoresist layer, causing unintended doping of non-implanted areas (such as metal wiring layers or gates), leading to device failure. Calculating photoresist thickness: Based on the ion stopping power formula, the photoresist must at least cover the maximum range of the ions. For example, for 1 MeV boron ion implantation, a photoresist thickness of >3 μm is required.

[0006] In the existing CIS (CMOS Image Sensor) process, to avoid electrical crosstalk between PDs (Photo diodes), shallow trench isolation (STI) and P+-type sidewall isolation are usually adopted between PDs. As the pixel size continues to shrink, in order to obtain a full well capacity that meets the requirements, the longitudinal depth of the PDs is continuously increased. As a result, the electrical isolation also requires the P+-type sidewall isolation to be deeper and deeper. Generally, P+ ion implantation is relatively deep and requires a thick photoresist (i.e., thick photoresist spin coating). Currently, as the pixel size shrinks and the longitudinal depth of the photodiode (PD) increases, when a thick photoresist is required in the process to form an isolated photoresist pattern (isolation pattern) with a high aspect ratio (>3:1) to achieve deep P+ isolation, specifically:

[0007] Ion implantation depth matching: Deep P+ isolation needs to form a deep junction (>2μm) through high-energy ion implantation (such as boron ions, energy >500 keV), and the photoresist thickness needs to at least cover the maximum range of the ions (known according to the stopping power formula). For example, the photoresist thickness needs to be ≥3μm to block the penetration of 1 MeV boron ions.

[0008] Lateral dimension constraint: When the pixel size shrinks to the sub-micron level (such as 0.8μm), the lateral width of the isolation area needs to be ≤0.3μm (to avoid occupying too much PD area), resulting in an aspect ratio >3:1 (3μm thick photoresist / 0.3μm wide pattern).

[0009] Resolution and lithography ability: The diffraction effect of deep ultraviolet (DUV) lithography will limit the minimum line width. The thick photoresist needs to achieve a narrow isolation area through optical proximity correction (OPC) or multiple exposures. The high aspect ratio is an inevitable result of the compromise between resolution and thickness.

[0010] Due to the too thick photoresist, the isolated photoresist pattern (isolation pattern) with a high aspect ratio (aspect ratio >3:1) formed after directly exposing the photoresist to the bottom and developing is prone to collapse and lateral displacement during the spin-drying (i.e., spin-drying the developer) process. Specifically:

[0011] Centrifugal force effect: The centrifugal force F = m·ω²·r (m is the mass of the photoresist, ω is the angular velocity, r is the radius of rotation) generated during the spin-drying process at high speed (usually 3000 - 6000 rpm). The top of the isolated pattern is subjected to a large force and the bottom support area is small, resulting in the bending moment exceeding the bending strength of the photoresist.

[0012] Structural vulnerability: The aspect ratio of the high aspect ratio pattern (such as 3μm high / 0.3μm wide) is extremely high, similar to a slender column, and is prone to Euler Buckling.

[0013] Developer Residue and Surface Tension: The developer residue in the pattern gaps forms capillary force, and the evaporation of the liquid during the drying process generates shrinkage stress, exacerbating the pattern lateral shift. At the same time, the roughness of the photoresist sidewall (LWR) and the development non-uniformity (such as underdevelopment at the bottom) will reduce the structural strength.

[0014] The collapse and lateral shift of isolated photoresist patterns will affect the dose of subsequent ion implantation and thus affect the performance of CIS. Specifically:

[0015] Ion Implantation Dose Deviation: The collapse causes the deformation of the photoresist mask pattern, and the area of the effective blocking region changes. For example, the lateral shift of the photoresist can enlarge the actual implantation window, resulting in excessive lateral diffusion in the P+ region and an increase in leakage current.

[0016] Implantation Angle Deviation: The collapsed pattern may cause the incident angle of the ion beam to deviate from the designed value, resulting in insufficient junction depth or abnormal doping distribution.

[0017] Electrical Isolation Failure: The collapse of the photoresist reduces the distance between the P+ isolation region and the PD (such as from 0.3μm to 0.2μm), increasing the risk of overlap of the depletion regions, resulting in charge crosstalk, and then leading to a decrease in the signal-to-noise ratio. Insufficient depth of the deep well isolation (due to out-of-control implantation dose) will cause an increase in dark current, seriously affecting the low-light performance.

[0018] Full Well Capacity (FWC) and Dynamic Range (DR) Decrease: The isolation failure leads to a reduction in the PD charge storage capacity, resulting in a decrease in the dynamic range.

[0019] In addition, due to the too-thick thickness and too-large aspect ratio of the photoresist, there are differences in the exposure degree of its upper and lower surfaces, resulting in poor sidewall perpendicularity of the isolated photoresist pattern, and even causing a bridging (bridge) phenomenon where the bottom of the isolated photoresist pattern is not exposed (that is, the bottom is not completely disconnected and there is still residual photoresist connected). Summary of the Invention

[0020] The present invention proposes a method for preparing a semiconductor structure, which solves the problem that in the existing CIS process, the isolated photoresist pattern with a high aspect ratio (aspect ratio > 3:1) caused by spin-coating of thick photoresist is prone to collapse and lateral shift under the action of centrifugal force during the spin-drying process.

[0021] The method for preparing the semiconductor structure according to the present invention has the following technical solutions:

[0022] The preparation method includes a processing step of an isolated photoresist pattern, and the processing step of the isolated photoresist pattern includes:

[0023] On the surface of a semiconductor wafer, spin-coat thick photoresist to form a photoresist coating;

[0024] The photoresist coating is exposed and developed to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is the exposure position. During the exposure, it is ensured that a given thickness of photoresist is retained at the bottom of the exposure position, so that the bottoms of the plurality of initial isolated photoresist patterns are connected as a whole;

[0025] A ashing process is used to remove the photoresist with a given thickness at the bottom of the exposure position, exposing the underlying semiconductor wafer surface, and obtaining a plurality of processed isolated photoresist patterns with unconnected bottoms.

[0026] Optionally, a redundancy is reserved for the feature size of the initial isolated photoresist pattern.

[0027] Optionally, the given thickness is 500 to 2000 angstroms.

[0028] Optionally, the thickness of the photoresist coating is 3.0 to 5.0 micrometers.

[0029] Optionally, the feature size of the processed isolated photoresist pattern is less than 1.5 micrometers.

[0030] Optionally, the aspect ratio of the processed isolated photoresist pattern is greater than 3:1.

[0031] Optionally, after the ashing process, the method further includes an ion implantation step.

[0032] Optionally, the photoresist coating is a positive photoresist layer;

[0033] The step of making the bottoms of the plurality of initial isolated photoresist patterns connected as a whole by retaining a given thickness of photoresist at the bottom of the exposure position where the periphery of each initial isolated photoresist pattern is the exposure position is as follows:

[0034] Control the exposure dose and focal length so that the photoresist with a given thickness at the bottom of the exposure position is not exposed.

[0035] Optionally, the photoresist with a given thickness at the bottom of the exposure position is a negative photoresist layer; the photoresist coating above the negative photoresist layer is a positive photoresist layer;

[0036] The step of making the bottoms of the plurality of initial isolated photoresist patterns connected as a whole by retaining a given thickness of photoresist at the bottom of the exposure position where the periphery of each initial isolated photoresist pattern is the exposure position is as follows:

[0037] Control the exposure dose and focal length to expose the positive photoresist layer and the negative photoresist layer at the exposure position.

[0038] The present invention also proposes a semiconductor structure, and its technical solution is as follows:

[0039] A semiconductor structure is prepared by using the preparation method of any one of the above semiconductor structures.

[0040] The present invention has the following beneficial effects:

[0041] In the preparation method of the semiconductor structure according to the present invention, in the processing step of the isolated photoresist pattern, during exposure and development, by retaining a given thickness of photoresist at the bottom of the exposed position, the bottom of the isolated photoresist pattern remains connected during the development process, thereby stabilizing each isolated photoresist pattern, and improving the problem that the isolated photoresist pattern formed after directly exposing the photoresist to the bottom and developing in the traditional method is prone to collapse during the spin-drying process due to the action of centrifugal force.

[0042] The preparation method of the semiconductor structure according to the present invention is applicable to the preparation of CMOS image sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0044] Figure 1 It is a schematic diagram of the change in the photoresist coating thickness and P-well depth in the CIS process before and after the pixel size is reduced; in the figure, the left side is before the pixel size is reduced, and the right side is after the pixel size is reduced. By comparison, it can be determined that both the photoresist coating thickness and the P-well depth have increased significantly;

[0045] Figure 2 It is a top view of the isolated photoresist pattern when it does not collapse and shift; in the figure, all isolated photoresist patterns are arranged in a matrix and at equal intervals;

[0046] Figure 3 It is a top view of the isolated photoresist pattern when it collapses and shifts; in the figure, two isolated photoresist patterns have collapsed and shifted, and their tops have overlapped on other adjacent isolated photoresist patterns;

[0047] Figure 4 It is a cross-sectional schematic diagram of the bottom bridging phenomenon of the isolated photoresist pattern; in the figure, obvious bridging phenomena occur at the bottoms of several adjacent isolated photoresist patterns, as shown in the positions of the red circles in the figure;

[0048] Figure 5 It is a flow schematic diagram of the preparation method of the semiconductor structure in one embodiment; wherein, Figure 5 in (a) is a schematic diagram of the semiconductor structure after spin-coating of thick photoresist, from bottom to top are P-sub layer, EPI layer, sacrificial oxide layer, and photoresist layer PR; Figure 5In (b) is a schematic diagram of PR exposure. In the figure, the exposure position is in the middle of the two black lines at the upper part. The dark area below this position is the exposure area, and a given thickness area is reserved at the bottom below this position without being exposed; Figure 5 In (c) is a diagram of the state after development. The bottoms between adjacent isolated photoresist patterns are connected by the photoresist with a reserved given thickness to make them relatively stable; Figure 5 In (d) is the state after removing the photoresist with a given thickness at the bottom by using an ashing process; Figure 5 In (e) is ion implantation;

[0049] Figure 6 is a schematic flow chart of a method for preparing a semiconductor structure in an embodiment; wherein, Figure 6 In (a) is a schematic diagram of the semiconductor structure after spin-coating a thick photoresist once. From bottom to top in the figure are the P-sub layer, the EPI layer, the sacrificial oxide layer, and the negative photoresist layer. The thickness of the negative photoresist layer is a given thickness; Figure 6 In (b) is a schematic diagram of the semiconductor structure after spin-coating a thick photoresist twice. A positive photoresist layer is added on top of the negative photoresist layer; Figure 6 In (c) is a schematic diagram of exposure. The exposure depth in this step does not need to be strictly controlled, and the positive photoresist layer and the negative photoresist layer at the exposure position can be exposed simultaneously; Figure 6 In (d) is a diagram of the state after development. The negative photoresist at the bottom between adjacent isolated photoresist patterns remains, achieving the effect of connecting the isolated photoresist patterns; Figure 6 In (e) is the state after removing the photoresist with a given thickness at the bottom by using an ashing process; Figure 6 In (f) is ion implantation;

[0050] Figure 7 is a schematic diagram of the position of the first focal depth plane when the photoresist coating is exposed for the first time;

[0051] Figure 8 is a schematic diagram of the position of the second focal depth plane when the photoresist coating is exposed for the second time.

[0052] Reference numerals:

[0053] 2, Photoresist Coating (Photo Resist PR); 201, Negative Photoresist Layer; 202, Positive Photoresist Layer; 3, Sacrificial Oxide Layer; 4, PW, i.e., P-well, is a doped region with a certain depth fabricated in the surface layer of the substrate; 5, EPI, i.e., Epitaxial Layer, is the part grown and deposited on the wafer substrate, with a thickness generally of 5.4 microns; 6, P-sub, i.e., p-type Substrate, is the silicon wafer used for epitaxy (Epi), with a thickness generally of 770 microns; d1, Thickness of the photoresist coating, which is 3.0 to 5.0 microns; d2, Given thickness, which is 500 to 2000 Å; d3 = 2.0 microns; 10, Exposure; 11, Ashing Process; 13, IMP, i.e., Ion Implantation; 21, Photomask; 22, Lens; 25a, First Depth of Focus Plane (fous1); 25b, Second Depth of Focus Plane (fous2). Detailed Implementation Modes

[0054] To make the technical solutions and advantages of the present invention more clearly expressed, the following will further describe in detail and completely the specific implementation modes of the present invention in conjunction with the accompanying drawings. The following described various implementation modes are only some preferred solutions of the present invention, rather than all implementation solutions; the following described various implementation modes are intended to explain the present invention and should not be construed as a limitation to the present invention; the reasonable combination of the technical features defined in the various implementation modes of the present invention, and all other implementation modes obtained by those of ordinary skill in the art based on the implementation modes of the present invention without creative efforts, fall within the scope of protection of the present invention.

[0055] In one implementation mode, a method for preparing a semiconductor structure is provided. The preparation method includes a processing step for isolated photoresist patterns, and the specific processing steps are as follows:

[0056] On the surface of a semiconductor wafer, a thick photoresist is spin-coated to form a photoresist coating;

[0057] The photoresist coating is exposed and developed to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is an exposure position. During the exposure, it is ensured that the exposure position retains a given thickness of photoresist at the bottom, so that the bottoms of the plurality of initial isolated photoresist patterns are connected as a whole;

[0058] An ashing process is used to remove the photoresist with a given thickness at the bottom of the exposure position, exposing the underlying semiconductor wafer surface, and obtaining a plurality of processed and completed isolated photoresist patterns with unconnected bottoms.

[0059] In this implementation mode, a semiconductor wafer (wafer) refers to a silicon (Si) chip used for fabricating silicon semiconductor integrated circuits and is the carrier for producing integrated circuits.

[0060] In this embodiment, an isolation pattern refers to a microscopic structure formed on a photoresist coating through a lithography process for isolating different functional regions.

[0061] In this embodiment, thick photoresist spin coating means uniformly coating a semiconductor wafer with photoresist by spin coating to form a photoresist layer with a certain thickness. Here, "thick photoresist" means that the thickness of the photoresist layer is relatively thick. The preparation method described in this embodiment is suitable for cases where the thick photoresist is greater than 3.0 microns, and the optimal thick photoresist is between 3.0 microns and 5.0 microns. Through multiple photoresist coating, thick photoresist uniformity can be achieved without sacrificing resolution.

[0062] In this embodiment, exposure: A wafer coated with a photoresist coating is exposed using a mask (or reticle); during the exposure process, light passes through the exposure positions on the mask (i.e., the transparent parts of the mask / reticle) and irradiates the photoresist coating to process the photoresist into a pattern (i.e., the initial isolation pattern).

[0063] During the exposure process, the quality and effect of the exposure can be controlled by controlling the exposure dose and focal length. For example, for a photoresist coating with a thickness of 3.5 microns, compared with a conventional exposure process, by shifting the exposure focal length (focus) up by 0.4 microns, a given thickness (500 to 2000 Å) of photoresist is retained at the bottom of the exposure position; in practice, the specific parameters of the focal length shift may vary depending on the lithography machine manufacturer.

[0064] In this embodiment, development includes steps such as pre-development preparation, development process, and post-development treatment:

[0065] Pre-development preparation: A developer is selected according to the type of photoresist. In this embodiment, a weakly alkaline solution (such as tetramethylammonium hydroxide [TMAH]) is selected as the developer to achieve the dissolution of the photoresist.

[0066] Development process: In this embodiment, spin development is used to achieve development. Spin development refers to using a dedicated spin coater / developer to automatically control the development process by rotating the semiconductor structure and spraying the developer.

[0067] Post-development treatment: The developer is rinsed with deionized water and spun dry to dilute the developer and prevent overdevelopment. When spun dry, the moisture on the semiconductor structure is spun dry by rotation or centrifugation.

[0068] In the traditional method, after the photoresist is directly exposed to the bottom and developed to form isolated photoresist patterns, during the spin-drying process, due to the action of centrifugal force, the isolated photoresist patterns are prone to collapse; in this embodiment, the bottom of the isolated photoresist patterns is kept connected to each other by the photoresist with a given thickness reserved at the bottom of the exposure position, improving the stability of the isolated photoresist patterns and ameliorating the phenomenon that the isolated photoresist patterns are prone to collapse and shift under the action of centrifugal force during the spin-drying process.

[0069] In addition, in one embodiment, a redundancy is reserved for the feature size of the initial isolated photoresist pattern.

[0070] In this embodiment, reserving a redundancy for the feature size of the initial isolated photoresist pattern means that the feature size of the initial isolated photoresist pattern is larger than the feature size of the processed isolated photoresist pattern.

[0071] It should be noted that the feature size of the isolated photoresist pattern, usually also referred to as the line width or critical dimension (Critical Dimension, abbreviated as CD), can reflect the graphic processing accuracy of integrated circuit photomask manufacturing and lithography processes. The smaller the feature size, the higher the resolution, the more difficult the process, and many factors need to be considered in its processing, such as ensuring the ion implantation amount, ion implantation process, electrical isolation performance, and the feasibility of existing lithography processes and equipment. The preparation method described in this embodiment is suitable for processing semiconductor structures with a feature size less than 1.5 microns.

[0072] It should be noted that using thick photoresist spin coating will also bring the following problems:

[0073] Due to the too thick thickness and too large aspect ratio of the photoresist, the exposure degree of its upper and lower surfaces is different, and standing wave effects are prone to occur at the bottom of the isolated photoresist pattern, resulting in uneven photoresist exposure. After development, it becomes serrated, resulting in poor sidewall perpendicularity of the isolated photoresist pattern, and even causing a bridging (bridge) phenomenon where the bottom of the isolated photoresist pattern is not exposed (i.e., the bottom is not completely disconnected and there is still residual photoresist connected), as shown in Figure 4 As shown, the positions with bridging phenomena are within the red circles in the figure. At present, there is no effective technical means to effectively detect this phenomenon during the processing, and the detection and repair technologies are also relatively difficult. This phenomenon will affect subsequent steps such as ion implantation, and once it occurs, it will affect the quality of the processed products, and can lead to problems such as circuit short circuits, signal transmission problems, and device failures.

[0074] In view of the above problems, in this embodiment, an ashing process is adopted to remove the photoresist with a given thickness remaining after development. The ashing process is a stable process that can effectively ensure the removal of the photoresist with the given thickness, solving the problem of uneven exposure of the photoresist caused by thick photoresist spin coating, which in turn causes poor sidewall perpendicularity of isolated photoresist patterns or even bridging at the bottom.

[0075] It should be noted that while using the ashing process to remove the photoresist with a given thickness at the bottom of the exposed position, side etching will occur on the photoresist, which in turn affects the feature size of the isolated photoresist pattern. In view of this problem, in this embodiment, by reserving redundancy in the feature size of the initial isolated photoresist pattern, that is, reserving the margin of side etching in the ashing process, the influence of the side etching of the ashing process is overcome, so that the feature size of the obtained isolated photoresist pattern meets the design requirements.

[0076] In addition, in one embodiment, there are two ways to reserve redundancy in the feature size of the initial isolated photoresist pattern:

[0077] One way: Reserve redundancy when designing the feature size using a mask (or reticle) before exposure;

[0078] Another way: Reserve redundancy when adjusting the feature size of the initial isolated photoresist pattern by controlling the exposure dose and focal length during exposure.

[0079] In addition, in one embodiment, the ashing process is an oxygen plasma ashing (O2 light Asher) process.

[0080] The oxygen plasma ashing process is a process that uses oxygen and ultraviolet light (or other light sources) to ash the photoresist. Compared with the traditional ashing process, the process temperature needs to be controlled within a given range to avoid deformation of the isolated photoresist pattern. Generally, the process temperature of the oxygen plasma ashing process is controlled within 150°C.

[0081] In addition, in one embodiment, the given thickness is 500 to 2000 angstroms.

[0082] In addition, in one embodiment, the thickness of the photoresist coating is 3.0 to 5.0 micrometers.

[0083] In addition, in one embodiment, the feature size of the processed isolated photoresist pattern is less than 1.5 micrometers.

[0084] In addition, in one embodiment, the aspect ratio of the processed isolated photoresist pattern is greater than 3:1.

[0085] In addition, in one embodiment, after the ashing process, the method further includes an ion implantation step.

[0086] The ion implantation process can be implemented using existing technologies. For example:

[0087] In addition, in one embodiment, the photoresist coating is a positive photoresist layer. In this case:

[0088] The steps of making the bottoms of multiple initial isolated photoresist patterns connected as a whole by taking the periphery of each initial isolated photoresist pattern as the exposure position and retaining the photoresist with a given thickness at the bottom of the exposure position are as follows:

[0089] Control the exposure dose and focal length so that the photoresist with a given thickness at the bottom of the exposure position is not exposed.

[0090] In this embodiment, control the exposure dose (dose) and focal length (focus) so that the photoresist with a given thickness at the bottom of the exposure position is not exposed, specifically as follows:

[0091] Expose the photoresist coating (positive photoresist layer) twice, and adjust the exposure focal length so that the photoresist with a given thickness at the bottom of the exposure position is not exposed;

[0092] The adjustment of the exposure focal length is divided into the following two methods:

[0093] One method: During the first exposure, the exposure focal length remains unchanged; during the second exposure, move the second focal depth plane upward (i.e., increase the focal length) so that the photoresist with a given thickness at the bottom of the exposure position is not exposed;

[0094] Another method: During the first exposure, move the first focal depth plane upward; at the same time, during the second exposure, move the second focal depth plane upward so that the photoresist with a given thickness at the bottom of the exposure position is not exposed;

[0095] Adjust the feature size by adjusting the exposure dose.

[0096] In addition, in one embodiment, the photoresist coating is divided into two layers, the bottom layer is a negative photoresist layer, and a positive photoresist layer is above the negative photoresist layer; the thickness of the negative photoresist layer is a given thickness; in this case:

[0097] The steps of making the bottoms of multiple initial isolated photoresist patterns connected as a whole by taking the periphery of each initial isolated photoresist pattern as the exposure position and retaining the photoresist with a given thickness at the bottom of the exposure position are as follows:

[0098] Control the exposure dose and focal length, and expose the positive photoresist layer and the negative photoresist layer at the exposure position.

[0099] It should be noted that the photoresist coating is composed of a positive photoresist layer on the top and a negative photoresist layer on the bottom. Since the positive photoresist layer and the negative photoresist layer have different reactions to light, in the exposure process, the positive photoresist layer dissolves in the developer and disappears, while the negative photoresist layer does not dissolve in the developer and remains, achieving the retention of the negative photoresist layer with a given thickness after exposure and development.

[0100] In addition, in one embodiment, before exposure, a baking process is used to ensure that the negative photoresist layer and the positive photoresist layer adhere more tightly together. At the same time, the baking process is used to remove the moisture in the positive photoresist layer and the negative photoresist layer.

[0101] It should be noted that the functions of removing the moisture in the positive photoresist layer and the negative photoresist layer are mainly as follows:

[0102] Improve lithography accuracy: Moisture may affect the uniformity and stability of the photoresist, thereby affecting the accuracy of isolated photoresist patterns. Removing moisture can improve the stable performance of the photoresist during exposure and development.

[0103] Prevent defects: Moisture may evaporate during the baking process and cause bubbles or cracks to form inside the photoresist. These defects will seriously affect the performance of subsequent process steps and the final product. Therefore, removing the moisture in the positive photoresist layer and the negative photoresist layer through the baking process can improve the overall processing quality and ensure the quality of the final product.

[0104] Improve adhesion: Removing moisture can also help the photoresist adhere better to the wafer surface, improve the bonding force between the photoresist and the wafer, and thus enhance the stability and reliability of isolated photoresist patterns.

[0105] In addition, in one embodiment, a semiconductor structure is provided, which is prepared by using the preparation method of the semiconductor structure in any one of the above.

[0106] In this embodiment, the isolation pattern refers to the pattern formed during lithography for isolating different circuit regions, not just a planar pattern. It includes the entire three-dimensional structure formed by the photoresist after exposure and development.

[0107] In this embodiment, by retaining the photoresist with a given thickness at the bottom of the exposed position, the bottom of the initial isolation pattern is hinged together by this given thickness of the photoresist, so that during the subsequent development process, the initial isolation pattern is protected from lateral displacement and collapse due to the centrifugal force of the development rotation.

[0108] After development and spin-drying, there is no high-speed rotation process in the subsequent process. At this time, an ashing process is used to remove the photoresist with a given thickness at the bottom of the exposed position, which can effectively improve the bridging phenomenon at the bottom of the isolation pattern.

[0109] It should be noted that an isolated photoresist pattern is a microscopic structure. During the processing, stress may be generated due to factors such as inhomogeneity within the material, temperature differences, humidity changes, chemical treatment, or physical effects (such as centrifugal force during the spin-drying process). This stress is manifested as tension or pressure in the structure (which can be called photoresist pattern tension), and may affect the stability and integrity of the structure.

[0110] During the spin-drying process, due to the action of centrifugal force, the photoresist material (usually in a liquid or semi-solid state) will be strongly pulled outward. At the same time, if the surrounding isolated photoresist patterns have solidified and have a certain stiffness, they may produce additional pulling or squeezing effects on the photoresist material due to the action of internal stress (i.e., photoresist pattern tension). This combined effect may cause the photoresist material to deform, collapse, or fall off during the drying process, thus affecting the quality and performance of the final product.

[0111] In this embodiment, by exposing the photoresist with a given thickness at the bottom of the exposure position, the bottom hinge of the initial isolated photoresist pattern is integrated. Whether it is a single positive photoresist layer or a photoresist coating containing a negative photoresist layer, the material properties of the photoresist coating are basically the same, so that the internal properties of the material of the initial isolated photoresist pattern with an integrated bottom hinge remain uniform, reducing the stress effects caused by factors such as temperature differences, humidity changes, chemical treatment, and physical effects, and further overcoming the combined effect of photoresist pattern tension on centrifugal force, making the initial isolated photoresist pattern not easily collapse or shift sideways.

[0112] It should be noted that referring to Figure 1 , in the existing lithography technology, before coating the photoresist coating, there is usually a sacrificial oxide layer (SiO2) on the surface of the semiconductor wafer (silicon chip), and its thickness is basically between 50 and 100 Å (angstroms). Its main function is to isolate the photoresist from the substrate and at the same time serve as a protective layer for EPI during subsequent ion implantation. The photoresist coating is coated on the sacrificial oxide layer.

[0113] It should be noted that there are dozens of lithography processes in the semiconductor wafer manufacturing process. Each time the photoresist is removed, a part of the sacrificial oxide layer will be etched by the acidic photoresist remover; after multiple lithography processes, the adhesion between the sacrificial oxide layer and the photoresist coating will become worse and worse, leading to the collapse of the isolated photoresist pattern.

[0114] It should be noted that in order to solve the problem of the collapse of the isolated photoresist pattern caused by the adhesion, the prior art usually coats a layer of HMDS (hexamethyldisilazane, which is a chemical substance used to improve the surface characteristics of the substrate) on the surface of the substrate to increase the adhesion between the photoresist coating and the substrate. In addition:

[0115] Some existing technologies will regrow a layer after removing the sacrificial oxide layer to maintain the adhesion between the photoresist coating and the sacrificial oxide layer;

[0116] Some existing technologies will activate the sacrificial oxide layer by ashing before coating the photoresist coating to enhance the adhesion between the photoresist coating and the sacrificial oxide layer;

[0117] Some existing technologies use thin film growth technology and oxidation technology to generate an adhesive oxide layer (which is essentially part of the sacrificial oxide layer) to enhance the adhesion between the photoresist coating and the sacrificial oxide layer;

[0118] The above existing technologies all start from the perspective of enhancing the adhesion at the interface between the photoresist coating and the sacrificial oxide layer and attempt to improve the problem of collapse of isolated photoresist patterns.

[0119] It should be noted that the adhesion between the isolated photoresist pattern and the sacrificial oxide layer is limited. The technical solution of improving the adhesion cannot solve the problem of collapse and lateral displacement of the isolated photoresist pattern caused by the centrifugal force during the development and spin-drying process in the case of a high aspect ratio (>3:1).

[0120] It should be noted that too strong adhesion between the photoresist coating and the substrate is one of the reasons for photoresist residue, which in turn causes bridging at the bottom of the isolated photoresist pattern. Therefore, the technical solution of enhancing the adhesion between the isolated photoresist pattern and the sacrificial oxide layer may instead increase the probability of bridging phenomenon, which is not conducive to subsequent processes.

[0121] In this embodiment, by retaining a given thickness of photoresist at the bottom of the exposed position, the bottoms of multiple initial isolated photoresist patterns are connected into one body, and the problem of easy collapse and lateral displacement of the isolated photoresist pattern can be solved without increasing the adhesion between the isolated photoresist pattern and the sacrificial oxide layer, and at the same time, the problem of bridging phenomenon caused by the enhancement of adhesion will not occur.

[0122] In this embodiment, for the pixel manufacturing process of a CMOS image sensor, the preparation method of the semiconductor structure focuses on solving the problems of collapse of the pattern during development and spin-drying due to centrifugal force and bridging at the bottom of the isolated photoresist pattern when forming an isolated photoresist pattern with a high aspect ratio (>3:1) of thick photoresist (3-5 μm). The technical effect is directly related to the stability of the photoresist pattern and the accuracy of ion implantation, and belongs to the optimization of structural stability in the lithography process.

[0123] I. Process steps and parameters of the preparation method of the semiconductor structure:

[0124] 1. Process steps: Expose and develop to retain the bottom photoresist (500-2000 angstroms); Ashing process to remove the bottom photoresist;

[0125] 2. Photoresist Structure: A double-layer structure (positive photoresist + negative photoresist) is optional.

[0126] 3. Key Parameters: The thickness of the photoresist coating is 3.0 to 5.0 micrometers, the aspect ratio (>3:1), the feature size (<1.5 μm), and a given thickness of 500 to 2000 angstroms of the bottom photoresist is retained.

[0127] 4. Subsequent Process: High-energy ion implantation (formation of deep P-well).

[0128] II. Uniqueness of the Technical Effects of the Preparation Method of the Semiconductor Structure:

[0129] 1. Bottom Hinge Integration:

[0130] The bottom photoresist is retained for physical connection (bottom hinge integration) to solve the problem of pattern collapse and lateral displacement. Specifically:

[0131] (1) Reducing the Bending Moment Concentration Effect:

[0132] ① Increasing the Support Width: Retaining the bottom photoresist extends the support width of the isolated photoresist pattern from the photoresist line width to the entire bottom layer area to overcome the centrifugal force.

[0133] ② Optimizing the Stress Distribution: Significantly reducing the root stress, retaining the bottom photoresist as a "flexible substrate" absorbs part of the centrifugal energy through elastic deformation, avoiding stress concentration at the pattern root.

[0134] (2) Suppressing Euler Buckling: Reducing the Effective Slenderness Ratio:

[0135] ① Shortening the Effective Length: The photoresist pattern changes from a free cantilever to a bottom-fixed one, reducing the effective length.

[0136] ② Increasing the Section Moment of Inertia: Retaining the bottom photoresist changes the section from rectangular to T-shaped, increasing the moment of inertia.

[0137] ③ Buckling Mode Transformation: Without retaining the bottom photoresist, the buckling mode is first-order bending (overall rollover); with the bottom photoresist retained, the buckling mode changes to local micro-bending (energy is absorbed by the photoresist layer), and the critical buckling load increases.

[0138] (3) Eliminating Capillary Forces: Interface Regulation and Stress Release:

[0139] ① Controlling the Residual Developer: Retaining the bottom photoresist reduces the residual amount of the developer in the pattern gaps by adjusting the surface hydrophilicity and hydrophobicity (increasing the contact angle), reducing the capillary force.

[0140] ② Drying Stress Release Path: Retaining the bottom photoresist as a stress buffer layer allows the pattern to undergo micron-level elastic deformation during drying, avoiding brittle fracture.

[0141] (4)Compensate for roughness defects: Mechanical reinforcement and crack inhibition:

[0142] ① Sidewall roughness (LWR) affects neutralization: The sidewall roughness of the photoresist can cause local stress concentration, and the reserved photoresist layer compensates in two ways:

[0143] Fill the grooves: The photoresist layer covers the rough area at the bottom of the sidewall to a certain height to form a smooth transition;

[0144] Crack passivation: The high fracture toughness of the photoresist layer prevents the propagation of microcracks.

[0145] ② Correct development non-uniformity: Insufficient development at the bottom will cause a sudden change in local hardness. Retaining the bottom photoresist as a homogenizing transition layer reduces the modulus gradient at the development interface and avoids stress mutation.

[0146] In summary, the bottom residual layer of the photoresist needs to act as a "hinge structure" (mechanical hinge). When spin-drying high aspect ratio (>3:1) patterns, it resists the pulling force of the centrifugal force on the sidewalls of the photoresist, connects the bottoms of multiple patterns into a whole, and disperses the centrifugal force through the bottom connection during spin-drying. A given thickness of 500 to 2000 angstroms can provide sufficient elastic modulus (about 3 - 5 GPa) and tensile strength to prevent pattern collapse.

[0147] It should be noted that for photoresist coatings with a thickness of 3.0 to 5.0 microns, feature sizes <1.5 μm, and patterns with a high aspect ratio >3:1, the given thickness should neither be too thin nor too thick. A design of 500 to 2000 angstroms is a better choice:

[0148] On the one hand, if the thickness is too thin (<500 angstroms): it will lead to insufficient mechanical support, unable to resist the effects of centrifugal force and stress, and unable to avoid pattern collapse.

[0149] On the other hand, if the thickness is too thick (>2000 angstroms): the rigidity of the photoresist layer is too high, resulting in an increase in the overall brittleness of the photoresist and a decrease in fracture toughness; the thickness needs to match the ashing rate. A too thick photoresist layer requires a longer ashing time, and long-term ashing causes thermal deformation of the photoresist, affecting the accuracy of the ion implantation mask, or resulting in incomplete removal of the photoresist layer, and the residual photoresist hinders ion implantation.

[0150] In summary, the given thickness of 500 to 2000 angstroms is the result of comprehensive optimization through mechanical design, ion blocking requirements, and process compatibility.

[0151] 2. Use the ashing process to remove the bottom residual photoresist and avoid bridging at the bottom:

[0152] In the traditional thick photoresist process, bridging is likely to occur at the bottom of isolated photoresist patterns due to uneven exposure. In this embodiment, the residual photoresist at the bottom is precisely removed through an ashing process, avoiding ion implantation deviation caused by bridging and improving the electrical isolation performance of the CMOS sensor. At the same time, by reserving redundancy in the feature size of the initial photoresist pattern, the influence of the ashing process on the pattern size is solved, ensuring that the final feature size meets the accuracy requirement of less than 1.5 microns.

[0153] 3. Process Compatibility and Yield Improvement:

[0154] The low-temperature characteristics (<150°C) of the ashing process (such as O2 oxidation ashing) avoid thermal deformation of the photoresist pattern and are compatible with existing CMOS processes without additional equipment investment.

[0155] The ashing process has no risk of exposing the metal layer and does not introduce the risk of metal contamination in the etching process, making it suitable for high-precision ion implantation scenarios.

[0156] The ashing process removes the photoresist through an oxidation reaction and has less impact on the sidewall perpendicularity, making it suitable for structures with an aspect ratio > 3:1.

[0157] The above further describes the technical solutions provided by the present invention through several specific embodiments to highlight the advantages and benefits of the technical solutions provided by the present invention. However, the above-mentioned several specific embodiments are not used as limitations on the present invention. Any reasonable changes and improvements to the present invention, reasonable combinations of embodiments, and equivalent replacements within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, the preparation method including a processing step of an isolated photoresist pattern, characterized in that, The processing steps of the isolated photoresist pattern include: On the surface of a semiconductor wafer, a thick photoresist is spin-coated to form a photoresist coating. The photoresist coating is exposed and developed to form a plurality of initial isolated photoresist patterns; the periphery of each initial isolated photoresist pattern is an exposure position, and during the exposure, a given thickness of photoresist is reserved at the bottom of the exposure position so that the bottoms of the plurality of initial isolated photoresist patterns are connected together. An ashing process is used to remove the photoresist with a given thickness at the bottom of the exposure position, exposing the underlying semiconductor wafer surface to obtain a plurality of processed isolated photoresist patterns with unconnected bottoms. The feature size of the initial isolated photoresist pattern has a reserved redundancy. After the ashing process, the method further includes an ion implantation step.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein The given thickness is 500 to 2000 angstroms.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein The thickness of the photoresist coating is 3.0 to 5.0 micrometers.

4. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The feature size of the processed isolated photoresist pattern is less than 1.5 micrometers.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The aspect ratio of the processed isolated photoresist pattern is greater than 3:

1.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, characterized in that The photoresist coating is a positive photoresist layer. The step of making the bottoms of the plurality of initial isolated photoresist patterns connected together by reserving a given thickness of photoresist at the bottom of the exposure position with the periphery of each initial isolated photoresist pattern being the exposure position is as follows: Control the exposure dose and focal length so that the photoresist with a given thickness at the bottom of the exposure position is not exposed.

7. The manufacturing method of the semiconductor structure according to any one of claims 1 to 5, characterized in that The photoresist with a given thickness at the bottom of the exposure position is a negative photoresist layer; the photoresist coating above the negative photoresist layer is a positive photoresist layer. The step of making the bottoms of the plurality of initial isolated photoresist patterns connected together by reserving a given thickness of photoresist at the bottom of the exposure position with the periphery of each initial isolated photoresist pattern being the exposure position is as follows: Control the exposure dose and focal length to expose the positive photoresist layer and the negative photoresist layer at the exposure position.

8. A semiconductor structure, characterized in that, Prepared by using the preparation method of the semiconductor structure according to any one of claims 1 to 5.

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