Package substrate and method for manufacturing package substrate

Abstract

The present specification relates to a package substrate and a method of manufacturing the same. The package substrate according to the present specification includes a core layer including: a glass core having a first surface and a second surface facing each other; a cavity portion which is recessed so as to open in the direction of the first surface or the second surface; and a plurality of core through-holes penetrating the glass core in the thickness direction, and the internal space of the cavity portion may include a first region recessed at a predetermined interval in the thickness direction and a second region recessed at a gradually narrowed interval in the thickness direction. As a result, it is possible to enhance the bonding force between the glasses forming the glass core having the half-cavity, and to prevent the problem of delamination of the glass forming the glass core even after a plurality of high-temperature processes.

Description

Technical Field

[0001] This document relates to a packaging substrate, a method for manufacturing a packaging substrate, a semiconductor package, a method for manufacturing a semiconductor package, etc. Background Art

[0002] When manufacturing electronic components, realizing circuits on semiconductor wafers is called the front-end (FE) process, and assembling the wafers into a state that can be used in actual products is called the back-end (BE) process. The back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have recently enabled the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology and software technology.

[0004] Semiconductor technology is developing in various forms, such as line widths of nanometer units below micrometers, more than 10 million cells, high-speed operation, and release of large amounts of heat, but there is still no technical support for relatively complete packaging of the above semiconductors.

[0005] Therefore, the electrical performance of a semiconductor sometimes depends on the packaging technology and the corresponding electrical connections, rather than on the performance of the semiconductor technology itself.

[0006] As the material of the packaging substrate, ceramic or resin is suitable. In the case of a ceramic substrate such as a silicon substrate, it is difficult to mount a high-performance high-frequency semiconductor device due to the high resistance value or high dielectric constant. In the case of a resin substrate, although relatively high-performance high-frequency semiconductor devices can be mounted, there are limitations in reducing the spacing of wiring.

[0007] Recently, silicon or glass can be applied to high-end packaging substrates. By forming a through hole on the silicon or glass substrate and applying a conductive material to the through hole, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be obtained.

[0008] In addition, the semiconductor package generates heat during operation, and sometimes additionally includes a heat sink for releasing the heat. Related prior art includes US patent US11694974 B2, US patent publication US2022-0367311 A1, etc. Summary of the invention

[0009] Technical issues

[0010] An object of the present embodiment is to provide a packaging substrate having a structure that can easily insert and position an electronic device in an inner space of a cavity in a packaging substrate using a glass core and improve manufacturing efficiency.

[0011] In addition, an object of the present embodiment is to provide a method for easily and efficiently providing a glass core having a cavity by bonding glasses, a method for manufacturing a package substrate using the method, and the like.

[0012] Solutions to the problem

[0013] In order to achieve the above objective, one embodiment relates to a packaging substrate and a method for manufacturing the packaging substrate.

[0014] In one or more embodiments, the packaging substrate includes a core layer, the core layer including: a glass core having a first surface and a second surface facing each other; a cavity portion, which is recessed in a manner opening in the direction of the first surface or the second surface; and a plurality of core through holes, which penetrate the glass core along the thickness direction.

[0015] The core through hole includes: a first opening connected to the first surface; a second opening connected to the second surface; and a minimum inner diameter portion, which is the area with the narrowest inner diameter in the entire core through hole connecting the first opening and the second opening.

[0016] The core through hole may include a first core through hole and a second core through hole having different arrangement heights of the minimum inner diameter portion.

[0017] When viewed from the upper surface side of the glass core, the second region of the glass core is a region where the cavity portion is arranged in the glass core, and the first region of the glass core is a region where the cavity portion is not arranged in the glass core.

[0018] The first core through hole is arranged in the first region, and the smallest inner diameter portion is arranged at a first position, and the second core through hole is arranged in the second region, and the smallest inner diameter portion is arranged at a second position.

[0019] With the second surface as a reference, a height of a minimum inner diameter portion of the first core through hole may be higher than a height of a minimum inner diameter portion of the second core through hole.

[0020] The glass core includes a first glass and a second glass stacked up and down, the first glass includes a through cavity, and a bonding interface is provided between a lower surface of the first glass and an upper surface of the second glass.

[0021] The second glass may have a concave surface.

[0022] The side wall angle of the through cavity of the first glass and the side wall angle of the recessed surface of the second glass may be different from each other.

[0023] Electronic components may be arranged in the inner space of the cavity.

[0024] The above-mentioned electronic components may include active components and / or passive components.

[0025] In one or more embodiments, the packaging substrate includes a core layer, the core layer including: a glass core having a first surface and a second surface facing each other; a cavity portion, a surface of which is recessed in a manner opening in the direction of the above-mentioned first surface and having an internal space; and a plurality of core through holes penetrating the above-mentioned glass core along the thickness direction.

[0026] The glass core includes a first glass and a second glass stacked up and down, and the first glass includes a through cavity.

[0027] When viewed from the upper surface side of the glass core, the second region of the glass core is a region of the glass core where the cavity portion is arranged.

[0028] The second glass may have a concave surface.

[0029] The side wall surface of the through cavity of the first glass is connected to the side wall surface of the recessed surface of the second glass, and when the cross section is observed in the thickness direction of the glass core, the internal space of the cavity portion may have a hexagonal shape.

[0030] When observing a cross section in a thickness direction of the glass core, the cavity portion is divided into a first section and a second section, the first section being a region arranged parallel to the first glass, and the second section being a region arranged parallel to the second glass.

[0031] The width of the cavity portion in the second section may be narrower than the width of the cavity portion in the first section.

[0032] The taper angle of the side wall of the cavity portion may be 87 degrees to 90 degrees.

[0033] In one or more embodiments, the package substrate includes a core layer, the core layer including: a glass core having a first surface and a second surface facing each other; and a plurality of core through holes penetrating the glass core in a thickness direction.

[0034] The glass core includes a first glass and a second glass stacked up and down, and the interface between the first glass and the second glass can be bonded by forming a chemical structure of Si-O-Si or O-Si-O structure.

[0035] The interface between the first glass and the second glass may not substantially include a polymer adhesive layer.

[0036] The first glass may include a through cavity.

[0037] The glass core may further include a cavity portion, a surface of the cavity portion being recessed so as to be open in a direction of the first surface and having an internal space.

[0038] In one or more embodiments, a method for manufacturing a packaging substrate includes: a primary core forming step, forming a primary core by joining a first glass and a second glass having a through cavity; and an etching step, forming a plurality of core through holes by etching the primary core; a glass core is formed by the primary core forming step and the etching step, the glass core having a first surface and a second surface facing each other, an internal space being arranged in a surface of the glass core that is open and recessed in the direction of the first surface, the core through hole penetrating the glass core in a thickness direction, the core through hole including: a first opening portion connected to the first surface; a second opening portion connected to the second surface; and a minimum inner diameter portion, which is the area with the narrowest inner diameter in the entire core through hole connecting the first opening portion and the second opening portion.

[0039] The core through hole may further include a first core through hole and a second core through hole having different arrangement heights of the minimum inner diameter portion.

[0040] When viewed from the upper surface side of the glass core, the second region of the glass core is a region of the glass core where the cavity portion is arranged.

[0041] The second glass may have a concave surface.

[0042] The side wall surface of the through cavity of the first glass is connected to the side wall surface of the recessed surface of the second glass, and in the cross section of the second region, the inner space of the cavity portion may have a hexagonal shape.

[0043] The bonding in the above-mentioned first core forming step can be achieved by anodic bonding.

[0044] Effects of the Invention

[0045] The package substrate and the method for manufacturing the package substrate of the present embodiment can easily insert and position the electronic device in the inner space of the cavity and improve the manufacturing efficiency. In addition, the glass can be conveniently bonded to efficiently manufacture the glass core.

[0046] The packaging substrate of this embodiment can reduce the damage of the glass core caused by multiple high-temperature processes in the manufacturing process of the packaging substrate. In addition, the packaging substrate of this embodiment can maintain the device margin, which is conducive to forming tolerances when performing the pick and place process of arranging electronic devices. At the same time, after the pick and place process, the space where the electronic device can move is small, thereby effectively preventing the problem of the electronic device deviating from the specified arrangement position. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Schematic diagram for explaining the cross-sectional structure of a package substrate according to the present embodiment.

[0048] Figure 2 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0049] Figure 3 Parts (a) and (b) of FIG. 1 are schematic diagrams each illustrating a portion of a package substrate according to the present embodiment in cross section.

[0050] Figure 4 The present invention is a cross-sectional flow chart for explaining a process of generating a core distribution layer in a process of manufacturing a package substrate according to the present embodiment.

[0051] Figure 5 The present invention is a cross-sectional flow chart for explaining a process of generating an insulating layer in a process of manufacturing a package substrate according to the present embodiment.

[0052] Figure 6 A cross-sectional flow chart illustrating a process of producing a glass core having a semi-cavity according to the present embodiment.

[0053] Figure 7 FIG. 1 is a schematic diagram illustrating a core layer including a glass core having a semi-cavity produced according to the present embodiment in cross section.

[0054] Figure 8 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate produced according to the present embodiment.

[0055] Description of Reference Numerals

[0056] 100: Semiconductor devices

[0057] 10: Motherboard

[0058] 15: Insulation layer

[0059] 30: Semiconductor Devices Department

[0060] 32: The first semiconductor device

[0061] 34: Second semiconductor device

[0062] 36: The third semiconductor device

[0063] 20: Package substrate

[0064] 21, 21a: Glass core

[0065] 22: Core layer

[0066] 223: Core insulation

[0067] 213: First Surface

[0068] 214: Second Surface

[0069] 23: Core through hole

[0070] 24: Core distribution layer

[0071] 241: Core distribution pattern

[0072] 26: Upper layer

[0073] 25: Upper distribution layer

[0074] 251: Upper distribution pattern

[0075] 253: Upper insulation layer

[0076] 27: Upper surface connection layer

[0077] 271: Top surface connection electrode

[0078] 272: Upper surface connection pattern

[0079] 28: Cavity

[0080] 29: Lower layer

[0081] 281: Interior Space

[0082] 282: Cavity distribution layer

[0083] 283: First interval

[0084] 284: Second interval

[0085] 40: Electronic devices

[0086] 50: Connection

[0087] 51: Device connection

[0088] 52: Plate connection

[0089] 61: First Glass

[0090] 62: Second Glass

[0091] 71: First position

[0092] 72: Second position

[0093] 73: First vertex

[0094] 74: Second Vertex DETAILED DESCRIPTION

[0095] The following detailed description is provided to help the reader fully understand the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the order of operations described herein is merely an example and is not limited to the operations set forth herein. The order of operations can be changed, as will be apparent after understanding the disclosure of the application, except for the operations that must occur in a specific order. In addition, after understanding the disclosure of the application, the description of known features can be omitted to increase clarity and simplicity. However, the omission of features and their descriptions is not intended to admit that they are common sense.

[0096] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0097] Although terms such as "first", "second", and "third" may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are only used to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section.

[0098] Throughout the specification, when a device such as a layer, a region or a substrate is described as being "on another device", "connected to another device" or "coupled to another device", it may be directly "on another device", "connected to another device" or "coupled to another device", or one or more other devices may be interposed therebetween. Conversely, when a device is described as being "directly on another device", "directly connected to another device" or "directly coupled to another device", no other device may be interposed therebetween. Similarly, expressions such as "between" and "immediately between" and "adjacent" and "immediately adjacent" may also be interpreted as described above.

[0099] The terms used herein are only used for the purpose of describing specific examples and are not used to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly states otherwise. As used herein, the term "and / or" includes any one of the items listed in the relevant list and any combination of any two or more items. As used herein, the terms "include", "comprise" and "have" specify the existence of stated features, numbers, operations, devices, parts and / or their combinations, but do not exclude the existence or addition of one or more other features, numbers, operations, devices, parts and / or their combinations. The use of the term "may" herein about examples or embodiments (for example, about the content that can be included or implemented in examples or embodiments) means that there is at least one example or embodiment in which such features are included or implemented, and all examples are not limited thereto.

[0100] In the present application, “B is placed on A” means that B is placed in direct contact with A or placed on A with another layer or structure interposed therebetween, and thus should not be construed as limited to B being placed in direct contact with A.

[0101] Unless otherwise defined, all terms used herein have the same meaning as generally understood in the technical field to which the present disclosure belongs based on one of the common techniques. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless explicitly defined herein.

[0102] In one or more examples, the description of "A and / or B" means "A, B, or A and B."

[0103] In one or more examples, terms such as "first," "second," "A," or "B" are used to distinguish the same terms.

[0104] In one or more examples, unless otherwise stated, an expression in the singular is interpreted to include the meaning of the singular or plural as interpreted in the context.

[0105] Figure 1 2 is a schematic diagram for explaining a cross-sectional structure of a package substrate according to the present embodiment. Figure 2 2 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment. Figure 3 Parts (a) and (b) of FIG. 1 are schematic diagrams each illustrating a portion of a package substrate according to the present embodiment in cross section.

[0106] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the present embodiment includes: a semiconductor device unit 30, in which one or more semiconductor devices 32, 34, 36 are located; a packaging substrate 20, which is electrically connected to the semiconductor device; and a motherboard 10, which is electrically connected to the packaging substrate 20, transmits external electrical signals to the semiconductor devices 32, 34, 36 and connects the above-mentioned semiconductor devices and the external electrical signals.

[0107] The package substrate 20 according to one embodiment includes: a core layer 22 ; an upper layer 26 located on a surface of the core layer 22 ; and a cavity portion 28 , in which the electronic device 40 may be located.

[0108] The semiconductor device section 30 is a device mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor device section 30, for example, a computing device such as a CPU, a GPU (first device: 32, a second device: 34), a storage device such as a memory chip (third device: 36), etc. can be applied, but any semiconductor device mounted on a semiconductor device can be applied without limitation.

[0109] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0110] The package substrate 20 may selectively further include a lower layer (not shown) located below the core layer.

[0111] The core layer 22 may include: a glass core 21, including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, and the second region 222 is adjacent to the first region 221 and has a second thickness 212 thinner than the first thickness; a plurality of core through holes 23, penetrating the glass core 21 in the thickness direction; and a core distribution layer 24, located on the surface of the glass core 21 or the core through holes 23, and electrically connecting the first surface 213 of the glass core 21 and the second surface 214 facing the first surface through the core through holes 23.

[0112] The second region 222 of the core layer 22 may function as a cavity structure.

[0113] In the same region, the glass core 21 has a first surface 213 and a second surface 214 facing each other. The two surfaces are substantially parallel to each other, so that the glass core 21 has a certain thickness as a whole.

[0114] The inner space 281 formed by the thickness difference between the first region 221 and the second region 222 serves to accommodate a part or all of the electronic device 40 .

[0115] The glass core 21 may include a core through hole 23 penetrating the first surface 213 and the second surface 214. The core through hole 23 may be formed in both the first region 221 and the second region 222, and may be formed at a desired pitch and pattern.

[0116] As a packaging substrate for semiconductor devices, a stacked form of silicon substrate and organic substrate has been used in the past. Due to the characteristics of semiconductors, silicon substrates may produce parasitic devices when used in high-speed circuits, and have the disadvantage of relatively large power loss. In addition, organic substrates need to be large in area in order to form more complex distribution patterns, but this does not conform to the trend of manufacturing ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a predetermined size, the pattern needs to be miniaturized, but due to the characteristics of materials such as polymers suitable for organic substrates, pattern miniaturization actually has limitations.

[0117] In this embodiment, as a method for solving the above-mentioned problem, the glass core 21 is used as a support body of the core layer 22. In addition, together with the glass core 21, the core through hole 23 formed through the glass core 21 is also applied, thereby providing a package substrate 20 with a shorter current length, more miniaturization, faster response, and less loss characteristics.

[0118] The glass core 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0119] The core through hole 23 penetrates the glass core 21. The core through hole 23 may be formed by removing a predetermined region of the glass core 21, and more specifically, may be formed by etching a plate-shaped glass using a physical and / or chemical method.

[0120] Specifically, when forming the core through hole 23, a method of forming a defect (stain) on the surface of the glass core by laser or the like and then performing chemical etching or laser etching may be used, but the present invention is not limited thereto.

[0121] Based on the unit area (1 cm×1 cm) of the glass core 21, 100 to 3000 core through holes 23 may be provided, or 100 to 2500 core through holes 23 may be provided, or 225 to 1024 core through holes 23 may be provided. When the above spacing conditions are met, it is more conducive to forming a conductive layer, etc., and the performance of the package substrate may be improved.

[0122] The core distribution layer 24 includes a core distribution pattern 241 and a core insulation layer 223. The core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass core through a through hole, and the core insulation layer 223 surrounds the core distribution pattern. The core layer 22 is formed with a conductive layer through the core through hole to serve as an electrical path across the glass core 21, thereby connecting the upper and lower parts of the glass core with a relatively short distance, and can have faster electrical signal transmission and low loss characteristics. For example, the conductive layer can be a copper plating layer, but the present invention is not limited to this.

[0123] The cavity 28 is generally in the shape of a circle, a triangle, a quadrilateral, a hexagon, an octagon, a cross, etc., and its shape is not limited.

[0124] The shape of the electronic device 40 may be cylindrical, rectangular or polygonal.

[0125] The cavity portion 28 may include a cavity distribution pattern as a conductive layer electrically connecting the electronic device 40 and the core distribution layer 24 and an insulating layer surrounding the cavity distribution pattern.

[0126] On the other hand, the cavity portion according to another embodiment may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed according to the same process as the core through hole 23, and the area and shape of the penetrating glass core 21 may be different from those of the core through hole 23.

[0127] In this embodiment, the insulating layer may be formed after the electronic device 40 is arranged in the cavity portion. That is, the insulating layer may also be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0128] The core allocation pattern 241 may be formed as a pattern capable of being electrically connected to the above-mentioned electronic device 40 .

[0129] The electronic device 40 may include an active device such as a transistor or a power transmission device, ie, a passive device, such as a multi-layer ceramic capacitor (MLCC).

[0130] When a device such as a transistor that converts an electrical signal between a motherboard and a semiconductor device portion into an appropriate level is used as the electronic device 40, the transistor is used in the path of the packaging substrate 20, thereby providing a semiconductor device 100 with higher efficiency and speed.

[0131] In addition, power transmission devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Typically, more than 200 power transmission devices as passive devices are applied to semiconductor devices, and their performance is also affected by the characteristics of the conductive layer surrounding the device when transmitting power. In one embodiment, non-circular core vias can be applied to places where low-resistance conductive layers are required, such as the above-mentioned power transmission devices, instead of circular core vias.

[0132] On the other hand, the electronic device 40 may be in the form of a passive device such as a capacitor inserted separately, or may be formed in the form of being embedded between insulator layers (electronic device insulating layers) so that the electrodes of a device group including a plurality of passive devices are exposed and then inserted into the electronic device. In the latter case, the workability of manufacturing the package substrate can be improved more smoothly, and it is more conducive to fully and reliably positioning the insulating layer in the space between complex devices.

[0133] The glass core 21 serves as an intermediate and mediating role for connecting the semiconductor device portion 30 and the motherboard 10 to the upper and lower parts, respectively, and the core through hole 23 serves as a path for transmitting their electrical signals, thereby achieving smooth signal transmission. In order to distinguish from the core through hole in the second area 222 described later, the core through hole arranged in the first area 221 is referred to as the first area core through hole 231.

[0134] The upper layer 26 is located on the first surface 213 .

[0135] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25 . The uppermost surface of the upper layer 26 may be protected by a cover layer 60 having an opening for direct contact of the connection electrode of the semiconductor device.

[0136] The upper distribution layer 25 includes: an upper insulating layer 253 located on the first surface; and an upper distribution pattern 251, which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, and the upper distribution pattern 251 is embedded in the upper insulating layer 253. The upper distribution layers 25 arranged above and below each other can be connected to each other through blind holes 252.

[0137] As the upper insulating layer 253 , any material as long as it is suitable for use as an insulating layer in a semiconductor device or a package substrate can be used. For example, epoxy resin including a filler can be used, but the present invention is not limited thereto.

[0138] The insulator layer may be formed by forming a coating and curing it, or may be formed by laminating an insulator film formed in an uncured or semi-cured state on the core layer 22 and curing it. At this time, if a reduced pressure lamination method or the like is adopted, the insulator is embedded in the space inside the core through hole 23, so that the process can be performed efficiently.

[0139] According to one embodiment, even if multiple insulator layers are stacked for application, it may be difficult to substantially distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case, their boundaries may be substantially indistinguishable. Alternatively, according to another embodiment, the boundaries of the insulating layers may be created by setting the pressure and temperature of curing the multiple insulating layers differently.

[0140] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined shape, and can be formed, for example, by a build-up layer method. Specifically, after forming an insulating layer, unnecessary portions of the insulating layer are removed, and then a conductive layer is formed by a method such as copper plating, and then unnecessary portions of the conductive layer are selectively removed, and then an insulating layer is formed again on the conductive layer, and then unnecessary portions are removed again, and then a conductive layer is formed by plating, and the above method is repeated, so that an upper distribution pattern 251 having a conductive layer formed in a desired pattern in a vertical or horizontal direction can be formed.

[0141] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device portion 30, and is therefore formed to include a fine pattern in at least a portion thereof, so as to smoothly transmit electrical signals with the semiconductor device portion 30 and fully accommodate the required complex pattern. At this time, the fine pattern refers to a pattern with a width and a spacing less than 4 μm, or a pattern with a width and a spacing less than 3.5 μm, or a pattern with a width and a spacing less than 3 μm, or a pattern with a width and a spacing less than 2.5 μm, or a pattern with a width and a spacing of 1 μm to 2.3 μm (hereinafter, the description of the fine pattern is the same).

[0142] The upper surface connection layer 27 includes: an upper surface connection pattern 272 , at least a portion of which is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253 ; and an upper surface connection electrode 271 , which electrically connects the semiconductor device portion 30 and the upper surface connection pattern 272 .

[0143] The upper surface connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in a manner that at least a portion thereof is exposed on the upper insulating layer. For example, in the case where the upper surface connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and in the case where the upper surface connection pattern is embedded in a manner that a portion thereof is exposed on the upper insulating layer, after forming a copper plating layer or the like, a portion of the insulating layer or the conductive layer may be removed by surface polishing, surface etching or the like.

[0144] Similar to the upper distribution pattern 251 described above, at least a portion of the upper surface connection pattern 272 may include a fine pattern. The upper surface connection pattern 272 including the fine pattern as described above allows more devices to be electrically connected even in a narrow area, thereby making the electrical signal connection between devices or with the outside smoother and enabling a more integrated package to be achieved.

[0145] The upper surface connection electrode 271 may be directly connected to the semiconductor device portion 30 through a terminal or the like, or may be connected via a device connection portion 51 such as a solder ball or the like.

[0146] The cavity portion 28 includes a cavity distribution layer 282 located above and / or below the second region 222 and electrically connected to the core distribution layer 241 and an inner space 281 for disposing the electronic device 40. The cavity distribution layer 282 may be formed through the second region core through hole 232.

[0147] Specifically, the thickness of the glass core 21 in the second region 222 is thinner than that in the first region 221, and the electronic device 40 can be located in the inner space 281 formed by the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass core 21 play a role of an electrical connection structure connecting the electronic device 40 and an external device.

[0148] In addition, as described above, a cavity portion may be formed in the form of penetrating the first region 221 instead of the second region 222 , ie, penetrating the first surface 213 and the second surface 214 of the glass core 21 , and the electronic device 40 may be arranged in the cavity portion.

[0149] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, and the motherboard 10 can be electrically connected via a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 connected to the motherboard 10 can be connected to the motherboard 10 via a lower layer (not shown in the figure) located at the lower part of the core layer 22. The device connection portion 51 and the board connection portion 52 are collectively referred to as a connection portion 50.

[0150] According to an example, except for the glass core 21 , the package substrate 20 between the semiconductor device portion 30 and the motherboard 10 may not substantially use an additional substrate.

[0151] In the past, the interposer and the organic substrate were stacked together and applied to the connection part between the device and the motherboard. It is understood that this multi-layer structure is adopted for at least two reasons: one is that there are scale problems in directly bonding the fine pattern of the device to the motherboard, and the other is that during the bonding process or the driving process of the semiconductor device, the difference in thermal expansion coefficient may cause wiring damage.

[0152] In this embodiment, the above problems are solved by using a glass core having a thermal expansion coefficient similar to that of a semiconductor device and forming a micro pattern having a size sufficient for mounting a device on the first surface of the glass core and its upper layer.

[0153] A method of manufacturing a package substrate according to an embodiment of the present invention will be described below.

[0154] Figure 4 and Figure 5 A cross-sectional flow chart illustrating a process of manufacturing a package substrate according to the present embodiment.

[0155] First, if Figure 4 As shown in part (a), a glass core 21a having a flat first surface and a flat second surface is prepared, and a defect 21b (groove) is formed at a predetermined position on the glass surface in order to form a core through hole. The above-mentioned glass can be a glass core suitable for a substrate of an electronic device, for example, an alkali-free glass core, etc. can be used, but it is not limited to this. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. The above-mentioned defect (groove) can be formed by mechanical etching, laser irradiation, etc.

[0156] like Figure 4 As shown in part (b) of FIG. 1 , an etching step is performed to form a core through hole 23 in the glass core 21a having the defect 21b (groove) formed therein by a physical or chemical etching process. During the etching process, the surface of the glass core 21a may be etched while forming the core through hole in the defective portion of the glass core. In order to prevent such etching of the glass surface, a mask film or the like may be applied, but in consideration of the trouble of the process of applying and removing the mask film, etc., the glass core itself with the defect may be etched, in which case the thickness of the glass core having the core through hole may be slightly thinner than the thickness of the original glass core.

[0157] Then, if Figure 4As shown in parts (c) and (d) of FIG. 2 , the core layer preparation step may be performed by forming a conductive layer 21d on the glass core. Representatively, the conductive layer may be a metal layer including copper metal, but the present invention is not limited thereto.

[0158] The surface of the glass (including the surface of the glass core and the surface of the core through hole) and the surface of the copper metal have different properties, so the adhesion is poor. In this embodiment, the adhesion between the glass surface and the metal is improved by two methods, a dry method and a wet method.

[0159] The dry method is a method for applying sputtering, that is, a method for forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by metal sputtering. When forming the above-mentioned seed layer, a dissimilar metal such as titanium, chromium, nickel, etc. can be sputtered together with copper, etc. In this case, it is believed that the adhesion between the glass and the metal is improved by the surface morphology of the glass and the anchoring effect of the interaction of the metal particles.

[0160] Wet method is the method for carrying out primer treatment, is the method for forming primer layer 21c by pre-treating with the compound substance with the functional group such as amine etc. According to the required adhesion degree, after pre-treating with silane coupling agent, primer treatment can be carried out with the compound or particle with amine functional group.As mentioned above, the support substrate of present embodiment needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep this state.Therefore, when this primer comprises nanoparticle, preferably suitable average diameter is the nanoparticle below 150nm, for example, the particle with amine group is preferably used as nanoparticle.For example, above-mentioned primer layer can be formed by being suitable for the adhesion improver made by the CZ series etc. of MEC company.

[0161] In the seed layer / primer layer 21c, the conductive layer can selectively form a metal layer with or without removing the portion where the conductive layer is not required to be formed. In addition, the seed layer / primer layer 21c selectively processes the portion where the conductive layer is required to be formed or the portion where the conductive layer is not required to be formed into an activated state or an inactivated state for metal plating to carry out subsequent processes. For example, the activation or inactivation treatment can use a light irradiation treatment or chemical treatment with a laser having a predetermined wavelength. When forming the metal layer, a copper plating method suitable for manufacturing semiconductor devices can be used, but the present invention is not limited thereto.

[0162] like Figure 4 As shown in part (e), when a portion of the core distribution layer is not needed, it can be removed, or metal plating can be performed after partially removing or inactivating the seed layer to form a conductive layer in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0163] Figure 5A preparation step of forming an insulating layer and an upper distribution pattern according to an embodiment is described.

[0164] like Figure 5 As shown in part (a), after forming the core distribution layer as the above-mentioned conductive layer, the core through hole can be subjected to an insulating layer forming step of filling the empty space with an insulating layer. At this time, the insulating layer applied can be an insulating layer prepared in the form of a film, for example, it can be applied by a method of decompressing and laminating an insulating layer in the form of a film, etc. When decompressing and laminating in this way, the insulating layer is fully embedded in the empty space inside the above-mentioned core through hole to form a core insulating layer without voids.

[0165] Figure 5 Parts (b) to (e) of FIG. 1 illustrate the upper layer preparation steps.

[0166] The upper layer preparation step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer 23a or by stacking insulating films. Simply, it is preferred to stack insulating films. The stacking of insulating films can be performed by laminating insulating films and curing. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully embedded in a layer where no conductive layer is formed inside the core through hole. At least a portion of the above-mentioned upper insulating layer is also in direct contact with the glass core, so a layer with sufficient adhesion is suitable. Specifically, the above-mentioned glass core and the above-mentioned upper insulating layer preferably have a property that the adhesion test value according to ASTM D3359 meets 4B or above.

[0167] The upper distribution pattern can be formed by repeatedly forming the above-mentioned insulating layer 23a and forming the conductive layer 23c in a predetermined pattern and etching the unnecessary part to form the etching layer 23d of the conductive layer. In the case of the conductive layer formed adjacently across the insulating layer, it can be formed by forming the blind hole 23b in the insulating layer and then performing a plating process. The blind hole can be formed by a dry etching method such as laser etching and plasma etching, a wet etching method using a mask layer and an etching solution, etc.

[0168] Thereafter, although not shown in the drawings, an upper surface connection layer and a cover layer may be formed.

[0169] The upper surface connection pattern and the upper surface connection electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etching layer of the insulating layer on the insulating layer 23e, and then forming a conductive layer thereon, and then forming an etching layer of the conductive layer, but it can also be formed by only selectively forming the conductive layer without using an etching method. An opening portion (not shown in the figure) is formed at a position of the covering layer corresponding to the upper surface connection electrode, and can be formed so that the upper surface connection electrode is exposed and directly connected to the device connection portion or the terminal of the device.

[0170] Once the upper layer is produced, the lower layer process can be carried out by forming the lower surface connection layer and the cover layer. The lower distribution layer and / or the lower surface connection layer can be formed in a similar manner to the upper surface connection layer and cover layer formation steps described above, and optionally, a cover layer (not shown) can also be formed.

[0171] On the other hand, as described above, the core layer may include a glass core, and the glass core may include a glass substrate having a first surface and a second surface facing each other. In addition, as described above, the glass core may include a cavity portion. The cavity portion is open and recessed in the direction of the first surface or the second surface, or has a space for arranging an electric device that passes through the glass core.

[0172] The cavity portion may be open and recessed in the direction of the first surface or the second surface of the glass core, or may have an internal space that penetrates the glass core and accommodates the electrical device. The cavity portion having an internal space that is open and recessed in the direction of the first surface or the second surface is called a half cavity, and the cavity portion that penetrates the glass core and has an internal space is called a full cavity. The electronic device may be arranged in the internal space of the cavity portion.

[0173] On the other hand, the following method has been used in the past to produce a glass core having a semi-cavity.

[0174] One example of a prior art for making a semi-cavity is a method using a sheet of glass. A method of selectively irradiating energy to a predetermined portion of the glass and removing a portion of the glass by mechanical removal and / or chemical etching to generate a semi-cavity can be used. In this case, a tapered zone with gradually narrowing intervals may appear at the edge of the cavity, and the margin area may increase. Therefore, problems such as a reduction in the device space in which electronic devices can be installed in the cavity may occur.

[0175] As another example of the prior art for manufacturing a semi-cavity, a method for producing a glass core with a semi-cavity by stacking glass with a full cavity and bottom glass can be used. In this case, when the process of forming electrodes in the through holes of the above-mentioned glass core or the lamination process for forming a distribution layer is repeatedly applied, the heating / cooling process is repeated, so that the stacked glass is prone to delamination. This delamination problem also occurs even when a polymer adhesive for bonding glass is applied alone. In addition, a core through hole is first generated in the bottom glass, and then when the bottom glass and the glass with the above-mentioned full cavity are stacked, there may be the trouble of needing to accurately align the glass with the above-mentioned full cavity and the above-mentioned bottom glass. Therefore, the present specification proposes an embodiment of manufacturing a semi-cavity for solving the above-mentioned problems.

[0176] Figure 6 FIG. 1 is a cross-sectional flow chart illustrating a process of producing a glass core having a semi-cavity according to the present embodiment. Figure 6 The present invention discloses a method for manufacturing a package substrate. Specifically, the present invention discloses a method for producing a glass core having a semi-cavity.

[0177] The manufacturing method of the packaging substrate of the present embodiment includes the following steps to form a glass core: a primary core forming step of forming a primary core by bonding a first glass having a through cavity and a second glass; and an etching step of forming a plurality of core through holes by etching the primary core.

[0178] In the primary core forming step, for example, a primary core is formed by bonding a sheet of glass (first glass) having a full cavity to another sheet of glass (second glass). At this time, bonding may be performed by anode bonding. The second glass may have a concave surface, and in the bonding step, the second glass may not have a concave surface.

[0179] Then, an etching step may be performed. That is, a plurality of core through holes may be formed by etching the primary core. If the core through holes are formed after bonding in this manner, it is not necessary to precisely bond the position of each formed core through hole, thereby improving process efficiency.

[0180] Etching can be performed by generating defects in the glass of the primary core and utilizing the difference in etching speed. For example, the formation of the above defects can be achieved by laser irradiation, etc., but is not limited thereto. Etching can be performed by forming defects at the position where the core through hole is to be formed and immersing the primary core in an etching solution.

[0181] The etching solution can not only etch the defective region, but also etch the surface of the primary core where no defect is formed. Therefore, the thickness of the glass core can be thinner than the thickness of the primary core.

[0182] The glass core thus formed has a first surface and a second surface facing each other, the core through hole is open in the direction of the first surface and an internal space is arranged in the recessed surface, and the core through hole penetrates the glass core in the thickness direction. Since the core through hole will be described in detail below, its description is omitted here.

[0183] Reference Figure 6 In part (a), the first glass 61 has a cavity portion penetrating the first glass 61.

[0184] Reference Figure 6 The first glass 61 and the second glass 62 are bonded in the (b) part. Anodic bonding can be used for bonding. A primary core is obtained by this process. Anodic bonding will be described below.

[0185] The first glass 61 formed with the full cavity is called cavity glass. If the glass formed with the cavity is used as the first glass, the efficiency of the etching step can be further improved.

[0186] The second glass 62 may be glass without a cavity. The second glass 62 may be bare glass.

[0187] The first glass 61 and the second glass 62 may be flat glass suitable for semiconductor processes. In addition, it is preferred that the first glass 61 and the second glass 62 are flat glass having the following properties.

[0188] At least one of the first glass 61 and the second glass 62 may have a Na2O3 content of 2.5 wt% or more, 3 wt% or more, or 3.5 wt% or more. In addition, the Na2O3 content in the glass may be 6 wt% or less. When the glass having the above-mentioned Na2O3 content is applied to at least one of the first glass 61 and the second glass 62, anodic bonding can be easily applied.

[0189] The maximum use temperature of each of the first glass 61 and the second glass 62 may be 240° C. or higher, 250° C. or higher, 260° C. or higher, 280° C. or higher, or 300° C. or higher, and the maximum use temperature may be 600° C. or lower, 580° C. or lower, or 560° C. or lower. In this case, sufficient thermal durability can be achieved during manufacturing and driving processes.

[0190] Preferably, the first glass 61 and the second glass 62 have substantially the same or slightly different linear thermal expansion coefficients (line thermal expansion coefficient α, temperature unit: ° C). The linear thermal expansion coefficient may be 2.8*10E -6 Up to 4.5*10E -6 or 3*10E -6 Up to 4*10E -6 .

[0191] Preferably, the first glass 61 and the second glass 62 have excellent chemical resistance. Specifically, when immersed in a 10 wt % hydrofluoric acid solution at 23° C. for 20 minutes, the chemical resistance per unit area (cm 2 ) can be 2 mg or less or 1.5 mg or less. Specifically, when immersed in a 5 wt% sodium hydroxide solution at 95°C for 6 hours, the weight loss per unit area (cm 2 ) can be less than 0.5 mg or less than 0.3 mg.

[0192] The thermal diffusivity of at least one of the first glass 61 and the second glass 62 may be 0.02 cm 2 / sec or less or 0.01cm 2 / sec or less. The thermal diffusivity can be 0.0001cm 2 When using glass with low thermal diffusivity, it can help to apply the bonding process more smoothly.

[0193] For example, at least one of the first glass 61 and the second glass 62 may be Corning 7740 (Pyrex), Schott Glass Borofloat, etc., but is not limited thereto.

[0194] The glass core 21 formed by bonding the first glass 61 and the second glass 62 by anodic bonding or the like may have a bonding interface of the first glass 61 and the second glass 62. When the anodic bonding or the like is used, the bonding strength at the bonding interface is strong and the peeling problem at the interface can be substantially prevented.

[0195] Reference Figure 6 In part (c), a plurality of core through holes can be formed in the primary core by applying mechanical etching and / or chemical etching methods. In particular, in the case of the chemical etching method, a relatively large area can be etched at the same time, thereby improving process efficiency.

[0196] Chemical etching is a process of forming defects in the primary core by laser irradiation or the like, and then applying an etching solution to the primary core to form a core through hole of a predetermined shape and size by a difference in etching speed. Thus, a glass core 21 having a plurality of core through holes penetrating in the thickness direction can be manufactured. In addition, the upper surface of the second glass corresponding to the bottom surface of the cavity of the primary core can also be etched by the above etching. The specific shape of the glass core will be described below.

[0197] The anodic bonding process is a bonding process for sealing glass without introducing an intermediate layer such as a polymer bonding composition.

[0198] At the interface, molecular bonds of Si and O respectively located in the first glass and the second glass are induced, thereby generating a relatively strong interface bonding force, so that even after repeated high-temperature processes that may be applied in the process of forming the glass core or the packaging substrate, the bonding force can be sufficiently maintained and the reliability of the product can be substantially maintained. The problem of delamination of the glass of the glass core 21 at the interface can be substantially prevented.

[0199] That is, the glass core 21 includes molecular bonds of Si and O at the interface between the first glass 61 and the second glass 62. This may be induced by an anodic bonding process.

[0200] The anodic bonding process is a process that uses electricity, heat and pressure to bond the interface of stacked materials. The above process can be applied to equipment such as SB-6E Bonder or EVG 520IS, but is not limited to this. The anodic bonding process can be carried out as follows. 1) The flattened and cleaned surfaces to be bonded are arranged in contact. In this embodiment, a stack of the first glass and the second glass is prepared to be arranged in contact. 2) The temperature of the stack is increased and a voltage is applied. Exemplarily, the temperature can be 180°C to 500°C, but can be adjusted according to the characteristics of the glass. In addition, a voltage of 200V to 1000V can be applied. The voltage is a DC voltage. At the above temperature and voltage, the glass is activated and charges such as sodium ions move according to the voltage. At this time, the metal atoms (for example, silicon) on the surface of the other glass can meet with the oxygen atoms in the activated glass to form interatomic bonds, and a strong bonding effect can be obtained by forming a metal oxide at the interface. In addition, since no separate polymer bonding layer is applied, it is essentially impossible for particles and other problems to occur in the semiconductor manufacturing process. Furthermore, since the metal oxide formed at the interface by anodic bonding substantially overlaps with the constituent components of the glass, the existing process can be easily applied when forming a through hole or the like in the etching step.

[0201] The shape of the glass core formed by the etching step will be described.

[0202] For example, Figure 6 As shown in part (c) of FIG. 1 , the glass core 21 has a first surface and a second surface facing each other. The glass core 21 includes a plurality of core through holes 23 penetrating the glass core 21 in the thickness direction. The glass core 21 is provided with a cavity 28, the surface of which is recessed in a manner opening in the direction of the first surface and having an internal space.

[0203] The core through hole may include a first opening portion connected to the first surface of the glass core 21; a second opening portion connected to the second surface; and a minimum inner diameter portion, which is a region with the narrowest inner diameter in the entire core through hole connecting the first opening portion and the second opening portion. The glass core 21 may also include a first core through hole and a second core through hole having different arrangement heights of the minimum inner diameter portion.

[0204] When viewed from the upper surface side of the glass core 21 , the second region of the glass core 21 is a region of the glass core 21 where the cavity 28 is disposed, and the first region of the glass core 21 is a region of the glass core 21 where the cavity 28 is not disposed.

[0205] The first core through hole is a core through hole arranged in the first region, and the second core through hole is a core through hole arranged in the second region.

[0206] The smallest inner diameter portion of the first core through hole is arranged at a first position, and the smallest inner diameter portion of the second core through hole is arranged at a second position.

[0207] With the second surface as a reference, a height of a minimum inner diameter portion of the first core through hole may be higher than a height of a minimum inner diameter portion of the second core through hole.

[0208] In addition, if Figure 6 As shown in part (c) of FIG. 2 , when a cross section of the glass core 21 is viewed in a thickness direction, the inner space of the cavity 28 of the glass core 21 may have a hexagonal shape.

[0209] The lower surface of the semi-cavity of the cavity portion 28 of the glass core 21 may be located on or inside the second glass.

[0210] The second glass may have a concave surface.

[0211] In the cavity 28 of the glass core 21, the side wall angle of the through cavity of the first glass and the side wall angle of the concave surface of the second glass may be different from each other. Specifically, the side wall angle of the through cavity of the first glass based on the lower surface of the second glass may be greater than the side wall angle of the concave surface of the second glass.

[0212] For example, when observing the cross section in the thickness direction of the glass core 21, the internal space of the above-mentioned cavity portion may include a first interval 283 and a second interval 284, and the wall surface angle of the above-mentioned first interval 283 is approximately 89 degrees to 90 degrees based on the above-mentioned first surface or the above-mentioned second surface, and the wall surface angle of the above-mentioned second interval 284 is more inclined than the above-mentioned first interval based on the above-mentioned first surface or the above-mentioned second surface.

[0213] As described above, if the angles of the cavity side walls of the first region 283 and the second region 284 are different, the overall angle of the cavity side walls can be closer to 90 degrees, which is beneficial for forming tolerances during the pick and place process of arranging electronic devices while maintaining device margins, and the space in which the electronic devices can move after the pick and place process is smaller, thereby preventing the electronic devices from deviating from the specified arrangement position.

[0214] In addition, if Figure 6 As shown in part (c) of FIG. 1 , in a package substrate according to one or more embodiments, the core layer includes: a glass core 21 having a first surface and a second surface facing each other; a cavity portion 28, which is recessed in a manner of opening in the direction of the first surface and has an internal space; and a plurality of core through holes 23, which penetrate the glass core 21 in the thickness direction, and the glass core 21 includes a first glass 61 and a second glass 62 stacked up and down. The first glass 61 includes a through cavity.

[0215] When viewed from the upper surface side of the glass core 21, the second region of the glass core 21 is a region in which the cavity 28 is arranged in the glass core 21, and the second glass 62 has a concave surface. The side wall surface of the through cavity of the first glass 61 and the side wall surface of the concave surface of the second glass 62 may be connected. When a cross section is viewed in the thickness direction of the glass core 21, the internal space of the cavity may have a hexagonal shape. Specifically, the opening may be regarded as a straight line, and the outline surrounded by the glass core may have a substantially hexagonal shape.

[0216] When the cross section is observed in the thickness direction of the glass core 21, the inner space of the cavity may include a first region 283 that is recessed at a certain interval in the thickness direction and a second region 284 that is recessed at a gradually narrowing interval in the thickness direction. That is, when the cross section is observed in the thickness direction of the glass core 21, the cavity may have a hexagonal inner space with the contact point contacting the first surface, the inflection point connecting the first region 283 and the second region 284, and the contact point contacting the bottom surface of the cavity as vertices.

[0217] For example, when observing the cross section in the thickness direction of the glass core 21, the bonding interface between the first glass 61 and the second glass 62 may be formed at the position where the inflection point is located. The first glass 61 may include the first section 283 of the inner space of the cavity portion, and the second glass 62 may include the second section 284 of the inner space of the cavity portion.

[0218] The electronic device may be arranged in the inner space of the cavity portion 28. The electronic device 40 may be inserted and arranged in the inner space of the cavity portion 28.

[0219] For example, electronic devices may be selected and arranged in the internal space of the above-mentioned cavity portion (designation of the position of the electronic device). In addition, a device group including a plurality of electronic devices embedded between insulator layers (electronic device insulating layers) may be formed in a manner that exposes electrodes and then inserted into the internal space of the cavity portion. The above-mentioned electronic device 40 may include active devices such as transistors or power transmission devices such as multilayer ceramic capacitors (MLCCs), i.e., passive devices.

[0220] The lower part of the cavity portion formed in the glass core according to the above embodiment, that is, the second region 284 recessed in a manner that the pitch gradually narrows in the thickness direction can maintain the device margin, so it is beneficial to form a tolerance in the pick & place process of arranging electronic devices, and the space where the electronic devices can move after the pick & place process is small, so that the problem of the electronic devices deviating from the designated arrangement position can be prevented. In addition, when the two glasses forming the glass core are bonded, no alignment mismatch occurs, so it is also advantageous in the PVD process, etc., and because bare glass is used, there is an advantage that one process step can be reduced compared with the existing method of producing a glass core with a semi-cavity.

[0221] Figure 7 FIG. 2 is a schematic diagram illustrating a core layer including a glass core having a semi-hollow cavity produced according to the present embodiment in cross section. For example, the embodiment of the glass core having a semi-hollow cavity proposed in the present specification can be described as follows.

[0222] Reference Figure 7 The core layer 22 includes: a glass core 21 having a first surface and a second surface facing each other; a cavity portion 28 recessed in a manner opening in the direction of the first surface or the second surface; and a plurality of core through holes 23 penetrating the glass core 21 in the thickness direction.

[0223] For example, the glass core 21 having a first surface and a second surface facing each other in the core layer 22 may include a first region having a first thickness and a second region for providing the above-mentioned cavity portion and having a second thickness less than the above-mentioned first thickness. For example, the above-mentioned first thickness may be 400 μm or more, 500 μm or more, 600 μm or more, or 700 μm or more. The above-mentioned first thickness may be 1500 μm or less, 1400 μm or less, 1300 μm or less, 1200 μm or less, 1100 μm or less, or 1000 μm or less. The above-mentioned second thickness may be 200 μm or more, 300 μm or more, 400 μm or more, or 500 μm or more. The above-mentioned second thickness may be less than the above-mentioned first thickness. In this case, a glass core with reduced occurrence of warping of the core layer, etc. may be prepared.

[0224] The specific description about the characteristics of the cavity portion, the characteristics of the core hole, etc. is repeated in the above description, so the detailed description will be omitted.

[0225] The inflection point where the side wall surface of the cavity portion adjoining the first surface of the glass core intersects is referred to as a first vertex 73 , and the inflection point where the bottom surface of the cavity portion and the side wall surface intersect is referred to as a second vertex 74 .

[0226] The taper angle of the side wall of the cavity can be measured as follows: The taper angle is the angle between an imaginary line passing through the first vertex 73 and the second vertex 74 based on the second surface of the glass core and an imaginary line of the second surface perpendicular to the imaginary line.

[0227] The side wall taper angle of this embodiment may be 87 to 90 degrees, 88 to 90 degrees, or 89 to 90 degrees. The cavity portion having such an angle can substantially reduce the gap between the side wall surface and the electronic device inserted into the cavity portion.

[0228] Figure 8 FIG. 2 is a schematic diagram illustrating the structure of a package substrate produced according to the present embodiment in cross section. Figure 8 When describing the package substrate of this embodiment, the package substrate has Figure 6 Part (c) and Figure 7 Features described in .

[0229] In the above-mentioned package substrate 20, the electronic device 30 can be arranged in the cavity portion. The above-mentioned electronic device can be connected up and down through a conductive layer, which passes through the inside of the core through hole and is connected to the lower end of the package substrate. In the internal space of the cavity, the empty area other than the area where the cavity device and the conductive layer are arranged can be filled with an insulating material.

[0230] The package substrate 20 has a core layer 22, which includes a conductive layer arranged on a glass core 21, and the core layer has the above-mentioned characteristics. In addition, the package substrate 20 includes an upper layer 26, which is arranged on the upper part of the core layer, and is arranged with a conductive layer of a predetermined pattern and an insulating material surrounding the conductive layer, and a cover layer 60 is arranged above it. The package substrate 20 may also include a lower layer 29, which is arranged on the lower part of the core layer, and is arranged with a conductive layer of a predetermined pattern and an insulating material surrounding the conductive layer, and a cover layer 60 is arranged below it, and a connection portion 50 such as a solder ball is also arranged.

[0231] In one or more embodiments, reference Figure 7 and Figure 8 The packaging substrate 20 includes a core layer 22, which includes: a glass core 21 having a first surface and a second surface facing each other; and a plurality of core through holes 23 penetrating the glass core along a thickness direction.

[0232] The glass core 21 includes a first glass and a second glass stacked up and down, and the interface between the first glass and the second glass can be bonded by forming a chemical structure of Si-O-Si or O-Si-O structure. The chemical structure can be induced by the anodic bonding or the like. In the glass core 21, O of the first glass and Si / Si of the second glass are bonded to form a Si-O-Si structure, so that a Si-O-Si structure can be formed at the interface. In the glass core 21, Si / Si of the first glass and O of the second glass are bonded to form an O-Si-O structure, so that an O-Si-O structure can be formed at the interface. Although the anodic bonding is described based on Si, metal atoms contained in the glass, i.e., Al or the like, can also be bonded with O to form an interface bonding structure.

[0233] The glass core 21 may not substantially include a polymer adhesive layer at an interface between the first glass and the second glass.

[0234] The first glass may include a through cavity.

[0235] The glass core may further include a cavity portion 28 , the surface of which is recessed so as to be open in the direction of the first surface and has an internal space.

[0236] The above-mentioned glass core, cavity portion, upper layer, lower layer and specific features respectively included therein are repeated in the above description, and thus their description will be omitted.

[0237] The method for manufacturing a packaging substrate and the packaging substrate using the same according to the above-described embodiment can enhance the bonding force between glasses forming a glass core having a semi-cavity, and can prevent the problem of glass delamination forming the glass core even after multiple high-temperature processes.

[0238] In addition, a cavity portion including a lower section that is recessed in a manner such that the spacing gradually narrows from a specific inflection point in the thickness direction can be formed in the glass core, thereby achieving the following effect, namely, the device margin can be maintained, which is beneficial for forming a tolerance during the pick and place process of arranging electronic devices, and the space in which the electronic devices can move after the pick and place process is smaller, thereby preventing the electronic devices from deviating from the specified arrangement position.

[0239] Above, this specification is described with reference to the embodiments illustrated in the accompanying drawings, but this is only an example. As long as a person skilled in the art will understand, various modifications and equivalent other embodiments can be derived from this. In other words, the scope of this specification is not limited to the above-mentioned embodiments, but various changes or modifications of the basic concepts of the embodiments defined in the attached claims by those skilled in the art belong to the scope of the embodiments. Therefore, the true technical protection scope of this specification should be determined according to the technical ideas of the attached claims.

Claims

1. A packaging substrate, characterized in that: Including the core layer, The core layer comprises: a glass core having a first surface and a second surface facing each other, a cavity portion whose surface is recessed in a manner opening in the direction of the first surface and having an internal space, and A plurality of core through holes penetrating the glass core in a thickness direction; The core through hole includes: a first opening connected to the first surface; a second opening connected to the second surface; and a minimum inner diameter portion, which is a region with the narrowest inner diameter in the entire core through hole connecting the first opening and the second opening; The core through-holes include a first core through-hole and a second core through-hole having different arrangement heights of the minimum inner diameter portion.

2. The packaging substrate according to claim 1, characterized in that: When viewed from the upper surface side of the glass core, the second region of the glass core is a region in which the cavity portion is arranged in the glass core, and the first region of the glass core is a region in which the cavity portion is not arranged in the glass core. The first core through hole is arranged in the first region and the smallest inner diameter portion is arranged at a first position, the second core through hole is arranged in the second region and the smallest inner diameter portion is arranged at a second position, With the second surface as a reference, a height of a minimum inner diameter portion of the first core through hole is higher than a height of a minimum inner diameter portion of the second core through hole.

3. The packaging substrate according to claim 1, characterized in that: The glass core comprises a first glass and a second glass stacked up and down. The first glass includes a through cavity, A bonding interface is provided between the lower surface of the first glass and the upper surface of the second glass.

4. The packaging substrate according to claim 3, characterized in that: The second glass has a concave surface, The side wall angle of the through cavity of the first glass and the side wall angle of the concave surface of the second glass are different from each other.

5. The packaging substrate according to claim 1, characterized in that: The electronic components are arranged in the inner space of the cavity. The above-mentioned electronic devices include active devices.

6. A packaging substrate, characterized in that: Including the core layer, The core layer comprises: a glass core having a first surface and a second surface facing each other, a cavity portion whose surface is recessed in a manner opening in the direction of the first surface and having an internal space, and A plurality of core through holes, penetrating the glass core in a thickness direction; The glass core comprises a first glass and a second glass stacked up and down. The first glass includes a through cavity, When viewed from the upper surface side of the glass core, the second region of the glass core is a region of the glass core where the cavity portion is arranged. The second glass has a concave surface, The side wall surface of the through cavity of the first glass is connected to the side wall surface of the concave surface of the second glass, When a cross section is viewed in a thickness direction of the glass core, an internal space of the cavity has a hexagonal shape.

7. The packaging substrate according to claim 6, characterized in that: When observing the cross section in the thickness direction of the glass core, the cavity portion is divided into a first section and a second section, the first section is a region arranged parallel to the first glass, and the second section is a region arranged parallel to the second glass. The width of the cavity portion in the second section is narrower than the width of the cavity portion in the first section.

8. The packaging substrate according to claim 6, characterized in that: The taper angle of the side wall of the cavity portion is 87 degrees to 90 degrees.

9. A method for manufacturing a packaging substrate, characterized in that: include: a primary core forming step of forming a primary core by bonding a first glass having a through cavity and a second glass, and an etching step of forming a plurality of core through holes by etching the primary core; A glass core is formed by the primary core forming step and the etching step. The glass core has a first surface and a second surface facing each other, The glass core has an inner space arranged in a surface that is open and recessed in the direction of the first surface. The core through hole penetrates the glass core in the thickness direction. The core through hole includes: a first opening portion connected to the first surface; a second opening portion connected to the second surface; and a minimum inner diameter portion, which is a region with the narrowest inner diameter in the entire core through hole connecting the first opening portion and the second opening portion. The core through-holes include a first core through-hole and a second core through-hole having different arrangement heights of the minimum inner diameter portion.

10. The method for manufacturing a packaging substrate according to claim 9, wherein: When viewed from the upper surface side of the glass core, the second region of the glass core is a region of the glass core where the cavity portion is arranged. The second glass has a concave surface, The side wall surface of the through cavity of the first glass is connected to the side wall surface of the concave surface of the second glass, When a cross section is viewed in a thickness direction of the glass core, an internal space of the cavity has a hexagonal shape.

11. The method for manufacturing a packaging substrate according to claim 9, wherein: The bonding in the above-mentioned primary core forming step is achieved by anodic bonding.

Images