Electronic package and fabrication method thereof

Abstract

An electronic package and a method of fabricating the same are provided, including respectively disposing a photoelectric chip and an electronic integrated circuit chip on both sides of an interposer, such that the photoelectric chip and the electronic integrated circuit chip can be in signal connection with each other directly through a plurality of conductive vias in the interposer. Therefore, power consumed by signal transmission between lines and transmission delay caused by the signal transmission between the lines are reduced.

Description

Technical Field

[0001] The present invention relates to an electronic packaging technology, in particular to an electronic packaging component integrating optoelectronic components and a manufacturing method thereof. Background Art

[0002] In response to the increasing importance and widespread application of high performance computing (HPC) technology in today's world life, such as the development of medical technology, such as the development of cancer drugs or the automatic sensing detection calculation of self-driving cars, the traffic of data processing centers has also increased in order to be applied to the aforementioned technology fields. In order to solve the pressure of data centers, silicon photonic solutions combined with various advanced packaging technologies have emerged.

[0003] At present, the internal optical communication of the Data Center mainly relies on pluggable devices as the interface of the optical fiber connection to realize the photoelectric or electro-optical conversion between the transmitter and the receiver. In the internal architecture of the Data Center, all switches, routers and nodes basically need to be installed with pluggable devices. For large Data Centers, the number of pluggable devices required to be deployed is also very large, which also brings a heavy burden and increases transmission delay and power consumption. More importantly, if the rate is required to reach 1.6Tb / s, 3.2Tb / s or even higher transmission rates in the future, pluggable devices will also be subject to performance limitations.

[0004] To solve this problem, the industry has discovered a way to combine optical components and electronic components into the same package through co-packaged optics (CPO) technology. Figure 1 As shown, it mainly packages an optoelectronic chip (Photo IC, PIC) 11 integrating a digital signal processor (DSP) together with an electronic integrated circuit (EIC) chip 12 on a substrate 13 to form a package module 1a which is then placed on a motherboard 14. This integration method is expected to overcome the challenges of pluggable devices and bring better performance for high-speed data transmission.

[0005] However, the aforementioned co-packaged optical structure still has problems such as insufficient transmission speed (the signal transmission between PIC / DSP and EIC still needs to be transmitted through the circuit layer on the same side of the substrate) and the high heat generated by signal processing cannot be solved. Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0006] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, including: an interposer having a first surface and a second surface opposite to each other and a plurality of conductive through-holes; an optoelectronic chip connected to the first surface of the interposer and electrically connected to the plurality of conductive through-holes; and an electronic integrated circuit chip connected to the second surface of the interposer and electrically connected to the plurality of conductive through-holes.

[0007] The present invention also provides a method for manufacturing an electronic package, comprising: providing an optoelectronic chip, an electronic integrated circuit chip and an intermediate board, wherein the intermediate board has a first surface and a second surface opposite to each other and a plurality of conductive through-holes; placing the optoelectronic chip on the first surface of the intermediate board and electrically connecting the plurality of conductive through-holes; and placing the electronic integrated circuit chip on the second surface of the intermediate board and electrically connecting the plurality of conductive through-holes.

[0008] In the aforementioned electronic package and its manufacturing method, the optoelectronic chip has a first active surface and a first inactive surface opposite to each other, the first active surface is provided with a plurality of first connection pads and at least one connection portion, and a plurality of first conductive bumps are provided on the plurality of first connection pads.

[0009] In the aforementioned electronic package and its manufacturing method, the electronic integrated circuit chip has a second active surface and a second inactive surface opposite to each other, the second active surface is provided with a plurality of second connection pads, and a plurality of second conductive bumps are provided on the plurality of second connection pads.

[0010] In the aforementioned electronic package and its manufacturing method, the first surface of the interposer is provided with a first circuit structure electrically connected to the conductive through-holes, and / or the second surface is provided with a second circuit structure electrically connected to the conductive through-holes.

[0011] In the aforementioned electronic package and the manufacturing method thereof, a heat dissipation layer is formed on the first surface and / or the second surface of the intermediate board.

[0012] The aforementioned electronic package and its manufacturing method also include a plurality of conductive elements disposed on the second surface of the intermediate board and a substrate combined with the plurality of conductive elements.

[0013] In the aforementioned electronic package and its manufacturing method, the substrate is provided with a recessed portion for accommodating the electronic integrated circuit chip located on the second surface of the interposer.

[0014] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly allow the optoelectronic chip and the electronic integrated circuit chip to directly connect the signals through the multiple conductive through-holes of the intermediate board, and the distance between the two is relatively close, which can effectively reduce the power consumed by the signal transmission between the lines and the transmission delay caused, and successfully achieve the performance of increasing the transmission rate. In addition, because a heat dissipation layer is provided on the surface of the intermediate board, the heat of the chip is conducted through the structural design of the whole metal piece through the material characteristics of the metal itself, thereby improving the heat dissipation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a cross-sectional schematic diagram of an existing co-packaged optical structure.

[0016] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.

[0017] Figure 2B-1 for Figure 2A A partial top view of the diagram.

[0018] Description of Reference Numerals

[0019] 1a Package module

[0020] 11 Optoelectronic Chip

[0021] 12 Electronic integrated circuit chips

[0022] 13 substrate

[0023] 14 Motherboard

[0024] 2 Electronic packaging

[0025] 20 Intermediary board

[0026] 20a First surface

[0027] 20b Second surface

[0028] 200 Conductive perforation

[0029] 201 First Line Structure

[0030] 2011 First Insulation Layer

[0031] 2012 First line redistribution layer

[0032] 2013 First electrical contact pad

[0033] 202 Second Line Structure

[0034] 2021 Second insulation layer

[0035] 2022 Second line redistribution layer

[0036] 2023 Second electrical contact pad

[0037] 203 heat dissipation layer

[0038] 21 Optoelectronic Chip

[0039] 21a First working surface

[0040] 21b First non-active surface

[0041] 211 First connection pad

[0042] 212 Connection

[0043] 213 first conductive bump

[0044] 214 First Primer

[0045] 22 Electronic integrated circuit chips

[0046] 22a Second working surface

[0047] 22b Second non-active surface

[0048] 221 Second connection pad

[0049] 223 second conductive bump

[0050] 224 Second primer

[0051] 24 Conductive elements

[0052] 25 substrate

[0053] 250 recess. DETAILED DESCRIPTION

[0054] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0055] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "one", "two", "first", "second", "third", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0056] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0057] like Figure 2A As shown, at least one first electronic component and at least one second electronic component are provided. The first electronic component is, for example, a photoelectric chip (Photo IC, PIC) 21, which has a first active surface 21a and a first inactive surface 21b opposite to each other, wherein the first active surface 21a is provided with a plurality of first connection pads 211 and at least one connection portion 212, and a plurality of first conductive bumps 213 are provided on the plurality of first connection pads 211, and the connection portion 212 is, for example, an optical fiber connection portion, which can be a connection point for connecting an optical fiber or an optical fiber cable. The second electronic component is, for example, an electronic integrated circuit chip (EIC, EIC) 22, which has a second active surface 22a and a second inactive surface 22b opposite to each other, wherein the second active surface 22a is provided with a plurality of second connection pads 221, and a plurality of second conductive bumps 223 are provided on the plurality of second connection pads 221. The first conductive bump 213 and the second conductive bump 223 are, for example, spherical solder balls, or pillars made of metal materials such as copper pillars and solder bumps, or stud conductive parts made by a wire bonding machine, but are not limited thereto.

[0058] like Figure 2B As shown, an interposer 20 having a plurality of conductive through-holes 200 is provided, and the interposer 20 has a first surface 20a and a second surface 20b opposite to each other, so that the conductive through-holes 200 connect the first surface 20a and the second surface 20b. The interposer 20 is made of a material containing silicon or organic polymer, preferably silicon.

[0059] In addition, a first circuit structure 201 electrically connected to the conductive through-vias 200 may be disposed on the first surface 20 a of the interposer 20 , and a second circuit structure 202 electrically connected to the conductive through-vias 200 may be disposed on the second surface 20 b of the interposer 20 .

[0060] The first circuit structure 201 includes at least one (or more) first insulating layers 2011 and at least one (or more) first redistribution layers (RDL) 2012 disposed on the first insulating layers 2011, and the outermost first redistribution layer 2012 is formed with a plurality of first electrical contact pads 2013. The second circuit structure 202 includes at least one (or more) second insulating layers 2021 and at least one (or more) second redistribution layers 2022 disposed on the second insulating layers 2021, and the outermost second redistribution layer 2022 is formed with a plurality of second electrical contact pads 2023. In one embodiment, the material forming the first circuit redistribution layer 2012 or the second circuit redistribution layer 2022 is copper, and the material forming the first insulating layer 2011 or the second insulating layer 2021 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., or a solder mask material such as green paint, ink, etc.

[0061] Please also see Figure 2B-1 , and a heat dissipation layer 203 is formed on the first surface 20a of the interposer 20. In this embodiment, a heat dissipation layer 203 adjacent to the plurality of first electrical contact pads 2013 is provided on the outermost first insulating layer 2011 of the first circuit structure 201. The material of the heat dissipation layer 203 can be the same as that of the plurality of first electrical contact pads 2013 and can be made at the same time, but it is not in contact with or electrically connected to the plurality of first electrical contact pads 2013. Alternatively, the heat dissipation layer 203 can be provided on the second surface 20b of the interposer 20, or the heat dissipation layer 203 can be provided on both the first surface 20a and the second surface 20b of the interposer 20, so that the heat dissipation efficiency of the chip subsequently connected to the interposer 20 can be improved by the provision of the heat dissipation layer 203.

[0062] In addition, it should be noted that in other embodiments, the first circuit structure 201 may be omitted, and a plurality of first electrical contact pads 2013 directly electrically connected (contacting) the plurality of conductive through-holes 200 and the heat dissipation layer 203 spaced apart from each other may be provided on the first surface 20a of the intermediate board 20; the second circuit structure 202 may also be omitted, and a plurality of second electrical contact pads 2023 directly electrically connected (contacting) the plurality of conductive through-holes 200 may be provided on the second surface 20b of the intermediate board 20.

[0063] like Figure 2C As shown, the optoelectronic chip 21 is placed on the first surface 20a of the interposer 20 and electrically connected to the multiple conductive through-holes 200, and the electronic integrated circuit chip 22 is placed on the second surface 20b of the interposer 20 and electrically connected to the multiple conductive through-holes 200, so that the optoelectronic chip 21 and the electronic integrated circuit chip 22 can achieve signal interconnection with each other through the multiple conductive through-holes 200 of the interposer.

[0064] In this embodiment, the optoelectronic chip 21 is connected to the first electrical contact pads 2013 through the first conductive bumps 213, and a first underfill 214 is formed between the optoelectronic chip 21 and the first circuit structure 201 to cover the first conductive bumps 213. The electronic integrated circuit chip 22 is connected to the second electrical contact pads 2023 through the second conductive bumps 223, and a second underfill 224 is formed between the electronic integrated circuit chip 22 and the second circuit structure 202 to cover the second conductive bumps 223.

[0065] like Figure 2D As shown, a plurality of conductive elements 24 (such as copper pillars or solder balls) are then implanted on the second surface 20b of the interposer 20, that is, a plurality of conductive elements 24 can be set on the plurality of second electrical contact pads 2023 for connection to a substrate 25, thereby obtaining the electronic package 2 of the present invention.

[0066] In addition, the substrate 25 may be provided with a recess 250 for accommodating the electronic integrated circuit chip 22 located on the second surface 20b of the interposer 20, thereby reducing the height of the overall package.

[0067] The present invention also provides an electronic package 2, comprising: an intermediate board 20, which has a first surface 20a and a second surface 20b opposite to each other and a plurality of conductive through-holes 200; an optoelectronic chip 21, which is connected to the first surface 20a of the intermediate board 20 and electrically connected to the plurality of conductive through-holes 200; and an electronic integrated circuit chip 22, which is connected to the second surface 20b of the intermediate board 20 and electrically connected to the plurality of conductive through-holes 200.

[0068] In one embodiment, a first circuit structure 201 electrically connected to the conductive through-vias 200 is disposed on the first surface 20 a of the interposer 20 , and / or a second circuit structure 202 electrically connected to the conductive through-vias 200 is disposed on the second surface 20 b of the interposer 20 .

[0069] In one embodiment, the optoelectronic chip 21 has a first active surface 21a and a first inactive surface 21b opposite to each other, wherein the first active surface 21a is provided with a plurality of first connection pads 211 and at least one connection portion 212, and a plurality of first conductive bumps 213 are provided on the plurality of first connection pads 211, and the connection portion 212 can be a connection point for connecting an optical fiber or an optical fiber cable. The electronic integrated circuit chip 22 has a second active surface 22a and a second inactive surface 22b opposite to each other, wherein the second active surface 22a is provided with a plurality of second connection pads 221, and a plurality of second conductive bumps 223 are provided on the plurality of second connection pads 221.

[0070] In one embodiment, a heat dissipation layer 203 is formed on the first surface 20 a of the interposer 20 to conduct the heat of the chip and improve the heat dissipation effect.

[0071] In one embodiment, a plurality of conductive elements 24 are disposed on the second surface 20 b of the interposer 20 , and the plurality of conductive elements 24 are bonded to a substrate 25 .

[0072] In summary, the electronic package and its manufacturing method of the present invention mainly allow the optoelectronic chip 21 and the electronic integrated circuit chip 22 to directly connect the signals to each other through the intermediate board 20 (multiple conductive through-holes 200). The distance between the two is relatively close, which can effectively reduce the power consumed by the signal transmission between the lines and the transmission delay caused, and successfully achieve the performance of increasing the transmission rate. In addition, because the heat dissipation layer 203 structure is provided on the surface of the intermediate board 20, the heat of the chip can be conducted through the structural design of the whole metal and the material properties of the metal itself, thereby improving the heat dissipation effect.

[0073] The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the inventive concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: An interposer having a first surface and a second surface opposite to each other and a plurality of conductive through holes; an optoelectronic chip, which is disposed on the first surface of the interposer and electrically connected to the plurality of conductive through-holes; and The electronic integrated circuit chip is placed on the second surface of the intermediate board and is electrically connected to the plurality of conductive through holes.

2. The electronic package of claim 1, wherein: The optoelectronic chip has a first active surface and a first inactive surface opposite to each other. The first active surface is provided with a plurality of first connection pads and at least one connection portion, and a plurality of first conductive bumps are provided on the plurality of first connection pads.

3. The electronic package of claim 1, wherein: The electronic integrated circuit chip has a second active surface and a second inactive surface opposite to each other. The second active surface is provided with a plurality of second connection pads, and a plurality of second conductive bumps are provided on the plurality of second connection pads.

4. The electronic package of claim 1, wherein: The first surface of the interposer is provided with a first circuit structure electrically connected to the conductive through-holes, and / or the second surface of the interposer is provided with a second circuit structure electrically connected to the conductive through-holes.

5. The electronic package of claim 1, wherein: A heat dissipation layer is formed on the first surface and / or the second surface of the intermediate board.

6. The electronic package of claim 1, wherein: The electronic package also includes a plurality of conductive elements arranged on the second surface of the intermediate board and a substrate combined with the plurality of conductive elements.

7. The electronic package of claim 6, wherein: The substrate is provided with a recessed portion for accommodating the electronic integrated circuit chip located on the second surface of the intermediate board.

8. A method for manufacturing an electronic package, comprising: Provide an optoelectronic chip, an electronic integrated circuit chip and an interposer, wherein the interposer has a first surface and a second surface opposite to each other and a plurality of conductive through holes; Placing the optoelectronic chip on the first surface of the interposer and electrically connecting the plurality of conductive through-holes; and The electronic integrated circuit chip is placed on the second surface of the intermediate board and electrically connected to the plurality of conductive through holes.

9. The method for manufacturing an electronic package as claimed in claim 8, wherein: The optoelectronic chip has a first active surface and a first inactive surface opposite to each other. The first active surface is provided with a plurality of first connection pads and at least one connection portion, and a plurality of first conductive bumps are provided on the plurality of first connection pads.

10. The method for manufacturing an electronic package as claimed in claim 8, wherein: The electronic integrated circuit chip has a second active surface and a second inactive surface opposite to each other. The second active surface is provided with a plurality of second connection pads, and a plurality of second conductive bumps are provided on the plurality of second connection pads.

11. The method for manufacturing an electronic package as claimed in claim 8, wherein: The first surface of the interposer is provided with a first circuit structure electrically connected to the conductive through-holes, and / or the second surface of the interposer is provided with a second circuit structure electrically connected to the conductive through-holes.

12. The method for manufacturing an electronic package as claimed in claim 8, wherein: A heat dissipation layer is formed on the first surface and / or the second surface of the intermediate board.

13. The method for manufacturing an electronic package as claimed in claim 8, wherein: The manufacturing method also includes disposing a plurality of conductive elements on the second surface of the interposer for bonding to a substrate.

14. The method for manufacturing an electronic package according to claim 13, wherein: The substrate is provided with a recessed portion for accommodating the electronic integrated circuit chip located on the second surface of the intermediate board.

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