A method for manufacturing an infrared dual-lattice photonic crystal surface-emitting laser

Abstract

The application belongs to the technical field of optoelectronic device manufacturing, and particularly relates to a manufacturing method of an infrared double-lattice photonic crystal surface-emitting laser, which comprises material growth and device manufacturing. 0.3 Ga 0.7 AsSb / In 0.3 Ga 0.7 AsSb multi-quantum well light-emitting layer, stress matching of quantum barriers and quantum wells can be realized, loss of carriers is less, and radiation recombination efficiency is high; Ni, Ag metal and p-GaSb are used to form good electrical conduction through annealing, contact resistance is relatively low, and this is beneficial to the improvement of electro-optical conversion efficiency; the photonic crystal structure hole diameter is 160-200 nm; the x, y interval is equidistantly arranged, the arrangement interval is 100-150 nm, and the hole depth is 300-500 nm; the device realized through the above application design has high electro-optical conversion efficiency of the x, y double-lattice structure device, and the threshold power density can reach 1.8-1.91 kW / cm 2 . The application significantly improves the output efficiency and frequency stability of the laser by combining the double-lattice structure and the photonic crystal characteristics.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of optoelectronic device manufacturing, and specifically relates to a manufacturing method of an infrared dual-lattice photonic crystal surface-emitting laser. BACKGROUND

[0002] With the rapid development of infrared laser technology, surface-emitting lasers have been widely used in communication, sensing and medical fields due to their high efficiency, miniaturization and easy integration. However, traditional infrared lasers still have deficiencies in beam quality and frequency stability.

[0003] Although existing photonic crystal lasers have good frequency selectivity, their manufacturing process is complex and it is difficult to achieve efficient surface-emitting output. In addition, the application of dual-lattice structure in photonic crystals is not mature, which limits its application potential in the infrared band.

[0004] Therefore, there is an urgent need for a new manufacturing method that can realize efficient infrared dual-lattice photonic crystal surface-emitting lasers while ensuring the characteristics of photonic crystals. SUMMARY

[0005] The application provides a manufacturing method of an infrared dual-lattice photonic crystal surface-emitting laser, which realizes efficient and stable infrared laser output by combining dual-lattice structure and photonic crystal characteristics.

[0006] To achieve the above purpose, the application adopts the following technical solutions:

[0007] A manufacturing method of an infrared dual-lattice photonic crystal surface-emitting laser, specifically comprising the following steps:

[0008] Step 1, material growth: growing an epitaxial structure on a substrate;

[0009] Step 2, device fabrication:

[0010] (1) Photolithography:

[0011] Using photolithography technology to photoetch a hole with a diameter of 160-200 nm on a semiconductor chip; the x, y spacing is equidistantly arranged, and the arrangement spacing is 100-150 nm;

[0012] (2) Etching: removing unnecessary materials by etching;

[0013] (3) Definition:

[0014] (3.1) define p-electrode pattern on P-type semiconductor surface, respectively evaporate Ni, Ag, TiW ohmic contact layer and Au, Ni, Pt, Au layer, thickness of each layer is 10-200nm, wherein thickness of Ni layer is 0.5-1nm; remove photoresist after stripping, finally form P-electrode layer;

[0015] (3.2) define N-electrode pattern on N-type semiconductor surface, evaporate Au, alloy layer, Au, Ti, Au layer, thickness of each layer is 10-200nm, remove photoresist after stripping, finally form n-electrode layer;

[0016] (4) annealing:

[0017] use annealing process to form good electrical conduction between metal and P-type semiconductor and N-type semiconductor.

[0018] Preferably, the substrate uses n-type GaSb substrate, GaSb material can gap is 0.726eV, its lattice constant is 6.1Å.

[0019] Preferably, the epitaxial structure comprises GaSb buffer layer, n-Al x Ga 1-x Sb extension layer, n-Al y Ga 1- y Sb distributed restriction layer, Al 0.3 Ga 0.7 Sb / In 0.3 Ga 0.7 Sb multiple quantum well light emitting layer, p-Al z Ga 1-z Sb distributed restriction layer, p-Al c Ga 1-c Sb extension layer, p-GaSb ohmic contact layer.

[0020] Preferably, the multiple quantum well layer thickness is 5-8nm, barrier layer thickness is 4-7nm, and there are 4-6 pairs respectively.

[0021] Preferably, the n-type GaSb substrate thickness is 200-300nm, n-Al x Ga 1-x Sb extension layer thickness is 2-3μm, n-Al y Ga 1-y Sb distributed restriction layer thickness is 200-300nm, p-Al z Ga 1-z Sb distributed restriction layer thickness is 200-300nm, p-Al c Ga 1-cAsSb extended layer thickness is 200~300nm,

[0022] Preferably, the p-GaSb ohmic contact layer, wherein p-GaSb, p-type doped Mg, the doping concentration is greater than 1*10 19 cm -3 , thickness is 100~200nm; n-type doped Si, the growth temperature of p-type other layers is 550~750 DEG C.

[0023] Preferably, after the growth of the material in step one is completed, Si3N4 is deposited by PECVD method, and the thickness is 100~200nm.

[0024] Preferably, the alloy layer material in step (3.2) is AuGe, AuGeNi.

[0025] Preferably, after the annealing process is completed, an Al2O3 protective layer is deposited on the surface by ALD method, and the thickness is 100~150nm.

[0026] Compared with the prior art, the present application has the following beneficial effects:

[0027] 1、The quantum well light emitting layer of the present application adopts Al 0.3 Ga 0.7 AsSb / In 0.3 Ga 0.7 AsSb multi-quantum well light emitting layer, wherein the multi-quantum well layer thickness is 5~8nm, the barrier layer thickness is 4~7nm, and the logarithm is 4~6 pairs, the lattice constants of the material under this component are equivalent, the band gap Eg is different, the quantum barrier and quantum well stress matching can be realized, the carrier loss is less, and the radiation recombination efficiency is high.

[0028] 2、The present application uses Ni, Ag metal and p-GaSb to form good electrical conduction through annealing; the contact resistance is relatively low, which is beneficial to the improvement of the electro-optical conversion efficiency; the horizontal electrode structure design makes the wire bonding easier, and the expandable space is large.

[0029] 3、The hole diameter of the photonic crystal structure of the present application is 160~200nm; the x, y spacing is equidistantly arranged, the arrangement spacing is 100~150nm, and the hole depth is 300~500nm; the device realized through the above application has high electro-optical conversion efficiency of the x, y double lattice structure, and the threshold power density can reach 1.8~1.91 kW / cm 2 。

[0030] 4、The present application significantly improves the output efficiency and frequency stability of the laser by combining the double lattice structure and the photonic crystal characteristics, and also provides new possibilities for its application in the infrared waveband. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 This is a diagram of the bidirectional photonic crystal arrangement of the present invention.

[0032] Figure 2 This is a vertical structural diagram of the device of the present invention. DETAILED DESCRIPTION

[0033] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the specific implementation methods, structures, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0034] The invention provides a method for manufacturing an infrared double-lattice photonic crystal surface-emitting laser, using a metal organic vapor deposition method, such as Figure 1 As shown, the specific steps include:

[0035] 1. Material growth:

[0036] 1. Growing a GaSb buffer layer 101 on an n-type GaSb substrate 100 with a thickness of 200-300 nm;

[0037] 2. Growing n-Al on the buffer layer 101 x Ga 1-x AsSb extension layer 102, with a thickness of 2-3 μm, where x ranges from 0.75 to 0.88;

[0038] 3. Growing n-Al on the extension layer 102 y Ga 1-y AsSb distributed confinement layer 103, thickness 200-300 nm, y range 0.25-0.35;

[0039] 4. Growing Al on the distributed confinement layer 103 0.3 Ga 0.7 AsSb / In 0.3 Ga 0.7 AsSb multi-quantum well light-emitting layer 104, wherein the multi-quantum well layer has a thickness of 5-8 nm and the barrier layer has a thickness of 4-7 nm, and there are 4-6 pairs of them respectively;

[0040] 5. Grow p-Al on the multi-quantum well light-emitting layer 104 z Ga 1-z AsSb distributed confinement layer 105, with a thickness of 200-300 nm, where z ranges from 0.25 to 0.35;

[0041] 6. Growing p-Al on the distributed confinement layer 105 c Ga 1-cAsSb extension layer 106, thickness 200~300nm, c range 0.45~0.65;

[0042] 7. Growth of p-GaSb ohmic contact layer 107 on the extension layer 106, wherein p-GaSb, p-type doped with Mg, doping concentration greater than 1*10 19 cm -3 , thickness 100~200nm; n-type doped with Si, p-type other layers grown at 550~750℃;

[0043] After the above growth, the surface is cleaned; Si3N4 is deposited by PECVD, thickness about 100~200nm.

[0044] II. Device fabrication

[0045] 1. Photolithography is performed by an electron beam exposure system, and a hole with a diameter of 160~200nm is lithographed; the x, y spacing is equidistantly arranged, and the arrangement spacing is 100~150nm, as shown in Figure 2 ;

[0046] 2. ICP-RIE technology is used to etch the surface Si3N4 to the surface of the epitaxial layer, and the photoresist is removed;

[0047] 3. ICP-RIE technology is used to etch the epitaxial layer, and the photoresist is removed; the etching depth is 300~500nm;

[0048] 4. The surface Si3N4 layer is removed by BOE;

[0049] 5. After the photolithography process, a 0.5~1mm spacing pattern is formed, ICP dry etching is performed on the n-AlGaAsSb extension layer, and the photoresist is removed;

[0050] 6. After the photolithography process, a p-electrode pattern is defined on the surface of the p-type semiconductor, a Ni, Ag, TiW ohmic contact layer is evaporated by sputtering (Sputtering), and an Au, Ni, Pt, Au layer is evaporated by electron beam method, the thickness of each layer is 10~200nm, and the thickness of the Ni layer is about 0.5~1nm; after stripping, the photoresist is removed, and finally a P-electrode layer 201 is formed;

[0051] An annealing process is used to form a good electrical conduction between the metal and the p-type semiconductor, the annealing temperature is 380~450℃, and the time is 10~15min;

[0052] 7. Defining N electrode pattern on the surface of n-AlGaAsSb extended layer by photolithography process, and then evaporating Au, alloy layer, Au, Ti, Au layer by electron beam, the thickness of each layer is 10-200 nm, and removing photoresist after stripping;

[0053] Forming good electrical conduction between metal and N-type semiconductor by annealing process, the annealing temperature is 280-350℃, and the time is 10-15 min;

[0054] 8. Depositing a layer of Al2O3 protective layer 203 on the surface by ALD method, the thickness is about 10-15 nm;

[0055] 9. Removing the protective layer above P and N electrodes by photolithography and ICP process, exposing the electrode layer, and removing photoresist; thinning the above chip to 200-250 μm; and separating the wafer into single mid-infrared surface-emitting laser with surface photonic crystal by cutting.

[0056] In summary, the fabrication of 0.5-1 mm, 2.2-2.3 μm laser device is completed.

Claims

1. A method for manufacturing an infrared double-lattice photonic crystal surface-emitting laser, characterized in that: The specific steps include: Step 1: Material growth: growing an epitaxial structure on a substrate, the epitaxial structure comprising a GaSb buffer layer, an n-Al x Ga 1-x AsSb extension layer, n-Al y Ga 1-y AsSb distributed confinement layer, Al 0.3 Ga 0.7 AsSb / In 0.3 Ga 0.7 AsSb multi-quantum well light-emitting layer, p-Al z Ga 1-z AsSb distributed confinement layer, p-Al c Ga 1-c AsSb extension layer, p-GaSb ohmic contact layer; The thickness of the substrate is 200-300 nm, and the n-Al x Ga 1-x The thickness of the AsSb extension layer is 2~3μm, and the n-Al y Ga 1-y The thickness of the AsSb distributed confinement layer is 200~300nm, and the p-Al z Ga 1-z The thickness of the AsSb distributed confinement layer is 200~300nm, the thickness of the p-AlcGa1-cAsSb extension layer is 200~300nm, the thickness of the multi-quantum well layer in the Al0.3Ga0.7AsSb / In0.3Ga0.7AsSb multi-quantum well light-emitting layer (104) is 5~8nm, the thickness of the barrier layer is 4~7nm, the thickness of the multi-quantum well layer is 5~8nm, the thickness of the barrier layer is 4~7nm, and there are 4~6 pairs respectively; Step 2: Device fabrication: (1) Photolithography: Using photolithography technology, holes with a diameter of 160-200 nm are etched on the semiconductor chip; the x and y spacing is arranged at equal intervals, with an arrangement spacing of 100-150 nm; (2) Corrosion: removal of unwanted materials by corrosion; (3) Definition: (3.1) Define a p-electrode pattern on the surface of a p-type semiconductor by evaporating Ni, Ag, and TiW ohmic contact layers and Au, Ni, Pt, and Au layers, with thicknesses ranging from 10 to 200 nm, including a Ni layer with a thickness of 0.5 to 1 nm. Remove the photoresist after stripping to form the p-electrode layer. (3.2) Defining an N-electrode pattern on the surface of an N-type semiconductor, evaporating Au, an alloy layer, Au, Ti, and an Au layer, each with a thickness of 10 to 200 nm, and removing the photoresist after stripping to form an N-electrode layer; the alloy layer material is AuGe or AuGeNi; (4) Annealing: An annealing process is used to form good electrical conduction between the metal and the P-type semiconductor and the N-type semiconductor respectively.

2. The method for manufacturing an infrared double-lattice photonic crystal surface-emitting laser according to claim 1, wherein: The substrate adopts an n-type GaSb substrate, the energy gap of the GaSb material is 0.726 eV, and the lattice constant thereof is 6.1 Å.

3. The method for manufacturing an infrared double-lattice photonic crystal surface-emitting laser according to claim 1, wherein: The p-GaSb ohmic contact layer, wherein the p-GaSb is p-type doped with Mg, and the doping concentration is greater than 1*10 19 cm -3 , thickness is 100~200nm; n-type is doped with Si, and the growth temperature of other p-type layers is 550~750℃.

4. A method for manufacturing an infrared double-lattice photonic crystal surface-emitting laser according to any one of claims 1 to 3, characterized in that: After the material growth in step 1 is completed, Si3N4 is deposited by PECVD method with a thickness of 100~200nm.

5. The method for manufacturing an infrared double-lattice photonic crystal surface-emitting laser according to claim 1, wherein: After the annealing process is completed, an Al2O3 protective layer with a thickness of 100~150nm is deposited on the surface using the ALD method.

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