Current-limiting protection circuit for wafer test and wafer test circuit

Abstract

The invention provides a current-limiting protection circuit for wafer testing and a wafer testing circuit, and relates to the technical field of electronics. The current-limiting protection circuit is arranged on a test loop of a wafer to be tested, and comprises at least one protection unit which is sequentially connected in series; wherein the protection unit comprises a depletion type MOSFET tube and a first resistor; the drain electrode of the depletion type MOSFET tube is the first end of the protection unit, the grid electrode of the depletion type MOSFET tube is connected with the first end of the first resistor, the source electrode of the depletion type MOSFET tube is connected with the second end of the first resistor, and the grid electrode of the depletion type MOSFET tube is the second end of the protection unit. Therefore, the MOSFET tube and the first resistor are arranged, so that when the wafer to be measured is in a normal blocking state, the leakage current measurement work of the current path is ensured to be normally carried out; and when the wafer to be tested is in a short-circuit failure state, the leakage current measurement work of other paths is ensured to be normally carried out, and the reliability test is ensured to be normally carried out.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a current limiting protection circuit and a wafer testing circuit for wafer testing. Background Art

[0002] In recent years, wide bandgap semiconductor materials have been widely used in the manufacture of power electronic devices. Wide bandgap semiconductor devices represented by silicon carbide power devices are replacing traditional silicon-based devices and are widely used in DC-DC converters, photovoltaic inverters, motor drives and other scenarios. Compared with silicon-based devices, silicon carbide power devices have lower on-resistance, better high-temperature performance, higher switching frequency upper limit and higher blocking voltage, which helps to improve the overall power density and efficiency of power electronic devices. However, due to the differences in the properties of semiconductor materials (the surface of silicon carbide wafers is rougher, the diameter is smaller, and the hardness is close to diamond), the production and manufacturing of silicon carbide power devices faces greater challenges and the yield rate of production is low. Since the silicon carbide power module contains multiple chips, the failure of one chip will affect the entire module, so the wafer-level reliability screening can greatly improve the yield rate of the module after packaging and reduce the cost caused by module failure. The silicon carbide wafer reliability test equipment is a special equipment for reliability screening of silicon carbide power chips at high temperatures at the wafer stage, which is an urgent need for power semiconductor packaging and testing manufacturers.

[0003] The HTRB (High Temperature Reverse Bias) test is a routine test for reliability screening. This test applies a reverse bias to the main blocking junction of the device under test at a voltage close to the maximum rated voltage at high temperature to assess the change in leakage current of the device under high temperature and long-term reverse bias voltage. When conducting the HTRB test, the reliability test equipment of silicon carbide wafers needs to consider the independent current limiting protection problem after a short circuit of a wafer under test in a certain test loop.

[0004] Wafer-level HTRB tests usually use the same high-voltage power supply to test hundreds of parallel wafers simultaneously. If a wafer fails and short-circuits during the test, the test circuit should be independently current-limited to not affect the normal tests of other wafers. Since the HTRB test voltage may be as high as several thousand volts, a megohm resistor must be connected in series in the circuit to limit the short-circuit current to a reasonable level (milliampere level). However, excessively high resistance values ​​may cause a higher voltage divider to be generated on the current-limiting resistor in the test circuit of some wafers with large leakage current during normal tests, which in turn causes the actual test voltage at both ends of the wafer in the circuit to be significantly lower than the preset value, which cannot meet the test requirements and the reliability test cannot be carried out normally. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies in the above-mentioned prior art. The present application provides a current limiting protection and wafer testing circuit for wafer testing to solve the problems in the prior art that reliability tests cannot be carried out normally.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: In a first aspect, an embodiment of the present application provides a current limiting protection circuit for wafer testing, wherein the current limiting protection circuit is arranged on a test loop of a wafer to be tested, and the current limiting protection circuit comprises: at least one protection unit connected in series in sequence; Wherein, the protection unit includes: a depletion-type MOSFET tube and a first resistor; the drain of the depletion-type MOSFET tube is the first end of the protection unit, the gate of the depletion-type MOSFET tube is connected to the first end of the first resistor, the source of the depletion-type MOSFET tube is connected to the second end of the first resistor, and the gate of the depletion-type MOSFET tube is the second end of the protection unit.

[0007] Optionally, the current limiting protection circuit further includes: a second resistor; A second terminal of a last protection unit in the at least one protection unit is grounded through the second resistor.

[0008] Optionally, the protection unit further includes: a third resistor; The third resistor is connected in parallel between the source and the drain of the depletion-type MOSFET tube.

[0009] Optionally, the protection unit further includes: a Zener diode; The Zener diode is connected in parallel between the source and the drain of the depletion-type MOSFET tube.

[0010] Optionally, the first resistor and the second resistor are both hundred-ohm resistors or thousand-ohm resistors.

[0011] Optionally, the third resistor is a megohm resistor.

[0012] Optionally, the resistance values ​​of the first resistors in different protection units are the same, and the resistance values ​​of the third resistors in different protection units are the same.

[0013] In a second aspect, an embodiment of the present application provides a wafer test circuit, the wafer test circuit comprising: a wafer to be tested, a current limiting protection circuit, and a preset power supply; the current limiting protection circuit is any current limiting protection circuit described in the first aspect above; One end of the wafer to be tested is connected to the positive electrode of the preset power supply, and the negative electrode of the preset power supply is grounded, so as to form a test loop of the wafer to be tested.

[0014] Optionally, the wafer test circuit further comprises: a leakage measuring instrument; The other end of the wafer to be tested is connected to the negative electrode of the preset power supply through the current limiting protection circuit and the leakage measuring instrument.

[0015] Optionally, the number of the wafers to be tested is at least one, the number of the current limiting protection circuit is at least one, and at least one current limiting protection circuit is respectively connected to a test circuit of at least one of the wafers to be tested.

[0016] Compared with the prior art, this application has the following beneficial effects: The present application provides a current limiting protection and wafer testing circuit for wafer testing. The current limiting protection circuit is arranged on the test loop of the wafer to be tested, and the current limiting protection circuit includes: at least one protection unit connected in series in sequence; wherein the protection unit includes: a depletion type MOSFET tube and a first resistor; the drain of the depletion type MOSFET tube is the first end of the protection unit, the gate of the depletion type MOSFET tube is connected to the first end of the first resistor, the source of the depletion type MOSFET tube is connected to the second end of the first resistor, and the gate of the depletion type MOSFET tube is the second end of the protection unit. Thus, by setting the MOSFET tube and the first resistor, when the wafer to be tested is in a normal blocking state, the leakage current measurement of the current path can be guaranteed to proceed normally; when the wafer to be tested is in a short circuit failure state, the leakage current measurement of other paths can also be guaranteed to proceed normally, effectively ensuring the normal progress of the reliability test. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of a current limiting protection circuit for wafer testing provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of another current limiting protection circuit for wafer testing provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a wafer testing circuit provided in an embodiment of the present application.

[0019] Icon: 1- protection unit, Q1- MOSFET tube, R1- first resistor, R2- second resistor, R3- third resistor, Z1- Zener diode, D1- wafer to be tested, U- preset power supply. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0022] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0023] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0024] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0025] The following is an explanation of a current limiting protection circuit for wafer testing provided in an embodiment of the present application through a specific embodiment. Figure 1 A schematic diagram of the structure of a current limiting protection circuit for wafer testing provided in an embodiment of the present application.

[0026] like Figure 1 As shown, the current limiting protection circuit is arranged on the test loop of the wafer to be tested, and the current limiting protection circuit comprises: at least one protection unit 1 connected in series in sequence.

[0027] Among them, the protection unit 1 includes: a depletion-type MOSFET tube Q1 and a first resistor R1; the drain of the depletion-type MOSFET tube Q1 is the first end of the protection unit 1, the gate of the depletion-type MOSFET tube Q1 is connected to the first end of the first resistor R1, the source of the depletion-type MOSFET tube Q1 is connected to the second end of the first resistor R1, and the gate of the depletion-type MOSFET tube Q1 is the second end of the protection unit 1.

[0028] The depletion-type MOSFET tube Q1 is different from the commonly used enhancement-type MOSFET. When the gate-source voltage of the depletion-type MOSFET is zero, it is in the on state. The depletion-type MOSFET has the characteristics of "zero voltage turn-on, negative voltage turn-off". By connecting the depletion-type MOSFETs in multiple protection units 1 in series, the withstand voltage value of the current limiting protection circuit can be increased to adapt to the high voltage scenario of the HTRB test. It should be noted that the number of protection units 1 is determined by the rated voltage value of the depletion-type MOSFET tube Q1 and the voltage value of the preset power supply. The smaller the rated voltage value of the depletion-type MOSFET tube Q1, or the larger the voltage value of the preset power supply, the more depletion-type MOSFET tubes Q1 are. The larger the rated voltage value of the depletion-type MOSFET tube Q1, or the smaller the voltage value of the preset power supply, the fewer the depletion-type MOSFET tubes Q1 are.

[0029] When the wafer to be tested is in a normal blocking state, the voltage proportion of the depletion MOSFET tube Q1 and the first resistor R1 in the entire test loop is very small and does not affect the test voltage required by the wafer to be tested in normal test work.

[0030] When the wafer to be tested suddenly fails due to a short circuit, the voltage at both ends of the depletion-type MOSFET will not change suddenly due to the presence of parasitic capacitance between the drain and source of the depletion-type MOSFET. The two ends of the multiple first resistors R1 will be subjected to transient voltage spikes, causing the gate-source voltage of the depletion-type MOSFET to become negative and significantly lower than the turn-off threshold voltage, and the depletion-type MOSFET tube Q1 enters the blocking state. The voltage division of each depletion-type MOSFET tube Q1 is balanced and there is no overvoltage. And because the depletion-type MOSFET tube Q1 enters the blocking state, the short-circuit current of the test loop is limited to an acceptable range. At the same time, other test loops can still work normally, and the current limiting protection circuit effectively ensures the normal progress of the reliability test.

[0031] Therefore, by setting the depletion-type MOSFET tube Q1 and the first resistor R1, when the wafer to be tested is in a normal blocking state, the leakage current measurement of the current path can be guaranteed to proceed normally; when the wafer to be tested is in a short-circuit failure state, the leakage current measurement of other paths can also be guaranteed to proceed normally, effectively ensuring the normal progress of the reliability test.

[0032] In summary, in this embodiment, the current limiting protection circuit is arranged on the test loop of the wafer to be tested, and the current limiting protection circuit includes: at least one protection unit connected in series in sequence; wherein, the protection unit includes: a depletion type MOSFET tube, a first resistor; the drain of the depletion type MOSFET tube is the first end of the protection unit, the gate of the depletion type MOSFET tube is connected to the first end of the first resistor, the source of the depletion type MOSFET tube is connected to the second end of the first resistor, and the gate of the depletion type MOSFET tube is the second end of the protection unit. Thus, by setting the depletion type MOSFET tube and the first resistor, when the wafer to be tested is in a normal blocking state, the leakage current measurement of the current path can be guaranteed to proceed normally; when the wafer to be tested is in a short circuit failure state, the leakage current measurement of other paths can also be guaranteed to proceed normally, which effectively ensures the normal progress of the reliability test.

[0033] In the above Figure 1 On the basis of the corresponding embodiments, the embodiments of the present application also provide another current limiting protection circuit for wafer testing. Figure 2 A schematic diagram of the structure of another current limiting protection circuit for wafer testing provided in an embodiment of the present application.

[0034] like Figure 2 As shown, the current limiting protection circuit also includes: a second resistor R2.

[0035] The second end of the last protection unit 1 in at least one protection unit is grounded through a second resistor R2.

[0036] The second resistor R2 plays a current limiting role in the test branch.

[0037] Continue to refer to Figure 2 In another embodiment of the present application, the protection unit 1 further includes: a third resistor R3.

[0038] The third resistor R3 is connected in parallel between the source and the drain of the depletion-type MOSFET tube Q1.

[0039] It can be seen from the analysis of the above embodiments that when the wafer to be tested suddenly fails due to a short circuit, the depletion-type MOSFET tube Q1 enters a blocking state. The voltage division of each depletion-type MOSFET tube Q1 is dominated by the third resistor R3 connected in parallel therewith, so that the voltage division is basically balanced and there is no overvoltage. After that, the total resistance of the current limiting protection circuit is the sum of the resistance values ​​of multiple first resistors R1, multiple third resistors R3, and the second resistor R2. The resistance value of the test loop becomes larger, and the short-circuit current is limited to an acceptable range. At the same time, other test loops can still work normally, and the current limiting protection circuit effectively ensures the normal progress of the reliability test.

[0040] In summary, in this embodiment, the protection unit further includes: a third resistor; the third resistor is connected in parallel between the source and the drain of the depletion-type MOSFET tube. Thus, the current limiting protection circuit effectively ensures the normal progress of the reliability test.

[0041] Continue to refer to Figure 2 In another embodiment of the present application, the protection unit 1 further includes: a Zener diode Z1.

[0042] The Zener diode Z1 is connected in parallel between the source and drain of the depletion-type MOSFET tube Q1.

[0043] The Zener diode Z1 and the third resistor R3 jointly realize voltage division, and the Zener diode Z1 also plays a role in voltage stabilization.

[0044] Continue to refer to Figure 2 In another embodiment of the present application, the first resistor R1 and the second resistor R2 are both hundred-ohm resistors or thousand-ohm resistors.

[0045] Continue to refer to Figure 2 In another embodiment of the present application, the third resistor R3 is a megohm resistor.

[0046] Continue to refer to Figure 2 , the resistance values ​​of the first resistors in different protection units are the same, and the resistance values ​​of the third resistors in different protection units are the same.

[0047] A wafer testing circuit provided in an embodiment of the present application is explained below through a specific embodiment. Figure 3 A schematic diagram of the structure of a wafer testing circuit provided in an embodiment of the present application.

[0048] like Figure 3 As shown, the wafer test circuit includes: a wafer D1 to be tested, a current limiting protection circuit, and a preset power supply U; the current limiting protection circuit is any current limiting protection circuit for wafer testing in the above embodiments.

[0049] One end of the wafer D1 to be tested is connected to the positive electrode of the preset power supply U, and the negative electrode of the preset power supply U is grounded, so as to form a test loop of the wafer D1 to be tested.

[0050] For example, the wafer test circuit may be for performing an HTRB test on the wafer.

[0051] When the wafer to be tested is in a normal blocking state, the leakage current of the wafer to be tested is in the μA to hundreds of μA level. Since the resistance of the first resistor R1 is in the kilo-ohm level, the gate-source voltage of the depletion-type MOSFET is approximately zero at this time, the depletion-type MOSFET tube Q1 is in the on state, and the resistance of the second resistor R2 is in the hundreds of kilo-ohm level. The total resistance of the current limiting protection branch is the sum of the on-resistance of multiple depletion-type MOSFET tubes Q1, multiple first resistors R1, and the resistance of the second resistor R2. Therefore, the voltage drop of the leakage current in the current limiting protection circuit accounts for a very small proportion of the test voltage and does not affect the normal test work.

[0052] When the wafer to be tested suddenly fails due to short circuit, due to the presence of parasitic capacitance between the drain and source of the depletion-type MOSFET, the voltage at both ends will not mutate. Multiple first resistors R1 and second resistors R2 will be subjected to transient voltage spikes, causing the gate-source voltage of the depletion-type MOSFET to become negative and significantly lower than the turn-off threshold voltage, and the depletion-type MOSFET tube Q1 enters the blocking state. The voltage division of each depletion-type MOSFET tube Q1 is dominated by the Zener diode Z1 and the third resistor R3 connected in parallel therewith, so that the voltage division is basically balanced and there is no overvoltage. Thereafter, the total resistance of the current limiting protection circuit is the sum of the resistance values ​​of multiple first resistors R1, multiple third resistors R3, and the second resistor R2, wherein the sum of the resistance values ​​of multiple third resistors R3 is in the megohm level, so the current of the test loop can be limited to the milliampere level when the wafer to be tested is short-circuited. At the same time, other test loops can still work normally, and the current limiting protection circuit effectively ensures the normal progress of the reliability test.

[0053] In summary, in this embodiment, the wafer test circuit includes: a wafer to be tested, a current limiting protection circuit, and a preset power supply; the current limiting protection circuit is any current limiting protection circuit for wafer testing in the above embodiments; one end of the wafer to be tested is connected to the positive pole of the preset power supply, and the negative pole of the preset power supply is grounded to form a test loop for the wafer to be tested. Thus, by setting the current limiting protection circuit, when the wafer to be tested is in a normal blocking state, the leakage current measurement of the current path can be guaranteed to proceed normally; when the wafer to be tested is in a short-circuit failure state, the leakage current measurement of other paths can also be guaranteed to proceed normally, effectively ensuring the normal progress of the reliability test.

[0054] Continue to refer to Figure 3 In another embodiment of the present application, the wafer testing circuit further includes: a leakage measuring instrument A.

[0055] The other end of the wafer D1 to be tested is connected to the negative pole of a preset power supply U through a current limiting protection circuit and a leakage measuring instrument A.

[0056] Continue to refer to Figure 3In another embodiment of the present application, the number of wafers D1 to be tested is at least one, the number of current limiting protection circuits is at least one, and at least one current limiting protection circuit is respectively connected to the test circuit of at least one wafer D1 to be tested. The wafer test circuit provided in the embodiment of the present application can test multiple wafers D1 to be tested at the same time.

[0057] It should be noted that each component and the connection method between the components in the present application are prior arts and are not described in detail to avoid confusion.

[0058] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

Claims

1. A current limiting protection circuit for wafer testing, characterized in that: The current limiting protection circuit is arranged on a test loop of the wafer to be tested, and the current limiting protection circuit comprises: at least one protection unit connected in series in sequence; Wherein, the protection unit includes: a depletion-type MOSFET tube and a first resistor; the drain of the depletion-type MOSFET tube is the first end of the protection unit, the gate of the depletion-type MOSFET tube is connected to the first end of the first resistor, the source of the depletion-type MOSFET tube is connected to the second end of the first resistor, and the gate of the depletion-type MOSFET tube is the second end of the protection unit.

2. The current limiting protection circuit according to claim 1, characterized in that: The current limiting protection circuit further includes: a second resistor; A second terminal of a last protection unit in the at least one protection unit is grounded through the second resistor.

3. The current limiting protection circuit according to claim 1, characterized in that: The protection unit further includes: a third resistor; The third resistor is connected in parallel between the source and the drain of the depletion-type MOSFET tube.

4. The current limiting protection circuit according to claim 3, characterized in that: The protection unit further includes: a Zener diode; The Zener diode is connected in parallel between the source and the drain of the depletion-type MOSFET tube.

5. The current limiting protection circuit according to claim 2, characterized in that: The first resistor and the second resistor are both hundred-ohm resistors or thousand-ohm resistors.

6. The current limiting protection circuit according to claim 3, characterized in that: The third resistor is a megohm-level resistor.

7. The current limiting protection circuit according to claim 3, characterized in that: The resistance values ​​of the first resistors in different protection units are the same, and the resistance values ​​of the third resistors in different protection units are the same.

8. A wafer testing circuit, characterized in that: The wafer test circuit comprises: a wafer to be tested, a current limiting protection circuit, and a preset power supply; the current limiting protection circuit is the current limiting protection circuit for wafer testing as described in any one of claims 1 to 7 above; One end of the wafer to be tested is connected to the positive electrode of the preset power supply, and the negative electrode of the preset power supply is grounded, so as to form a test loop of the wafer to be tested.

9. The wafer testing circuit according to claim 8, characterized in that: The wafer test circuit also includes: a leakage measuring instrument; The other end of the wafer to be tested is connected to the negative electrode of the preset power supply through the current limiting protection circuit and the leakage measuring instrument.

10. The wafer testing circuit according to claim 8, characterized in that: The number of the wafers to be tested is at least one, the number of the current limiting protection circuit is at least one, and at least one current limiting protection circuit is respectively connected to a test circuit of at least one of the wafers to be tested.

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