Synchronization circuit and method of energy storage inverter parallel operation system

Abstract

The invention discloses a synchronous circuit and method of an energy storage inverter parallel operation system, and belongs to the field of photovoltaic technology. The circuit comprises a CAN bus; the plurality of synchronous communication components are respectively arranged in each energy storage inverter of the energy storage inverter parallel operation system; the synchronous communication component comprises an ePWM module, and the ePWM module comprises corresponding time base counter registers; one of the energy storage inverters is a host, and the rest of the energy storage inverters are slaves; a main synchronous communication component in the host is used for sending a kth-phase carrier synchronization signal to the CAN bus when a count value of a time base counter register corresponding to the kth phase in the main synchronous communication component is 0; the slave synchronization communication component in each slave is used for setting the count value of the time base counter register corresponding to the kth phase in the slave to be 0 when receiving the kth phase carrier synchronization signal, and k is a positive integer. According to the embodiment of the invention, synchronous operation among the energy storage inverters can be realized, and the operation reliability and safety of the parallel operation system are ensured.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a synchronization circuit and method for an energy storage inverter parallel system. Background Art

[0002] With the development of photovoltaic energy storage technology, the power demanded by the photovoltaic energy storage market is getting higher and higher. It is difficult for a single energy storage inverter to meet the high power demand of the market, so the parallel operation of energy storage inverters is gradually increasing. In the parallel system, multiple energy storage inverters output to the same load, so multiple machines need to run synchronously. If the operation is not synchronized, there will be circulation between the machines, causing the energy storage inverter to malfunction or even damage, causing functional and safety problems. Summary of the invention

[0003] The present invention provides a synchronization circuit and method for an energy storage inverter parallel system, so as to realize the synchronous operation between the energy storage inverters in the energy storage inverter parallel system and ensure the operation reliability and safety of the energy storage inverter parallel system.

[0004] In a first aspect, an embodiment of the present invention provides a synchronization circuit of an energy storage inverter parallel system, comprising:

[0005] CAN bus;

[0006] A plurality of synchronous communication components are connected to the CAN bus; each of the synchronous communication components is respectively arranged in each energy storage inverter in the energy storage inverter parallel system; the energy storage inverter has at least one phase output signal, the synchronous communication component includes an ePWM module, the ePWM module includes corresponding time base counter registers, and the ePWM module is used to control the phase of the corresponding phase output signal in the energy storage inverter according to the count value of each corresponding time base counter register;

[0007] Among them, one of the energy storage inverters in the energy storage inverter parallel system is a host, and the rest are slaves; the synchronous communication component in the host is a master synchronous communication component, and the synchronous communication component in the slave is a slave synchronous communication component; the master synchronous communication component is used to send a k-phase carrier synchronization signal to the CAN bus when the count value of the k-th corresponding time base counter register in the master synchronous communication component is 0; each of the slave synchronous communication components is used to set the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0 when receiving the k-th phase carrier synchronization signal transmitted on the CAN bus, and k is a positive integer.

[0008] Optionally, the CAN bus includes a first bus and a second bus; the synchronous communication component includes: a control module, an isolation module and a CAN processing module;

[0009] The control module includes the ePWM module; the output end of the control module is connected to the first input end of the isolation module, the first output end of the isolation module is connected to the transmitting end of the CAN processing module, the first communication connection end of the CAN processing module is connected to the first bus, the second communication end of the CAN processing module is connected to the second bus, the receiving end of the CAN processing module is connected to the second input end of the isolation module, and the second output end of the isolation module is connected to the input end of the control module.

[0010] Optionally, the CAN processing module includes:

[0011] A CAN processing unit, wherein a transmitting end of the CAN processing unit is connected to a transmitting end of the CAN processing module, and a receiving end of the CAN processing unit is connected to a receiving end of the CAN processing module;

[0012] A common mode filtering unit, wherein a first end of the common mode filtering unit is connected to a first communication end of the CAN processing unit, a second end of the common mode filtering unit is connected to a second communication end of the CAN processing unit, a third end of the common mode filtering unit is connected to a first communication connection end of the CAN processing module, and a fourth end of the common mode filtering unit is connected to a second communication connection end of the CAN processing module.

[0013] Optionally, the CAN processing module further includes:

[0014] A first filtering unit, connected between a transmitting end of the CAN processing unit and a transmitting end of the CAN processing module;

[0015] a second filtering unit connected between a receiving end of the CAN processing unit and a receiving end of the CAN processing module;

[0016] The lightning protection unit is respectively connected to the third end of the common mode filtering unit, the fourth end of the common mode filtering unit, the first bus and the second bus.

[0017] Optionally, the CAN processing unit includes: a CAN chip and a first resistor; a receiving pin of the CAN chip serves as a receiving end of the CAN processing unit, a sending pin of the CAN chip serves as a sending end of the CAN processing unit, a first communication pin of the CAN chip serves as a first communication end of the CAN processing unit, and a second communication pin of the CAN chip serves as a second communication end of the CAN processing unit; a standby control pin of the CAN chip is connected to a first end of the first resistor, and a second end of the first resistor is connected to a first ground end of the synchronous communication component;

[0018] The common mode filtering unit comprises: a common mode inductor;

[0019] The first filtering unit includes: a second resistor and a first capacitor; the second resistor is connected between the sending pin of the CAN chip and the sending end of the CAN processing module, and the first capacitor is connected between the sending pin of the CAN chip and the first grounding end;

[0020] The second filtering unit includes: a third resistor and a second capacitor; the third resistor is connected between the receiving pin of the CAN chip and the receiving end of the CAN processing module, and the second capacitor is connected between the receiving end of the CAN processing module and the first grounding end;

[0021] The lightning protection unit includes: a first bidirectional voltage regulator, a second bidirectional voltage regulator, a third bidirectional voltage regulator, a first thermistor, a second thermistor and a gas discharge tube; the first bidirectional voltage regulator is connected between the third end and the fourth end of the common mode filter unit; the second bidirectional voltage regulator is connected between the third end of the common mode filter unit and the first ground end; the third bidirectional voltage regulator is connected between the fourth end of the common mode filter unit and the first ground end; the first thermistor is connected between the third end of the common mode filter unit and the first bus; the second thermistor is connected between the fourth end of the common mode filter unit and the second bus; the gas discharge tube is connected between the first bus and the second bus.

[0022] Optionally, the control module includes: a digital signal processor and a complex programmable logic device; the ePWM module is arranged in the digital signal processor, the digital signal processor is connected to the complex programmable logic device, and the complex programmable logic device is respectively connected to the input end and the output end of the control module;

[0023] And / or, the isolation module includes: an isolation unit, a third filtering unit, a first pull-up unit, a second pull-up unit and a current limiting unit; the third filtering unit is connected between the output end of the control module and the first input end of the isolation unit, the first end of the first pull-up unit is connected to the first power supply signal, the second end of the first pull-up unit is connected to the first input end of the isolation unit, and the first output end of the isolation unit is connected to the transmitting end of the CAN processing module; the second input end of the isolation unit is connected to the receiving end of the CAN processing module, the current limiting unit is connected between the second output end of the isolation unit and the input end of the control module, the first end of the second pull-up unit is connected to the first power supply signal, and the second end of the second pull-up unit is connected to the second output end of the isolation unit;

[0024] And / or, the synchronous communication component further includes: a parallel communication module; the parallel communication module is connected to the control module; the parallel communication module of any of the synchronous communication components is communicatively connected to the parallel communication modules of other synchronous communication components.

[0025] Optionally, the synchronous communication component further includes: an external interface module, including a first external interface and a second external interface; each of the synchronous communication components is connected to the CAN bus through the external interface module, and the second external interface of each synchronous communication component is connected to the first external interface of the next synchronous communication component to form a hand-in-hand connection structure;

[0026] And / or, the CAN bus includes a first bus and a second bus, and the synchronous communication component connects the first bus and the second bus; the synchronization circuit of the energy storage inverter parallel system also includes:

[0027] A first matching resistor connected between a first end of the first bus and a first end of the second bus;

[0028] The second matching resistor is connected between an end of the first bus and an end of the second bus.

[0029] In a second aspect, an embodiment of the present invention further provides a synchronization method of an energy storage inverter parallel system, which is applied to a synchronization circuit of an energy storage inverter parallel system provided by any embodiment of the present invention; the synchronization method of the energy storage inverter parallel system comprises:

[0030] The main synchronous communication component sends a k-th phase carrier synchronization signal to the CAN bus when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0;

[0031] For any of the slave synchronous communication components, when the slave synchronous communication component receives the k-th phase carrier synchronization signal transmitted on the CAN bus, the slave synchronous communication component sets the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0.

[0032] Optionally, the CAN bus includes a first bus and a second bus, and the synchronous communication component includes: a control module, an isolation module and a CAN processing module connected in sequence, and the CAN processing module connects the first bus and the second bus;

[0033] The main synchronous communication component sends a k-th phase carrier synchronization signal to the CAN bus when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0, including:

[0034] The control module of the main synchronous communication component outputs a k-th phase control signal when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0;

[0035] The isolation module of the main synchronous communication component isolates the k-th phase control signal to generate a k-th phase first isolation signal;

[0036] The CAN processing module of the main synchronous communication component processes the k-th phase first isolation signal and outputs the k-th phase carrier synchronization signal in differential form to the first bus and the second bus;

[0037] When the slave synchronous communication component receives the k-th phase carrier synchronization signal transmitted on the CAN bus, the count value of the k-th corresponding time base counter register in the slave synchronous communication component is set to 0, including:

[0038] The CAN processing module of the slave synchronous communication component receives the k-th phase carrier synchronization signal from the first bus and the second bus and processes and generates a k-th phase processing signal;

[0039] The isolation module of the slave synchronous communication component isolates the k-th phase processing signal to generate a k-th phase second isolation signal;

[0040] When receiving the k-th phase second isolation signal, the control module of the slave synchronous communication component sets the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0.

[0041] Optionally, the main synchronous communication component receives a signal transmitted on the CAN bus while sending the k-th phase carrier synchronization signal to the CAN bus; when the main synchronous communication component receives the k-th phase carrier synchronization signal, it confirms that the k-th phase carrier synchronization signal is sent successfully;

[0042] And / or, the synchronization circuit of the energy storage inverter parallel system further includes: a host computer; the synchronous communication component includes: a control module and a parallel communication module; the control modules of each of the synchronous communication components are connected to the host computer;

[0043] The synchronization method of the energy storage inverter parallel system also includes:

[0044] When the control module of the main synchronous communication component detects a host failure, the host failure information is uploaded to the host computer;

[0045] When the control module of the slave synchronous communication component detects a fault in the slave machine, the control module of the slave synchronous communication component uploads the slave fault information to the control module of the master synchronous communication component through the parallel communication module of the slave synchronous communication component and the parallel communication module of the master synchronous communication component, and the control module of the master synchronous communication component uploads the slave fault information to the host computer.

[0046] In the synchronization circuit of the energy storage inverter parallel system provided by the embodiment of the present invention, by setting a synchronous communication component in each energy storage inverter of the parallel system, and connecting them with a CAN bus, the CAN bus is used to realize the transmission of the carrier synchronization signal, which is conducive to realizing high-speed carrier synchronization between multiple machines and making multiple energy storage inverters run in unison. Specifically, when the count value of any phase time base counter register in the master synchronous communication component is 0, the corresponding phase carrier synchronization signal is sent to the CAN bus; when the slave synchronous communication component receives any phase carrier synchronization signal, no matter what value the internal corresponding phase time base counter register has currently counted to, the count value is forced to be set to 0, so that each ePWM module works with the same time base, and the ePWM module in the slave can control the output phase of the phase in the slave to be the same as that in the host. Therefore, the embodiments of the present invention can coordinate the corresponding phase relationship between the ePWM modules through each synchronous communication component and stably transmit the carrier synchronization signal based on the CAN protocol, which is conducive to achieving the same frequency, amplitude and phase of the AC output of each phase on the inverter side of the host and each slave, avoiding the damage of the energy storage inverter due to the circulation current between machines due to asynchronous operation, and ensuring the operation reliability and safety of the parallel system.

[0047] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 It is a structural schematic diagram of a synchronization circuit of an energy storage inverter parallel system provided by an embodiment of the present invention;

[0050] Figure 2 is a structural diagram of a synchronous communication component provided by an embodiment of the present invention;

[0051] Figure 3is a schematic diagram of the structure of another synchronous communication component provided by an embodiment of the present invention;

[0052] Figure 4 is a structural diagram of another synchronous communication component provided by an embodiment of the present invention;

[0053] Figure 5 It is a structural schematic diagram of another synchronous circuit of an energy storage inverter parallel system provided by an embodiment of the present invention;

[0054] Figure 6 It is a flow chart of a synchronization method of an energy storage inverter parallel system provided by an embodiment of the present invention;

[0055] Figure 7 It is a schematic diagram of a synchronous communication experiment verification result provided by an embodiment of the present invention;

[0056] Figure 8 It is another schematic diagram of synchronous communication experiment verification results provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0059] An embodiment of the present invention provides a synchronization circuit of an energy storage inverter parallel system, which is used to achieve synchronous operation between energy storage inverters in the energy storage inverter parallel system (also referred to as a parallel system). Figure 1 Schematic diagram of a synchronous circuit of an energy storage inverter parallel system provided by an embodiment of the present invention. Figure 1The synchronous circuit of the energy storage inverter parallel system includes: a CAN (Controller Area Network) bus and a plurality of synchronous communication components 100. Each synchronous communication component 100 is connected to the CAN bus L, and each synchronous communication component 100 exchanges information through the CAN bus L based on the CAN protocol.

[0060] Among them, multiple synchronous communication components 100 are respectively arranged in each energy storage inverter in the energy storage inverter parallel system. Specifically, the parallel system includes multiple energy storage inverters, and each synchronous communication component 100 is arranged in each energy storage inverter one by one. The output side (or inverter side) of the energy storage inverter has at least one phase output signal. The synchronous communication component 100 includes an ePWM module (enhanced pulse width modulator), and the ePWM module 110 includes a time base counter register 111 corresponding to each phase. The ePWM module 110 is used to control the phase of the corresponding phase output signal in the energy storage inverter according to the count value of each corresponding time base counter register 111. Among them, the ePWM module 110 can also include a series of registers such as a phase register and other functional elements to realize its phase control function. The specific structure and working process of the ePWM module 110 are not described here.

[0061] Among them, one of the energy storage inverters in the energy storage inverter parallel system is a master, and the rest are slaves. The structures of the synchronous communication components 100 are the same. For the convenience of subsequent description, the synchronous communication component 100 in the host is recorded as the master synchronous communication component, and the synchronous communication component 100 in the slave is recorded as the slave synchronous communication component.

[0062] In the synchronization circuit, the master synchronization communication component is used to send the kth phase carrier synchronization signal to the CAN bus when the count value of the kth corresponding time base counter register in the master synchronization communication component is 0. The carrier synchronization signal of each phase includes, for example, the identification information of the corresponding output phase, and may also include the amplitude, frequency and phase of the output signal of the corresponding output phase. Each slave synchronization communication component is used to set the count value of the kth corresponding time base counter register in the slave synchronization communication component to 0 when receiving the kth phase carrier synchronization signal transmitted on the CAN bus, and k is a positive integer. Exemplarily, the energy storage inverter has a three-phase output signal, and the 1st to 3rd phases are, for example, phase a, phase b and phase c, respectively. For any phase in the abc phase, the host and each slave machine realize the same frequency, same amplitude and same phase operation of each energy storage inverter on the phase through the sending and receiving of the phase carrier synchronization signal. It can be understood that the phase difference between different phases in the same energy storage inverter can be set according to actual needs, and the synchronization circuit provided in the embodiment of the present invention is for synchronization between different energy storage inverters in the same phase output.

[0063] In the synchronous circuit of the energy storage inverter parallel system provided by the embodiment of the present invention, by setting a synchronous communication component 100 in each energy storage inverter of the parallel system, and connecting them with a CAN bus L, the CAN bus L is used to realize the transmission of the carrier synchronization signal, which is conducive to realizing high-speed carrier synchronization between multiple machines, so that multiple energy storage inverters can run in unison. Specifically, when the count value of any phase time base counter register 111 in the master synchronous communication component is 0, the corresponding phase carrier synchronization signal is sent to the CAN bus L; when the slave synchronous communication component receives any phase carrier synchronization signal, no matter what value the internal corresponding phase time base counter register 111 has currently counted, the count value is forced to be set to 0, so that each ePWM module 110 works with the same time base, and the ePWM module 110 in the slave can control the output phase of the phase in the slave to be the same as that in the master. Therefore, the embodiment of the present invention can coordinate the corresponding phase relationship between the ePWM modules 110 through each synchronous communication component 100 and stably transmit the carrier synchronization signal based on the CAN protocol, which is conducive to achieving the same frequency, amplitude and phase of the AC output of each phase on the inverter side of the host and each slave, avoiding the damage of the energy storage inverter due to the circulation current between machines due to asynchronous operation, and ensuring the operation reliability and safety of the parallel system.

[0064] Figure 2 is a structural diagram of a synchronous communication component provided by an embodiment of the present invention. Figure 2 The CAN bus may specifically include a first bus LCANH and a second bus LCANL, which are used to transmit signals in a differential form. The synchronous communication component 100 may include: a control module 10, an isolation module 20 and a CAN processing module 30. The control module 10 includes an ePWM module.

[0065] Specifically, the output end Snc of the control module 10 is connected to the first input end IN1 of the isolation module 20, the first output end OUT1 of the isolation module 20 is connected to the transmitting end TX of the CAN processing module 30, the first communication connection end CH of the CAN processing module 30 is connected to the first bus LCANH, the second communication end CL of the CAN processing module 330 is connected to the second bus LCANL, the receiving end RX of the CAN processing module 330 is connected to the second input end IN2 of the isolation module 20, and the second output end OUT2 of the isolation module 20 is connected to the input end Fdb of the control module 10.

[0066] Among them, the control module 10 serves as the core data processing component in the synchronous communication component 100. The isolation module 20 is used to achieve isolation between the control module 10 and the CAN processing module 30 to improve circuit safety. The CAN processing module 30 is used to send and receive signals so that each synchronous communication component 100 can achieve information interaction through the CAN bus. Specifically, when the synchronous communication component 100 is set in the host, the control module 10 can output the k-th phase control signal when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0; the isolation module 20 can isolate the k-th phase control signal and generate the k-th phase first isolation signal; the CAN processing module 30 can process the k-th phase first isolation signal and output the k-th phase carrier synchronization signal in differential form to the first bus LCANH and the second bus LCANL. Each synchronous communication component 100, whether it is set in the host or the slave, can receive and analyze the signal on the CAN bus, specifically: the CAN processing module 30 receives the k-th phase carrier synchronization signal from the first bus LCANH and the second bus LCANL and processes it to generate the k-th phase processing signal; the isolation module 20 isolates the k-th phase processing signal, generates the k-th phase second isolation signal and transmits it to the control module 30. Among them, the control module 30 of the slave synchronous communication component can set the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0 when receiving the k-th phase second isolation signal; the control module 30 of the master synchronous communication component can confirm that the master synchronous communication component has successfully sent the k-th phase carrier synchronization signal when receiving the k-th phase second isolation signal, thereby confirming that the master synchronous communication component functions normally.

[0067] Figure 3 is a schematic diagram of the structure of another synchronous communication component provided by an embodiment of the present invention. Figure 3 In one embodiment, the control module 10 may include: a digital signal processor (DSP) and a complex programmable logic device (CPLD). The ePWM module is disposed in the digital signal processor 11, the digital signal processor 11 is connected to the complex programmable logic device 12, and the complex programmable logic device 12 is respectively connected to the input end and the output end of the control module 10.

[0068] The digital signal processor 11 is a core data processing component in the control module 10, and is used to generate / parse signals related to the carrier synchronization signal; the complex programmable logic device 12 is used to filter, delay and perform logic processing on the received signal. Exemplarily, any one of the digital signal processor 11 and the complex programmable logic device 12 can also be replaced by a different type of digital processing chip, such as a single-chip microcomputer and an FPGA (Field-Programmable Gate Array).

[0069] It can be understood that the moment when the digital signal processor 11 receives the signal after the complex programmable logic device 12 processes the second isolated signal of the kth phase, can be used as the moment when the synchronous communication component 100 receives the carrier synchronization signal of the kth phase. That is, from the synchronous communication component, when the digital signal processor 11 receives the signal after the complex programmable logic device 12 processes the second isolated signal of the kth phase, the count value of the time base counter register corresponding to the kth phase in the synchronous communication component is set to 0. Since the signal transmission within the same synchronous communication component is very fast, the data transmission delay between different functional devices is at the ps level, so the signal transmission time consumption within the synchronous communication component can be ignored. In addition, for carrier synchronization, the baud rate is usually 500Kbt / s, and one cycle takes 4us. Therefore, the time difference between different synchronous communication components receiving and parsing the carrier synchronization signal of the kth phase is within the us level, for example, within 1us, which will not affect the synchronization effect between the corresponding phases of different energy storage inverters.

[0070] Continue to see Figure 3On the basis of the above embodiments, optionally, the isolation module 20 includes: an isolation unit 23, a third filtering unit 21, a first pull-up unit 22, a second pull-up unit 25 and a current limiting unit 24. The third filtering unit 21 is connected between the output end of the control module 10 and the first input end of the isolation unit 23, and is used to filter the k-th phase control signal output by the control module 10 and provide it to the isolation unit 23. The first end of the first pull-up unit 22 is connected to the first power signal V1, and the second end of the first pull-up unit 22 is connected to the first input end of the isolation unit 23; the first pull-up unit 22 is used to pull up the first input end of the isolation unit 23 to the potential of the first power signal V1 when the output end of the control module 10 does not output a signal, for example, when the control module 10 in the main synchronous communication component does not output any phase control signal; the first power signal V1, for example, has a high potential, which can be a 3.3V DC voltage. The first output end of the isolation unit 23 is connected to the transmitting end of the CAN processing module 30, and the second input end of the isolation unit is connected to the receiving end of the CAN processing module; the isolation unit 23 is used to isolate the signal connected to its first input end and output it through its first output end, and isolate the signal connected to its second input end and output it through its second output end. The current limiting unit 24 is connected between the second output end of the isolation unit 23 and the input end of the control module 10, and is used to achieve current limiting on the line to avoid damage to the components / chips connected to the relevant line. The first end of the second pull-up unit 25 is connected to the first power supply signal V1, and the second end of the second pull-up unit 25 is connected to the second output end of the isolation unit 23; the second pull-up unit 25 is used to pull up the input end of the control module 10 to the potential of the first power supply signal V1 when the second output end of the isolation unit 23 does not output a signal, for example, when the CAN processing module 30 does not output any phase processing signal or when any phase synchronization carrier signal is not transmitted on the CAN bus.

[0071] Exemplarily, the isolation unit 23 can use different isolation methods, which can be capacitive isolation, optical isolation or magnetic isolation. And, specifically, isolation chips of different widths and different withstand voltages can be selected according to the voltage level of the system to form the isolation unit 23, so as to meet the requirements of safety spacing, creepage distance and withstand voltage test of different voltage level systems. In this synchronous circuit, the isolation module 20 is used in each synchronous communication component 100 to meet the safety requirements. At least one isolation can be set in the isolation module 30, and at least the required isolation is set according to the safety requirements (the safety requirements require that there should be one or double isolation between the place where the hand can touch and the internal high voltage), for example, a 1500V system requires a clearance of 15mm and a creepage of 30mm. The isolation unit 23 may include an isolation chip, and the isolation chip power supply can choose to use 3.3V power supply or 5V power supply, which can be flexibly selected according to actual needs. When the power supply voltage is high, the anti-interference ability of the signal can be increased.

[0072] Continue to see Figure 3 On the basis of the above embodiments, optionally, the CAN processing module 30 includes: a CAN processing unit 31 and a common mode filter unit 32. Among them, the transmitting end of the CAN processing unit 31 is connected to the transmitting end of the CAN processing module 30, and the receiving end of the CAN processing unit 31 is connected to the receiving end of the CAN processing module 30; the CAN processing unit 31 serves as the core transceiver processing component in the CAN processing module 30. The first end of the common mode filter unit 32 is connected to the first communication end of the CAN processing unit 31, the second end of the common mode filter unit 32 is connected to the second communication end of the CAN processing unit 31, the third end of the common mode filter unit 32 is connected to the first communication connection end of the CAN processing module 30, and the fourth end of the common mode filter unit 32 is connected to the second communication connection end of the CAN processing module 30; the common mode filter unit 32 is used to implement signal filtering between the CAN processing unit 31 and the CAN bus.

[0073] Furthermore, the CAN processing module 30 may also include: a first filtering unit 33, a second filtering unit 34 and a lightning protection unit 35. Among them, the first filtering unit 33 is connected between the transmitting end of the CAN processing unit 31 and the transmitting end of the CAN processing module 30; the first filtering unit 33 is used to implement input filtering of the transmitting end of the CAN processing unit 31. The second filtering unit 34 is connected between the receiving end of the CAN processing unit 31 and the receiving end of the CAN processing module 30; the second filtering unit 34 is used to implement output filtering of the receiving end of the CAN processing unit 31. The lightning protection unit 35 is respectively connected to the third end of the common mode filtering unit 32, the fourth end of the common mode filtering unit 32, the first bus LCANH and the second bus LCANL; the lightning protection unit 35 is used to implement lightning protection to prevent surges caused by lightning strikes and other reasons from damaging components inside the synchronous communication component 100.

[0074] Continue to see Figure 3On the basis of the above embodiments, the synchronous communication component 100 may optionally further include: a parallel communication module 50; the parallel communication module 50 is connected to the control module 10, and may be specifically connected to the digital signal processor 11. The parallel communication module 50 of any synchronous communication component 100 is connected to the parallel communication module 50 of other synchronous communication components 100 in communication, so as to realize information interaction between energy storage inverters in the parallel system. Among them, each slave can upload fault information (such as information related to operating faults related to temperature, voltage, current, power and synchronization) to the host through the parallel communication module 50, so that the host can determine the specific fault information in the system. The fault information may specifically include relevant data such as the fault type and the identity information (such as the number) of the energy storage inverter where the fault occurs. Exemplarily, the parallel communication module 50 may include a CAN chip, and may also be replaced by a processing chip with the same or similar functions, such as a single-chip microcomputer with transceiver functions, a digital processor and an analog processing device.

[0075] The above embodiments illustrate the functional modules and their functions in the synchronization circuit. The synchronization communication process in the parallel system is as follows:

[0076] The digital signal processor 11 in the host sends a high-speed synchronization signal to the complex programmable logic device 12 when the count value of the k-th time base counter register corresponding thereto is 0. The complex programmable logic device 12 forms a k-th phase control signal after filtering and delaying logic processing, and sends it from the output end of the control module 10 to the first input end of the isolation module 20. The isolation module 20 isolates the k-th phase control signal to achieve isolation required by safety regulations, and then forms a k-th phase first isolation signal, which is transmitted to the transmitting end of the CAN processing module 30 via the first output end of the isolation module 20. The k-th phase first isolation signal is processed by the CAN processing module 30 to form a k-th phase carrier synchronization signal. The k-th phase carrier synchronization signal is transmitted to the first bus LCANH and the second bus LCANL in the CAN bus in a differential form via the first communication connection end and the second communication connection end of the CAN processing module 30, respectively, to complete the sending of synchronous communication related signals in the host.

[0077] When the slave transmits the k-th phase carrier synchronization signal on the CAN bus, the signal is received. Specifically: the first communication connection end and the second communication connection end of the CAN processing module 30 receive the k-th phase carrier synchronization signal in differential form, perform signal processing to generate the k-th phase processing signal, and transmit it to the second input end of the isolation module 20 via the receiving end of the CAN processing module 30. The isolation module 20 isolates the k-th phase processing signal to generate the k-th phase second isolation signal, and transmits it to the input end of the control module 10 via the second output end of the isolation module 20. In the control module 10, the complex programmable logic 12 performs filtering and delay logic processing on the k-th phase second isolation signal, and sends the processed signal to the digital signal processor 11 for final processing. When the signal processed by the complex programmable logic 12 arrives, the digital signal processor 11 will set the time base counter register to 0 value regardless of the value that the k-th corresponding time base counter register in the current slave has counted to, so as to coordinate the fixed phase difference between the ePWM modules of each channel, so as to achieve the same frequency, amplitude and phase of the AC output of the host and the slave.

[0078] Among them, the synchronous communication component 100 in the host is receiving the signal transmitted on the CAN bus while sending the k-th phase carrier synchronization signal to confirm whether it has completed the signal sending correctly.

[0079] That is, in this synchronization circuit, when the host sends a carrier synchronization signal (for example, a 16kHz signal), the host sends and receives at the same time, and the slave only receives the signal; when the slave receives any phase of the carrier synchronization signal of the host, it takes the rising edge (or falling edge) of the carrier synchronization signal sent by the host as the basis to achieve the same frequency, amplitude and phase operation.

[0080] Exemplarily, a host computer can also be set in the synchronization circuit to realize the unified management of each energy storage inverter. When a slave fails, it can shut down the machine, and report the fault information to the host through the parallel communication module 50, and then the host reports it to the host; in this case, the digital signal processor 11 in the faulty slave can automatically control the faulty slave to leave the parallel system, so that the remaining machines continue to run. When the host fails, the host can report the fault information to the host and wait for manual processing; the digital signal processor 11 in the faulty host can control the faulty host to shut down and leave the parallel system, and at the same time inform the remaining slaves through the parallel communication module 50 to determine a new host through competition, and the rest will continue to run as slaves, or inform the remaining slaves to shut down with the host. Exemplarily, the host can report the fault information to the host through the digital signal processor 11; the host can include at least one of an energy management system (EMS) and a cloud platform.

[0081] The following is an illustrative description of the specific structures that each functional module in the synchronous communication component 100 may have, but it is not intended to limit the present invention.

[0082] Figure 4 is a structural diagram of another synchronous communication component provided by an embodiment of the present invention. Figure 4 The CAN processing unit 31 may include: a CAN chip U1 and a first resistor R1; a receiving pin RXD of the CAN chip U1 serves as a receiving end of the CAN processing unit 31, a transmitting pin TXD of the CAN chip serves as a transmitting end of the CAN processing unit 31, a first communication pin CANH of the CAN chip U1 serves as a first communication end of the CAN processing unit 31, and a second communication pin CHNL of the CAN chip U1 serves as a second communication end of the CAN processing unit 31; a standby control pin STB of the CAN chip U1 is connected to a first end of the first resistor R1, and a second end of the first resistor R2 is connected to a first ground terminal GND1 of the synchronous communication component 100.

[0083] Among them, the first resistor R1 serves as the standby mode selection resistor of the CAN chip U1, and the standby control pin STB, for example, is not in sleep mode when it is set low, and will enter sleep mode after working for a period of time when it is set high. In addition, the CAN chip U1 may also include a power pin VCC, which is connected to the second power signal V2, and the second power signal is, for example, a 5V DC voltage signal, and the power pin VCC can also be connected to the first power supply filter capacitor C3. The CAN chip U1 may also include a ground pin GND, which is connected to the first ground terminal GND1. The CAN chip U1 may also include an empty pin NC, which is connected to the third power signal V3, and the third power signal V3 is, for example, a DC voltage signal with a positive voltage; and the empty pin NC can also be connected to the second power supply filter capacitor C4. Exemplarily, the CAN chip U1 can also be replaced by a processing chip with the same or similar functions, such as a single-chip microcomputer with transceiver functions, a digital processor or an analog processor, etc.

[0084] Continue to see Figure 4 On the basis of the above embodiments, optionally, the common-mode filtering unit 32 includes: a common-mode inductor L1; a first end of the common-mode inductor L1 serves as a first end of the common-mode filtering unit 32, a second end of the common-mode inductor L1 serves as a second end of the common-mode filtering unit 32, a third end of the common-mode inductor L1 serves as a third end of the common-mode filtering unit 32, and a fourth end of the common-mode inductor L1 serves as a fourth end of the common-mode filtering unit 32.

[0085] The first filtering unit 33 includes: a second resistor R2 and a first capacitor C1; the second resistor R2 is connected between the sending pin TXD of the CAN chip U1 and the sending terminal TX of the CAN processing module 30, and the first capacitor C1 is connected between the sending pin TXD of the CAN chip U1 and the first ground terminal GND1.

[0086] The second filtering unit 34 includes: a third resistor R3 and a second capacitor C2; the third resistor R3 is connected between the receiving pin RXD of the CAN chip U1 and the receiving terminal RX of the CAN processing module 30, and the second capacitor C2 is connected between the receiving terminal RX of the CAN processing module 30 and the first ground terminal GND1.

[0087] The lightning protection unit 35 includes: a first bidirectional voltage regulator tube TVS1, a second bidirectional voltage regulator tube TVS2, a third bidirectional voltage regulator tube TVS3, a first thermistor RT1, a second thermistor RT2 and a gas discharge tube DS1; the first bidirectional voltage regulator tube TVS1 is connected between the third end and the fourth end of the common mode filter unit 32; the second bidirectional voltage regulator tube TVS is connected between the third end of the common mode filter unit 32 and the first ground terminal GND1; the third bidirectional voltage regulator tube TVS3 is connected between the fourth end of the common mode filter unit 32 and the first ground terminal GND1; The first thermistor RT1 is connected between the third end of the common mode filter unit 32 and the first communication connection terminal CH (connected to the first bus LCANH) of the CAN processing module 30; the second thermistor RT2 is connected between the fourth end of the common mode filter unit 32 and the second communication connection terminal CL (connected to the second bus) of the CAN processing module 30; the gas discharge tube DS1 is connected between the first communication connection terminal CH and the second communication connection terminal CL of the CAN processing module 30, that is, connected between the first bus LCANH and the second bus LCANL. Among them, the bidirectional voltage regulator can be composed of two transient suppression diodes connected anode to anode.

[0088] The specific working process of the CAN processing module 30 is as follows:

[0089] After the first output terminal OUT1 of the isolation module 20 outputs the first isolation signal of the kth phase, the first isolation signal of the kth phase enters the sending pin TXD of the CAN chip U1 after low-pass filtering through the second resistor R2 and the first capacitor C1, and is processed by the CAN chip U1 into a differential signal and output from the first communication pin CANH and the second communication pin CANL of the CAN chip U1. The differential signal passes through the common-mode filtering of the common-mode inductor L1, and then passes through the second bidirectional voltage regulator tube TVS2, the first bidirectional voltage regulator tube TVS1, the first thermistor RT1 and the gas discharge tube DS1 for lightning protection to form the kth phase carrier synchronization signal, which is sent to the CAN bus and appears as a dominant level or an invisible level.

[0090] The k-th phase carrier synchronization signal transmitted on the CAN bus passes through the lightning protection of the gas discharge tube DS1, the second thermistor RT2, the first bidirectional voltage regulator TVS1 and the third bidirectional voltage regulator TVS3, and then passes through the common-mode filtering of the common-mode inductor L1, and then enters the first communication pin CANH and the second communication pin CANL of the CAN chip U1 for signal reception. The signal received and processed by the CAN chip U1 is output from the receiving pin RXD of the CAN chip U1 and passes through the low-pass filtering of the third resistor R3 and the second capacitor C2 to form the k-th phase processed signal transmitted to the second input terminal IN2 of the isolation module 30.

[0091] Continue to see Figure 4 On the basis of the above embodiments, optionally, in the isolation module 30, the first pull-up unit 22 includes a fourth resistor R4; the first end of the fourth resistor R4 is connected to the first power signal V1, and the second end of the fourth resistor R4 is connected to the first input end of the isolation unit 23. The third filtering unit 21 includes a fifth resistor and a fifth capacitor; the fifth resistor R5 is connected between the first input end IN1 of the isolation module 20 and the first input end of the isolation unit 23, and the fifth capacitor C5 is connected between the first input end of the isolation unit 23 and the second grounding end GND2 of the synchronous communication component. Among them, the first grounding end GND1 and the second grounding end GND2 of the synchronous communication component 100 are different grounding ends, which are respectively used to provide ground signals to the components on both sides of the isolation module 20. The current limiting unit 24 includes a sixth resistor R6, which is connected between the second output end OUT2 of the isolation module 20 and the second output end of the isolation unit 23. The second pull-up unit 25 includes a seventh resistor R7; the first end of the seventh resistor R7 is connected to the first power signal V1, and the second end of the seventh resistor R7 is connected to the second output end of the isolation unit 23.

[0092] In the isolation module 30, by setting two pull-up units, when there is no carrier synchronization signal transmission in the system, the input terminal Fdb of the CAN bus and the control module 10 can be kept at a high level. For the data transmission path from the control module 10 to the CAN bus, the k-th phase control signal enters the first input terminal of the isolation unit 23 for processing after filtering by the fifth resistor R5 and the fifth capacitor C5, and outputs the k-th phase first isolation signal at the first output terminal of the isolation unit 23. For the data transmission path from the CAN bus to the control module 10, the k-th phase processing signal enters the isolation unit 23 from the second input terminal of the isolation unit 23 for isolation processing, and is output from the second output terminal of the isolation unit 23 after the processing is completed, and forms the k-th phase second isolation signal after current limiting by the sixth resistor R6, and is transmitted to the control module 10 for receiving, judging and processing.

[0093] In the above embodiments, each filter unit is exemplarily given as a first-order RC low-pass filter structure, but this is not intended to limit the present invention. In other embodiments, any filter unit can also be set as a first-order filter circuit of other structures, a multi-order filter circuit or a digital filter circuit, etc. according to requirements.

[0094] Figure 5 is a structural schematic diagram of another synchronous circuit of an energy storage inverter parallel system provided by an embodiment of the present invention. Figure 5 Each synchronous communication component 100 also includes an external interface module 40 , and each synchronous communication component 100 is connected to the CAN bus via the external interface module 40 .

[0095] The external interface module 40 may include a first external interface P1 and a second external interface P2; the second external interface P2 of each synchronous communication component 100 is connected to the first external interface P1 of the next synchronous communication component 100 to form a hand-in-hand connection structure.

[0096] For details, see Figure 4 In any synchronous communication component 100, the first external interface P1 may include a first contact J1 and a second contact J2, and the second external interface P2 may include a third contact J3 and a fourth contact J4; the first bus LCANH connects the first contact J1 and the third contact J3 in each synchronous communication component in the order of the first contact J1 in the first synchronous communication component, the third contact J3 in the first synchronous communication component, the first contact J1 in the second synchronous communication component, the third contact J3 in the second synchronous communication component, until the first contact J1 in the last synchronous communication component and the third contact J3 in the last synchronous communication component; the second bus LCANL connects the second contact J2 and the fourth contact J4 in each synchronous communication component in the order of the second contact J2 in the first synchronous communication component, the fourth contact J4 in the first synchronous communication component, the second contact J2 in the second synchronous communication component, the fourth contact J4 in the second synchronous communication component, until the second contact J2 in the last synchronous communication component and the fourth contact J4 in the last synchronous communication component. In the same synchronous communication component, the first communication connection terminal CH of the CAN processing module 30 can be connected to the first connection point J1, and the second communication connection terminal CL of the CAN processing module 30 can be connected to the fourth connection point J4.

[0097] Continue to see Figure 5, based on the above embodiments, optionally, the synchronous circuit of the energy storage inverter parallel system also includes: a first matching resistor RP1 and a second matching resistor RP2. Among them, the first matching resistor RP1 is connected between the head end of the first bus LCANH and the head end of the second bus LCANL; the second matching resistor RP2 is connected between the end of the first bus LCANH and the end of the second bus LCANL. Specifically, the first matching resistor RP1 can be connected between the first contact J1 and the second contact J2 in the first external interface P1 of the first synchronous communication component 100; the second matching resistor RP2 can be connected between the third contact J3 and the fourth contact J4 in the second external interface P2 of the last synchronous communication component 100. However, the above connection method is not intended to limit the present invention. The first matching resistor RP1 and the second matching resistor RP2 are respectively connected to the first external interface P1 of one synchronous communication component 100 and the second external interface P2 of another synchronous communication component 100, so as to achieve impedance matching in communication. Exemplarily, the first matching resistor RP1 and the second matching resistor RP2 are both matching resistors of 120Ω.

[0098] Continue to see Figure 5 On the basis of the above-mentioned embodiments, optionally, the synchronous circuit of the energy storage inverter parallel system also includes: a host computer for realizing unified control of each energy storage inverter. The host computer can be connected to the control module 10 in each synchronous communication component 100, and can be specifically connected to the digital signal processor 11. The host computer can include at least one of the cloud platform 200 and the energy management system 300. The structures of each synchronous communication component 100 are consistent, and one of the energy storage inverters in the parallel system can be selected as the host, and the others can be selected as slaves.

[0099] In summary, the embodiment of the present invention provides a parallel synchronization solution for energy storage inverters, which is particularly conducive to achieving high-speed carrier synchronization between multiple machines, making multiple machines run in unison, achieving the same frequency, amplitude and phase on the inverter side, eliminating the influence of circulating current between machines, achieving the parallel operation of multiple energy storage inverters, and achieving high-power output of multiple parallel machines to meet market demand. Moreover, the carrier synchronization signal in the embodiment of the present invention has a long transmission distance and strong anti-interference ability, and can achieve frequency operation between 250Hz-2MHz, and can simultaneously meet the requirements of outdoor lightning protection and safety spacing dual isolation, and the circuit operation is stable and reliable. This synchronization circuit can be applied to a parallel project of 12 energy storage inverters, for example.

[0100] An embodiment of the present invention further provides a synchronization method for a parallel energy storage inverter system, which is applied to a synchronization circuit for a parallel energy storage inverter system provided by any embodiment of the present invention and has corresponding beneficial effects. Figure 6 Schematic diagram of a synchronization method of a parallel energy storage inverter system provided by an embodiment of the present invention. Figure 6 The synchronization method of the energy storage inverter parallel system includes the following steps:

[0101] S110 , when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0, the main synchronous communication component sends a k-th phase carrier synchronization signal to the CAN bus.

[0102] S120. For any slave synchronous communication component, when the slave synchronous communication component receives the k-th phase carrier synchronization signal transmitted on the CAN bus, the count value of the k-th corresponding time base counter register in the slave synchronous communication component is set to 0.

[0103] The synchronization method of the energy storage inverter parallel system provided by the embodiment of the present invention adopts the CAN bus to realize the transmission of the carrier synchronization signal, which is conducive to realizing high-speed carrier synchronization between multiple machines and making multiple energy storage inverters run in unison. Specifically, when the count value of any phase time base counter register in the master synchronous communication component is 0, the corresponding phase carrier synchronization signal is sent to the CAN bus; when the slave synchronous communication component receives any phase carrier synchronization signal, no matter what value the internal corresponding phase time base counter register has currently counted to, it forces the count value to be set to 0, so that each ePWM module works with the same time reference, and the ePWM module in the slave can control the output phase of the phase in the slave to be the same as that in the master. Therefore, the embodiment of the present invention can coordinate the corresponding phase relationship between each ePWM module through each synchronous communication component, based on the CAN protocol to stably transmit the carrier synchronization signal, which is conducive to achieving the same frequency, amplitude and phase of each phase AC output on the inverter side of the master and each slave, avoiding the damage of the energy storage inverter due to the circulation between the machines caused by the asynchronous operation, and ensuring the operation reliability and safety of the parallel system.

[0104] On the basis of the above embodiments, optionally, the CAN bus includes a first bus and a second bus, and the synchronous communication component includes: a control module, an isolation module and a CAN processing module connected in sequence, and the CAN processing module connects the first bus and the second bus.

[0105] Accordingly, the above S110 specifically includes the following steps:

[0106] 1) The control module of the main synchronous communication component outputs the k-th phase control signal when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0.

[0107] 2) The isolation module of the main synchronous communication component isolates the k-th phase control signal to generate a k-th phase first isolation signal.

[0108] 3) The CAN processing module of the main synchronous communication component processes the k-th phase first isolation signal and outputs the k-th phase carrier synchronization signal in a differential form to the first bus and the second bus.

[0109] The above S120 specifically includes the following steps:

[0110] 1) A CAN processing module of a slave synchronous communication component receives a k-th phase carrier synchronization signal from a first bus and a second bus and processes and generates a k-th phase processed signal.

[0111] 2) The isolation module of the synchronous communication component isolates the k-th phase processing signal to generate a k-th phase second isolation signal.

[0112] 3) When receiving the k-th phase second isolation signal, the control module of the slave synchronous communication component sets the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0.

[0113] On the basis of the above-mentioned embodiments, optionally, in the synchronization method of the energy storage inverter parallel system, the main synchronous communication component sends the k-th phase carrier synchronization signal to the CAN bus while also receiving the signal transmitted on the CAN bus; when the main synchronous communication component receives the k-th phase carrier synchronization signal, it confirms that the k-th phase carrier synchronization signal has been sent successfully.

[0114] Based on the above embodiments, optionally, the synchronization circuit of the energy storage inverter parallel system further includes: a host computer; the synchronization communication component includes: a control module and a parallel communication module; the control modules of each synchronization communication component are connected to the host computer. The synchronization method of the energy storage inverter parallel system also includes:

[0115] When the control module of the master synchronous communication component detects a master fault, it uploads the master fault information to the host computer. At the same time, the control module in the master synchronous communication component can also control the master to shut down, and send fault-related control commands to each slave through the parallel communication module, such as controlling each slave to shut down, or informing each slave to compete for a new master.

[0116] When the control module of the slave synchronous communication component detects a fault in the slave, it uploads the fault information of the slave to the control module of the master synchronous communication component through the parallel communication module of the slave synchronous communication component and the parallel communication module of the master synchronous communication component, and the control module of the master synchronous communication component uploads the fault information of the slave to the host computer. While uploading the fault information of the slave to the host, the control module of the slave synchronous communication component can also control the shutdown of the slave.

[0117] Exemplarily, the generation, transmission and analysis of the above fault-related signals in each synchronous communication component can be performed by a digital signal processor in the control module. It is understandable that after the energy storage inverter is shut down, the inverter-related functions can be stopped, but the various control components therein can continue to operate, for example, the control module 10 can continue to operate.

[0118] In order to verify the synchronous communication effect of the above parallel system, the inventor conducted an experimental verification of the synchronous circuit. The verification results can be found in Figure 7 and Figure 8 .in, Figure 7 The waveforms of the synchronous carrier signal LM received by the host and the synchronous carrier signal LS received by the slave having the largest time difference with the signal received by the host are shown when the 12 energy storage inverters actually tested are in parallel operation, wherein the lower half is an enlarged schematic diagram of the rectangular frame in the upper half; Figure 7 In order to capture the time difference, the brightness function of the oscilloscope is used to display the received signal brightness overlay. Figure 7 In the experiment, the time difference △T between the rising edge of the synchronization carrier signal LM received by the host and the rising edge of the synchronization carrier signal LS received by the slave is 69.1ns. For carrier synchronization, the baud rate is usually 500Kbt / s, and one cycle takes 4us. For 12 machines in parallel, as long as the time difference between the synchronization signals does not exceed 1us, they can be well synchronized, and almost no circulating current is generated; the above experimental results show that the maximum time difference between the host and the slave receiving signals is 69.1ns, which is much less than 1us. This time difference has almost no effect on the synchronization effect, and the parallel system can achieve a good synchronization effect. Figure 8 It is the actual test waveform on the high-speed synchronous parallel CAN bus when 12 units are running in parallel, specifically the waveform of the voltage difference between the first bus and the second bus, where the lower half is the enlarged schematic diagram in the rectangular box in the upper half; the waveform frequency used in the experiment is a switching frequency of 17kHz, it can be seen that the signal on the CAN bus can be transmitted stably and correctly.

[0119] In addition, the inventors also conducted statistics on the rising edge time delay between each slave receiving the carrier synchronization signal and the master sending the synchronization carrier signal, as well as the falling edge time delay between each slave receiving the carrier synchronization signal and the master sending the synchronization carrier signal in a parallel system with 12 slaves. The statistical results can be seen in Table 1.

[0120] Table 1

[0121] Signal transmission and reception relationship Rising edge time delay / us Falling edge time delay / us Master sends - Slave 1 receives 0.47 0.09 Master sends - Slave 2 receives 0.46 0.14 Master sends - Slave 3 receives 0.43 0.16 Master sends - slave 4 receives 0.43 0.165 Master sends - slave 5 receives 0.42 0.185 Master sends - slave 6 receives 0.42 0.195 Master sends - slave 7 receives 0.425 0.205 Master sends - slave 8 receives 0.385 0.23 Master sends - slave 9 receives 0.38 0.245 Master sends - slave 10 receives 0.425 0.27 Master sends - slave 11 receives 0.42 0.27 Master sends - slave 12 receives 0.425 0.275

[0122] As shown in Table 1, in actual operation, the rising edge delay and falling edge delay between the carrier synchronization signal received by each slave and the synchronization carrier signal sent by the master are both less than 1us. Based on the consistency of signal sending and receiving data on the CAN bus, a good parallel synchronization effect can be achieved.

[0123] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0124] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A synchronous circuit of an energy storage inverter parallel system, characterized in that: include: CAN bus; A plurality of synchronous communication components, all connected to the CAN bus; Each of the synchronous communication components is respectively arranged in each energy storage inverter in the energy storage inverter parallel system; the energy storage inverter has at least one phase output signal, the synchronous communication component includes an ePWM module, the ePWM module includes corresponding time base counter registers, and the ePWM module is used to control the phase of the corresponding phase output signal in the energy storage inverter according to the count value of each corresponding time base counter register; Among them, one of the energy storage inverters in the energy storage inverter parallel system is a host, and the rest are slaves; the synchronous communication component in the host is a master synchronous communication component, and the synchronous communication component in the slave is a slave synchronous communication component; the master synchronous communication component is used to send a k-phase carrier synchronization signal to the CAN bus when the count value of the k-th corresponding time base counter register in the master synchronous communication component is 0; each of the slave synchronous communication components is used to set the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0 when receiving the k-th phase carrier synchronization signal transmitted on the CAN bus, and k is a positive integer.

2. The synchronous circuit of the energy storage inverter parallel system according to claim 1, characterized in that: The CAN bus includes a first bus and a second bus; the synchronous communication component includes: a control module, an isolation module and a CAN processing module; The control module includes the ePWM module; the output end of the control module is connected to the first input end of the isolation module, the first output end of the isolation module is connected to the transmitting end of the CAN processing module, the first communication connection end of the CAN processing module is connected to the first bus, the second communication end of the CAN processing module is connected to the second bus, the receiving end of the CAN processing module is connected to the second input end of the isolation module, and the second output end of the isolation module is connected to the input end of the control module.

3. The synchronous circuit of the energy storage inverter parallel system according to claim 2, characterized in that: The CAN processing module includes: A CAN processing unit, wherein a transmitting end of the CAN processing unit is connected to a transmitting end of the CAN processing module, and a receiving end of the CAN processing unit is connected to a receiving end of the CAN processing module; A common mode filtering unit, wherein a first end of the common mode filtering unit is connected to a first communication end of the CAN processing unit, a second end of the common mode filtering unit is connected to a second communication end of the CAN processing unit, a third end of the common mode filtering unit is connected to a first communication connection end of the CAN processing module, and a fourth end of the common mode filtering unit is connected to a second communication connection end of the CAN processing module.

4. The synchronous circuit of the energy storage inverter parallel system according to claim 3, characterized in that: The CAN processing module also includes: A first filtering unit, connected between a transmitting end of the CAN processing unit and a transmitting end of the CAN processing module; a second filtering unit connected between a receiving end of the CAN processing unit and a receiving end of the CAN processing module; The lightning protection unit is respectively connected to the third end of the common mode filtering unit, the fourth end of the common mode filtering unit, the first bus and the second bus.

5. The synchronous circuit of the energy storage inverter parallel system according to claim 4, characterized in that: The CAN processing unit comprises: a CAN chip and a first resistor; a receiving pin of the CAN chip serves as a receiving end of the CAN processing unit, a sending pin of the CAN chip serves as a sending end of the CAN processing unit, a first communication pin of the CAN chip serves as a first communication end of the CAN processing unit, and a second communication pin of the CAN chip serves as a second communication end of the CAN processing unit; a standby control pin of the CAN chip is connected to a first end of the first resistor, and a second end of the first resistor is connected to a first ground end of the synchronous communication component; The common mode filtering unit comprises: a common mode inductor; The first filtering unit includes: a second resistor and a first capacitor; the second resistor is connected between the sending pin of the CAN chip and the sending end of the CAN processing module, and the first capacitor is connected between the sending pin of the CAN chip and the first grounding end; The second filtering unit includes: a third resistor and a second capacitor; the third resistor is connected between the receiving pin of the CAN chip and the receiving end of the CAN processing module, and the second capacitor is connected between the receiving end of the CAN processing module and the first grounding end; The lightning protection unit includes: a first bidirectional voltage regulator, a second bidirectional voltage regulator, a third bidirectional voltage regulator, a first thermistor, a second thermistor and a gas discharge tube; the first bidirectional voltage regulator is connected between the third end and the fourth end of the common mode filter unit; the second bidirectional voltage regulator is connected between the third end of the common mode filter unit and the first ground end; the third bidirectional voltage regulator is connected between the fourth end of the common mode filter unit and the first ground end; the first thermistor is connected between the third end of the common mode filter unit and the first bus; the second thermistor is connected between the fourth end of the common mode filter unit and the second bus; the gas discharge tube is connected between the first bus and the second bus.

6. The synchronous circuit of the energy storage inverter parallel system according to claim 2, characterized in that: The control module includes: a digital signal processor and a complex programmable logic device; the ePWM module is arranged in the digital signal processor, the digital signal processor is connected to the complex programmable logic device, and the complex programmable logic device is respectively connected to the input end and the output end of the control module; And / or, the isolation module includes: an isolation unit, a third filtering unit, a first pull-up unit, a second pull-up unit and a current limiting unit; the third filtering unit is connected between the output end of the control module and the first input end of the isolation unit, the first end of the first pull-up unit is connected to the first power supply signal, the second end of the first pull-up unit is connected to the first input end of the isolation unit, and the first output end of the isolation unit is connected to the transmitting end of the CAN processing module; the second input end of the isolation unit is connected to the receiving end of the CAN processing module, the current limiting unit is connected between the second output end of the isolation unit and the input end of the control module, the first end of the second pull-up unit is connected to the first power supply signal, and the second end of the second pull-up unit is connected to the second output end of the isolation unit; And / or, the synchronous communication component further includes: a parallel communication module; the parallel communication module is connected to the control module; the parallel communication module of any of the synchronous communication components is communicatively connected to the parallel communication modules of other synchronous communication components.

7. The synchronous circuit of the energy storage inverter parallel system according to claim 1, characterized in that: The synchronous communication component further includes: an external interface module, including a first external interface and a second external interface; each of the synchronous communication components is connected to the CAN bus through the external interface module, and the second external interface of each synchronous communication component is connected to the first external interface of the next synchronous communication component to form a hand-in-hand connection structure; And / or, the CAN bus includes a first bus and a second bus, and the synchronous communication component connects the first bus and the second bus; the synchronization circuit of the energy storage inverter parallel system also includes: A first matching resistor connected between a first end of the first bus and a first end of the second bus; The second matching resistor is connected between an end of the first bus and an end of the second bus.

8. A synchronization method for a parallel energy storage inverter system, characterized in that: A synchronization circuit for an energy storage inverter parallel system according to any one of claims 1 to 7; a synchronization method for the energy storage inverter parallel system comprising: The main synchronous communication component sends a k-th phase carrier synchronization signal to the CAN bus when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0; For any of the slave synchronous communication components, when the slave synchronous communication component receives the k-th phase carrier synchronization signal transmitted on the CAN bus, the slave synchronous communication component sets the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0.

9. The synchronization method of the energy storage inverter parallel system according to claim 8, characterized in that: The CAN bus includes a first bus and a second bus, and the synchronous communication component includes: a control module, an isolation module and a CAN processing module connected in sequence, and the CAN processing module connects the first bus and the second bus; The main synchronous communication component sends a k-phase carrier synchronization signal to the CAN bus when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0, including: The control module of the main synchronous communication component outputs a k-th phase control signal when the count value of the k-th corresponding time base counter register in the main synchronous communication component is 0; The isolation module of the main synchronous communication component isolates the k-th phase control signal to generate a k-th phase first isolation signal; The CAN processing module of the main synchronous communication component processes the k-th phase first isolation signal and outputs the k-th phase carrier synchronization signal in differential form to the first bus and the second bus; When the slave synchronous communication component receives the k-th phase carrier synchronization signal transmitted on the CAN bus, the count value of the k-th corresponding time base counter register in the slave synchronous communication component is set to 0, including: The CAN processing module of the slave synchronous communication component receives the k-th phase carrier synchronization signal from the first bus and the second bus and processes and generates a k-th phase processing signal; The isolation module of the slave synchronous communication component isolates the k-th phase processing signal to generate a k-th phase second isolation signal; When receiving the k-th phase second isolation signal, the control module of the slave synchronous communication component sets the count value of the k-th corresponding time base counter register in the slave synchronous communication component to 0.

10. The synchronization method of the energy storage inverter parallel system according to claim 8, characterized in that: The main synchronous communication component receives a signal transmitted on the CAN bus while sending the k-th phase carrier synchronization signal to the CAN bus; when the main synchronous communication component receives the k-th phase carrier synchronization signal, it confirms that the k-th phase carrier synchronization signal is successfully sent; And / or, the synchronization circuit of the energy storage inverter parallel system further includes: a host computer; the synchronous communication component includes: a control module and a parallel communication module; the control modules of each of the synchronous communication components are connected to the host computer; The synchronization method of the energy storage inverter parallel system also includes: When the control module of the main synchronous communication component detects a host failure, the host failure information is uploaded to the host computer; When the control module of the slave synchronous communication component detects a fault in the slave machine, the control module of the slave synchronous communication component uploads the slave fault information to the control module of the master synchronous communication component through the parallel communication module of the slave synchronous communication component and the parallel communication module of the master synchronous communication component, and the control module of the master synchronous communication component uploads the slave fault information to the host computer.

Images