Programmable gain amplifier
By introducing a gain-regulating resistor feedback circuit, preamplifier and offset voltage cancellation module into the programmable gain amplifier, the problem of difficulty in reducing the PGA input offset voltage in traditional technology is solved, and automatic offset voltage cancellation and high-precision signal acquisition are achieved.
Patent Information
- Application Number
- CN202411980677.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-02
AI Technical Summary
The prior art is difficult to effectively reduce the input offset voltage of programmable gain amplifier (PGA) in biological signal acquisition systems, especially in applications such as brain-computer interfaces. Traditional chopping technology cannot reduce the offset voltage below microvolts.
The programmable gain amplifier design is adopted, including a main operational amplifier, a gain-regulating resistor feedback circuit, a pre-amplifier, a offset voltage cancellation module and a compensation resistor module. Through components such as latch comparator, digital control logic circuit and current rudder, the offset voltage is automatically detected and eliminated, and the equivalent resistance of the compensation resistor module is gradually adjusted.
Automatic offset voltage cancellation is achieved, which can reduce offset voltage below microvolts, improve the accuracy and efficiency of signal acquisition, and avoid the inefficiency of manual measurement and elimination.
Smart Images
Figure CN119921699A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a programmable gain amplifier. Background Art
[0002] With the rapid development of electronic technology, the application fields of integrated circuits are becoming more and more extensive, among which the biomedical field is an important direction. Especially in the field of biological signal acquisition, integrated circuit technology plays a vital role.
[0003] Programmable gain amplifier (PGA) is a key component of biological signal acquisition system. In biological signal acquisition system, fixed gain will cause large signal to enter nonlinear working area and may cause amplified signal to exceed the range of data acquisition. Therefore, the use of programmable gain amplifier can make channel gain controllable and avoid the above problems. However, due to the inevitable device mismatch in the integrated circuit manufacturing process, PGA usually has an input offset voltage as high as millivolt level without any processing. When PGA is applied to biological signal acquisition system, its offset voltage will cause serious signal acquisition error. In severe cases, the offset voltage may even cause PGA output saturation and fail to effectively amplify the input signal. In applications such as brain-computer interface, the input offset voltage of PGA usually needs to be less than 1 microvolt to meet the high-precision acquisition requirements of weak EEG signals. Therefore, in the design of PGA for biological signal acquisition, offset voltage suppression technology must be introduced.
[0004] Currently, offset voltage suppression is achieved by manual elimination or through chopping technology. Manual elimination requires testing of each chip and eliminating the offset voltage based on the test results. Manual elimination is inefficient. At the same time, random fluctuations in manufacturing process parameters will cause large fluctuations in the PGA offset voltage. Low power consumption requirements will also increase the offset voltage. Traditional chopping technology alone cannot reduce the offset voltage to below microvolts. Summary of the invention
[0005] Based on the defects of the above-mentioned prior art, the present invention provides a programmable gain amplifier, which solves the problem that the existing manual elimination of offset voltage is inefficient and the traditional chopping technology cannot reduce the offset voltage below microvolts.
[0006] The present invention adopts the following technical solutions:
[0007] The present invention provides a programmable gain amplifier, comprising:
[0008] The main operational amplifiers OP1 and OP2, the non-inverting input terminal of OP1 is used to input the positive voltage V ip OP2’s non-inverting input is used to input the reverse voltage V in ;
[0009] Two compensation resistance modules, one end of one compensation resistance module is connected to the inverting input end of OP1, and one end of the other compensation resistance module is connected to the inverting input end of OP2, and the compensation resistance module is used to generate an equivalent resistance;
[0010] The gain adjustment resistor feedback circuit includes two feedback resistors R1 and one feedback resistor R2, wherein two ends of the feedback resistor R2 are respectively connected to the other ends of the two compensation resistor modules, and two ends of the feedback resistor R2 are also connected to one end of the two feedback resistors R1, and the other ends of the two feedback resistors R1 are respectively connected to the output ends of OP1 and OP2, and the gain of the PGA is configured by adjusting the feedback resistors R1 and R2;
[0011] A pre-amplifier OP3, wherein an input end of the pre-amplifier OP3 is connected to the other end of the two feedback resistors R1 and the output ends of the main operational amplifiers OP1 and OP2, and is used to amplify the offset voltage;
[0012] The offset voltage elimination module includes a latch comparator COMP1, a digital control logic circuit and two current rudders, wherein the input end of the latch comparator COMP1 is connected to the output end of the pre-amplifier, and is used to judge the positive or negative of the offset voltage after amplification according to the voltages V1 and V2 at both ends of the feedback resistor R2; the input end of the digital control logic circuit is connected to the output end of the latch comparator COMP1, and is used to receive the offset voltage and determine the direction of the compensation current according to the positive or negative of the offset voltage; the current rudder is used to generate a compensation current according to the direction of the compensation current; the output end of the digital control logic circuit is connected to two compensation resistor modules, and is used to continuously adjust the equivalent resistance of the compensation resistor modules by successive approximation, and the compensation current is input to the two compensation resistor modules to eliminate the offset voltage.
[0013] Preferably, the output end of the digital control logic circuit is also connected to transmission gates TG1, TG2, TG3 and TG4 and the input end of the supplementary module, the output end of the supplementary module is connected to two current rudder input ends, and the two current rudder output ends are respectively connected to transmission gates TG1 and TG2 and TG3 and TG4.
[0014] Preferably, the main operational amplifiers OP1 and OP2 have the same structure, and both include NMOS tubes NM1, NM2a, NM2b, NM3a, NM3b, NM4a, NM4b, NM6, NM5a and NM5b, and PMOS tubes PM1, PM2a, PM2b, PM3a, PM3b, PM4a, PM4b, PM6, PM5a and PM5b; the sources of the PMOS tubes PM3a and PM3b are both connected to the supply voltage VDD, and their gates are connected to each other and connected to the node A or D through the chopper switch CHOP2; the gate of the PMOS tube PM6 is connected to the node A or D through the chopper switch CHOP2, the source is connected to the supply voltage VDD, and the drain is connected to the source of NM6; the gates of PM4a and PM4b are both loaded with the bias voltage V BP2 The source of the PMOS tube PM1 is connected to the supply voltage VDD, the drain is connected to the drains of the PMOS tubes PM2a and PM2b, and the gate is loaded with a bias voltage V BP1 ; The source of NMOS tube NM1 is grounded, the drain is connected to the source of NMOS tube NM2a, and the gate is loaded with bias voltage V BN1 ; The sources of NMOS tubes NM2a and NM2b are connected to the drain of NMOS tube NM1, the drain of NM2a is connected to the drain of PMOS tube PM3a, and the drain of NM2b is connected to the source of PMOS tube PM4b; the sources of PMOS tubes PM4a and PM4b are connected to the drains of PMOS tubes PM3a and PM3b respectively; the drain of PM4a is connected to node D, and the drain of PM4b is connected to node A, and the gates of both are loaded with bias voltage V BP2 The sources of NMOS tubes NM4a and NM4b are connected to the drains of NMOS tubes NM3a and NM3b respectively, the drain of NM4a is connected to the drain of PMOS tube PM5a, the drain of NM4b is connected to the drain of PMOS tube PM5b, and the gates of NM4a and NM4b are both loaded with bias voltage V BN2 The sources of PMOS tubes PM5a and PM5b are connected to nodes D and A respectively, the drain of PM5a is connected to node C, the drain of PM5b is connected to node B, and the gates of both are loaded with bias voltage V BP3 The sources of NMOS tubes NM3a and NM3b are both grounded, the drain of NM3a is connected to the source of NM4a, the drain of NM3b is connected to the source of NM4b, the gates of NM3a and NM3b are connected to node B or C through the chopper switch CHOP3, the gate of NMOS tube NM6 is connected to node B or node C through the chopper switch, and the source is connected to the drain of transistor PM6; resistor R z1 With capacitor C C1 Connect in series, with the two ends connected to the gate and drain of PM6 respectively; resistor R z2 With capacitor C C2Connect in series, with the two ends connected to the gate and drain of NM6 respectively.
[0015] Preferably, the preamplifier includes PMOS tubes PM7a and PM7b, whose sources are both loaded with supply voltage VDD and whose gates are both loaded with bias voltage V BP5 , whose drains are connected to the sources of NMOS tubes NM8a and NM8b respectively; the gate of PMOS tube PM8a is connected to the loading signal V through transmission gates TG5 and TG6. in or V ip connected, the gate of PM8b is connected to the load signal V in The drains of the two are connected to the sources of NM8a and NM8b respectively, and the sources are connected to the drain of PMOS tube PM10; the sources of NM8a and NM8b are connected to the drains of NM7a and NM7b respectively, and the gates are loaded with bias voltage V BN5 The sources of PMOS tubes PM9a and PM9b are connected to the supply voltage VDD, the drains are connected to the drains of NM9a and NM9b, and the gates are connected to their own drains; the sources of NM9a and NM9b are grounded, and the gates are connected to the supply voltage VDD / 2 and the voltage V A 、V B The average voltage of the PMOS tube PM10; the source of the PMOS tube PM10 is connected to the supply voltage VDD, and the gate load voltage V BP4 , the drain is connected to the source of PM8a and PM8b; the drain of NMOS tube NM11 is connected to the source of NM9a and NM9b, the source is connected to the ground, and the gate is loaded with a bias voltage V BN4 ; Capacitor C 1a One end and node V A connected, and the other end connected to the output V outp ; Capacitor C 1b One end and node V b connected, and the other end connected to the output V outp The drains of NMOS tubes NM10a and NM10b are connected to capacitors C 1a and C 1b The gate is connected to the resistor R 1a With R 1b connected.
[0016] Preferably, the latch comparator includes a PMOS tube PM11, whose source is connected to the supply voltage VDD, the drain is connected to the node B, and the gate is connected to the node A; the source of the PMOS tube PM12 is connected to the supply voltage VDD, the drain is connected to the node A, and the gate is connected to the node B; the source of the PMOS tube PM13 is connected to the supply voltage VDD, the drain is connected to the clock signal CLK_N loading point, and the gate is loaded with the clock signal CLK; the source of the PMOS tube PM14 is connected to the supply voltage VDD, the drain is connected to the input of the inverter, and the gate is connected to the clock signal CIK_N; the drain of the NMOS tube NM15 is connected to the node B, the source is connected to the drain of the NMOS tube NM13, and the gate is connected to the node A; the drain of the NMOS tube NM16 is connected to the node A, the source is connected to the drain of the NMOS tube NM3, and the gate is connected to the node B; the source of the NMOS tube NM12 is grounded, the drain is connected to the common source node of the NMOS tubes NM15 and NMOS tubes NM16, and the gate is loaded with the clock signal CIK_N. LK_N; the source of the NMOS tube NM13 is grounded, the drain is connected to the node B, and the gate is loaded with the input signal; the source of the NMOS tube NM14 is grounded, the drain is connected to the node A, and the gate is loaded with the input signal V; the logic circuit part includes two inverters, the input of the first inverter is connected to the drain of the PMOS tube PM15, and the output signal is Q; the input of the second inverter is connected to the drain of the PMOS tube PM14, and the output signal is QN; the input of the AND gate is the signals Q and QN, and the output signal is Valid, which is used to indicate the validity of the logic state, the input signals include V loaded on the gate of the NMOS tube NM15, V loaded on the gate of the NMOS tube NM16, the clock signal CLK loaded on the gate of the PMOS tube PM13, and the clock signal CLK_N loaded on the gate of the PMOS tube PM14 and the gate of the NMOS tube NM12, the output signal includes Q generated by the first inverter, QN generated by the second inverter, and Valid generated by the AND gate, which is used to indicate the validity of the logic state.
[0017] Preferably, the digital control logic circuit is composed of a plurality of cascaded triggers, the clock input of each trigger is loaded with clock signals CLK10-CLK0 respectively, the input terminal D receives the output Q or control signal of the previous stage trigger, and finally drives the output signal TRIM <0> -TRIM <n>; Each trigger is provided with a reset terminal Reset and a set terminal Set, which are initialized or cleared by external control; the direction control logic is formed by the input signals Direction, DirectionN and the comparison signal Comp through logic gates to realize direction selection, wherein the comparison signal Comp is inverted and input into the AND gate together with the signal DirectionN to form the control logic; the input valid signal Valid enters the trigger array after being processed by the delay module DELAY, and the delay module is used to synchronize and delay the signal; the NPG circuit is located in each level of the clock path, respectively connected to CLK10-CLK0, for adjusting and distributing the clock signal; the digital output enable signal Digital_EN is generated by the trigger cascade, and is used to control the logic validity and operation status of the subsequent circuit.
[0018] Preferably, the current steering includes a PMOS tube PM15, whose source is connected to the power supply VDD, the gate is connected to the drain of PM16, and at the same time, its drain is connected to the drain of PM18; the gate of the PMOS tube PM16 is connected to the drain of PM15, and at the same time, its drain is connected to the drain of PM17, and the source is connected to the supply voltage VDD; the source of the PMOS tube PM17 is connected to the supply voltage VDD, the drain is connected to the drain of the NMOS tube NM20, and the gate is loaded with the signal CLK_N after the clock signal passes through the inverter; the drain of the PMOS tube PM18 is connected to the drain of the NMOS tube NM21, and the gate is loaded with the signal The number is consistent with PM17; the drain of NMOS tube NM20 is connected to the drain of PMOS tube PM15, its source is connected to the drain of NM18, and the gate is connected to the drain of NM21; the drain of NMOS tube NM21 is connected to the drain of PMOS tube PM16, its source is connected to the drain of NMOS tube NM19, and the gate is connected to the drain of NM20; the source of NMOS tube NM17 is grounded, the drain is connected to the sources of NM18 and NM19, and the gate is connected to the clock signal CLK_N; the source of NMOS tube NM18 is connected to the drain of NM17 and the source of NM19 at the same time, and the gate is loaded with the control signal V in ; The source of NMOS tube NM19 is connected to the drain of NM18, and the gate is loaded with control signal V ip .
[0019] Preferably, the compensation resistor module includes a plurality of parallel resistor branches, each resistor branch includes a resistor and a switch control transistor, when the switch control transistor is disconnected, the corresponding resistor is activated and enters the series network to adjust the equivalent resistance of the compensation resistor module; the resistance values of the plurality of resistors of the compensation resistor module decrease from 512R to R; the on and off of each resistor branch is controlled by a control signal TRIM <9> -TRIM <0> control.
[0020] Preferably, the supplementary module is used to maintain the calibration effect of the main operational amplifier of the PGA after chopping is turned on, and includes XOR gates XOR1 and XOR2, the first input terminal of XOR1 is loaded with the signal CHOP_CLK, the second input terminal is loaded with the signal Direction, and its output is connected to the input terminal of the inverter INV1 and the first input terminal of the AND gate AND1; the output of the inverter INV1 is connected to the first input terminal of the AND gate AND1, the second input terminal of the AND gate AND1 is connected to the output terminal of the inverter INV2, and the input terminal of the inverter INV2 is loaded with the signal CHOP_ENN; the outputs of the AND gates AND1 and AND2 are respectively connected to the two input terminals of the OR gate OR1, and the output of the OR gate OR1 generates the signal Dout ; The first input terminal of the XOR gate XOR2 is loaded with the signal CHOP_CLK, the second input terminal is loaded with the signal DirectionN, and its output is connected to the input terminal of the inverter INV3, and is also connected to the first input terminal of the AND gate AND4; the output of the inverter INV3 is connected to the first input terminal of the AND gate AND4, the second input terminal of the AND gate AND4 is connected to the output terminal of the inverter INV4, and the input terminal of the inverter INV4 is loaded with the signal CHOP_ENN; the outputs of the AND gates AND3 and AND4 are respectively connected to the two input terminals of the OR gate OR2, and the output of the OR gate OR2 generates the signal DoutN; through the above logical operations, the circuit realizes the generation of complementary output signals Dout and DoutN according to the input signals.
[0021] Compared with the prior art, at least one of the above technical solutions adopted by the present invention can achieve the following beneficial effects:
[0022] The programmable gain amplifier of the present invention includes a compensation resistor module, a gain adjustment resistor feedback circuit and an offset voltage elimination module. In the present invention, before the offset voltage is sent to the comparator, the gain adjustment resistor feedback circuit is configured with the gain and the pre-amplification effect of the pre-amplifier, which significantly reduces the offset index requirements of the comparator. The offset voltage elimination module first determines the positive and negative of the offset voltage after amplification according to the voltage across the feedback resistor R2, and then determines the direction of the compensation current according to the positive and negative of the offset voltage. Finally, the compensation current is generated according to the direction of the compensation current, and the equivalent resistance of the compensation resistor module is continuously adjusted by successive approximation. The compensation current is input to the two compensation resistor modules to automatically eliminate the offset voltage. Therefore, the programmable gain amplifier of the present invention does not need to specifically measure the offset voltage size and manually eliminate the offset voltage. As long as the offset voltage is within the designed calibration range, the offset voltage can be automatically eliminated on the chip, and the offset voltage can be reduced to below microvolts, which greatly improves the efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0024] Figure 1 It is a schematic diagram of the overall structure of the PGA of the present invention;
[0025] Figure 2 is a structural diagram of a main operational amplifier of the present invention;
[0026] Figure 3 It is a structural diagram of the PGA gain adjustment feedback circuit of the present invention;
[0027] Figure 4 It is a structural diagram of the pre-amplifier OP3 with self-zeroing technology of the present invention;
[0028] Figure 5 is a structural diagram of a dynamic latch comparator COMP1 of the present invention;
[0029] Figure 6 is a structural diagram of the current steering I_DAC of the present invention;
[0030] Figure 7 The compensation resistor module R of the present invention trim Structure diagram of
[0031] Figure 8 It is a structural diagram of a successive approximation logic SAR LOGIC circuit for offset calibration of the present invention;
[0032] Fig. 9 It is a structural diagram of a low-level pulse generating circuit NPG for an offset calibration circuit of the present invention;
[0033] Fig.10 It is a structure diagram of a logic circuit used in the invention to maintain a digital calibration function after chopping is turned on;
[0034] Fig.11 is a flow chart of the offset digital calibration algorithm of the present invention;
[0035] Fig.12 The Monte Carlo simulation result of the PGA offset voltage without digital offset calibration and only introducing chopping in the present invention;
[0036] Fig.13 This is the Monte Carlo simulation result of the PGA offset voltage after the digital offset calibration technology is introduced into the present invention. DETAILED DESCRIPTION
[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0038] In order to solve the deficiencies of the prior art, the present invention provides a programmable gain amplifier. Figure 1 , including a main operational amplifier, a PGA gain adjustment feedback circuit, a pre-amplifier OP3, a dynamic latch comparator COMP1, a current steering, a compensation resistor module and a successive approximation logic circuit.
[0039] Figure 2 This is the main operational amplifier structure diagram of the present invention, which is mainly composed of two stages of operational amplifiers in cascade. The input end of the first stage operational amplifier adopts a rail-to-rail (i.e., power rail to ground rail) input stage structure. It is composed of transistors NM1, NM2a, NM2b, NM3a, NM3b, NM4a, NM4b, PM1, PM2a, PM2b, PM3a, PM3b, PM4a and PM4b. It ensures that the PGA can handle the differential input signal range of ±VDD, while increasing the input transconductance value of the amplifier. The first stage operational amplifier adopts a double folded common source and common gate structure as a whole to obtain a high output impedance, thereby obtaining a higher gain. The second stage adopts a Class-AB structure, which is composed of transistors NM6 and PM6, which ensures that the output swing can almost reach the full swing of rail-to-rail, and at the same time, by adding a Miller compensation capacitor (C C ) and resistance (R z ) to ensure the stability of the main operational amplifier. The floating gate unit composed of four transistors, PM5a, PM5b, NM5a and NM5b, provides a suitable and stable bias for the Class-AB structure operational amplifier. A chopper switch is added to the circuit to reduce the 1 / f noise and offset voltage of the operational amplifier. From the above description, it can be seen that the operational amplifier of this structure has the advantages of high gain, low noise, low offset and high gain-bandwidth product.
[0040] The sources of PMOS transistors PM3a and PM3b are connected to the supply voltage VDD, and their gates are connected to each other and connected to node A or D through chopper switch CHOP2; the gate of PMOS transistor PM6 is connected to node A or D through chopper switch CHOP2, the source is connected to the supply voltage VDD, and the drain is connected to the source of NM6; the gates of PM4a and PM4b are both loaded with bias voltage V BP2 The source of the PMOS tube PM1 is connected to the supply voltage VDD, the drain is connected to the drains of the PMOS tubes PM2a and PM2b, and the gate is loaded with a bias voltage V BP1 ; The source of NMOS tube NM1 is grounded, the drain is connected to the source of NMOS tube NM2a, and the gate is loaded with bias voltage V BN1 ; The sources of NMOS tubes NM2a and NM2b are connected to the drain of NMOS tube NM1, the drain of NM2a is connected to the drain of PMOS tube PM3a, and the drain of NM2b is connected to the source of PMOS tube PM4b; the sources of PMOS tubes PM4a and PM4b are connected to the drains of PMOS tubes PM3a and PM3b respectively; the drain of PM4a is connected to node D, and the drain of PM4b is connected to node A, and the gates of both are loaded with bias voltage V BP2 The sources of NMOS tubes NM4a and NM4b are connected to the drains of NMOS tubes NM3a and NM3b respectively, the drain of NM4a is connected to the drain of PMOS tube PM5a, the drain of NM4b is connected to the drain of PMOS tube PM5b, and the gates of NM4a and NM4b are both loaded with bias voltage V BN2 The sources of PMOS tubes PM5a and PM5b are connected to nodes D and A respectively, the drain of PM5a is connected to node C, the drain of PM5b is connected to node B, and the gates of both are loaded with bias voltage V BP3 The sources of NMOS tubes NM3a and NM3b are both grounded, the drain of NM3a is connected to the source of NM4a, the drain of NM3b is connected to the source of NM4b, the gates of NM3a and NM3b are connected to node B or C through the chopper switch CHOP3, the gate of NMOS tube NM6 is connected to node B or node C through the chopper switch, and the source is connected to the drain of transistor PM6; resistor R z1 With capacitor C C1 Connect in series, with the two ends connected to the gate and drain of PM6 respectively; resistor R z2 With capacitor C C2 Connect in series, with the two ends connected to the gate and drain of NM6 respectively.
[0041] Figure 3 The figure is a structural diagram of the PGA gain adjustment feedback circuit of the present invention. In this structure, the resistor feedback array is symmetrical from top to bottom, and only one of the eight switches on each side is turned on at the same time. At the same time, since one end of the switch is connected to the negative input terminal of the op amp, that is, the gate of the transistor, it is equivalent to a virtual disconnection, so no current will flow through the switch, and there will be no nonlinear effect on the amplification factor. The eight switch options of this structure can provide configurable gains of 1, 2, 4, 8...64, 128. The calculation expression of the configuration gain is:
[0042]
[0043] Taking the circuit shown in the figure as an example, R1=124R, R2=8R, it can be calculated that the configuration gain is 32.
[0044] Figure 4 The structure diagram of the pre-amplifier OP3 with the self-zero technology in the present invention includes PMOS tubes PM7a and PM7b, whose sources are loaded with the supply voltage VDD and whose gates are loaded with the bias voltage V BP5 , whose drains are connected to the sources of NMOS tubes NM8a and NM8b respectively; the gate of PMOS tube PM8a is connected to the loading signal V through transmission gates TG5 and TG6. in or V ip connected, the gate of PM8b is connected to the load signal V in The drains of the two are connected to the sources of NM8a and NM8b respectively, and the sources are connected to the drain of PMOS tube PM10; the sources of NM8a and NM8b are connected to the drains of NM7a and NM7b respectively, and the gates are loaded with bias voltage V BN5 The sources of PMOS tubes PM9a and PM9b are connected to the supply voltage VDD, the drains are connected to the drains of NM9a and NM9b, and the gates are connected to their own drains; the sources of NM9a and NM9b are grounded, and the gates are connected to the supply voltage VDD / 2 and the voltage V A 、V B The average voltage of the PMOS tube PM10; the source of the PMOS tube PM10 is connected to the supply voltage VDD, and the gate load voltage V BP4 , the drain is connected to the source of PM8a and PM8b; the drain of NMOS tube NM11 is connected to the source of NM9a and NM9b, the source is connected to the ground, and the gate is loaded with a bias voltage V BN4 ; Capacitor C 1a One end and node V A connected, and the other end connected to the output V outp ; Capacitor C 1b One end and node V b connected, and the other end connected to the output V outp The drains of NMOS tubes NM10a and NM10b are connected to capacitors C 1a and C 1b The gate is connected to the resistor R 1a With R 1b connected.
[0045] The common-mode feedback circuit in the figure ensures that V A 、V B The common-mode voltage is VDD / 2. When the common-mode voltage is greater than VDD / 2, VBP5 will increase, thereby reducing V A 、V B When the clock signal CLK is high, the transmission gate TG1 shorts the input terminal and connects the output terminal to the common mode voltage VDD / 2. At this time, the input offset voltage can be amplified and stored in the form of charge on the capacitor C. 1a , C 1b When CLK is low, the input signal and the offset voltage are connected to the input of the op amp at the same time, and the offset voltage can be eliminated well at the output by charge conservation. It should be noted that the gain of the operational amplifier OP3 should not be too large, otherwise the output will be saturated during the offset voltage storage stage and the offset self-zeroing function cannot be achieved.
[0046] The gain expression of the pre-amplifier OP3 with self-zero technology is:
[0047] A diff_amp =g mp2a,b (r op1a,b ||g mn2a,b ·r on2a,b ·r on1a,b ||R2)≈g mp2a,b R2
[0048] A diff_amp represents the open-loop gain of OP3, g mn2a,b represents the transconductance of transistors NM8a and NM8b, g mp2a,b represents the transconductance of transistors PM8a and PM8b, r on1a,b represents the output impedance of transistors NM7a and NM7b, r on2a,b represents the output impedance of transistors NM8a and NM8b, r op1a,b represents the output impedance of transistors PM7a and PM7b, and R2 represents the common-mode feedback resistor. mp2a,b The value of R2 is adjusted to obtain the required open loop gain. In the present invention, the open loop gain is designed to be less than 20 dB under the condition of considering the process fluctuation.
[0049] Figure 5 The structure diagram of the dynamic latch comparator COMP1 of the present invention includes a PMOS tube PM11, whose source is connected to the supply voltage VDD, the drain is connected to the node B, and the gate is connected to the node A; the source of the PMOS tube PM12 is connected to the supply voltage VDD, the drain is connected to the node A, and the gate is connected to the node B; the source of the PMOS tube PM13 is connected to the supply voltage VDD, the drain is connected to the clock signal CLK_N loading point, and the gate is loaded with the clock signal CLK; the source of the PMOS tube PM14 is connected to the supply voltage VDD, the drain is connected to the input of the inverter, and the gate is connected to the clock signal CIK_N; the drain of the NMOS tube NM15 is connected to the node B, the source is connected to the drain of the NMOS tube NM13, and the gate is connected to the node A; the drain of the NMOS tube NM16 is connected to the node A, the source is connected to the drain of the NMOS tube NM3, and the gate is connected to the node B; the source of the NMOS tube NM12 is grounded, the drain is connected to the common source node of the NMOS tubes NM15 and NMOS tubes NM16, and the gate is loaded with the clock signal CLK_N; The source of the MOS tube NM13 is grounded, the drain is connected to the node B, and the gate is loaded with the input signal; the source of the NMOS tube NM14 is grounded, the drain is connected to the node A, and the gate is loaded with the input signal V; the logic circuit part includes two inverters, the input of the first inverter is connected to the drain of the PMOS tube PM15, and the output signal is Q; the input of the second inverter is connected to the drain of the PMOS tube PM14, and the output signal is QN; the input of the AND gate is the signals Q and QN, and the output signal is Valid, which is used to indicate the validity of the logic state, the input signals include V loaded on the gate of the NMOS tube NM15, V loaded on the gate of the NMOS tube NM16, the clock signal CLK loaded on the gate of the PMOS tube PM13, and the clock signal CLK_N loaded on the gate of the PMOS tube PM14 and the gate of the NMOS tube NM12, and the output signal includes Q generated by the first inverter, QN generated by the second inverter, and Valid generated by the AND gate, which is used for indicating the validity of the logic state.
[0050] In the PGA architecture of the present invention, since PGA and OP3 provide relatively large gain, the comparator offset voltage and noise basically do not affect the performance of the offset automatic offset system. Therefore, the offset index requirement of the comparator is relatively low, and it is only necessary to complete the comparison and reset of the result within one cycle. When the voltage of the clock CLK is at a high level, the two transistors PM13 and PM14 will pull Q and QN to a high level. This stage is the reset stage, and the Valid signal is at a low level; when the CLK voltage is at a low level, the transistor NM12 is turned on. If the Vip voltage is greater than the Vin voltage, the current flowing through the NM14 transistor is larger, and the voltage VA of the node A will decrease at a faster speed relative to the node B. Through the positive feedback latching action of the four transistors NM15, NM16, PM11, and PM12, NM15 will eventually be disconnected from PM12, and the node A voltage VA will be pulled to a low level by the transistors NM13 and NM14, and the node B voltage VB will be pulled to a high level by the transistor PM11. Finally, the node Q voltage outputs a high level, and the Valid signal changes from a low level to a high level. Similarly, when Vin is greater than Vip, the voltage at node Q outputs a low level, and the Valid signal changes from a low level to a high level. It is worth noting that in this latch structure comparator, once the comparison result is obtained within a cycle, even if the size of Vip and Vin changes again, the output result will not change, and the comparison can only be done after the next cycle is reset, which provides convenience for the design of SAR LOGIC with automatic offset calibration.
[0051] Figure 6 The current rudder I_DAC of the present invention is a structural diagram. The current rudder includes a PMOS tube PM15, whose source is connected to the power supply VDD, the gate is connected to the drain of PM16, and at the same time, its drain is connected to the drain of PM18. The gate of the PMOS tube PM16 is connected to the drain of PM15, and at the same time, its drain is connected to the drain of PM17, and the source is connected to the supply voltage VDD; the source of the PMOS tube PM17 is connected to the supply voltage VDD, the drain is connected to the drain of the NMOS tube NM20, and the gate is loaded with the signal CLK_N after the clock signal passes through the inverter; the drain of the PMOS tube PM18 is connected to the drain of the NMOS tube NM21, and the gate loading signal is connected to the PMOS tube PM18. M17 is consistent; the drain of NMOS tube NM20 is connected to the drain of PMOS tube PM15, its source is connected to the drain of NM18, and the gate is connected to the drain of NM21; the drain of NMOS tube NM21 is connected to the drain of PMOS tube PM16, its source is connected to the drain of NMOS tube NM19, and the gate is connected to the drain of NM20; the source of NMOS tube NM17 is grounded, the drain is connected to the sources of NM18 and NM19, and the gate is connected to the clock signal CLK_N; the source of NMOS tube NM18 is connected to the drain of NM17 and the source of NM19 at the same time, and the gate is loaded with the control signal V in ; The source of NMOS tube NM19 is connected to the drain of NM18, and the gate is loaded with control signal V ip .
[0052] When the input signals Dout and DoutN are 1 and 0 respectively, PM18 and NM20 are turned on, PM17 and PM19 are turned off, and the current of the IDAC size flows from the IOUT port to the IOUTN port, and vice versa, the current will flow from IOUTN to IOUT.
[0053] Figure 7 The compensation resistor module R of the present invention trim In the initial stage of the circuit, TRIM<9:0> are all high level, and there is no R trim To avoid the influence of the switch tube's own resistance on the circuit, the switch tube designed in the present invention is larger in size. TRIM<9:0> is provided by SAR LOTGIC. When a code value becomes 0, the corresponding resistor is connected to R trim In this way, the corresponding compensation amount is provided for the offset voltage of the PGA.
[0054] Figure 8 FIG. 1 is a structural diagram of a successive approximation logic circuit SAR LOGIC for offset calibration of the present invention, wherein a low-level pulse generating circuit inside the SAR LOGIC is Fig. 9 It is composed of multiple cascaded triggers. The clock input of each trigger is loaded with clock signals CLK10, CLK9, CLK8, ..., CLK0. The input terminal D receives the output Q or control signal of the previous trigger, and finally drives the output signal TRIM <0> To TRIM <n>; Each trigger is provided with a reset terminal Reset and a set terminal Set, which are initialized or cleared by external control; the direction control logic is formed by the input signals Direction, DirectionN and the comparison signal Comp through logic gates to realize direction selection, wherein the comparison signal Comp is inverted and input into the AND gate together with the signal DirectionN to form the control logic; the input valid signal Valid enters the trigger array after being processed by the delay module DELAY, and the delay module is used to synchronize and delay the signal; the NPG circuit is located in each level of the clock path, and is respectively connected to CLK10, CLK9,..., CLK0, for adjusting and distributing the clock signal; the digital output enable signal Digital_EN is generated by the trigger cascade, and is used to control the logic validity and operation status of the subsequent circuit.
[0055] The designed low-level pulse generating circuit is high level when the output is stable, regardless of whether the input signal Input is high level or low level. Only when the Input signal changes from low level to high level, a low level pulse with a duration of DELAY will be output. Fig.10 It is a logic circuit used in the present invention to maintain the digital calibration function after chopping is turned on. Fig.11 FIG. 4 is a flow chart of the offset digital calibration algorithm of the present invention.
[0056] Combination Figures 8 to 11 , the working principle of the PGA of the present invention is introduced. When the SARLOGIC enable function is not turned on, CLK0~CLK10 are all low level, TRIM<9:0> are all high level, and the R connected to the PGA at this time trim The value is 0, I_DAC and R trim The transmission gate between is controlled by CLK10 and is disconnected at this time, that is, no current flows into R trim Before calibration, adjust the PGA input to the common-mode level and configure the PGA gain to 128. Fig.10 In the example, CHOP_ENN is at a low level, and the output Dout signal and DoutN signal are Direction and DirectionN signals respectively. When Digital_EN is at a high level, SARLOGIC starts to work. According to the assumption that the offset voltage is greater than 0, the comparator will output a high level in the first cycle, and the Valid signal changes from a low level to a high level, causing CLK10 to become a high level, thereby allowing the D flip-flop to sample the comparison result COMP=1 of the comparator, and output Direction=1, DirectionN=0. At this time, the I_DAC current will flow out of the IOUT port and flow back from the IOUTN port. At the same time, when CLK10 changes from a low level to a high level, the output signal of the corresponding NPG is briefly set to 0, and the TRIM of the next bit is reset. <9> Set to 0, so that R trim The resistance value is 256R. In the next clock cycle, the PGA output result after the previous cycle will be compared. If the comparison result is still 1, it proves that the offset voltage is not well compensated, so the TRIM will be retained. <9> = 0, the next TRIM <8> Also set to 0, then R trim The value of TRIM is 384R; if the comparator result is 0, it means that the first compensation amount is too large, then TRIM <9> Adjust to high level, and CLK9 will also generate a short low level through NPG to TRIM <8> Set to 0, that is, R of 256R trim Access circuit. The SARLOGIC circuit adjusts the output of TRIM<9:0> in sequence according to this logic, and finally eliminates the influence of the input offset of the PGA on the output, which is equivalent to completely eliminating the input offset. When chopping is not turned on, the offset voltage can be reduced to less than 10μV by relying solely on the digital automatic calibration of the offset voltage. When the system offset voltage is less than 0, its control logic is basically the same. Only when the D flip-flop latches the COMP comparison result, the inverted result of the COMP signal is stored in TRIM<9:0>.
[0057] Reference Fig.12 and Fig.13 When the chopper switch is turned on, the corresponding digital logic will work, so that the outputs Dout and DoutN that control the direction of the compensation current will change with the chopper switch, so that the digital calibration offset is not affected by the chopper circuit. The residual offset voltage will be modulated to a high frequency and can eventually be further eliminated by a low-pass filter.
[0058] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.
[0059] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.< / n> < / n>
Claims
1. A programmable gain amplifier, characterized in that: include: The main operational amplifiers OP1 and OP2, the non-inverting input terminal of OP1 is used to input the positive voltage V ip OP2’s non-inverting input is used to input the reverse voltage V in ; Two compensation resistance modules, one end of one compensation resistance module is connected to the inverting input end of OP1, and one end of the other compensation resistance module is connected to the inverting input end of OP2, and the compensation resistance module is used to generate an equivalent resistance; The gain adjustment resistor feedback circuit includes two feedback resistors R1 and one feedback resistor R2, wherein two ends of the feedback resistor R2 are respectively connected to the other ends of the two compensation resistor modules, and two ends of the feedback resistor R2 are also connected to one end of the two feedback resistors R1, and the other ends of the two feedback resistors R1 are respectively connected to the output ends of OP1 and OP2, and the gain of the PGA is configured by adjusting the feedback resistors R1 and R2; A pre-amplifier OP3, wherein an input end of the pre-amplifier OP3 is connected to the other end of the two feedback resistors R1 and the output ends of the main operational amplifiers OP1 and OP2, and is used to amplify the offset voltage; The offset voltage elimination module includes a latch comparator COMP1, a digital control logic circuit and two current rudders, wherein the input end of the latch comparator COMP1 is connected to the output end of the pre-amplifier, and is used to judge the positive or negative of the offset voltage after amplification according to the voltages V1 and V2 at both ends of the feedback resistor R2; the input end of the digital control logic circuit is connected to the output end of the latch comparator COMP1, and is used to receive the offset voltage and determine the direction of the compensation current according to the positive or negative of the offset voltage; the current rudder is used to generate a compensation current according to the direction of the compensation current; the output end of the digital control logic circuit is connected to two compensation resistor modules, and is used to continuously adjust the equivalent resistance of the compensation resistor modules by successive approximation, and the compensation current is input to the two compensation resistor modules to eliminate the offset voltage.
2. A programmable gain amplifier as claimed in claim 1, characterized in that: The output end of the digital control logic circuit is also connected to transmission gates TG1, TG2, TG3 and TG4 and the input end of the supplementary module. The output end of the supplementary module is connected to two current steering input ends. The two current steering output ends are respectively connected to transmission gates TG1 and TG2 and TG3 and TG4.
3. A programmable gain amplifier as claimed in claim 1, characterized in that: The main operational amplifiers OP1 and OP2 have the same structure, and both include NMOS tubes NM1, NM2a, NM2b, NM3a, NM3b, NM4a, NM4b, NM6, NM5a and NM5b, and PMOS tubes PM1, PM2a, PM2b, PM3a, PM3b, PM4a, PM4b, PM6, PM5a and PM5b; the sources of the PMOS tubes PM3a and PM3b are both connected to the supply voltage VDD, and their gates are connected to each other and connected to the node A or D through the chopper switch CHOP2; the gate of the PMOS tube PM6 is connected to the node A or D through the chopper switch CHOP2, the source is connected to the supply voltage VDD, and the drain is connected to the source of NM6; the gates of PM4a and PM4b are both loaded with the bias voltage V BP2 The source of the PMOS tube PM1 is connected to the supply voltage VDD, the drain is connected to the drains of the PMOS tubes PM2a and PM2b, and the gate is loaded with a bias voltage V BP1 ; The source of NMOS tube NM1 is grounded, the drain is connected to the source of NMOS tube NM2a, and the gate is loaded with bias voltage V BN1 ; The sources of NMOS tubes NM2a and NM2b are connected to the drain of NMOS tube NM1, the drain of NM2a is connected to the drain of PMOS tube PM3a, and the drain of NM2b is connected to the source of PMOS tube PM4b; the sources of PMOS tubes PM4a and PM4b are connected to the drains of PMOS tubes PM3a and PM3b respectively; the drain of PM4a is connected to node D, and the drain of PM4b is connected to node A, and the gates of both are loaded with bias voltage V BP2 The sources of NMOS tubes NM4a and NM4b are connected to the drains of NMOS tubes NM3a and NM3b respectively, the drain of NM4a is connected to the drain of PMOS tube PM5a, the drain of NM4b is connected to the drain of PMOS tube PM5b, and the gates of NM4a and NM4b are both loaded with bias voltage V BN2 The sources of PMOS tubes PM5a and PM5b are connected to nodes D and A respectively, the drain of PM5a is connected to node C, the drain of PM5b is connected to node B, and the gates of both are loaded with bias voltage V BP3 The sources of NMOS tubes NM3a and NM3b are both grounded, the drain of NM3a is connected to the source of NM4a, the drain of NM3b is connected to the source of NM4b, the gates of NM3a and NM3b are connected to node B or C through the chopper switch CHOP3, the gate of NMOS tube NM6 is connected to node B or node C through the chopper switch, and the source is connected to the drain of transistor PM6; resistor R z1 With capacitor C C1 Connect in series, with the two ends connected to the gate and drain of PM6 respectively; resistor R z2 With capacitor C C2 Connect in series, with the two ends connected to the gate and drain of NM6 respectively.
4. A programmable gain amplifier as claimed in claim 1, characterized in that: The preamplifier includes PMOS transistors PM7a and PM7b, whose sources are both loaded with supply voltage VDD and whose gates are both loaded with bias voltage V BP5 , whose drains are connected to the sources of NMOS tubes NM8a and NM8b respectively; the gate of PMOS tube PM8a is connected to the loading signal V through transmission gates TG5 and TG6. in or V ip connected, the gate of PM8b is connected to the load signal V in The drains of the two are connected to the sources of NM8a and NM8b respectively, and the sources are connected to the drain of PMOS tube PM10; the sources of NM8a and NM8b are connected to the drains of NM7a and NM7b respectively, and the gates are loaded with bias voltage V BN5 The sources of PMOS tubes PM9a and PM9b are connected to the supply voltage VDD, the drains are connected to the drains of NM9a and NM9b, and the gates are connected to their own drains; the sources of NM9a and NM9b are grounded, and the gates are connected to the supply voltage VDD / 2 and the voltage V A 、V B The average voltage of the PMOS tube PM10; the source of the PMOS tube PM10 is connected to the supply voltage VDD, and the gate load voltage V BP4 , the drain is connected to the source of PM8a and PM8b; the drain of NMOS tube NM11 is connected to the source of NM9a and NM9b, the source is connected to the ground, and the gate is loaded with a bias voltage V BN4 ; Capacitor C 1a One end and node V A connected, and the other end connected to the output V outp ; Capacitor C 1b One end and node V b connected, and the other end connected to the output V outp The drains of NMOS tubes NM10a and NM10b are connected to capacitors C 1a and C 1b The gate is connected to the resistor R 1a With R 1b connected.
5. A programmable gain amplifier as claimed in claim 1, characterized in that: The latch comparator includes a PMOS tube PM11, whose source is connected to the supply voltage VDD, the drain is connected to the node B, and the gate is connected to the node A; the source of the PMOS tube PM12 is connected to the supply voltage VDD, the drain is connected to the node A, and the gate is connected to the node B; the source of the PMOS tube PM13 is connected to the supply voltage VDD, the drain is connected to the clock signal CLK_N loading point, and the gate is loaded with the clock signal CLK; the source of the PMOS tube PM14 is connected to the supply voltage VDD, the drain is connected to the input of the inverter, and the gate is connected to the clock signal CIK_N; the drain of the NMOS tube NM15 is connected to the node B, the source is connected to the drain of the NMOS tube NM13, and the gate is connected to the node A; the drain of the NMOS tube NM16 is connected to the node A, the source is connected to the drain of the NMOS tube NM3, and the gate is connected to the node B; the source of the NMOS tube NM12 is grounded, the drain is connected to the common source node of the NMOS tubes NM15 and NMOS tubes NM16, and the gate is loaded with the clock signal CLK _N; the source of the NMOS tube NM13 is grounded, the drain is connected to the node B, and the gate is loaded with the input signal; the source of the NMOS tube NM14 is grounded, the drain is connected to the node A, and the gate is loaded with the input signal V; the logic circuit part includes two inverters, the input of the first inverter is connected to the drain of the PMOS tube PM15, and the output signal is Q; the input of the second inverter is connected to the drain of the PMOS tube PM14, and the output signal is QN; the input of the AND gate is the signals Q and QN, and the output signal is Valid, which is used to indicate the validity of the logic state, the input signals include V loaded on the gate of the NMOS tube NM15, V loaded on the gate of the NMOS tube NM16, the clock signal CLK loaded on the gate of the PMOS tube PM13, and the clock signal CLK_N loaded on the gate of the PMOS tube PM14 and the gate of the NMOS tube NM12, the output signal includes Q generated by the first inverter, QN generated by the second inverter, and Valid generated by the AND gate, which is used to indicate the validity of the logic state.
6. A programmable gain amplifier as claimed in claim 2, characterized in that: The digital control logic circuit is composed of a plurality of cascaded triggers. The clock input of each trigger is loaded with clock signals CLK10-CLK0 respectively, and the input terminal D receives the output Q or control signal of the previous trigger, and finally drives the output signal TRIM <0> -TRIM <n> ; Each trigger is provided with a reset terminal Reset and a set terminal Set, which are initialized or cleared by external control; the direction control logic is formed by the input signals Direction, DirectionN and the comparison signal Comp through logic gates to realize direction selection, wherein the comparison signal Comp is inverted and input into the AND gate together with the signal DirectionN to form the control logic; the input valid signal Valid enters the trigger array after being processed by the delay module DELAY, and the delay module is used to synchronize and delay the signal; the NPG circuit is located in each level of the clock path, respectively connected to CLK10-CLK0, for adjusting and distributing the clock signal; the digital output enable signal Digital_EN is generated by the trigger cascade, and is used to control the logic validity and operation status of the subsequent circuit.< / n> 7. A programmable gain amplifier as claimed in claim 1, characterized in that: The current steering includes a PMOS tube PM15, whose source is connected to the power supply VDD, the gate is connected to the drain of PM16, and the drain is connected to the drain of PM18. The gate of the PMOS tube PM16 is connected to the drain of PM15, and the drain is connected to the drain of PM17, and the source is connected to the supply voltage VDD; the source of the PMOS tube PM17 is connected to the supply voltage VDD, the drain is connected to the drain of the NMOS tube NM20, and the gate is loaded with the signal CLK_N after the clock signal passes through the inverter; the drain of the PMOS tube PM18 is connected to the drain of the NMOS tube NM21, and the gate load signal is connected to the drain of the NMOS tube NM21. PM17 is consistent; the drain of NMOS tube NM20 is connected to the drain of PMOS tube PM15, its source is connected to the drain of NM18, and the gate is connected to the drain of NM21; the drain of NMOS tube NM21 is connected to the drain of PMOS tube PM16, its source is connected to the drain of NMOS tube NM19, and the gate is connected to the drain of NM20; the source of NMOS tube NM17 is grounded, the drain is connected to the sources of NM18 and NM19, and the gate is connected to the clock signal CLK_N; the source of NMOS tube NM18 is connected to the drain of NM17 and the source of NM19 at the same time, and the gate is loaded with the control signal V in ; The source of NMOS tube NM19 is connected to the drain of NM18, and the gate is loaded with control signal V ip .
8. A programmable gain amplifier as claimed in claim 6, characterized in that: The compensation resistor module includes a plurality of parallel resistor branches, each resistor branch includes a resistor and a switch control transistor. When the switch control transistor is disconnected, the corresponding resistor is activated and enters the series network to adjust the equivalent resistance of the compensation resistor module. The resistance values of the plurality of resistors of the compensation resistor module decrease from 512R to R. The on and off of each resistor branch is controlled by a control signal TRIM <9> -TRIM <0> control.
9. A programmable gain amplifier as claimed in claim 6, characterized in that: The supplementary module is used to maintain the calibration effect of the main operational amplifier of the PGA after the chopping is turned on, and includes XOR gates XOR1 and XOR2. The first input end of XOR1 is loaded with a signal CHOP_CLK, the second input end is loaded with a signal Direction, and its output is connected to the input end of the inverter INV1 and the first input end of the AND gate AND1; the output of the inverter INV1 is connected to the first input end of the AND gate AND1, the second input end of the AND gate AND1 is connected to the output end of the inverter INV2, and the input end of the inverter INV2 is loaded with a signal CHOP_ENN; the outputs of the AND gates AND1 and AND2 are respectively connected to the two input ends of the OR gate OR1, and the output of the OR gate OR1 generates a signal Dout; The first input terminal of the XOR gate XOR2 is loaded with the signal CHOP_CLK, the second input terminal is loaded with the signal DirectionN, and the output thereof is connected to the input terminal of the inverter INV3 and the first input terminal of the AND gate AND4; the output of the inverter INV3 is connected to the first input terminal of the AND gate AND4, the second input terminal of the AND gate AND4 is connected to the output terminal of the inverter INV4, and the input terminal of the inverter INV4 is loaded with the signal CHOP_ENN; the outputs of the AND gates AND3 and AND4 are respectively connected to the two input terminals of the OR gate OR2, and the output of the OR gate OR2 generates the signal DoutN; through the above logic operations, the circuit realizes the generation of complementary output signals Dout and DoutN according to the input signals.