IIR (Infinite Impulse Response) filter device and filtering method thereof

Abstract

The invention discloses an IIR (Infinite Impulse Response) filter device and a filtering method thereof, and the IIR filter device comprises a head data module which stores current input data and two pieces of input historical data; the filtering module is used for storing output data of each stage through a first position, corresponding to each stage of filtering, of the intermediate data module, exchanging addresses of the first position and a second position, reading current input data and two pieces of input historical data from a specified position through the calculation module, and outputting the data; two pieces of output historical data are read from the intermediate data module and stored in the tail data module, data are output after filtering, and lower-level filtering is triggered; the tail data module is used for storing the output data of the level of filtering as the input data of the lower level of filtering when any level of filtering is completed; wherein the designated position of the first-stage filtering is a head data module, and the designated positions of the other-stage filtering are tail data modules. According to the method, the data reading and writing time is shortened, the calculation pipeline is prevented from being interrupted, the required data storage is reduced by half, and the required clock frequency is reduced.

Description

Technical Field

[0001] The present application relates to the field of filter technology, and in particular to an IIR filter device and a filtering method thereof. Background Art

[0002] An IIR filter device and a filtering method thereof (Infinite Impulse Response Filter) is a digital filter, and its output signal is composed of a weighted sum of past input signals and output signals.

[0003] IIR with too high order is unstable. Generally speaking, high-order IIR will be transformed into a cascade of multiple biquad IIRs, where each biquad IIR is called a section.

[0004] For biquad IIR, each section needs to store and read the current input data and 2 input history data and 2 output history data. Thus, according to the traditional implementation method, the N-section cascaded biquad IIR filter working in serial computing mode requires a RAM (Random Access Memory) size of 5*N words. Since the input and output history values ​​of the current stage need to be read and written in the middle of the stage, the total computing time requires 10*N clock cycles, and the required clock frequency needs to be above 10*N times the sampling rate. When the sampling rate is constant, the clock frequency is relatively high, which will increase the cost and power consumption. Summary of the invention

[0005] The purpose of the present application is to provide an IIR filter device and a filtering method thereof, which are used to solve the problems that the existing IIR filter requires a large RAM space, a long read and write time, and a relatively high clock frequency.

[0006] In a first aspect, an embodiment of the present application provides an IIR filter device, comprising:

[0007] The head data module receives the current input data, latches it in a way of overwriting the earliest input historical data, and keeps storing the current input data and two input historical data;

[0008] A filtering module, used for performing multi-stage filtering calculations, including an intermediate data module and a calculation module, wherein the intermediate data module includes a first position and a second position corresponding to each stage of filtering, and uses the first position corresponding to each stage of filtering to store output data of the filtering at that stage, and exchanges the addresses of the first position and the second position. When the calculation module determines to trigger the current stage of filtering, the current input data and two input historical data are read from the specified position, and the data of the first position and the second position corresponding to the current stage of filtering are read from the intermediate data module as two output historical data, and the two output historical data are stored in the tail data module as two input historical data of the next stage of filtering, and the current output data is obtained after filtering and the next stage of filtering is triggered;

[0009] A tail data module, used to store the two output historical data read by the calculation module as two input historical data, and when any level of filtering is completed, store the output data of the filtering at that level as the current input data of the next level of filtering;

[0010] Among them, the designated position of the first level of filtering is the head data module, and the designated position of other levels of filtering is the tail data module.

[0011] In some possible embodiments, the header data module includes:

[0012] Header data registers, including a first header register, a second header register and a third header register;

[0013] The header data manager is used to receive current input data, latch the input history data of the first header register to the second header register / third header register where the earliest input history data is located, and latch the current input data to the first header register.

[0014] In some possible embodiments, the header data register further includes a status register;

[0015] The header data manager is used to trigger the change of the state value of the state register after the first level of filtering is completed;

[0016] When the state value is a first state value, the input historical data of the first register is latched into the second register, and when the state value is a second state value, the input historical data of the first register is latched into the third register.

[0017] In some possible embodiments, the intermediate data module includes:

[0018] An intermediate data manager stores output data of each level of filtering in a first location and exchanges addresses of the first location and a second location;

[0019] The intermediate data storage device includes a first address and a second address corresponding to each level of filtering, wherein the first address and the second address are used to store corresponding data.

[0020] In some possible embodiments, the calculation module includes:

[0021] A data selector is used to read the current input data and two input historical data from the specified position when triggering the current level filtering, read the data at the first position and the second position corresponding to the current level filtering from the intermediate data module as two output historical data, read the coefficients corresponding to the current input data, the two input historical data and the two output historical data from the coefficient memory, and output them to the multiplier accumulator;

[0022] A coefficient memory, used to store coefficients corresponding to current input data, two input historical data and two output historical data of each level of filtering;

[0023] The multiplier-accumulator is used to perform multiplication-accumulation operations according to current input data, two input historical data, two output historical data and corresponding coefficients to obtain current output data.

[0024] In some possible embodiments, the calculation module further includes:

[0025] The output latch is connected to the multiplier-accumulator and is used to latch the current output data.

[0026] In some possible embodiments, the tail data module includes:

[0027] The tail data manager is used to latch the output history data read by the calculation module from the first position corresponding to the current level filter in the intermediate data module into the second tail register when the current level filter is calculated, latch the output history data read from the second position corresponding to the current level filter in the intermediate data module into the third tail register, and latch the output data of the current level filter into the first tail register when the current level filter is completed;

[0028] The tail data registers include a first tail register, a second tail register and a third tail register.

[0029] In some possible embodiments, the device further includes:

[0030] A beat counter is used to start counting when any level of filtering is triggered. Each time the beat count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, second output historical data and corresponding coefficients. When the current level of filtering is completed, the beat count value is cleared;

[0031] The node counter is used to increase the node count value by one when any level of filtering is completed. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

[0032] In a second aspect, an embodiment of the present application further provides a filtering method of an IIR filter device, comprising:

[0033] The head data module is used to receive the current input data, and latches the data in a manner of overwriting the earliest input historical data, so as to keep storing the current input data and two input historical data;

[0034] Trigger the first level of filtering, read the current input data and two input historical data from the head data module, and read two output historical data from the first position and the second position corresponding to the first level of filtering in the intermediate data module for filtering;

[0035] Determine to trigger other level filtering, read current input data and two input historical data from the tail data module, read two output historical data from the first position and the second position of the level filtering in the intermediate data module for filtering, and store the two output historical data in the tail storage module as two input historical data for the next level filtering;

[0036] When it is determined that any level of filtering is completed, the tail data module is used to store the output data of the filtering at that level as the current input data of the next level filtering; and the next level filtering is triggered until the filtering is completed.

[0037] In some possible embodiments, the method further includes:

[0038] When any level of filtering is triggered, counting starts. Each time the count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, and second output historical data and corresponding coefficients;

[0039] Determine that the beat count value is cleared when the current level filtering is completed;

[0040] When any level of filtering is completed, the node count value is increased by one. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

[0041] In some possible embodiments, a parameter group is read in the following order:

[0042] The second input historical data and corresponding coefficients, the current input data and corresponding coefficients, the first output historical data and corresponding coefficients, the first input historical data and corresponding coefficients, the second output historical data and corresponding coefficients;

[0043] The first input historical data is earlier than the second input historical data, and the first output historical data is earlier than the second output historical data.

[0044] The embodiment of the present application introduces a header data module, an intermediate data module, and a tail data module, and uses exchange addresses instead of multiple data reading and writing, so that the calculation results of the intermediate sections are propagated in the register by section, and the intermediate results are not stored in the RAM, which reduces the time for reading and writing RAM and avoids interrupting the calculation pipeline. Compared with the traditional serial calculation direct I type IIR, the required data RAM is reduced by half, and the required clock frequency is reduced by more than 40%.

[0045] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 It is a schematic diagram of the grid structure of the direct type IIR filter;

[0048] Figure 2 It is a schematic diagram of the cascade of multi-stage biquad IIR filters;

[0049] Figure 3 Schematic diagram of the grid structure of direct type I biquad IIR;

[0050] Figure 4 This is a schematic diagram of the structure of an IIR filter device provided in an embodiment of the present application;

[0051] Figure 5a This is a schematic diagram of the structure of the first-stage filter performing filtering calculation in an embodiment of the present application;

[0052] Figure 5b This is a schematic diagram of the structure of other filters performing filtering calculations in the embodiments of the present application;

[0053] Figure 6 This is a schematic diagram of the working of the header data manager in the embodiment of the present application;

[0054] Figure 7 This is a schematic diagram of the intermediate data storage device exchanging addresses and storing data in an embodiment of the present application;

[0055] Figure 8 This is a schematic diagram of the filtering calculation process of other level filters in the embodiment of the present application;

[0056] Fig. 9 This is an overall flow chart of the operation of the beat calculator and the beat counter in the embodiment of the present application;

[0057] Fig.10 4 is a flow chart of a filtering method of an IIR filter device in an embodiment of the present application. DETAILED DESCRIPTION

[0058] To further illustrate the technical solution provided by the embodiment of the present application, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiment of the present application provides the method operation steps as shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiment of the present application. The method can be executed in the order of the method shown in the embodiment or drawings or in parallel during the actual processing process or when the control device is executed.

[0059] The time domain expression of IIR is as follows:

[0060]

[0061] The direct type IIR filter grid structure is as follows Figure 1 shown.

[0062] IIR with too high order is unstable. Generally speaking, high-order IIR will be transformed into a cascade of multiple biquad IIR filters, such as Figure 2 shown.

[0063] Each level of biquad IIR filter is called a section. The grid structure of a direct type I biquad IIR filter is as follows: Figure 3 shown.

[0064] For a biquad IIR filter, each section needs to store and read 3 input history data and 2 output history data. Thus, according to the traditional implementation method, the N-section cascaded biquad IIR filter working in serial computing mode requires a RAM size of 5*N words. Since the input and output history values ​​of the current stage need to be read and written in the middle of the stage, the total computing time requires 10*N clock cycles, and the required clock frequency needs to be above 10*N times the sampling rate. When the sampling rate is constant, the clock frequency is relatively high, which will increase the cost and power consumption.

[0065] In view of this, the present application provides an IIR filter device, which, although still a cascaded biquad IIR direct type I, reduces RAM usage and lowers the required clock frequency by optimizing data access methods and adjusting calculation steps.

[0066] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0067] The IIR filter device and filtering method thereof in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0068] The present application embodiment provides an IIR filter device, such as Figure 4 As shown, including:

[0069] The header data module 10 receives the current input data, latches it in a way of overwriting the earliest input historical data, and keeps storing the current input data and two input historical data;

[0070] That is to say, the head data module uses three storage locations. Every time a new data is input, if there is free space in the three storage locations, the data can be stored in the free locations. If there is data in all three locations, the earliest historical data can be overwritten. The head data module always stores the current input data and the two most recent input historical data.

[0071] The filter module 20 is used to perform multi-stage filtering calculations. Each filter includes an intermediate data module 201 and a calculation module 202. The intermediate data module 201 includes a first position and a second position corresponding to each level of filtering. The first position corresponding to each level of filtering is used to store the output data of the filtering at this level, and the addresses of the first position and the second position are exchanged. When the calculation module determines to trigger the current level of filtering, the current input data and two input historical data are read from the specified position, and the data of the first position and the second position corresponding to the current level of filtering are read from the intermediate data module as two output historical data, and the two output historical data are stored in the tail data module as two input historical data of the next level of filtering. After filtering, the current output data is obtained and the next level of filtering is triggered; the calculation module 202 is used to realize the function of a multi-stage cascade filter. The cascade filter is a direct I-type double quadratic IIR filter. After completing the first level of filtering, the newly calculated output data are all stored in the first position corresponding to the filtering at this level, but after being stored in the first position, the addresses of the first position and the second position are exchanged, and the output data are alternately stored using the two addresses. In this way, when the filtering calculation is triggered, the two addresses store the output historical data of the most recent two times.

[0072] The calculation module 202 triggers the first-level filtering calculation after a new data is input, and then triggers the next-level filtering calculation after each level of filtering calculation is completed in a cascade order. After the last level of filtering calculation is completed, a new data is input to the first-level filtering to start the next serial filtering calculation. The calculation module 202 needs the current input data, two input historical data, and two output historical data to perform filtering calculations at each level. In the embodiment of the present application, the current input data is identified as x0, the previous input historical data is identified as x1, the previous input historical data is identified as x2, the previous output historical data is identified as y1, and the previous output historical data is identified as y2.

[0073] The tail data module 30 is used to store the two output historical data read by the calculation module as two input historical data, and when any level of filtering is completed, store the output data of the filtering at that level as the current input data of the next level of filtering;

[0074] In the embodiment of the present application, the data that is always stored in the tail data module is: two input history data of the lower-level filter and the current input data. For the specific storage method, please refer to the above description.

[0075] Among them, the designated position of the first level of filtering is the head data module, and the designated position of other levels of filtering is the tail data module.

[0076] The embodiment of the present application introduces a header data module, an intermediate data module, and a tail data module. The intermediate data module uses an exchange address instead of multiple data reading and writing. The tail data module always stores the current output data and two historical output data of the current calculation, and uses them as the input of the next section of filtering calculation, so that the calculation results of the intermediate sections are propagated in the register by section, and the intermediate results are not stored in the RAM, which reduces the time for reading and writing RAM and avoids interrupting the calculation pipeline. Compared with the traditional serial calculation direct I type IIR, the required data RAM is reduced by half, and the required clock frequency is reduced by more than 40%.

[0077] The head data module 10 is used to provide x0, x1 and x2 for the first level of filtering, and the tail data module 30 is used to provide x0, x1 and x2 for the next level of filtering after the filtering is completed.

[0078] The header data module 10 is used to store and manage the current input data x0 of the first level filter and two input historical data x1 and x2. Figure 5a As shown, the header data module 10 includes:

[0079] The header data manager 101 is used to receive the current input data x0, latch the input history data of the first header register rx0 to the second header register rx1 / third header register rx2 where the earliest input history data is located, and latch the current input data x0 to the first header register rx0. In this way, when x0 arrives, the data last latched to rx0 is moved to rx1 or rx2 as x1, covering the earliest input history data, and the data latched by the other rx2 or rx1 is used as x2, and x0, x1 and x2 are kept latched;

[0080] The header data register 102 includes a first header register rx0, a second header register rx1 and a third header register rx2.

[0081] In this embodiment, the header data register 102 also includes a status register z1_addr;

[0082] The header data manager 101 is used to trigger the change of the state value of the state register z1_addr after the first level filtering is completed;

[0083] Among them, when the state value is the first state value, the input historical data of the first register rx0 is latched to the second register rx1, and when the state value is the second state value, the input historical data of the first register rx0 is latched to the third register rx2. The above-mentioned first state value is 0, the second state value is 1, or the first state value is 1, and the second state value is 0.

[0084] like Figure 6 The figure shows the data storage process of the header data management module. When the data x0 is input, if z1_addr is 0, the value of rx0 is latched into rx1. If z1_addr is 1, the value of rx0 is latched into rx2, and then x0 is latched into rx0, and the state value of z1_addr is flipped.

[0085] The intermediate data module 201 is used to store and manage intermediate historical data, such as Figure 5a and Figure 5b As shown, in the embodiment of the present application, the intermediate data module 201 includes:

[0086] The intermediate data manager 2011 stores the output data of each level of filtering to the first position (y1 position) corresponding to the filtering of the corresponding level, and exchanges the addresses of the first position (y1 position) and the second position (y2 position);

[0087] The intermediate data memory 2012 includes first addresses and second addresses corresponding to each level of filtering, and the first addresses and the second addresses are used to store corresponding data.

[0088] In the embodiment of the present application, the calculation module realizes the function of the IIR filter. The IIR filter is composed of N biquad IIR filters connected in series. Each biquad IIR filter corresponds to an intermediate data memory in the intermediate data module. N is the number of cascaded sections of the IIR filter. Figure 7 As shown, the N intermediate data memories are a RAM with a depth of 2*N. After each level of biquad IIR filter filtering calculation is completed, the current output data y_next is stored in the y1 position of the intermediate data memory of this section. After the storage is completed, the addresses of the y1 position and the y2 position of this section are exchanged.

[0089] The tail data module 30 is used to store and manage the current output data and its two output historical data of each section, which are used as the current input data and its two input historical data of the next section, so that the historical data can be propagated in each section, saving the clock cycles of RAM and RAM reading and writing. Figure 5a and Figure 5b As shown, the tail data module 30 includes:

[0090] The tail data manager 301 is used to latch the output history data y1 read by the calculation module 202 from the first position corresponding to the current level filter in the intermediate data module 201 into the second tail register ry1 during the current level filter calculation, latch the output history data y2 read from the second position corresponding to the current level filter in the intermediate data module 201 into the third tail register ry2, and latch the output data y_next of the current level filter into the first tail register ry0 when the current level filter is completed;

[0091] The tail data register 302 includes a first tail register ry0, a second tail register ry1 and a third tail register ry2.

[0092] When each section of calculation is completed, the output result y_next of this section is stored in register ry0, which is the input data x0 to be used in the next section of calculation.

[0093] During each calculation, the historical data y1 and y2 are read back from the intermediate data storage. While these two data are used for calculation, they are latched into ry1 and ry2 respectively. These two data are x1 and x2 to be used in the next calculation.

[0094] Through the tail data manager 301 and the tail register 302, the historical data x0, x1, x2 that originally needed to be stored in each section no longer need to be stored separately, but are sequentially transmitted between each section through the tail register 302, thereby saving RAM and the clock cycles required to read and write RAM.

[0095] The calculation module 202 in the embodiment of the present application is used to perform multi-stage filtering calculations, such as Figure 5a and Figure 5b As shown, the calculation module 202 includes:

[0096] The data selector 2021 is used to read the current input data x0 and the two input historical data x1 and x2 from the specified position when triggering the current level filtering, read the two output historical data y1 and y2 from the first position and the second position corresponding to the current level filtering from the intermediate data module, read the coefficients b0, b1, b2, a1, a2 corresponding to the current input data x0, the two input historical data x1 and x2 and the two output historical data y1 and y2 from the coefficient memory 2022, and output them to the multiplier accumulator 2023;

[0097] Figure 5a The structure diagram corresponding to the first-stage filtering calculation is shown in FIG. 2 . The data selector 2021 reads x0, x1, x2 from registers rx0, rx1, and rx2, and the intermediate data manager 2011 reads y1, y2 from the intermediate data memory 2012 and sends them to the data selector 2021;

[0098] Figure 5b For the corresponding structure diagram of the filter calculation of other levels except the first level, the tail manager 301 reads data from ry0, ry1 and ry2 in the tail data register 302, obtains x0, x1, x2 and sends it to the data selector 2021, and the intermediate data manager 2011 reads y1 and y2 from the intermediate data memory 2012 and sends it to the data selector 2021;

[0099] The coefficient memory 2022 is used to store the coefficients b0, b1, b2, a1, a2 corresponding to the current input data x0, two input historical data x1, x2 and two output historical data y1, y2 of each level of filtering;

[0100] The multiplier-accumulator 2023 is used to perform multiplication and accumulation operations according to the current input data x0, the two input historical data x1, x2, the two output historical data y1, y2 and the corresponding coefficients b0, b1, b2, a1, a2, to obtain the current output data. The specific calculation formula is as follows:

[0101] ACC = ACC + C*D (2)

[0102] Among them, the multiplier accumulator 2023 accumulates the original accumulated value by multiplying the coefficient sequence (b0, b1, b2, a1, a2) by the corresponding data sequence (x0, x1, x2, y1, y2).

[0103] Optionally, the calculation module 202 further includes: an output latch 2024 connected to the multiplier-accumulator and used for latching current output data y_next.

[0104] In this way, when a section of calculation is completed, the tail data manager 301 reads the current output data from the output latch 2024 to y_next, and interacts with the intermediate data management 2011 to read y1 and y2 from the intermediate data storage 2012 to ry1 and ry2.

[0105] like Figure 8 As shown, for the calculation module, when the calculation of section M starts, x0, x1, x2 of this section are read in the above manner, that is, y_next, y1, y2 of the previous section are stored in ry0, ry1 and ry2, and y1 and y2 of this section are read in the above manner; y1 is latched to ry1, and y2 is latched to ry2; the multiplier accumulator starts calculation; y_next is latched to ry0 at the end of calculation; the calculation of section M+1 is triggered, and the calculation process is the same as above and will not be repeated here.

[0106] like Figure 5a and Figure 5b As shown, the IIR filter device also includes:

[0107] The beat counter 50 is used to start counting when filtering. Each time the beat count value increases by one, a parameter group is read correspondingly. The parameter group includes: current input data x0 and corresponding coefficients, first input historical data x1 and corresponding coefficients, second input historical data x2 and corresponding coefficients, first output historical data y1 and corresponding coefficients, second output historical data y2 and corresponding coefficients. It is determined that the beat count value is cleared when the current level of filtering is completed. The set beat count of the beat counter is 5. In this way, the beat count value of the beat counter is counted from 0, 1, 2, 3, and 4 to achieve 5 beat counts. The data selector 2021 can read one data and corresponding coefficient for each beat according to the beat count, and complete the data reading of x0, x1, x2, y1, y2 and the corresponding coefficients b0, b1, b2, a1, and a2;

[0108] The section counter 40 is used to add one to the section count value when any level of filtering is completed. When the section count value reaches the set number of sections, it is determined that all levels of filtering are completed and the section count value is cleared. When the beat counter counts the set number of beats, the section count value is added by one, and is cleared when it is determined to count the set number of sections. The set number of sections is N. That is, every 5 beats, ACC outputs the result y_next value of the current section. When all sections are completed, they are latched by the output latch as the final result output.

[0109] The control of the calculation process can be realized through the section counter 40 and the beat counter 50. The head data manager, the middle data manager and the tail data manager read and latch the data according to the count values ​​of the beat counter and the section counter. The specific process is as follows: Fig. 9 As shown:

[0110] Enter a batch of data;

[0111] Start the section counter and initialize the section counter;

[0112] Start the beat counter and initialize the beat counter;

[0113] Other components work according to the count values ​​of the beat counter and the beat count value;

[0114] The beat count value is increased by 1, and one of the data among x0, x1, x2, y1, y2 and its coefficient is read;

[0115] Determine whether the beat count is greater than or equal to 5 according to the beat count value;

[0116] If the beat count reaches 5, it means that x0, x1, x2, y1, y2 and the corresponding coefficients b0, b1, b2, a1, a2 have been read. Multiplication and accumulation operations are performed using x0, x1, x2, y1, y2 and the corresponding coefficients b0, b1, b2, a1, a2. After the calculation is completed, the section count value is increased by 1. If the beat count does not reach 5, it returns to other components to work according to the count values ​​of the section counter and the beat count value;

[0117] Determine whether the node count value is greater than or equal to N;

[0118] If the beat count value reaches N, it means that the N-level filtering is completed and the current filtering calculation ends. If the beat count value does not reach N, the beat counter is started, the beat counter is initialized, and the next level of filtering calculation begins.

[0119] The present application also provides a filtering method of an IIR filter device, such as Fig.10 As shown, including:

[0120] Step 101, using the header data module to receive current input data, and latching it in a manner of overwriting the earliest input historical data, so as to keep storing the current input data and two input historical data;

[0121] Step 102, triggering the first level filtering, reading the current input data and two input historical data from the head data module, and reading two output historical data from the first position and the second position corresponding to the first level filtering in the intermediate data module for filtering;

[0122] Step 103, determine to trigger other level filtering, read current input data and two input historical data from the tail data module, read two output historical data from the first position and the second position of the level filtering in the intermediate data module for filtering, and store the two input historical data in the tail storage module as two input historical data for the next level filtering;

[0123] Step 104, when it is determined that any level of filtering is completed, the tail data module is used to store the output data of the filtering at that level as the current input data of the next level of filtering; and the next level of filtering is triggered until the filtering is completed.

[0124] As an optional implementation, counting starts when any level of filtering is triggered, and each time the count value is increased by one, a corresponding parameter group is read, and the parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, and second output historical data and corresponding coefficients;

[0125] Determine that the beat count value is cleared when the current level filtering is completed;

[0126] When any level of filtering is completed, the node count value is increased by one. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

[0127] In this embodiment of the application, a parameter group is read in the following order:

[0128] The second input historical data x2 and coefficient b2, the current input data x0 and coefficient b0, the first output historical data y1 and coefficient a1, the first input historical data x1 and coefficient b1, the second output historical data y2 and coefficient a2.

[0129] The specific rules for selecting data by the data selector are shown in Table 1:

[0130] Table 1

[0131]

[0132] The coefficient memory stores all IIR coefficients and outputs the coefficients according to the value of the beat counter as shown in Table 2:

[0133] Table 2

[0134]

[0135] Only by following the data reading arrangement in Table 1 and Table 2 can the conflict between data reading and writing and coefficient reading be avoided, and all data reading and writing can be completed within 5 clock cycles, thus avoiding the idle cycle of the data storage and computing module during data reading and writing, and reducing the clock speed requirement.

[0136] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0137] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An IIR filter device, characterized in that: include: The head data module receives the current input data, latches it in a way of overwriting the earliest input historical data, and keeps storing the current input data and two input historical data; A filtering module, used for performing multi-stage filtering calculations, including an intermediate data module and a calculation module, wherein the intermediate data module includes a first position and a second position corresponding to each stage of filtering, and uses the first position corresponding to each stage of filtering to store output data of the filtering at the stage, and exchanges the addresses of the first position and the second position, and when the calculation module determines to trigger the current stage of filtering, reads the current input data and two input historical data from the specified position, reads the data of the first position and the second position corresponding to the current stage of filtering from the intermediate data module as two output historical data, stores the two output historical data in the tail data module as two input historical data of the next stage of filtering, obtains the current output data after filtering, and triggers the next stage of filtering; A tail data module, used to store the two output historical data read by the calculation module as two input historical data, and when any level of filtering is completed, store the output data of the filtering at that level as the current input data of the next level of filtering; Among them, the designated position of the first level of filtering is the head data module, and the designated position of other levels of filtering is the tail data module.

2. The device according to claim 1, characterized in that The header data module includes: Header data registers, including a first header register, a second header register and a third header register; The header data manager is used to receive current input data, latch the input history data of the first header register to the second header register / third header register where the earliest input history data is located, and latch the current input data to the first header register.

3. The device according to claim 2, characterized in that The header data register also includes a status register; The header data manager is used to trigger the change of the state value of the state register after the first level of filtering is completed; When the state value is a first state value, the input historical data of the first register is latched into the second register, and when the state value is a second state value, the input historical data of the first register is latched into the third register.

4. The device according to claim 1, characterized in that The intermediate data module includes: An intermediate data manager stores output data of each level of filtering in a first location and exchanges addresses of the first location and a second location; The intermediate data storage device includes a first address and a second address corresponding to each level of filtering, wherein the first address and the second address are used to store corresponding data.

5. The device according to claim 1, characterized in that The calculation module comprises: A data selector is used to read the current input data and two input historical data from the specified position when triggering the current level filtering, read the data at the first position and the second position corresponding to the current level filtering from the intermediate data module as two output historical data, read the coefficients corresponding to the current input data, the two input historical data and the two output historical data from the coefficient memory, and output them to the multiplier accumulator; A coefficient memory, used to store coefficients corresponding to current input data, two input historical data and two output historical data of each level of filtering; The multiplier-accumulator is used to perform multiplication-accumulation operations according to current input data, two input historical data, two output historical data and corresponding coefficients to obtain current output data.

6. The device according to claim 5, characterized in that The calculation module also includes: The output latch is connected to the multiplier-accumulator and is used to latch the current output data.

7. The device according to claim 1, characterized in that The tail data module includes: The tail data manager is used to latch the output history data read by the calculation module from the first position corresponding to the current level filter in the intermediate data module into the second tail register when the current level filter is calculated, latch the output history data read from the second position corresponding to the current level filter in the intermediate data module into the third tail register, and latch the output data of the current level filter into the first tail register when the current level filter is completed; The tail data registers include a first tail register, a second tail register and a third tail register.

8. The device according to claim 1, characterized in that Also includes: A beat counter is used to start counting when any level of filtering is triggered. Each time the beat count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, second output historical data and corresponding coefficients. When the current level of filtering is completed, the beat count value is cleared; The node counter is used to increase the node count value by one when any level of filtering is completed. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

9. A filtering method of an IIR filter device, characterized in that: include: The head data module is used to receive the current input data, and latches the data in a manner of overwriting the earliest input historical data, so as to keep storing the current input data and two input historical data; Trigger the first level of filtering, read the current input data and two input historical data from the head data module, and read two output historical data from the first position and the second position corresponding to the first level of filtering in the intermediate data module for filtering; Determine to trigger other level filtering, read current input data and two input historical data from the tail data module, read two output historical data from the first position and the second position of the level filtering in the intermediate data module for filtering, and store the two output historical data in the tail storage module as two input historical data for the next level filtering; When it is determined that any level of filtering is completed, the tail data module is used to store the output data of the filtering at that level as the current input data of the next level of filtering; And trigger the next level filtering until the filtering is completed.

10. The method according to claim 9, characterized in that Also includes: When any level of filtering is triggered, counting starts. Each time the count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, and second output historical data and corresponding coefficients; Determine that the beat count value is cleared when the current level filtering is completed; When any level of filtering is completed, the node count value is increased by one. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

11. The method according to claim 9, characterized in that Read a parameter group in the following order: The second input historical data and corresponding coefficients, the current input data and corresponding coefficients, the first output historical data and corresponding coefficients, the first input historical data and corresponding coefficients, the second output historical data and corresponding coefficients; The first input historical data is earlier than the second input historical data, and the first output historical data is earlier than the second output historical data.

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