FPGA-based reconfigurable digital filter

Abstract

The invention discloses a reconfigurable digital filter based on an FPGA (Field Programmable Gate Array), which comprises an FPGA chip, and the FPGA chip comprises an ROM (Read Only Memory) module, an RAM (Random Access Memory) module, a multiplier, an accumulator, a pulse counter, a filtering control module and a reconfiguration interface, the inertial device comprises at least one gyroscope and an accelerometer, and the gyroscope and the accelerometer both output pulse signals to the FPGA chip; the pulse counter counts the pulse signals, converts count values of the N channels into floating-point numbers after the counting period is ended, and stores the floating-point numbers into the RAM module; the filtering control module controls the multiplier, the accumulator, the ROM module and the RAM module to work cooperatively, multiplexes the same group of computing resources to process signals of N channels in series, and completes filtering calculation according to an IIR filter algorithm; the reconfiguration interface can adjust the order and coefficient of the IIR filter online. The filter replaces DSP filtering, the FPGA resource utilization rate is increased, the chip cost is reduced, the execution efficiency of an inertial navigation system is improved, and online reconstruction can be carried out to adapt to different filtering requirements.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a reconfigurable digital filter based on FPGA. Background Technology

[0002] Inertial device signal processing is a core component of embedded inertial navigation systems. The inertial devices mainly include gyroscopes for measuring the angular increment of the carrier and accelerometers for measuring sensitive axial acceleration. Their output signals need to be quantized and digitally filtered to eliminate noise such as high-frequency power supply interference and laser gyroscope jitter. In existing technologies, inertial device signal filtering is typically performed in a DSP, which must serially complete both signal preprocessing (filtering) and inertial navigation calculation. The filtering process encroaches on the execution time of the main program (navigation calculation), resulting in low overall system efficiency. In recent years, the parallel computing advantages of FPGAs have become increasingly apparent, as they can process multiple inertial device signals simultaneously. However, traditional FPGA filtering schemes, in pursuit of parallelism, consume a large amount of on-chip resources (such as ROM, RAM, and multipliers), significantly increasing the cost of FPGA chips and making it difficult to balance high-efficiency processing with low-cost requirements. Summary of the Invention

[0003] This invention aims to provide a reconfigurable digital filter based on FPGA, which achieves high-efficiency preprocessing of N channels of inertial device signals while occupying less on-chip FPGA resources; improves the overall execution efficiency of the inertial navigation system, reduces the cost of FPGA chip selection; and supports online reconstruction of filter order and coefficients to adapt to filtering requirements in different working environments.

[0004] To achieve the aforementioned technical objectives, this invention discloses a reconfigurable digital filter based on an FPGA, comprising an FPGA chip. The FPGA chip includes a ROM module for storing IIR filter coefficients, a RAM module for storing input and output signals from previous times, a multiplier for weighted operations on the signals and IIR filter coefficients, an accumulator for summing the weighted signals, a pulse counter for counting output pulses from an inertial device, a filter control module for controlling the filter calculation process, and a reconfiguration interface for online modification of filter parameters. The inertial device includes at least one gyroscope and at least one accelerometer. The gyroscope measures the angular increment of the carrier, and the accelerometer measures the sensitive axial acceleration. Both the gyroscope and the accelerometer output pulse signals to the FPGA chip. The pulse counter counts the pulse signals, and after the counting cycle, converts the count values ​​of N channels into floating-point numbers and stores them in the RAM module, where N is a positive integer and N≥1. The filter control module controls the multiplier, accumulator, ROM module, and RAM module. The M modules work together, reusing the same set of computing resources to serially process signals from N channels and complete filtering calculations according to the IIR filter algorithm; the reconfiguration interface can receive control signals from external devices or internal FPGA modules to adjust the order and coefficients of the IIR filter online.

[0005] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the ROM module stores the forward coefficients b[k] and feedback coefficients a[k] of the IIR filter in the order of b[0], b[1]...b[L-1] and a[1], a[2]...a[L-1] during the FPGA chip compilation stage. After the FPGA chip is powered on and initialized, the ROM module can output the target coefficients through the address signal.

[0006] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the RAM includes a previous time step signal input storage RAM module and a previous time step signal output storage RAM module; the previous time step signal input storage RAM module is used to store N channels of floating-point form input signals x[nk], k is 0 to L-1, and the previous time step signal output storage RAM module is used to store N channels of floating-point form output signals y[nk], k is 1 to L-1, and both the previous time step signal input storage RAM module and the previous time step signal output storage RAM module use the channel number and the delay step k as address encoding.

[0007] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the counting period of the pulse counter is consistent with the signal output period of the inertial device. After each counting period, the pulse counter automatically converts the pulse count values ​​of N channels into 32-bit floating-point numbers and triggers the write enable signal of the RAM module to write the floating-point numbers into the corresponding RAM module.

[0008] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the filtering control module controls the filtering of N channels to be performed serially in the order of channel 1, channel 2... channel N. The filtering calculation time of a single channel is less than the ratio of the counting period to N, and the total calculation time of N channels is less than the counting period, ensuring that the filtering calculation of the previous cycle is completed before the signal of the next counting cycle arrives.

[0009] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the operation process of the IIR filter algorithm is shown in the following formula:

[0010]

[0011] Where y[n] is the result after filtering by the IIR filter, and L is the total number of forward coefficients. L controls the order of the forward path and feedback path of the IIR filter. When k = 0, the weighted value b[0]x[n] of the current input signal x[n] and the forward coefficient b[0] is calculated and directly included in the current output calculation to avoid ignoring the signal lag caused by the direct participation of the current input. When k > 1, the weighted value b[k]x[n-1] of the previous input signal x[n-1] and b[k] and the weighted value a[k]y[n-1] of the previous output signal y[n-1] and a[k] are calculated at the same time. Through the early intervention of the feedback signal, the response speed of the filter to dynamic high-frequency interference is enhanced.

[0012] Furthermore, this invention provides a reconfigurable digital filter based on an FPGA, wherein the input enable signal of the multiplier is controlled by the readout valid signal of the RAM module. When the RAM module successfully reads x[nk] or y[nk], the readout valid signal goes high, triggering the multiplier to receive the signal and the corresponding coefficient and perform the multiplication operation. The output valid signal of the multiplier serves as the enable signal of the accumulator. The accumulator performs the summation operation only when the multiplier outputs a valid weighted value, thus avoiding invalid data from being mixed into the calculation.

[0013] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the FPGA chip integrates N result latch registers. After the filtering calculation of each channel is completed, the output result of the accumulator is automatically latched into the corresponding register. When all N channels have completed the filtering calculation, the filtering control module pulls up the filtering effective signal to indicate to the external navigation calculation module that the filtering result in the register can be read.

[0014] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the reconfiguration interface supports access from multiple types of devices and the navigation control module inside the FPGA; the user sends an order modification command or new coefficient data through the reconfiguration interface, and the filter control module automatically updates the coefficient storage content in the ROM module and the address decoding logic of the RAM module after receiving the command, thereby realizing uninterrupted online reconstruction of filter parameters.

[0015] Furthermore, the present invention provides a reconfigurable digital filter based on FPGA, wherein the IIR filter is a low-pass filter, and by adjusting the order L, the forward coefficient b[k], and the feedback coefficient a[k], it can specifically eliminate high-frequency power supply interference and laser gyroscope jitter signals in the inertial device signal.

[0016] The beneficial effects of this invention are as follows: Using an FPGA as the core processing unit, compared to the traditional DSP-based filtering scheme, it fully leverages the parallel computing characteristics and customizable hardware resources of the FPGA, separating the filtering function from the serial tasks of the DSP, allowing the DSP to focus on core tasks such as navigation calculation, significantly improving the overall execution efficiency of the inertial navigation system; the filtering control module serially processes signals from N channels by reusing the same set of computing resources, avoiding the waste of FPGA resources caused by configuring computing resources separately for each channel, and significantly reducing the occupancy rate of key resources such as ROM, RAM, and multipliers; the pulse counter counts the pulse signals output by the inertial device and converts them into floating-point numbers for storage, ensuring the accuracy of signal quantization and providing a reliable raw data foundation for subsequent filtering calculations; the reconfiguration interface supports online adjustment of the order and coefficients of the IIR filter, adapting to filtering requirements under different working environments without power interruption, greatly enhancing the environmental adaptability and flexible scalability of the filter; the core module of inertial device signal processing is integrated into the FPGA. Internally, GA simplifies the system hardware architecture, reduces signal transmission delay between modules, and improves the real-time performance and stability of filtering. Ultimately, precise filtering effectively improves the signal-to-noise ratio of the output signal of the inertial device, providing higher quality measurement data for the inertial navigation system and helping the system achieve more accurate navigation calculations. Attached Figure Description

[0017] Figure 1This is a schematic diagram of the structure of a reconfigurable digital filter based on FPGA according to the present invention;

[0018] Figure 2 This is a schematic diagram illustrating the calculation process of an IIR filter in a reconfigurable digital filter based on FPGA according to the present invention.

[0019] Figure 3 This is a schematic diagram of the operation flow of a reconfigurable digital filter based on FPGA according to the present invention. Detailed Implementation

[0020] The following description, in conjunction with the accompanying drawings, provides a detailed explanation and illustration of a reconfigurable digital filter based on an FPGA according to the present invention.

[0021] like Figure 1 and combined Figure 3 As shown, this embodiment of the invention discloses a reconfigurable digital filter based on an FPGA, including an FPGA chip. The FPGA chip includes a ROM module for storing IIR filter coefficients, a RAM module for storing input and output signals from previous times, a multiplier for performing weighted operations on the signals and IIR filter coefficients, an accumulator for performing weighted signal summation operations, a pulse counter for counting output pulses of an inertial device, a filter control module for controlling the filter calculation process, and a reconfiguration interface for online modification of filter parameters. The inertial device includes at least one gyroscope and at least one accelerometer. The gyroscope is used to measure the load. The body angle increment is measured by an accelerometer, which measures the sensitive axial acceleration. Both the gyroscope and accelerometer output pulse signals to the FPGA chip. A pulse counter counts the pulse signals, and after the counting cycle ends, it converts the count values ​​of N channels into floating-point numbers and stores them in the RAM module. N is a positive integer and N≥1. The filter control module controls the multiplier, accumulator, ROM module, and RAM module to work together, reusing the same set of computing resources to serially process the signals of N channels and complete the filtering calculation according to the IIR filter algorithm. The reconfiguration interface can receive control signals from external devices or internal FPGA modules to adjust the order and coefficients of the IIR filter online.

[0022] Specifically, the FPGA chip can be a Xilinx Artix-7 series chip, which is a medium-resource and low-cost chip. The inertial device is connected to the FPGA chip through GPIO ports and outputs pulse signals at a frequency of 5KHz. The pulse counter completes a count every 200μs, converting the count values ​​of N channels into 32-bit floating-point numbers and writing them into the input RAM module. The filter control module, according to state machine logic, controls the multiplier to read coefficients from ROM and signals from RAM, performs weighted operations, and then sends the sum to the accumulator to obtain the filtering result. The reconfiguration interface is connected to an external MCU (such as STM32F407) (or other external processors such as DSPs, or other control function modules inside the FPGA) via SPI, and can receive orders or coefficient modification commands.

[0023] In this embodiment, an FPGA is used as the core processing unit. Compared with the traditional solution that relies on a DSP for filtering, this fully leverages the parallel computing capabilities and customizable hardware resources of the FPGA. The filtering function is separated from the serial tasks of the DSP, allowing the DSP to focus on core tasks such as navigation calculation, significantly improving the overall execution efficiency of the inertial navigation system. The filtering control module reuses the same set of computing resources to serially process signals from N channels, avoiding the waste of FPGA resources caused by configuring computing resources separately for each channel, and significantly reducing the occupancy rate of critical resources such as ROM, RAM, and multipliers. The pulse counter counts and converts the pulse signals output by the inertial device. Floating-point storage ensures the accuracy of signal quantization, providing a reliable raw data foundation for subsequent filtering calculations. The reconfiguration interface supports online adjustment of the order and coefficients of the IIR filter, adapting to filtering requirements in different working environments without power interruption, greatly enhancing the filter's environmental adaptability and flexible scalability. Integrating the core module of inertial device signal processing into the FPGA simplifies the system hardware architecture, reduces signal transmission delay between modules, and improves the real-time performance and stability of filtering processing. Ultimately, precise filtering effectively improves the signal-to-noise ratio of the inertial device output signal, providing higher-quality measurement data for the inertial navigation system and helping the system achieve more accurate navigation calculations.

[0024] In one embodiment of the present invention, the ROM module stores the forward coefficients b[k] and feedback coefficients a[k] of the IIR filter in the order of b[0], b[1]...b[L-1] and a[1], a[2]...a[L-1] during the FPGA chip compilation stage. After the FPGA chip is powered on and initialized, the ROM module can output the target coefficients through the address signal.

[0025] Specifically, during compilation, the FPGA software uses the ROM initialization file (.coe) function of the Vivado tool to write the coefficients of the IIR filter into the ROM initialization file in the order of b[0], b[1], b[2] (if L=3), a[1], a[2]. After compilation, the file is burned into the FPGA configuration chip. After the FPGA is powered on, the configuration chip automatically loads the initialization file. The ROM does not need to wait for external data to be written and can output the coefficients using the k value and channel number as the address (e.g., the address of b[0] of channel 1 is 0x0001).

[0026] In this embodiment, the FPGA chip can load the coefficients required by the ROM module immediately after power-on. Compared to the traditional method of reading coefficients from the DSP after power-on, the filter startup time is significantly shortened, ensuring that the inertial navigation system quickly enters a stable working state after power-on, unaffected by the number of channels N. Storing coefficients in a fixed order allows address decoding to be performed using only a simple combination of the k-value and channel number, eliminating the need for a complex address mapping module and significantly reducing the FPGA's internal logic resources (LUT) usage. Pre-stored coefficients avoid the risk of packet loss during external data transmission in the initial power-on phase, improving the accuracy of coefficient reading and the stability of filter calculations.

[0027] In one embodiment of the present invention, the RAM includes a previous time step signal input storage RAM module and a previous time step signal output storage RAM module; the previous time step signal input storage RAM module is used to store N channels of floating-point input signals x[nk], k is 0 to L-1, and the previous time step signal output storage RAM module is used to store N channels of floating-point output signals y[nk], k is 1 to L-1, and both the previous time step signal input storage RAM module and the previous time step signal output storage RAM module use the channel number and the delay step k as address encoding.

[0028] Specifically, the previous time-time signal input storage RAM module (input RAM) and the previous time-time signal output storage RAM module (output RAM) can be dual-port RAMs. The address encoding of the input RAM is an 8-bit address consisting of a 4-bit channel number and a 4-bit delay step k (e.g., the address of channel 1, k=0 is 0x10), storing x[nk] for N channels, k=0 to L-1. The address encoding of the output RAM is the same, storing y[nk] for N channels, k=1 to L-1. Read and write operations are implemented through different ports, and read operations (for multiplier to fetch data) and write operations (for storing new signals) can be executed in parallel.

[0029] In this embodiment, input and output signals are stored separately and encoded using channel numbers and k values. Regardless of whether N is 1 or N=8, address conflicts between signals from different channels and with different delays are prevented, thus preventing data storage errors. The dual-port RAM supports simultaneous writing of new signals and reading of old signals, reducing the signal storage and retrieval time for each channel by at least half. The encoding method requires only simple bit-by-bit logic for address generation, significantly reducing logic resource consumption compared to custom address mapping schemes.

[0030] In one embodiment of the present invention, the counting period of the pulse counter is consistent with the signal output period of the inertial device. After each counting period, the pulse counter automatically converts the pulse count values ​​of N channels into 32-bit floating-point numbers and triggers the write enable signal of the RAM module to write the floating-point numbers into the corresponding RAM module.

[0031] Specifically, the pulse counter uses a high-frequency clock counting and periodic triggering method. Each counting cycle (200μs) is triggered by the FPGA's internal timer. After the cycle ends, the counter converts the pulse count values ​​of N channels into 32-bit floating-point numbers through the integer-to-floating-point IP core, and at the same time generates a RAM write enable signal to write the floating-point number to the corresponding address of the input RAM.

[0032] In this embodiment, the error of pulse counting can be reduced, the quantization accuracy of the inertial device signal can be improved, and the accuracy is not affected by the number of channels N. The use of floating-point format avoids the truncation error of integer operation, improves the calculation accuracy of subsequent multipliers and accumulators, and the timer can automatically trigger the counting cycle without external control signals, reducing the interaction between the FPGA chip and external devices and improving system stability.

[0033] In one embodiment of the present invention, the filtering control module controls the signal filtering of N channels to be performed serially in the order of channel 1, channel 2, ... channel N. The filtering calculation time of a single channel is less than the ratio of the counting period to N, and the total calculation time of N channels is less than the counting period, ensuring that the filtering calculation of the previous cycle is completed before the signal of the next counting cycle arrives.

[0034] Specifically, the state machine of the filter control module has N+1 states: calculation for channel 1, calculation for channel 2, ..., calculation for channel N, and waiting for the next cycle. The calculation state of each channel includes seven sub-states: reading b[k] and x[nk], multiplication, accumulation (forward summation), reading a[k] and y[nk], multiplication, accumulation (feedback summation), and result latching. Through timing simulation optimization, the calculation time of a single channel is controlled within a specified time and a certain amount of time is reserved as timing redundancy.

[0035] In this embodiment, the total computation time is less than the counting cycle, ensuring that the filtering calculation of the previous cycle is completed before the pulse count value of the next cycle arrives, thus avoiding data packet loss. Redundancy time can handle timing delays caused by variations in FPGA operating temperature, preventing timing violations and improving reliability in wide-temperature environments. Serial processing requires only one set of computing resources (multipliers, accumulators) to meet the needs of N channels. Compared to parallel processing schemes, reduced resource consumption further lowers FPGA costs.

[0036] like Figure 2 As shown in one embodiment of the present invention, the operation process of the IIR filter algorithm is as follows:

[0037]

[0038] Where y[n] is the result after filtering by the IIR filter, and L is the total number of forward coefficients. L controls the order of the forward path and feedback path of the IIR filter. When k = 0, the weighted value b[0]x[n] of the current input signal x[n] and the forward coefficient b[0] is calculated and directly included in the current output calculation to avoid ignoring the signal lag caused by the direct participation of the current input. When k > 1, the weighted value b[k]x[n-1] of the previous input signal x[n-1] and b[k] and the weighted value a[k]y[n-1] of the previous output signal y[n-1] and a[k] are calculated at the same time. Through the early intervention of the feedback signal, the response speed of the filter to dynamic high-frequency interference is enhanced.

[0039] Specifically, in the IIR filter algorithm, the order of both the forward path (controlled by the forward coefficient b[k]) and the feedback path (controlled by the feedback coefficient a[k]) is L-1 (the forward path contains L coefficients from k=0 to L-1, with an order of L-1; the feedback path contains L-1 coefficients from k=1 to L-1, with an order of L-1). The forward path needs to read the input signal x[nk] from k=0 to L-1, and the feedback path needs to read the output signal y[nk] from k=1 to L-1. The upper limit of the delay steps for both is L-1. Therefore, the address generation inside the FPGA can share a single set of L-based decoding logic, eliminating the need to design two sets of address circuits for different orders and reducing logic resource consumption. The forward path includes k=0 (the current input directly participates), and the current input x[n] is directly weighted and included in the output y[n], avoiding the delay caused by ignoring the current input (as in existing technologies starting from k=1, the current input must wait for the next input before it can be processed). This improves the response speed to dynamic signals (angular increments / accelerometers during rapid carrier motion) from inertial devices (such as gyroscopes and accelerometers). The current input contains the most real-time valid information (such as the current angular increment), and its direct participation in the calculation preserves these details more completely, improving the fidelity of the filtered signal. The feedback path starts from k=1 (using only historical outputs). The feedback path only uses the outputs from past moments (y[n-1], y[n-2], ...), not the y[n] to be calculated currently, avoiding the recursive contradiction of calculating y[n] with unknown y[n] and ensuring stable recursive calculation of the filter. The historical output contains previous filtering results. Through weighting by the feedback term, historical information can be used to continuously correct the current output, resulting in more thorough attenuation of high-frequency interference (such as 10kHz power supply interference and 5kHz-8kHz gyroscope frequency dithering). By modifying L, the number of forward / feedback coefficients can be directly changed, thereby adjusting the filter order (order = L-1). The higher the order, the stronger the ability to process complex frequencies (such as suppressing narrowband interference); the lower the order, the less computation is required (adapting to FPGA resources). This approach makes online reconfiguration of filters more convenient (such as dynamically changing the order based on the interference intensity).

[0040] In this embodiment, the current input directly participates in the calculation at k=0. Compared with the existing technology that ignores k=0 and starts the calculation from k=1, the signal processing delay is reduced by one sampling period (200μs), and the filtering response speed to dynamic signals (such as gyroscope signals when the carrier turns rapidly) is improved. This advantage is not affected by the number of channels or the filter order. When k>1, the feedback signal (y[n-1]a[k]) intervenes early, which can quickly adjust the output to cancel high-frequency interference (such as 10KHz power supply interference). Through spectrum analysis, the suppression ratio of 10KHz interference is improved, and the suppression ratio of 5KHz-8KHz dithering signals of laser gyroscope is improved. The calculation logic at k=0 and k>1 can reuse the same address generation and multiplication control module, without the need for additional special processing logic design, reducing the occupation of FPGA internal logic resources.

[0041] In one embodiment of the present invention, the input enable signal of the multiplier is controlled by the read valid signal of the RAM module. When the RAM module successfully reads x[nk] or y[nk], the read valid signal is pulled high, triggering the multiplier to receive the signal and the corresponding coefficient and perform the multiplication operation. The output valid signal of the multiplier serves as the enable signal of the accumulator. The accumulator performs the summation operation only when the multiplier outputs a valid weighted value, thus avoiding invalid data from being mixed into the calculation.

[0042] Specifically, the RAM module's read interface is configured with a read-valid signal. When the RAM's address and chip select signals are stable and data has been read onto the data bus, this signal is pulled high (active high). This signal is directly used as the input enable signal for the multiplier. Only when this enable signal is high will the multiplier receive x[nk] / y[nk] and the coefficients and perform multiplication. The multiplier's output is configured with a multiplication-valid signal. When the multiplication operation is complete and the result is correct, this signal is pulled high, serving as the enable signal for the accumulator. The accumulator performs summation only when this enable signal is high.

[0043] In this embodiment, the multiplier is triggered only when the RAM data is valid, and the accumulator is triggered only when the multiplication result is valid. This prevents the multiplier from performing empty calculations when no data has been read from the RAM and prevents the accumulator from adding data incorrectly when the multiplication result is wrong. The multiplier and accumulator are in a sleep state when the enable signal is low. Compared to a scheme that operates continuously, this reduces the dynamic power consumption of the FPGA chip and extends the battery life of the embedded system. Synchronous control of the enable signal clarifies the timing paths of the multiplier and accumulator, reduces the difficulty of timing constraints, and improves the timing convergence speed of the FPGA chip.

[0044] In one embodiment of the present invention, the FPGA chip also integrates N result latch registers. After the filtering calculation of each channel is completed, the output result of the accumulator is automatically latched into the corresponding register. When all N channels have completed the filtering calculation, the filtering control module pulls up the filtering effective signal to indicate to the external navigation solution module that the filtering result in the register can be read.

[0045] Specifically, the FPGA integrates N 32-bit result latch registers, corresponding to N channels. After the filtering calculation for each channel is completed, the filtering control module generates a latch signal to latch the accumulator output into the corresponding register. Once all N channel registers have been latched, the filtering control module pulls the filter validity signal high. The external navigation calculation module (such as a DSP) detects this signal and reads the filtering result from the register when it is high.

[0046] In this embodiment, register latching prevents the accumulator from overwriting the current result in subsequent channel calculations, ensuring that the navigation solution module reads a complete and stable filtering result. A high-level, valid filtering signal serves as a clear indicator that the result is ready; the navigation solution module does not need to poll and wait, but only reads data when the signal is high, improving the efficiency of inter-module interaction.

[0047] In one embodiment of the present invention, the reconfiguration interface supports access from multiple types of devices and the navigation control module inside the FPGA; the user sends an order modification command or new coefficient data through the reconfiguration interface, and the filter control module automatically updates the coefficient storage content in the ROM module and the address decoding logic of the RAM module after receiving the data, thereby realizing uninterrupted online reconstruction of the filter parameters.

[0048] Specifically, the reconfiguration interface can adopt a dual-mode approach combining SPI and internal bus. The external interface supports the SPI protocol (which can connect to MCUs and DSPs), while the internal interface supports the AXI4-Lite bus (which can connect to the navigation control module inside the FPGA). The reconfiguration commands sent by the user include order commands, coefficient length commands, or new coefficient data. After receiving the command, the filter control module first pauses the calculation of the current channel (if it is in the process of calculation, it waits for the current channel to complete before pausing), then updates the coefficient data in the ROM module (through the write enable port of the ROM module) and the address decoding logic of the RAM, and resumes the filter calculation after the update is completed.

[0049] This embodiment supports two reconfiguration methods: external MCU / DSP and internal module. External adaptation allows for remote debugging (e.g., modifying parameters at a ground station), while internal adaptation allows for real-time adjustment (e.g., the navigation control module dynamically modifies coefficients based on interference intensity), improving the filter's scene adaptability. The method of pausing current channel calculation and resuming after an update avoids data loss during reconstruction. The signal processing interruption time during reconstruction is less than the calculation time for a single channel, improving system continuity.

[0050] In one embodiment of the present invention, the IIR filter is a low-pass filter. By adjusting the order L, the forward coefficient b[k], and the feedback coefficient a[k], the high-frequency power supply interference and the frequency dithering signal of the laser gyroscope in the inertial device signal can be specifically eliminated.

[0051] Specifically, the order L of the IIR low-pass filter is adjusted according to the interference frequency (e.g., L=4 when suppressing 10kHz power supply interference, and L=3 when suppressing 5kHz dithering signals). The forward coefficient b[k] and feedback coefficient a[k] can be generated using Matlab's Butterworth filter design tool. Taking N=6 (3 gyroscopes + 3 accelerometers) as an example, tests using a spectrum analyzer show that the amplitude of the 10kHz interference in the gyroscope signal before filtering is 0.5V, which can be reduced to 0.02V after filtering, and the amplitude of the 8kHz dithering signal can be reduced from 0.3V to 0.03V.

[0052] In this embodiment, the low-pass characteristic can accurately filter out high-frequency interference (power supply interference, frequency dithering signals) above 2kHz, while retaining effective signals below 2kHz (carrier angular increment, acceleration), thus improving the fidelity of the effective signal. After the interference amplitude is reduced, the angular increment measurement error of the gyroscope and the acceleration measurement error of the accelerometer can be reduced, thereby improving the measurement accuracy of the inertial device. By adjusting the cutoff frequency and order, the filter can be adapted to different types of gyroscopes (such as laser gyroscopes and MEMS gyroscopes) and accelerometers without redesigning the hardware, thus improving device compatibility.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and simple improvements made on the substantive content of the present invention should be included within the protection scope of the present invention.

Claims

1. An FPGA-based reconfigurable digital filter, characterized by: The FPGA chip comprises a ROM module for storing IIR filter coefficients, a RAM module for storing input signals and output signals at previous time, a multiplier for implementing signal and IIR filter coefficient weighting operation, an accumulator for implementing weighted signal summation operation, a pulse counter for counting output pulses of inertial devices, a filter control module for controlling filter calculation flow, and a reconfiguration interface for online modification of filter parameters; the inertial devices comprise at least one gyroscope for measuring carrier angular increment and at least one accelerometer for measuring sensitive axis acceleration, and both the gyroscope and the accelerometer output pulse signals to the FPGA chip; the pulse counter counts the pulse signals, converts the count values of N channels into floating point numbers at the end of a counting period, and stores the floating point numbers into the RAM module, where N is a positive integer and N≥1; the filter control module controls the multiplier, the accumulator, the ROM module and the RAM module to work cooperatively, serially processes signals of N channels by multiplexing the same set of calculation resources, and completes filter calculation according to the IIR filter algorithm; and the reconfiguration interface can receive control signals of external devices or internal modules of the FPGA, and adjusts the order and coefficients of the IIR filter online.

2. The FPGA-based reconfigurable digital filter of claim 1, wherein: The ROM module stores the forward coefficients b[k] and feedback coefficients a[k] of the IIR filter in the order of b[0], b[1]…b[L-1] and a[1], a[2]…a[L-1] during the compilation stage of the FPGA chip, and the ROM module can output target coefficients through address signals after the FPGA chip is powered on and initialized.

3. The FPGA-based reconfigurable digital filter of claim 1, wherein: The RAM comprises a previous time signal input storage RAM module and a previous time signal output storage RAM module; the previous time signal input storage RAM module is used for storing input signals x[n-k] of N channels in floating point form, where k is 0 to L-1, and the previous time signal output storage RAM module is used for storing output signals y[n-k] of N channels in floating point form, where k is 1 to L-1, and both the previous time signal input storage RAM module and the previous time signal output storage RAM module are address coded by channel number and delay step number k.

4. The FPGA-based reconfigurable digital filter of claim 1, wherein: The counting period of the pulse counter is consistent with the signal output period of the inertial devices, and after each counting period ends, the pulse counter automatically converts the pulse count values of N channels into 32-bit floating point numbers, and triggers the write enable signal of the RAM module to write the floating point numbers into the corresponding RAM module.

5. The FPGA-based reconfigurable digital filter of claim 1, wherein: The filter control module controls the signal filtering of N channels to be serially executed in the order of the 1st channel, the 2nd channel, …, and the Nth channel, the filter calculation time of a single channel is less than the ratio of the counting period to N, and the total calculation time of N channels is less than the counting period, so that the filter calculation of the previous period is completed before the signal of the next counting period arrives.

6. The FPGA-based reconfigurable digital filter of claim 1, wherein: The operation process of the IIR filter algorithm is shown in the following formula: Wherein, y[n] is the result of the IIR filter filtering, L is the total number of forward coefficients, the order of the IIR filter forward path and feedback path is controlled by L, when k=0, the weighted value b[0]x[n] of the input signal x[n] at the current moment and the forward coefficient b[0] is calculated, and is directly included in the current output calculation, so as to avoid signal lag caused by the direct participation of the current input; when k>1, the weighted value b[k]x[n-1] of the input signal x[n-1] at the previous moment and b[k] and the weighted value a[k]y[n-1] of the output signal y[n-1] at the previous moment and a[k] are calculated, the response speed of the filter to dynamic high-frequency interference is enhanced through the early intervention of the feedback signal.

7. The FPGA-based reconfigurable digital filter of claim 1, wherein: The input enable signal of the multiplier is controlled by the read valid signal of the RAM module, when the RAM module successfully reads x[n-k] or y[n-k], the read valid signal is pulled high, triggering the multiplier to receive the signal and the corresponding coefficient and perform multiplication operation; the output valid signal of the multiplier is used as the enable signal of the accumulator, only when the multiplier outputs the valid weighted value, the accumulator performs summation operation, avoiding invalid data mixing into the calculation.

8. The FPGA-based reconfigurable digital filter of claim 1, wherein: The FPGA chip also integrates N result latch registers inside, after the filter calculation of each channel is completed, the output result of the accumulator is automatically latched to the corresponding register; when the filter calculation of N channels is completed, the filter control module pulls up the filter valid signal to prompt the external navigation solution module to read the filter result in the register.

9. The FPGA-based reconfigurable digital filter of claim 1, wherein: The reconfiguration interface supports multiple types of device access and the navigation control module inside the FPGA; the user sends order modification instructions or new coefficient data through the reconfiguration interface, the filter control module automatically updates the coefficient storage content in the ROM module and the address decoding logic of the RAM module after receiving, realizing uninterrupted online reconstruction of the filter parameters.

10. The FPGA-based reconfigurable digital filter of claim 1, wherein: The IIR filter is a low-pass filter, by adjusting the order L, the forward coefficient b[k] and the feedback coefficient a[k], the power supply high-frequency interference in the inertial device signal and the laser gyroscope dither frequency signal can be eliminated.

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