ADC uninterrupted sampling method based on DMA

Abstract

The invention aims to provide a DMA-based ADC uninterrupted sampling method, which realizes length-unlimited ADC uninterrupted sampling by utilizing a DMA half-transmission interruption mode and a DMA cyclic transmission mode, and simultaneously processes sampling data in parallel by a CPU (Central Processing Unit), thereby improving the sampling performance and efficiency. The method comprises an ADC unit, a DMA unit and a CPU unit. The method comprises the following steps: S1, initializing; s2, starting sampling; s3, when the data volume is greater than half of the size of the buffer, checking the state of the lower half buffer, and releasing the data; s4, performing data processing on the upper half buffer area, and adjusting the state of the buffer area when the processing is completed; s5, when the data volume is larger than the size of the buffer, checking the state of the upper half buffer, and releasing the data; s6, performing data processing on the lower half buffer area, and adjusting the state of the buffer area when the processing is completed; and S7, repeating the steps S3 to S6 until the sampling is finished. The method is applied to the technical field of data sampling.

Description

Technical Field

[0001] The present invention is applied to the technical field of data sampling, and particularly relates to an ADC uninterrupted sampling method based on DMA. Background Art

[0002] The analog-to-digital converter (ADC) is mainly used to convert continuously transmitted analog signals into digital signals, so that the processor (CPU) can quickly process and analyze the transmitted information. Usually, when the sampling rate (the number of times the analog signal is collected per second) is low, triggered sampling is used, such as triggering a sample once every second. When the sampling rate is high, continuous sampling is used. The ADC continuously samples at a certain sampling rate, and notifies the CPU to read the sampled data after the sampling is completed. However, the CPU usually performs many tasks. Frequent notifications to the CPU to read ADC data will reduce the efficiency of the system. Therefore, when the sampling rate is high, the direct memory access (DMA) method is usually used to read the ADC data. That is, the DMA is notified after the sampling is completed, and the DMA automatically stores the data in the specified memory buffer. When the CPU needs to use the data, this part of the data will be processed uniformly, such as Figure 1 Shown is a typical usage of DMA-based ADC.

[0003] In the typical usage of ADC sampling based on DMA, it is assumed that the size of the DMA buffer is M, the size of the ADC signal that needs to be continuously collected is N, the ADC sampling rate is Vc, and the speed at which the CPU processes ADC data is Vp. Since the system memory and DMA buffer size are limited, the size of M is limited. When N>M, it is necessary to re-enable ADC conversion and DMA transmission after processing the data in the buffer, which will cause ADC signal discontinuity. This is not allowed in situations where digital filtering, signal analysis, etc. are required. ADC sampling and CPU data processing are carried out sequentially. It is necessary to wait until M data collections are completed before starting to process the data in the buffer. The data processing delay is M / Vc, and the data processing delay is high. Every time the CPU is notified to process data, M data needs to be processed. The single data processing time is M / Vp. The instantaneous large amount of data to be processed will affect the CPU's execution of other tasks.

[0004] If an ADC uninterrupted sampling method can be provided, the integrity of the sampled data can be well guaranteed and the sampled data can be processed stably. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide an ADC uninterrupted sampling method based on DMA. By utilizing DMA half-transfer interrupt and DMA cyclic transmission mode, ADC uninterrupted sampling of unlimited length is achieved while the CPU processes the sampled data in parallel, thereby improving the sampling performance and efficiency.

[0006] The technical solution adopted by the present invention is: the present invention includes an ADC unit, a DMA unit and a CPU unit, the input end of the ADC unit is connected to the acquisition signal source, the output end of the ADC unit communicates with the CPU unit through the DMA unit, the DMA unit includes a connected DMA controller and a buffer manager, and the sampling method also includes the following specific steps: Step S1, initializing the ADC unit, the DMA controller and the buffer manager, wherein the ADC unit is configured in a continuous conversion mode, the DMA controller is configured in a cyclic mode, the buffer manager sets a buffer pointer and a buffer size, sets an upper half buffer flag and a lower half buffer flag to be empty, and initializes the half buffer to-be-processed signal quantity to be 0; Step S2, starting the ADC unit for continuous sampling and conversion, and the DMA controller transferring the converted data to the buffer manager; Step S3, when the data transmitted by the DMA controller is greater than half of the current buffer size, a DMA transmission half interrupt is generated, and the interrupt signal is sent to the CPU unit, and the CPU unit executes a DMA transmission half interrupt processing, and the DMA transmission half interrupt processing performs a lower half buffer flag check, and if the lower half buffer flag is empty, the flag is cleared to continue the transmission, and then a half buffer to be processed semaphore is released; The operation of releasing the semaphore to be processed in the half buffer in step S4 and step S3 wakes up the data processing thread, and the data processing thread obtains the semaphore and processes the data in the upper half buffer; when the data processing is completed, the upper half buffer flag is set to empty, and the thread continues to wait for the semaphore to be processed in the half buffer; Step S5, when the data transmitted by the DMA controller is larger than the current buffer size, a DMA transmission completion interrupt is generated, and the interrupt signal is sent to the CPU unit, and the CPU unit executes DMA transmission completion interrupt processing, and the DMA transmission completion interrupt processing performs an upper half buffer flag check, and if the upper half buffer flag is empty, the flag is cleared to continue the transmission, and then a half buffer to be processed semaphore is released; Step S6: The operation of releasing the semaphore to be processed in the half buffer in step S3 wakes up the data processing thread, and the data processing thread obtains the semaphore and processes the data in the lower half buffer; when the data processing is completed, the lower half buffer flag is set to empty, and the thread continues to wait for the semaphore to be processed in the half buffer; Step S7: Since the ADC unit is configured in continuous conversion mode and the DMA controller is configured in cyclic mode, the DMA controller will automatically start transmission from the buffer start address after each transmission is completed, and repeat steps S3 to S6 until the acquisition is completed.

[0007] It can be seen from the above scheme that by dividing the buffer into upper and lower halves, the functions of the upper and lower buffers are alternated, one half is used for DMA data transmission, and the other half is used for CPU data processing, thereby achieving the effect of parallel execution of data transmission and data processing. This ensures that there is no need to pause DMA during the entire sampling process, and there is no limit on the data acquisition length, so as to achieve the effect of uninterrupted ADC sampling.

[0008] A preferred solution is to first cache data in the upper buffer when entering step S3 from step S2.

[0009] A preferred solution is that if the lower half buffer flag is not empty in step S3, it indicates that the buffer overflows, and at this time, a corresponding error handling function is executed according to the specific situation.

[0010] A preferred solution is that if the upper buffer is not empty in step S5, it indicates that the buffer overflows, and a corresponding error handling function is executed according to the specific situation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a flowchart of a typical ADC usage method based on DMA; Figure 2 is a system block diagram of the present invention; Figure 3 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0012] like Figure 2 and Figure 3As shown, in this embodiment, the present invention includes an ADC unit, a DMA unit and a CPU unit, the input end of the ADC unit is connected to the acquisition signal source, the output end of the ADC unit communicates with the CPU unit through the DMA unit, and the DMA unit includes a connected DMA controller and a buffer manager; the ADC unit is used to convert an external analog signal into a digital signal; the DMA controller is used to sequentially transmit the converted digital signal from the ADC to the DMA buffer; the buffer manager is composed of a DMA buffer, two flag bits and a semaphore; the CPU unit has the following functions: 1. It is used to process the data transferred to the buffer by DMA; 2. When the DMA controller generates a DMA transfer half interrupt, the DMA transfer half interrupt processing is executed; 3. When the DMA controller generates a DMA transfer completion interrupt, the DMA transfer completion interrupt processing is executed; the sampling method also includes the following specific steps: Step S1, initializing the ADC unit, the DMA controller and the buffer manager, wherein the ADC unit is configured in a continuous conversion mode; the DMA controller is configured in a cyclic mode, and when the DMA controller is in the cyclic mode, when the buffer is full, the data is automatically transmitted from the first byte of the buffer; the buffer manager sets the buffer pointer and the buffer size, and sets the upper half buffer flag and the lower half buffer flag to be empty, and initializes the half buffer to be processed signal to 0; Step S2, starting the ADC unit for continuous sampling conversion, the DMA controller transferring the converted data to the buffer manager, and the buffer manager buffering the data from the starting position of the buffer; Step S3, when the data transmitted by the DMA controller is greater than half of the current buffer size, a DMA transmission half interrupt is generated, and the interrupt signal is sent to the CPU unit, and the CPU unit executes a DMA transmission half interrupt processing, and the DMA transmission half interrupt processing performs a lower half buffer flag check, and if the lower half buffer flag is empty, the flag is cleared to continue the transmission, and then a half buffer to be processed semaphore is released; if the lower half buffer flag is not empty, it indicates that the buffer overflows, and at this time, the corresponding error handling function is executed according to the specific situation; The operation of releasing the semaphore to be processed in the half buffer in step S4 and step S3 wakes up the data processing thread, and the data processing thread obtains the semaphore and processes the data in the upper half buffer; at this time, the entire system is in a state of parallel operation of data processing and data communication; when the data processing is completed, the upper half buffer flag is set to empty, and the semaphore to be processed in the half buffer is continued to be waited; Step S5, when the data transmitted by the DMA controller is larger than the current buffer size, a DMA transmission completion interrupt is generated, and the interrupt signal is sent to the CPU unit, and the CPU unit executes DMA transmission completion interrupt processing, and the DMA transmission completion interrupt processing performs an upper half buffer flag check, and if the upper half buffer flag is empty, the flag is cleared to continue the transmission, and then a half buffer to be processed semaphore is released; if the upper half buffer is not empty, it indicates that the buffer overflows, and at this time, the corresponding error handling function is executed according to the specific situation; In step S6 and step S3, the operation of releasing the semaphore to be processed in the half buffer wakes up the data processing thread, and the data processing thread obtains the semaphore and processes the data in the lower half buffer. At this time, the entire system is in a state of parallel operation of data processing and data communication. When the data processing is completed, the lower half buffer flag is set to empty, and the waiting for the semaphore to be processed in the half buffer continues. Step S7: Since the ADC unit is configured in continuous conversion mode and the DMA controller is configured in cyclic mode, the DMA controller will automatically start transmission from the buffer start address after each transmission is completed, and repeat steps S3 to S6 until the acquisition is completed.

[0013] By alternating the functions of the upper and lower half buffers, one half is used for DMA data transmission and the other half is used for CPU data processing. Data transmission and data processing are performed in parallel. Due to the use of the DMA loop mode, the entire process does not need to pause DMA, and there is no limit on the data acquisition length, which can achieve uninterrupted acquisition and processing of ADC signals. Each time half of the buffer is acquired and data is processed once, the data processing delay is M / 2Vc, and the single data processing time is M / 2Vp, which is better than the typical use method of ADC based on DMA.

[0014] Although the embodiments of the present invention are described with practical solutions, they do not constitute limitations on the meaning of the present invention. For those skilled in the art, it is obvious to modify the implementation scheme and combine it with other solutions based on this description.

Claims

1. A DMA-based ADC uninterrupted sampling method, comprising an ADC unit, a DMA unit and a CPU unit, wherein the input end of the ADC unit is connected to a collection signal source, the output end of the ADC unit communicates with the CPU unit through the DMA unit, and the DMA unit comprises a connected DMA controller and a buffer manager, characterized in that: The sampling method also includes the following specific steps: Step S1, initializing the ADC unit, the DMA controller and the buffer manager, wherein the ADC unit is configured in a continuous conversion mode, the DMA controller is configured in a cyclic mode, the buffer manager sets a buffer pointer and a buffer size, sets an upper half buffer flag and a lower half buffer flag to be empty, and initializes the half buffer to-be-processed signal quantity to be 0; Step S2, starting the ADC unit for continuous sampling and conversion, and the DMA controller transferring the converted data to the buffer manager; Step S3, when the data transmitted by the DMA controller is greater than half of the current buffer size, a DMA transmission half interrupt is generated, and the interrupt signal is sent to the CPU unit, and the CPU unit executes a DMA transmission half interrupt processing, and the DMA transmission half interrupt processing performs a lower half buffer flag check, and if the lower half buffer flag is empty, the flag is cleared to continue the transmission, and then a half buffer to be processed semaphore is released; The operation of releasing the semaphore to be processed in the half buffer in step S4 and step S3 wakes up the data processing thread, and the data processing thread obtains the semaphore and processes the data in the upper half buffer; when the data processing is completed, the upper half buffer flag is set to empty, and the thread continues to wait for the semaphore to be processed in the half buffer; Step S5, when the data transmitted by the DMA controller is larger than the current buffer size, a DMA transmission completion interrupt is generated, and the interrupt signal is sent to the CPU unit, and the CPU unit executes DMA transmission completion interrupt processing, and the DMA transmission completion interrupt processing performs an upper half buffer flag check, and if the upper half buffer flag is empty, the flag is cleared to continue the transmission, and then a half buffer to be processed semaphore is released; Step S6: The operation of releasing the semaphore to be processed in the half buffer in step S3 wakes up the data processing thread, and the data processing thread obtains the semaphore and processes the data in the lower half buffer; when the data processing is completed, the lower half buffer flag is set to empty, and the thread continues to wait for the semaphore to be processed in the half buffer; Step S7: Since the ADC unit is configured in continuous conversion mode and the DMA controller is configured in cyclic mode, the DMA controller will automatically start transmission from the buffer start address after each transmission is completed, and repeat steps S3 to S6 until the acquisition is completed.

2. The ADC uninterrupted sampling method based on DMA according to claim 1, characterized in that: When entering step S3 from step S2, data in the upper buffer is first cached.

3. The ADC uninterrupted sampling method based on DMA according to claim 1, characterized in that: In step S3, if the lower buffer flag is not empty, it indicates that the buffer overflows. At this time, the corresponding error handling function is executed according to the specific situation.

4. The ADC uninterrupted sampling method based on DMA according to claim 1, characterized in that: In step S5, if the upper buffer is not empty, it indicates that the buffer overflows, and at this time, the corresponding error handling function is executed according to the specific situation.

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