FPGA development board circuit and burning method

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) development board circuit and a burning method, the FPGA development board circuit comprises a microprocessor circuit, a memory chip and a CPLD (Complex Programmable Logic Device) chip, the microprocessor circuit comprises a main control chip power supply circuit with a main control chip, a work indication circuit, a clock circuit, a crystal oscillator circuit, a reset circuit, a Type-c interface circuit and a JTAG (Joint Test Action Group) interface circuit. The development board can be connected with a computer through a USB-Type-C data line, and the computer can identify the development board into a USB flash disk format, so that the packaged code file can be directly burnt in a dragging manner, the entry threshold of an FPGA for teenagers is reduced, the general requirements of general developers can be met, and the development board can be conveniently and rapidly programmed. And the novel burning mode can simplify the burning program to a great extent, so that the workload of developers is greatly reduced under the condition that the basic development process is not changed, and the entry threshold is reduced.

Description

Technical Field

[0001] The invention relates to the field of FPGA development boards, in particular to an FPGA development board circuit and a burning method. Background Art

[0002] In the current FPGA development process, in order to burn the software program into the development board, we need to choose different IDEs according to the production companies of different development boards. This process may involve several different softwares, which increases the learning cost and time cost; at the same time, this process is not stable, which increases the possibility of errors.

[0003] In the current field of youth education, in order to inspire young people's thinking ability, hands-on ability, cultivate interest in the fields of electronics and circuits, and lay a foundation for future physics learning, it is undoubtedly very beneficial to start learning about FPGA development boards. However, in the actual production practice process, sufficient knowledge reserves are often required before contacting FPGA development boards, including but not limited to requiring students to master basic circuit knowledge and understand how the development board and computer interact, the software needed, how to install and configure, etc. Therefore, it is often difficult for young students to start learning about FPGA development boards. To put it bluntly, there is often an unequal situation between effort and reward.

[0004] Therefore, those skilled in the art provide an FPGA development board circuit and a programming method to solve the problems raised in the above background technology. Summary of the invention

[0005] The purpose of the present invention is to provide a FPGA development board circuit and a burning method to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] An FPGA development board circuit includes a microprocessor circuit, a memory chip and a CPLD chip. The microprocessor circuit includes a main control chip power supply circuit, a work indication circuit, a clock circuit, a crystal oscillator circuit, a reset circuit, a Type-C interface circuit and a JTAG interface circuit. The main control chip is also connected to the memory chip and the CPLD chip respectively.

[0008] The crystal oscillator circuit consists of quartz crystal resonators Y1 and Y2 connected in series with capacitors C7, C8 and C9, C10 respectively, among which the quartz crystal resonator Y1 is also connected in parallel with a resistor R13. Both ends of the capacitor of the quartz crystal resonator Y1 circuit are connected to the ground, and only the capacitor end of the quartz crystal resonator Y2 circuit is connected to the ground. The clock signal is input and output from both ends of the resonator.

[0009] As a further solution of the present invention: the main control chip power supply circuit includes a voltage stabilizing chip and multiple groups of filter circuits, each group of filter circuits is composed of multiple capacitors C connected in parallel and grounded; the working indication circuit is composed of at least one light emitting diode LED and one resistor R connected in series.

[0010] As a further solution of the present invention: the reset circuit is composed of a resistor R14, a button U3, and a capacitor C11. One end of the button U3 is grounded, and the other end is connected to the resistor R14 and the capacitor C11 respectively. The other end of the capacitor C11 is grounded, and the other end of the resistor R14 is connected to the main control chip power supply circuit.

[0011] As a further solution of the present invention: the memory chip is an important component for realizing data storage and management, and the CPLD chip is used for realizing data logic functions.

[0012] As a further solution of the present invention: the switch button is composed of a touch button SW and a resistor R connected in series, and the button is composed of a color temperature and brightness adjustment button BIN and a resistor R.

[0013] As a further solution of the present invention: the Type-c interface circuit has A4, B9, B4, A9, B8, A5, B7, A6, A7, B6, A8, B5, A1, B1, A12, B12 and S1 interfaces, the A5 interface in the Type-c interface circuit is connected to resistor R7 and then grounded, the A7 and B7 interfaces in the Type-c interface circuit are connected to resistor R8, the A6 and B6 interfaces in the Type-c interface circuit are connected to resistor R9, and the A1, B1, A12, B12 and S1 interfaces in the Type-c interface circuit are connected to ground.

[0014] As a further solution of the present invention, the circuit board has 2428 equivalent LTU4s and 3036 flip-flops, which can meet the general requirements for FPGA and has the characteristics of low cost and clear and concise structure.

[0015] A method for burning an FPGA development board circuit, wherein a development board having the FPGA development board circuit described above is connected to a computer through a USB-Type-C data cable, and the computer recognizes the development board as a U disk format, so that the packaged code file is directly burned by dragging and dropping.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention can connect the development board to the computer through a USB-Type-C data cable. The computer can identify the development board as a U disk format, so that the packaged code file can be directly burned by dragging and dropping, which reduces the entry threshold of FPGA for teenagers and can meet the general needs of general developers. Moreover, the new burning method can greatly simplify the burning procedure. Under the condition that the basic development process remains unchanged, the workload of developers is greatly reduced, and the entry threshold is lowered. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit diagram of a microprocessor circuit in the present invention;

[0019] Figure 2 is a circuit diagram of the power supply in the present invention;

[0020] Figure 3 A circuit diagram of a switch, a button, and a light emitting diode in the present invention;

[0021] Figure 4 is a circuit diagram of BANK1 in the present invention;

[0022] Figure 5 It is the circuit diagram of BANK2 in the present invention;

[0023] Figure 6 It is the circuit diagram of BANK3 in the present invention;

[0024] Figure 7 It is the circuit diagram of BANK0 in the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] See also Figures 1 to 7 In an embodiment of the present invention, an FPGA development board circuit includes a microprocessor circuit, a memory chip and a CPLD chip, characterized in that: the microprocessor circuit includes a main control chip power supply circuit, a work indication circuit, a clock circuit, a crystal oscillator circuit, a reset circuit, a Type-c interface circuit and a JTAG interface circuit with a main control chip, and the main control chip is also connected to the memory chip and the CPLD chip respectively;

[0027] The crystal oscillator circuit consists of quartz crystal resonators Y1 and Y2 connected in series with capacitors C7, C8 and C9, C10 respectively, among which the quartz crystal resonator Y1 is also connected in parallel with a resistor R13. Both ends of the capacitor of the quartz crystal resonator Y1 circuit are connected to the ground, and only the capacitor end of the quartz crystal resonator Y2 circuit is connected to the ground. The clock signal is input and output from both ends of the resonator.

[0028] Among them, the main control chip power supply circuit includes a voltage stabilizing chip and multiple groups of filter circuits, each group of filter circuits is composed of multiple capacitors C connected in parallel and grounded; the working indication circuit is composed of at least one light emitting diode LED and one resistor R connected in series.

[0029] Among them, the reset circuit is composed of a resistor R14, a button U3, and a capacitor C11. One end of the button U3 is grounded, and the other end is connected to the resistor R14 and the capacitor C11 respectively. The other end of the capacitor C11 is grounded, and the other end of the resistor R14 is connected to the main control chip power circuit.

[0030] Among them, memory chips are important components for data storage and management, and CPLD chips are used to implement data logic functions.

[0031] Among them, the switch button is composed of a touch button SW and a resistor R in series, and the button is composed of a color temperature and brightness adjustment button BIN and a resistor R.

[0032] Among them, the Type-c interface circuit has A4, B9, B4, A9, B8, A5, B7, A6, A7, B6, A8, B5, A1, B1, A12, B12 and S1 interfaces. The A5 interface in the Type-c interface circuit is connected to resistor R7 and then grounded. The A7 and B7 interfaces in the Type-c interface circuit are connected to resistor R8. The A6 and B6 interfaces in the Type-c interface circuit are connected to resistor R9. The A1, B1, A12, B12 and S1 interfaces in the Type-c interface circuit are connected and then grounded.

[0033] In this embodiment, the circuit board has 2428 equivalent LTU4s and 3036 flip-flops, which can meet the general needs of FPGA and has the characteristics of low cost, clear and concise structure. The memory chip is an important component for data storage and management. In addition, drag-and-drop programming breaks through the shackles of traditional complex programming methods and can be completed using only one data line.

[0034] Specifically, burning the program into the development board mainly means burning the program into the CPLD chip that constitutes the main functions of the FPGA development board. The PGC4KG CPLD chip is produced by Tsinghua Unigroup Tongchuang Co., Ltd., which also released Pango Design Suite (PDS), an integrated design and development software that supports its full range of FPGA chips. To burn the program into the FPGA development board based on the PGC4KG chip, you need to use the PDS software. The present application can use the PDS to flash the designed firmware (that is, burn a program that will not change when the development board is reset) into the FPGA development board (here, to the MCU chip STM32F103C8Tx). After that, the MCU can simulate the desktop PDS and burn it directly. For users, it is equivalent to skipping the process of using the PDS, which greatly reduces the software learning cost and the complexity of the process.

[0035] In this embodiment, Figure 4-Figure 7 It is divided according to the pin supply voltage and corresponding functions of the PGC4KG CPLD chip. Each BANK can independently support different I / O standards, and can adapt to different electrical standards and I / O physical characteristics by burning different programs.

[0036] The present invention also has a new burning method, which can connect the development board to the computer with a USB-Type-C data cable, and the computer can recognize the development board as a U disk format, so that the packaged code file can be directly burned by dragging and dropping. Lowering the entry threshold of FPGA for teenagers, first of all, the FPGA development board has common development board functions and can meet the general needs of general developers. Secondly, the new burning method can be said to greatly simplify the burning procedure. Under the condition that the basic development process remains unchanged, it greatly reduces the workload of developers and lowers the entry threshold.

[0037] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An FPGA development board circuit, including a microprocessor circuit, a memory chip and a CPLD chip, characterized in that: The microprocessor circuit includes a main control chip power supply circuit, a work indication circuit, a clock circuit, a crystal oscillator circuit, a reset circuit, a Type-c interface circuit and a JTAG interface circuit with a main control chip, and the main control chip is also connected to a memory chip and a CPLD chip respectively; The crystal oscillator circuit is composed of quartz crystal resonators Y1 and Y2 connected in series with capacitors C7, C8 and C9, C10 respectively, wherein the quartz crystal resonator Y1 is also connected in parallel with a resistor R13, the two ends of the capacitor of the quartz crystal resonator Y1 circuit are connected to the ground, and only the capacitor end of the quartz crystal resonator Y2 circuit is connected to the ground, and the clock signal is input and output from the two ends of the resonator.

2. The FPGA development board circuit according to claim 1, characterized in that: The main control chip power supply circuit includes a voltage stabilizing chip and multiple filter circuits, each filter circuit is composed of multiple capacitors C connected in parallel and grounded; the work indication circuit is composed of at least one light emitting diode LED and one resistor R connected in series.

3. The FPGA development board circuit according to claim 1, characterized in that: The reset circuit is composed of a resistor R14, a button U3, and a capacitor C11. One end of the button U3 is grounded, and the other end is connected to the resistor R14 and the capacitor C11 respectively. The other end of the capacitor C11 is grounded, and the other end of the resistor R14 is connected to the main control chip power circuit.

4. The FPGA development board circuit according to claim 1, characterized in that: The switch button is composed of a touch button SW and a resistor R connected in series, and the button is composed of a color temperature and brightness adjustment button BIN and a resistor R.

5. The FPGA development board circuit according to claim 1, characterized in that: The Type-c interface circuit comprises A4, B9, B4, A9, B8, A5, B7, A6, A7, B6, A8, B5, A1, B1, A12, B12 and S1 interfaces. The A5 interface in the Type-c interface circuit is connected to resistor R7 and then grounded. The A7 and B7 interfaces in the Type-c interface circuit are connected to resistor R8. The A6 and B6 interfaces in the Type-c interface circuit are connected to resistor R9. The A1, B1, A12, B12 and S1 interfaces in the Type-c interface circuit are connected to ground.

6. A method for programming a circuit of an FPGA development board, characterized in that: By connecting a development board having the FPGA development board circuit described in any one of claims 1 to 5 to a computer through a USB-Type-C data cable, the computer recognizes the development board as a USB flash drive format, so that the packaged code file can be directly burned by dragging and dropping.

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