Fast programming OTP device and preparation method thereof
By adding electrodes and applying voltage to the bottom of the substrate of the OTP memory device, the problem of excessive voltage during the programming process is solved, and the rapid programming and performance improvement of the OTP memory cell is achieved.
Patent Information
- Application Number
- CN202510094020.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-05-02
AI Technical Summary
During the programming process of OTP memory devices, the large voltage applied may cause the insulating layer under the select gate to pass through, resulting in device failure, and no effective solution has been proposed in the prior art.
By adding electrodes at the bottom of the substrate and applying a voltage, such that a channel carrier tunneling to the floating gate layer can be achieved by simply applying a smaller voltage to the selected gate, thereby enabling rapid programming of the OTP memory cell.
This method not only shortens the programming cycle time of the OTP memory cell, but also avoids device damage caused by excessive voltage, significantly improving the working performance of the OTP memory device.
Smart Images
Figure CN119922915A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of OTP storage technology, in particular to a fast-programmed OTP device and a preparation method thereof. Background Art
[0002] OTP (One Time Programmable) memory, namely one-time programmable memory, belongs to non-volatile memory (NVM), so it has the excellent characteristics of fast access speed, safety and stability of non-volatile memory. As a one-time storage device, it is relative to multiple programming, and its programming process is irreversible. Because it is low-cost and programmable, it is widely used in technical fields such as data-unchanging keys, chip storage, redundant design, and radio frequency identification to process data.
[0003] The manufacturing method of a one-time programmable memory device is basically carried out in the following steps: forming a well, source, drain, gate oxide, select gate, floating gate, gate polysilicon and sidewall on a substrate using conventional processes; depositing plasma etching and etching away the thin film outside the silicide barrier layer; performing a cobalt metal process to form cobalt metal in the silicon exposed area; depositing plasma again to form a floating gate as a data storage protective film; depositing a dielectric film between layers and finally forming a contact hole through chemical mechanical polishing, photolithography and etching. The storage state of the OTP memory device includes two states: storing information 0 and information 1: when the storage state of the device is 0, the reverse PN junction formed by the N+ doped area and the P+ doped area isolates the bit line and the channel area from each other; when the storage information is 1, the N+ doped area and the P+ doped area will cause the resistance structure generated by thermal breakdown to connect the bit line and the channel area, and the thermal breakdown between them will turn on the PNPN transistor. This is because the thermal breakdown causes the anode to connect to the forward potential, the cathode to ground, and the bit line is suspended and the control electrode is connected to the current.
[0004] When programming the above OTP memory cell, in order to charge the carriers into the floating gate, a voltage opposite to that of the channel carriers must be applied to the control gate. The greater the applied voltage, the shorter the time it takes for the channel carriers to charge into the floating gate. In this process, in order to achieve fast programming, the voltage applied to the select gate must be large enough, but this will also lead to a problem. If the programming conditions are not met within a certain period of time, the large voltage applied will penetrate the insulating layer under the select gate, causing the select gate to be conductive with the channel, and the device to fail.
[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention
[0006] In view of the problems in the related art, the present invention proposes a fast-programmed OTP device and a preparation method thereof to overcome the above-mentioned technical problems existing in the existing related art.
[0007] To this end, the specific technical solution adopted by the present invention is as follows:
[0008] According to one aspect of the present invention, a fast programming OTP device is provided, including a substrate, a reserved contact hole is opened at the inner bottom of the substrate, a second conductive type well is arranged on the top of the substrate, and a plurality of gate dielectric layers are arranged on the top of the second conductive type well.
[0009] Furthermore, in order to add an electrode at the bottom of the substrate and apply a voltage thereto, so that only a small voltage is applied to the select gate, the channel carriers can be tunneled to the floating gate layer, and the OTP memory cell can be quickly programmed, which can not only shorten the programming cycle of the OTP memory cell, but also avoid the situation where the device is damaged by excessive voltage, thereby greatly improving the working performance of the OTP memory device, the top of the gate dielectric layer is respectively provided with a first field effect transistor select gate and a second field effect transistor floating gate, and both sides of the first field effect transistor select gate and the second field effect transistor floating gate are provided with A side wall is arranged, a plasma silicon oxide film is arranged on the outside of the side wall, a cobaltized metal matching the first field effect transistor selection gate is arranged on one side of the inner top of the plasma silicon oxide film, a first contact hole, a second contact hole and a third contact hole are opened in sequence inside the plasma silicon oxide film, the first contact hole is located on one side of the first field effect transistor selection gate, the second contact hole is located on the top of the first field effect transistor selection gate, the third contact hole is located on one side of the second field effect transistor floating gate, an electrode is arranged on the bottom of the substrate, and the first field effect transistor selection gate and the second field effect transistor floating gate respectively form a trapezoidal structure with the side walls on both sides.
[0010] It should be noted that when the first conductivity type is P type and the second conductivity type is N type, when a forward voltage is applied to the electrode, under the action of the electric field, the hole concentration in the lower part of the floating gate of the second field effect transistor is higher than that in other areas. Therefore, only a smaller voltage needs to be applied at this time, and the holes tunnel into the floating gate of the second field effect transistor. A smaller negative voltage is applied to the select gate of the first field effect transistor, a positive voltage difference is applied between the source and the drain (source voltage>drain voltage), and the holes tunnel into the floating gate of the second field effect transistor to complete the programming operation.
[0011] When the first conductivity type is N type and the second conductivity type is P type, when a negative voltage is applied to the electrode, under the action of the electric field, the electron concentration in the lower part of the floating gate is higher than that in other areas. Therefore, only a smaller voltage needs to be applied at this time, and the electrons tunnel into the floating gate of the second field effect transistor. A smaller forward voltage is applied to the select gate of the first field effect transistor, and a reverse voltage difference is applied between the source and the drain (source voltage < drain voltage), and the electrons tunnel into the floating gate of the second field effect transistor to complete the programming operation.
[0012] According to another aspect of the present invention, a method for preparing a fast-programmed OTP device is also provided, the method comprising:
[0013] S1, obtaining a substrate of a first conductivity type, forming a reserved contact hole at the bottom of the substrate by an etching process, and forming a well of a second conductivity type at the top of the substrate by a doping process;
[0014] S2, forming a gate dielectric layer on the top of the second conductive type well, depositing and growing polysilicon on the surface of the gate dielectric layer, and etching the polysilicon to form a first field effect transistor select gate and a second field effect transistor floating gate respectively;
[0015] S3, depositing an oxide insulating layer outside the first field effect transistor select gate and the second field effect transistor floating gate, and etching the oxide insulating layer to form sidewalls located on both sides of the first field effect transistor select gate and the second field effect transistor floating gate;
[0016] S4, depositing a plasma silicon oxide film on the second conductive type well by a vacuum process, using the plasma silicon oxide film as a mask, and performing a cobaltization metal process on the mask to form a cobaltized metal;
[0017] S5, depositing again to form a plasma silicon oxide film, and using an etching process to filter impurities to form a FG data storage protection film, depositing an interlayer dielectric film, and using an etching process to form a first contact hole, a second contact hole, and a third contact hole;
[0018] S6. Use the back-end process to form the source, select gate and drain of the OTP device, and install electrodes at the bottom of the substrate to form a unit cross-sectional structure of the OTP device to complete the preparation of the OTP device.
[0019] Furthermore, the reserved contact hole is located directly below the floating gate of the second field effect transistor in the horizontal direction, and the upper surface of the reserved contact hole contacts the lower surface of the second conductive type well.
[0020] Furthermore, the source and gate of the first field effect transistor and the second field effect transistor are implanted into the second conductive type well by first conductive type ions, and the drain of the first field effect transistor and the source of the second field effect transistor are the same active region.
[0021] The beneficial effects of the present invention are as follows: by adding electrodes at the bottom of the substrate and applying voltage thereto, the present invention enables channel carriers to tunnel to the floating gate layer only when a relatively small voltage is applied to the selection gate, thereby realizing rapid programming of the OTP memory cell. This not only shortens the programming cycle of the OTP memory cell, but also avoids damage to the device caused by excessive voltage, thereby greatly improving the working performance of the OTP memory device. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 is a schematic structural diagram of a substrate in a fast-programmed OTP device according to an embodiment of the present invention;
[0024] Figure 2 It is a schematic diagram of the coordination between the substrate and the second conductivity type well in a fast programming OTP device according to an embodiment of the present invention;
[0025] Figure 3 It is a schematic diagram of the coordination between the first field effect transistor selection gate and the second field effect transistor floating gate in a fast programming OTP device according to an embodiment of the present invention;
[0026] Figure 4 1 is a schematic diagram of the structure of a sidewall in a fast programming OTP device according to an embodiment of the present invention;
[0027] Figure 5 It is a schematic diagram of MOS source and drain injection in a fast programming OTP device according to an embodiment of the present invention;
[0028] Figure 6 1 is a schematic structural diagram of a plasma silicon oxide film in a fast-programmed OTP device according to an embodiment of the present invention;
[0029] Figure 7 is a schematic structural diagram of a cobaltized metal in a fast-programmed OTP device according to an embodiment of the present invention;
[0030] Figure 8 1 is a schematic structural diagram of a plasma silicon oxide film 8 in a fast programming OTP device according to an embodiment of the present invention;
[0031] Fig. 9 It is a schematic diagram of the coordination of a first contact hole, a second contact hole and a third contact hole in a fast programming OTP device according to an embodiment of the present invention;
[0032] Fig.10 is a schematic structural diagram of a fast-programmed OTP device according to an embodiment of the present invention;
[0033] Fig.11 The present invention is a flowchart of a method for preparing a fast-programmed OTP device according to an embodiment of the present invention.
[0034] In the figure:
[0035] 1. Substrate; 2. Reserved contact hole; 3. Second conductive type well; 4. Gate dielectric layer; 5. Sidewall; 6. Second field effect transistor floating gate; 7. First field effect transistor selection gate; 8. Plasma silicon oxide film; 9. Cobalt metal; 10. First contact hole; 11. Second contact hole; 12. Third contact hole; 13. Electrode; 14. Interlayer dielectric film. DETAILED DESCRIPTION
[0036] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in the field should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0037] According to an embodiment of the present invention, a fast-programmed OTP device and a method for preparing the same are provided.
[0038] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1-Figure 10 As shown, the fast programming OTP device according to an embodiment of the present invention includes a substrate 1, a reserved contact hole 2 is opened at the inner bottom of the substrate 1, a second conductive type well 3 is arranged on the top of the substrate 1, and a plurality of gate dielectric layers 4 are arranged on the top of the second conductive type well 3.
[0039] In one embodiment, for the above-mentioned gate dielectric layer 4, the top of the gate dielectric layer 4 is respectively provided with a first field effect transistor selection gate 7 and a second field effect transistor floating gate 6, and side walls 5 are provided on both sides of the first field effect transistor selection gate 7 and the second field effect transistor floating gate 6, and a plasma silicon oxide film 8 is provided on the outside of the side wall 5. A cobaltized metal 9 matching the first field effect transistor selection gate 7 is provided on one side of the inner top of the plasma silicon oxide film 8. A first contact hole 10, a second contact hole 11 and a third contact hole 12 are sequentially opened inside the plasma silicon oxide film 8. The first contact hole 10 is located on one side of the first field effect transistor selection gate 7, and the second contact hole 11 is located on the other side of the first field effect transistor selection gate 7. The third contact hole 12 is located on the top of the first field effect transistor selection gate 7 and on one side of the second field effect transistor floating gate 6. An electrode 13 is provided at the bottom of the substrate 1. The first field effect transistor selection gate 7 and the second field effect transistor floating gate 6 respectively form a trapezoidal structure with the side walls 5 on both sides. Thus, by adding electrodes at the bottom of the substrate and applying voltage thereto, it is only necessary to apply a small voltage to the selection gate to enable the channel carriers to tunnel to the floating gate layer, thereby realizing rapid programming of the OTP memory cell. This can not only shorten the programming cycle of the OTP memory cell, but also avoid the situation where the device is damaged due to excessive voltage, thereby greatly improving the working performance of the OTP memory device.
[0040] According to another embodiment of the present invention, Fig.11 As shown, a method for preparing a fast-programmed OTP device is also provided, the preparation method comprising:
[0041] S1, obtaining a substrate 1 of a first conductivity type, forming a reserved contact hole 2 at the bottom of the substrate 1 by an etching process, and forming a well 3 of a second conductivity type at the top of the substrate 1 by a doping process;
[0042] S2, forming a gate dielectric layer 4 on the top of the second conductive type well 3, depositing and growing polysilicon on the surface of the gate dielectric layer 4, and etching the polysilicon to form a first field effect transistor select gate 7 and a second field effect transistor floating gate 6 respectively;
[0043] S3, depositing an oxide insulating layer outside the first field effect transistor selection gate 7 and the second field effect transistor floating gate 6, and etching the oxide insulating layer to form sidewalls 5 located on both sides of the first field effect transistor selection gate 7 and the second field effect transistor floating gate 6;
[0044] S4, depositing a plasma silicon oxide film 8 on the second conductive type well 3 by a vacuum process, using the plasma silicon oxide film 8 as a mask, and performing a cobaltization metal process on the mask to form a cobaltized metal 9;
[0045] S5, depositing again to form a plasma silicon oxide film 8, and using an etching process to filter impurities to form a FG data storage protection film, depositing an interlayer dielectric film 14, and using an etching process to form a first contact hole 10, a second contact hole 11 and a third contact hole 12;
[0046] S6. Use the CMOS back-end process to form the source, select gate and drain of the OTP device, and install the electrode 13 at the bottom of the substrate 1 to form the unit cross-sectional structure of the OTP device to complete the preparation of the OTP device.
[0047] In one embodiment, the reserved contact hole 2 is located directly below the second field effect transistor floating gate 6 in the horizontal direction, and the upper surface of the reserved contact hole 2 contacts the lower surface of the second conductive type well 3 .
[0048] In one embodiment, the source and gate of the first field effect transistor and the second field effect transistor are implanted into the second conductive type well 3 by first conductive type ions, and the drain of the first field effect transistor and the source of the second field effect transistor are the same active region.
[0049] In order to facilitate understanding of the above technical solution of the present invention, the following is a preparation method of the fast programming OTP device in the actual process of the present invention, which includes:
[0050] like Figure 1As shown, a substrate 1 of the first conductivity type is obtained, and a reserved contact hole 2 is formed at the bottom by photolithography and etching processes. The reserved contact hole 2 is located directly below the subsequent second field effect transistor floating gate 6 in the horizontal direction.
[0051] like Figure 2 As shown, an effectively isolated second conductivity type well 3 is formed on the substrate 1 by a doping process, wherein the upper surface of the reserved contact hole 2 reaches the lower surface of the second conductivity type well 3 .
[0052] like Figure 3 As shown, a gate dielectric layer 4 is formed above the second conductive type well 3, and polysilicon is deposited and grown above the gate dielectric layer 4; the polysilicon is etched to form a first field effect transistor select gate SG (equivalent to the first field effect transistor select gate 7) and a floating gate FG of the second field effect transistor (equivalent to the second field effect transistor floating gate 6).
[0053] like Figure 4 As shown, an oxide insulating layer is deposited, and the oxide insulating layer is etched to retain both sides of the gate structure of the first field effect transistor (MOS) and the second field effect transistor to form a sidewall 5.
[0054] like Figure 5 As shown, in the second conductive type well 3, the source of the first field effect transistor and the second field effect transistor are defined by implanting the first conductive type ions (equivalent to Figure 5-Figure 10 The region S in the drain (equivalent to Figure 5-Figure 10 The drain of the first field effect tube and the source of the second field effect tube are in the same active region, that is, the same region (equivalent to Figure 5-Figure 10 region D').
[0055] like Figure 6 As shown, a plasma silicon oxide film 8 formed by a vacuum process is deposited as a mask.
[0056] like Figure 7 As shown, a cobaltization metal process is performed on the mask, and finally a cobaltization metal 9 is formed in the silicon exposed area.
[0057] like Figure 8 As shown, the plasma silicon oxide film 8 is deposited again, and the excess portion of the plasma silicon oxide film 8 is removed by photolithography to form a FG data storage protective film with an appropriate thickness. The FG data storage protective film is the plasma silicon oxide film 8 with the excess portion removed.
[0058] like Fig. 9 As shown, an interlayer dielectric film 14 is deposited, and after a chemical mechanical polishing process, a first contact hole 10, a second contact hole 11 and a third contact hole 12 are formed by photolithography and etching. Subsequently, the OTP device is manufactured according to the CMOS back-end process to form a source, a select gate and a drain respectively.
[0059] like Fig.10 As shown, an electrode 13 is added to the bottom of the substrate 1 to form a cell cross-sectional structure of the OTP device, thereby completing the preparation of the OTP device.
[0060] In order to facilitate understanding of the above technical solutions of the present invention, the working principle or operation mode of the present invention in the actual process is described in detail below.
[0061] In actual application, when the first conductivity type is P type and the second conductivity type is N type, when a positive voltage is applied to the electrode 13, under the action of the electric field, the hole concentration in the lower part of the second field effect transistor floating gate 6 is higher than that in other areas. Therefore, only a smaller voltage needs to be applied at this time, and the holes tunnel into the second field effect transistor floating gate 6. A smaller negative voltage is applied to the first field effect transistor selection gate 7, and a positive voltage difference is applied between the source and the drain (source voltage>drain voltage), and the holes tunnel into the second field effect transistor floating gate 6 to complete the programming operation.
[0062] When the first conductivity type is N type and the second conductivity type is P type, when a negative voltage is applied to the electrode 13, under the action of the electric field, the electron concentration in the lower part of the floating gate is higher than that in other areas. Therefore, only a smaller voltage needs to be applied at this time, and the electrons tunnel into the floating gate 6 of the second field effect transistor. A smaller forward voltage is applied to the selection gate 7 of the first field effect transistor, and a reverse voltage difference is applied between the source and the drain (source voltage < drain voltage), and the electrons tunnel into the floating gate 6 of the second field effect transistor to complete the programming operation.
[0063] To sum up, with the help of the above-mentioned technical scheme of the present invention, the present invention adds an electrode at the bottom of the substrate and applies a voltage thereto, so that only a small voltage needs to be applied to the select gate to make the channel carriers tunnel to the floating gate layer, thereby realizing fast programming of the OTP memory cell. This can not only shorten the programming cycle of the OTP memory cell, but also avoid the situation where the device is damaged by excessive voltage, thereby greatly improving the working performance of the OTP memory device.
[0064] The OTP device shown in the present invention can be used to store the serial number information of the FLASH inside the FLASH chip. This information is written by the manufacturer and locked when leaving the factory to prevent the ID number of the FLASH from being copied.
[0065] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "screw-on" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.
[0066] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A fast-programmed OTP device, comprising a substrate (1), characterized in that: A reserved contact hole (2) is provided at the inner bottom of the substrate (1), a second conductive type well (3) is provided at the top of the substrate (1), and a plurality of gate dielectric layers (4) are provided at the top of the second conductive type well (3).
2. A fast-programmed OTP device according to claim 1, characterized in that: A first field effect transistor selection gate (7) and a second field effect transistor floating gate (6) are respectively arranged on the top of the gate dielectric layer (4), and side walls (5) are arranged on both sides of the first field effect transistor selection gate (7) and the second field effect transistor floating gate (6).
3. A fast-programmed OTP device according to claim 2, characterized in that: A plasma silicon oxide film (8) is arranged outside the side wall (5), and a cobaltized metal (9) matching the first field effect transistor selection gate (7) is arranged on one side of the inner top of the plasma silicon oxide film (8).
4. A fast-programmed OTP device according to claim 3, characterized in that: A first contact hole (10), a second contact hole (11) and a third contact hole (12) are sequentially opened inside the plasma silicon oxide film (8).
5. A fast-programmed OTP device according to claim 4, characterized in that: The first contact hole (10) is located on one side of the first field effect transistor selection gate (7), the second contact hole (11) is located on the top of the first field effect transistor selection gate (7), and the third contact hole (12) is located on one side of the second field effect transistor floating gate (6).
6. A fast-programmed OTP device according to claim 5, characterized in that: An electrode (13) is provided at the bottom of the substrate (1).
7. A fast-programmable OTP device according to claim 6, characterized in that: The first field effect transistor selection gate (7) and the second field effect transistor floating gate (6) respectively form a trapezoidal structure with the side walls (5) on both sides.
8. A method for preparing a fast-programmed OTP device, for realizing the preparation of the fast-programmed OTP device according to any one of claims 1 to 7, characterized in that: The preparation method comprises: S1, obtaining a substrate (1) of a first conductivity type, forming a reserved contact hole (2) at the bottom of the substrate (1) by an etching process, and forming a well (3) of a second conductivity type at the top of the substrate (1) by a doping process; S2, forming a gate dielectric layer (4) on the top of the second conductive type well (3), depositing and growing polysilicon on the surface of the gate dielectric layer (4), and etching the polysilicon to form a first field effect transistor selection gate (7) and a second field effect transistor floating gate (6); S3, depositing an oxide insulating layer outside the first field effect transistor selection gate (7) and the second field effect transistor floating gate (6), and etching the oxide insulating layer to form side walls (5) located on both sides of the first field effect transistor selection gate (7) and the second field effect transistor floating gate (6); S4, depositing a plasma silicon oxide film (8) on the second conductive type well (3) using a vacuum process, using the plasma silicon oxide film (8) as a mask, and performing a cobaltization metal process on the mask to form a cobaltized metal (9); S5, depositing again to form a plasma silicon oxide film (8), and using an etching process to filter impurities to form a FG data storage protection film, depositing an interlayer dielectric film, and using an etching process to form a first contact hole (10), a second contact hole (11), and a third contact hole (12); S6. Using the back-end process, a source electrode, a selection gate electrode and a drain electrode of the OTP device are formed, and an electrode (13) is installed at the bottom of the substrate (1) to form a unit cross-sectional structure of the OTP device, thereby completing the preparation of the OTP device.
9. The method for preparing a fast-programmed OTP device according to claim 8, characterized in that: The reserved contact hole (2) is located directly below the second field effect transistor floating gate (6) in the horizontal direction, and the upper surface of the reserved contact hole (2) contacts the lower surface of the second conductive type well (3).
10. The method for preparing a fast-programmable OTP device according to claim 9, characterized in that: The source and gate of the first field effect transistor and the second field effect transistor are implanted into the second conductive type well (3) by first conductive type ions, and the drain of the first field effect transistor and the source of the second field effect transistor are the same active region.