Cellular structure of integrated gate commutated thyristor and preparation method thereof

Abstract

The invention provides a cellular structure of an integrated gate commutated thyristor and a preparation method of the cellular structure. The cellular structure comprises a substrate; the drift layer has a first surface on one side away from the substrate; the first doping layer comprises first doping sub-regions and second doping sub-regions, the first doping sub-regions and the second doping sub-regions are alternately arranged along a first direction, the first doping sub-regions have a first doping type, and the second doping sub-regions have a second doping type; one side surface, deviating from the substrate, of the second doping layer is a second surface; one part of the cathode structure is located in the second doping layer, and the other part is located on the second surface; the gate poles are located on the two sides of the cathode structure in the first direction. By forming the semi-super junction structure formed by the first doping sub-region and the second doping sub-region on the drift layer, the thickness of the drift layer is reduced, and the reduction of the thickness of the drift layer can also reduce the on-resistance of the thyristor and improve the switching speed of the thyristor. The problems that a cellular structure is large in size and poor in comprehensive performance are solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a cell structure of an integrated gate-commutated thyristor, a preparation method thereof, and an integrated gate-commutated thyristor. Background Art

[0002] The cell structure of a traditional integrated gate-commutated thyristor (GCT) is mainly composed of four layers: + Anode area, N - Drift region, P base region and N + Cathode region. During operation, when a forward voltage is applied to the device, N - The charge in the drift region is depleted to form a depletion region to withstand the longitudinal electric field. Although this longitudinal withstand voltage structure can provide a higher blocking voltage, it requires a larger drift region thickness to ensure sufficient withstand voltage, resulting in a larger overall size of the device, increased on-resistance, and thus increased conduction loss. In addition, an overly thick drift region also limits the switching speed of the device, reduces its performance in high-frequency applications, and thus makes the overall performance of the integrated gate-commutated thyristor not high.

[0003] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0004] The main purpose of the present application is to provide a cell structure of an integrated gate-commutated thyristor, a preparation method thereof and an integrated gate-commutated thyristor, so as to solve the problem that the integrated gate-commutated thyristor in the prior art is large in size and poor in overall performance.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a cell structure of an integrated gate-commutated thyristor is provided, comprising: a substrate having a first doping type; a drift layer located on one side of the substrate, the drift layer having a first surface on a side away from the substrate, the drift layer having a second doping type, and the first doping type is different from the second doping type; a first doping layer located on the first surface, the first doping layer comprising a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region being alternately arranged along a first direction, the first sub-doping region having the first doping type, the second sub-doping region having the second doping type, and the first direction being perpendicular to the direction from the substrate to the drift layer; a second doping layer located on a side of the first doping layer away from the substrate, the surface of the second doping layer on a side away from the substrate being a second surface, and the second doping layer having the first doping type; a cathode structure, a part of which is located in the second doping layer, and the other part of which is located on the second surface; a plurality of gates located on the second surface at intervals, and the plurality of gates are located on both sides of the cathode structure in the first direction.

[0006] Optionally, a contact surface between the first sub-doping region and the second sub-doping region is perpendicular to the first surface.

[0007] Optionally, the second doping layer includes a first sub-doping layer and a second sub-doping layer, wherein: the first sub-doping layer is located on a side of the first doping layer away from the substrate; the second sub-doping layer is located on a side of the first sub-doping layer away from the substrate, and the doping concentration of the second sub-doping layer is greater than the doping concentration of the first sub-doping layer.

[0008] Optionally, a width of the first sub-doping region and the second sub-doping region in the first direction is 1 μm to 10 μm.

[0009] Optionally, the cathode structure comprises: a cathode emitter and a cathode, wherein: at least a portion of the cathode emitter is located in the second doping layer; the cathode is located on a side of the cathode emitter away from the drift layer, and the cathode is in contact with the cathode emitter.

[0010] Optionally, the cell structure further includes a plurality of first insulating layers, wherein the first insulating layers are located between the gate and the cathode structure, and the first insulating layers are in contact with the gate and the cathode and cover side walls of the cathode emitter.

[0011] Optionally, the cell structure further includes a plurality of second insulating layers, wherein the second insulating layers cover the gate and the first insulating layer.

[0012] According to another aspect of the present application, a method for preparing a cell structure of an integrated gate-commutated thyristor is provided, which is used to prepare the cell structure of the integrated gate-commutated thyristor, and the method comprises: providing a substrate, wherein the substrate has a first doping type; forming a drift layer on the substrate, wherein the drift layer has a first surface on a side away from the substrate, and the drift layer has a second doping type, and the first doping type is different from the second doping type; forming a first doping layer on the first surface, wherein the first doping layer comprises a first sub-doping region and a second sub-doping region, wherein the first sub-doping region and the second sub-doping region are alternately arranged along a first direction, wherein the first sub-doping region has the first doping type, and the second sub-doping region has the second doping type, and the first direction is parallel to the first surface and perpendicular to a direction from the substrate to the drift layer; forming a second doping layer on a side of the first doping layer away from the substrate, wherein a surface of the second doping layer on a side away from the substrate is a second surface, and the second doping layer has the first doping type; forming a cathode structure at least in the second doping layer; and forming a plurality of gates distributed at intervals on the second surface, wherein the plurality of gates are located on both sides of the cathode structure in the first direction.

[0013] Optionally, the step of forming a first doping layer on the first surface includes: forming a first semiconductor layer on the first surface, the first semiconductor layer having a plurality of first regions and second regions, the second regions and the first regions being alternately arranged along the first direction; performing a first ion implantation on the first region to form the first sub-doping region; performing a second ion implantation on the second region to form the second sub-doping region, the first sub-doping region and the second sub-doping region forming the first doping layer.

[0014] According to another aspect of the present application, an integrated gate-commutated thyristor is provided, comprising at least one cellular structure of the integrated gate-commutated thyristor.

[0015] By applying the technical solution of the present application, a cell structure of an integrated gate-commutated thyristor includes a substrate, a drift layer, a first doping layer, a second doping layer, a cathode structure and a gate, wherein the first doping layer is located on the drift layer, the first doping layer includes a first sub-doping region and a second sub-doping region with different doping types, the first sub-doping region and the second sub-doping region are alternately arranged along a first direction, and the first direction is perpendicular to the direction from the substrate to the drift layer; the second doping layer is located on a side of the first doping layer away from the substrate, a surface of the second doping layer away from the substrate is a second surface, and the second doping layer has a first doping type; a portion of the cathode structure is located in the second doping layer, and another portion is located on the second surface; a plurality of gates are located on the second surface at intervals, and a plurality of gates are located on both sides of the cathode structure in the first direction. In the prior art, a larger drift layer thickness and width are required to ensure sufficient longitudinal voltage resistance, resulting in a larger overall size of the device. In the present application, the contact area between the first sub-doping region and the second sub-doping region in the first doping layer is the depletion region of the thyristor. By arranging the first sub-doping region and the second sub-doping region alternately, a semi-superjunction structure is formed on the drift layer. The semi-superjunction structure converts a part of the original longitudinal depletion region into a transverse depletion region to generate a transverse electric field. Since the transverse electric field can share the voltage stress laterally, the stress intensity of the longitudinal voltage is reduced, thereby reducing the requirement for the drift layer to disperse the longitudinal voltage stress. Therefore, the thickness and width of the drift layer in the cell structure can be reduced, thereby reducing the size of the overall thyristor. Moreover, the reduction in the thickness of the drift layer can also reduce the on-resistance of the thyristor and increase the switching speed of the thyristor. The cell structure of the integrated gate-commutated thyristor proposed in the present application solves the problem that the integrated gate-commutated thyristor in the prior art is large in size and has poor overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic cross-sectional structure diagram of a cell structure of a first integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0018] Figure 2 A schematic cross-sectional structure diagram of a cell structure of a second integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic cross-sectional structure diagram of a first doping layer according to an embodiment of the present application is shown;

[0020] Figure 4A schematic cross-sectional structure diagram of a cell structure of a third integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0021] Figure 5 A schematic cross-sectional structure diagram of a cell structure of a fourth integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0022] Figure 6 A schematic cross-sectional structure diagram of a cell structure of a fifth integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0023] Figure 7 A schematic diagram of the process structure of a method for preparing a cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0024] Figure 8 A schematic cross-sectional structure diagram of forming a first doping layer in a method for preparing a cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0025] Fig. 9 A schematic cross-sectional structure diagram of forming a first doping layer in another method for preparing a cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application is shown;

[0026] Fig.10 A schematic cross-sectional structure diagram of an integrated gate-commutated thyristor according to an embodiment of the present application is shown.

[0027] The above drawings include the following reference numerals:

[0028] 1. Cell structure; 10. Substrate; 20. Drift layer; 30. First doping layer; 31. First sub-doping region; 32. Second sub-doping region; 310. First region; 320. Second region; 40. Second doping layer; 41. First sub-doping layer; 42. Second sub-doping layer; 50. Cathode structure; 51. Cathode emitter; 52. Cathode; 60. Gate; 70. First insulating layer; 80. Second insulating layer; 90. Anode; 100. Carbon nanotube; 300. First semiconductor layer. DETAILED DESCRIPTION

[0029] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0030] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0033] As introduced in the background technology, the cell structure of the conventional integrated gate-commutated thyristor (GCT) in the prior art is mainly composed of four layers: an anode region, a drift region, a base region, and a cathode region. During operation, when a forward voltage is applied to the device, the charge in the drift region is depleted to form a depletion region to withstand the longitudinal electric field. Although this longitudinal withstand voltage structure can provide a higher blocking voltage, it requires a larger drift region thickness and width to ensure sufficient withstand voltage, resulting in a larger overall size of the device, increased on-resistance, and thus increased conduction loss. In addition, an overly thick drift region also limits the switching speed of the device and reduces its performance in high-frequency applications. In order to solve the problem that the integrated gate-commutated thyristor in the prior art is large in size and has poor overall performance, the embodiments of the present application provide a cell structure of an integrated gate-commutated thyristor, a preparation method thereof, and an integrated gate-commutated thyristor.

[0034] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0035] According to one aspect of the present application, a cell structure of an integrated gate-commutated thyristor is proposed, such as Figure 1 and Figure 2 As shown, it includes: a substrate 10 having a first doping type; a drift layer 20 located on one side of the substrate 10, the drift layer 20 having a first surface on the side away from the substrate 10, the drift layer 20 having a second doping type, and the first doping type is different from the second doping type; a first doping layer 30 located on the first surface, the first doping layer 30 including a first sub-doping region 31 and a second sub-doping region 32, the first sub-doping region 31 and the second sub-doping region 32 are alternately arranged along a first direction X, the first sub-doping region 31 has the first doping type, and the second sub-doping region 32 has the second doping type, and the first direction X is perpendicular to the direction from the substrate 10 to the drift layer 20; a second doping layer 40 located on the side of the first doping layer 30 away from the substrate 10, the side surface of the second doping layer 40 away from the substrate 10 is the second surface, and the second doping layer 40 has the first doping type; a cathode structure 50, a part of which is located in the second doping layer 40, and the other part is located on the second surface; a plurality of gate electrodes 60, which are located on the second surface at intervals, and the plurality of gate electrodes 60 are located on both sides of the cathode structure 50 in the first direction X.

[0036] The problem of large size and poor overall performance of the integrated gate-commutated thyristor is solved by setting a first doping layer on the drift layer of the cell structure of the integrated gate-commutated thyristor. The first doping layer includes a first sub-doping region and a second sub-doping region, and the contact area between the two is the depletion region of the thyristor. The contact area between the first sub-doping region and the second sub-doping region can generate a lateral electric field. Since the lateral electric field can share the voltage stress, the stress intensity of the longitudinal voltage is reduced, thereby reducing the thyristor's demand for the drift layer to disperse the longitudinal voltage stress (voltage resistance). Therefore, the thickness and width of the drift layer in the cell structure can be reduced, thereby reducing the size of the overall thyristor, and the reduction in the thickness of the drift layer can also reduce the on-resistance of the thyristor and increase the switching speed of the thyristor. By setting a semi-superjunction structure formed by the first doping layer on the drift layer, the overall performance of the thyristor is improved.

[0037] In traditional vertically structured thyristor devices, the electric field is mainly distributed in the opposite direction of the current flow (i.e., vertically), which means that the electric field will be concentrated in a certain part in the thickness direction of the device, causing the part to be subjected to a higher electric field strength, easily forming an electric field hotspot, and then causing local early breakdown. The present application introduces a first doping layer having a first sub-doping region and a second sub-doping region alternately distributed in the thyristor, and the current and electric field that generate the lateral electric field are distributed in directions perpendicular to each other. The electric field is evenly distributed in the depletion region in the width direction of the device, making the electric field strength more uniform, avoiding the early breakdown caused by excessive local electric field. This uniformly distributed lateral electric field can significantly improve the overall voltage resistance of the device, effectively increase the blocking voltage of the device, and make the device perform better in high-voltage applications.

[0038] The conventional superjunction structure forms a first sub-doping region and a second sub-doping region that are alternately distributed on the substrate. The superjunction structure penetrates the drift layer, has a deep depth, and is difficult to prepare. The present application forms a semi-superjunction structure in which the first sub-doping region and the second sub-doping region are alternately arranged above the drift layer, making it easier to achieve uniform doping and precise columnar structure of the semi-superjunction structure.

[0039] The thyristor proposed in the present application improves the on-resistance, switching speed, overall withstand voltage, blocking voltage and preparation process of the device while being small in size, thereby improving the comprehensive performance of the device.

[0040] In some embodiments, the materials of the substrate, drift layer, first doping layer and second doping layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitride. Among them, the substrate is located at the top of the device as the main channel for current injection, the drift layer is used to withstand the reverse voltage when the thyristor is in the off state, the first doping layer is used to convert the longitudinal electric field into a transverse electric field and uniform the electric field strength, and the second doping layer can make the current flow smoothly when the device is turned on, and prevent the current from flowing when the device is turned off, thereby playing a role in controlling the flow of current.

[0041] In some embodiments, the gate electrode may be made of any one of aluminum, titanium, tungsten and molybdenum, or alloys of the above metals.

[0042] In some embodiments, the first doping type may be N-type doping and the second doping type may be P-type doping, or the first doping type may be P-type doping and the second doping type may be N-type doping, the P-type dopant may be boron and the N-type dopant may be phosphorus or arsenic.

[0043] In some optional embodiments, such as Figure 1 and Figure 2As shown, the contact surface of the first sub-doping region 31 and the second sub-doping region 32 is perpendicular to the first surface. In this case, the contact area of ​​the first sub-doping region 31 and the second sub-doping region 32 can generate a lateral electric field close to that along the first direction X, which can better reduce the thyristor's demand for the withstand voltage of the drift layer 20 to disperse the longitudinal voltage, and thus reduce the thickness and width of the drift layer 20. The reduction in the thickness of the drift layer 20 reduces the on-resistance of the drift layer 20 and reduces the conduction loss. In addition, the introduction of a lateral electric field so that the lateral electric field and the longitudinal electric field work together can also improve the overall withstand voltage and blocking voltage of the device. The semi-super junction structure in the present application can take into account both the withstand voltage and conduction loss of the device. Among them, the doping concentration of the first sub-doping region and the second sub-doping region can be 10 16 ~10 18 cm -3 , such as 10 17 cm -3 .

[0044] It should be noted that when the first sub-doping region and the second sub-doping region are formed by the ion implantation process, the junction surface of the first sub-doping region and the second sub-doping region will not be a flat plane due to the partial diffusion phenomenon caused by the ion implantation. However, the depletion region is a region, and the generation of a lateral electric field in the depletion region will not be affected by the fact that the junction surface of the first sub-doping region and the second sub-doping region is not a flat plane.

[0045] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the cathode structure 50 includes: a cathode emitter 51 and a cathode 52, wherein: at least part of the cathode emitter 51 is located in the second doping layer 40; the cathode 52 is located on the side of the cathode emitter 51 away from the drift layer 20, and the cathode 52 is in contact with the cathode emitter 51. The cathode structure 50 is used to receive the current conducted from the second doping layer 40. The cathode emitter 51 can collect the current flowing from the second doping layer 40 and transmit it to the cathode 52. The doping type of the cathode emitter 51 is opposite to the doping type of the second doping layer 40, and a PN junction structure is formed between the two, which can control the flow of device current.

[0046] In some optional embodiments, such as Figure 2As shown, the second doping layer 40 includes a first sub-doping layer 41 and a second sub-doping layer 42, wherein: the first sub-doping layer 41 is located on the side of the first doping layer 30 away from the substrate 10; the second sub-doping layer 42 is located on the side of the first sub-doping layer 41 away from the substrate 10, and the doping concentration of the second sub-doping layer 42 is greater than the doping concentration of the first sub-doping layer 41. The higher doping concentration of the second sub-doping layer 42 can more easily form an ohmic contact with the gate 60, thereby reducing the contact resistance of the gate 60. When a forward voltage is applied to the gate 60, the turn-on voltage of the PN junction formed by the second sub-doping layer 42 and the cathode emitter 51 can be made smaller, and it is easier to open, so that the electrons of the cathode emitter 51 are injected into the first sub-doping layer 41 and the second sub-doping layer 42. The electron injection can significantly reduce the resistance of the first sub-doping layer 41 and the second sub-doping layer 42, thereby reducing the on-state voltage drop of the entire device and reducing the power loss in the on state.

[0047] In some optional embodiments, such as Figure 3 As shown, the width of the first sub-doping region 31 and the second sub-doping region 32 in the first direction X is 1 μm to 10 μm. The width of the first sub-doping region 31 and the second sub-doping region 32 is in the above range, which can simultaneously have the advantages of uniform electric field distribution inside the device, good voltage resistance of the device, and easy manufacturing process.

[0048] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the cell structure 1 further includes a plurality of first insulating layers 70, the first insulating layer 70 being located between the gate 60 and the cathode structure 50, the first insulating layer 70 being in contact with the gate 60 and the cathode 52 and covering the sidewalls of the cathode emitter 51. The material of the first insulating layer 70 may be insulating materials such as silicon dioxide, silicon oxide, and silicon oxynitride, and the first insulating layer 70 is used to insulate the gate 60 and the cathode structure 50.

[0049] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the cell structure 1 also includes a plurality of second insulating layers 80, and the second insulating layer 80 covers the gate 60 and the first insulating layer 70. The second insulating layer 80 can be PI glue (Polyimide) or other insulating materials. The second insulating layer 80 is used to further insulate and encapsulate the gate 60 to prevent the gate 60 from being corroded by external water vapor. The thickness of the first insulating layer 70 and the second insulating layer 80 can be 100nm~500nm, such as 200nm, 300nm or 400nm. Limiting the thickness of the first insulating layer 70 and the second insulating layer 80 to the above range can ensure the insulation performance of the device and also ensure that the device has a lower parasitic capacitance.

[0050] In the above optional implementation, if Figure 1 and Figure 2 As shown, the cell structure 1 also includes an anode 90, which is located on the side of the substrate 10 away from the drift layer 20. The material of the anode 90 can be any one or more of aluminum, copper and silver, and can also be a multilayer metal formed by multiple types of titanium, aluminum, copper, nickel and gold.

[0051] The present application can also form a multi-level semi-superjunction structure on the drift layer, such as Figure 4 As shown, multiple layers of semi-super junction structures are stacked in the depth direction of the device, so that the contact area between the first sub-doping region 31 and the second sub-doping region 32 is stepped, forming a multi-level semi-super junction structure. Figure 5 As shown, multiple layers of semi-super junction structures are stacked in the depth direction of the device, so that the first sub-doping region 31 and the second sub-doping region 32 form more columnar structures, forming a multi-level semi-super junction structure. The depletion region of the multi-level semi-super junction structure becomes larger, and the lateral electric field distribution can be further made more uniform while converting part of the longitudinal electric field into the lateral electric field, thereby optimizing the electric field distribution and further improving the withstand voltage capability of the device.

[0052] like Figure 6 As shown, carbon nanotubes 100 are placed in the second doping layer 40 and the cathode emitter 51 of the thyristor. The carbon nanotubes 100 in the second doping layer 40 are in contact with the gate 60. The surface of the carbon nanotubes 100 facing away from the substrate 10 is located at the interface between the gate 60 and the second doping layer 40. The carbon nanotubes 100 in the cathode emitter 51 are in contact with the cathode 52. The surface of the carbon nanotubes 100 facing away from the substrate 10 is located at the interface between the cathode 52 and the cathode emitter 51. The carbon nanotubes 100 serve as a transition layer at the interface between the gate 60 and the second doping layer 40 (gold semi-contact interface), and an embedding medium for the second doping layer 40 and the cathode emitter 51. The carbon nanotubes 100 have high electron mobility, which can effectively improve the carrier input and extraction speed of the device and improve the switching efficiency of the device. The good conductivity of carbon nanotubes 100 can reduce the resistance of the gold semiconductor interface and reduce device loss. The good flexibility of carbon nanotubes 100 can make the gold semiconductor contact more closely and improve the density of the gold semiconductor contact. The overall performance of the device is improved. Figures 4 to 6 The label structure not mentioned in Figures 1 to 3 The description in is consistent.

[0053] Figure 7 FIG. 1 is a flow chart of a method for preparing a cell structure of an integrated gate-commutated thyristor according to an embodiment of the present application. Figure 7 As shown, the method comprises the following steps:

[0054] Step S201, providing a substrate, wherein the substrate has a first doping type;

[0055] Specifically, the material of the substrate can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitride. The first doping type can be N-type doping, or P-type doping, the P-type dopant can be boron, and the N-type dopant can be phosphorus or arsenic.

[0056] Step S202, forming a drift layer on the substrate, wherein the drift layer has a first surface on a side facing away from the substrate, and the drift layer has a second doping type, and the first doping type is different from the second doping type;

[0057] Specifically, the material of the drift layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitride. The drift layer is used to withstand the reverse voltage when the thyristor is in the off state. The doping type of the drift layer is opposite to that of the substrate. For example, the doping type of the substrate is P type and the doping type of the drift layer is N type. The doping concentration of the drift layer is about 10 13 cm -3 .

[0058] Step S203, forming a first doping layer on the first surface, the first doping layer comprising a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region are alternately arranged along a first direction, the first sub-doping region has a first doping type, the second sub-doping region has a second doping type, and the first direction is parallel to the first surface and perpendicular to a direction from the substrate to the drift layer;

[0059] Specifically, the material of the first doping layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitride. The first sub-doping region and the second sub-doping region are arranged alternately along the first direction, which converts the original longitudinal electric field into a transverse electric field, and shares the longitudinal voltage stress for the drift layer, so that the thickness of the drift layer can be greatly reduced, and the size of the device is reduced. The reduction in the thickness of the drift layer can reduce the on-resistance of the drift layer and reduce the conduction loss.

[0060] Step S204, forming a second doping layer on a side of the first doping layer away from the substrate, wherein a surface of the second doping layer away from the substrate is a second surface, and the second doping layer has a first doping type;

[0061] Specifically, the material of the second doping layer can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitrogen. The second doping layer can allow current to flow smoothly when the device is on, and prevent current from flowing when the device is off, thereby playing a role in controlling the flow of current.

[0062] Step S205, forming a cathode structure at least in the second doping layer;

[0063] Specifically, the cathode structure is used to receive the current conducted from the second doped layer. The cathode structure includes a cathode emitter and a cathode, the cathode emitter is opposite to the doping type of the second doped layer, and the cathode emitter and the second doped layer form a PN junction structure to control the opening and closing of the thyristor. The material of the cathode can be any one or more of aluminum, copper, tungsten and molybdenum.

[0064] Step S206 , forming a plurality of gate electrodes distributed at intervals on the second surface, wherein the plurality of gate electrodes are located on both sides of the cathode structure in the first direction.

[0065] Specifically, the material of the gate electrode may be any one or more of aluminum, titanium, tungsten and molybdenum, and the material of the gate electrode may be the same as or different from that of the cathode.

[0066] The cellular structure prepared by the preparation method of the cellular structure of the above-mentioned integrated gate-commutated thyristor has a semi-superjunction structure formed by the alternating arrangement of the first sub-doping region and the second sub-doping region on the drift layer, which converts a part of the original longitudinal electric field of the device into a transverse electric field, and shares the longitudinal voltage stress for the drift layer, so that the thickness and width of the drift layer can be reduced, thereby reducing the on-resistance and conduction loss of the drift layer. Because it is a semi-superjunction structure, it is easier to form a columnar structure with uniform doping, so that the electric field intensity distribution is more uniform, avoiding the early breakdown phenomenon caused by excessive local electric field. This uniformly distributed electric field can significantly improve the overall withstand voltage capability of the device and increase the blocking voltage. The reduction in the thickness and width of the drift layer also reduces the size of the device, and improves the various performances of the thyristor, solving the problem that the integrated gate-commutated thyristor in the prior art is large in size and poor in comprehensive performance.

[0067] The following is a more detailed description of exemplary embodiments of the method for preparing the cell structure of the integrated gate-commutated thyristor provided in the present application. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to ordinary technicians in the field.

[0068] In some optional embodiments, such as Figure 8 and Fig. 9As shown, the step of forming the first doping layer 30 on the first surface in the above step S203 includes: forming a first semiconductor layer 300 on the first surface of the drift layer 20, the first semiconductor layer 300 having a plurality of first regions 310 and second regions 320, the second regions 320 and the first regions 310 being alternately arranged along the first direction X; performing a first ion implantation on the first region 310 to form a first sub-doping region 31; performing a second ion implantation on the second region 320 to form a second sub-doping region 32, the first sub-doping region 31 and the second sub-doping region 32 forming the first doping layer 30.

[0069] In the above optional implementation, if Figure 8 As shown, a first semiconductor layer 300 is deposited on the drift layer 20 on the substrate 10, and a first region 310 and a second region 320 are divided in the first semiconductor layer 300. Fig. 9 As shown, a first mask is placed on a side surface of the first semiconductor layer away from the substrate 10, and ions are implanted into the first region to form a first sub-doping region 31, and then a second mask layer is placed on a side surface of the first semiconductor layer away from the drift layer 20, and ions are implanted into the second region to form a second sub-doping region 32, and the first sub-doping region 31 and the second sub-doping region 32 form a first doping layer 30. Ion implantation will produce some diffusion phenomena, but will not affect the generation of a lateral electric field in the depletion region between the first sub-doping region 31 and the second sub-doping region 32. The first sub-doping region 31 and the second sub-doping region 32 can also be formed by an epitaxial growth process or a diffusion method, which is not specifically limited in this application. The material of the first semiconductor layer 300 can be any one of silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, aluminum gallium arsenide, zinc oxide and aluminum gallium nitrogen.

[0070] According to another aspect of the present application, an integrated gate-commutated thyristor is provided, such as Fig.10 As shown, a cell structure 1 including at least one integrated gate-commutated thyristor is provided. A semi-superjunction structure formed by alternating the first sub-doping region and the second sub-doping region in the integrated gate-commutated thyristor can be formed, which can convert the longitudinal electric field in the integrated gate-commutated thyristor into a transverse electric field, thereby sharing the voltage stress for the drift layer, and can reduce the thickness and width of the drift layer in the integrated gate-commutated thyristor, thereby reducing the size of the integrated gate-commutated thyristor. The thickness of the drift layer is reduced, which can reduce the on-resistance and conduction loss of the drift layer. Since the thickness of the semi-superjunction structure is small, a first sub-doping region and a second sub-doping region with uniform doping can be prepared, thereby making the electric field uniform, improving the withstand voltage capability of the device, and increasing the blocking voltage.

[0071] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for preparing the cell structure of the integrated gate-commutated thyristor of the present application will be described in detail below in combination with specific embodiments.

[0072] This embodiment relates to a specific method for preparing a cell structure of an integrated gate-commutated thyristor, comprising the following steps:

[0073] Step S1: providing a P-type substrate, cleaning and polishing the substrate to ensure that its surface is flat and defect-free, and forming an N-type drift layer on the substrate;

[0074] Step S2: forming a first doping layer on the drift layer, the first doping layer comprising a P-type first sub-doping region and an N-type second sub-doping region alternately arranged along a first direction, and performing a high-temperature annealing treatment on the device to activate dopants in the first sub-doping region and the second sub-doping region and repair lattice damage;

[0075] Step S3: forming a P-type second doping layer on the first doping layer, and forming a portion of an N-type cathode emitter in the second doping layer, with another portion of the cathode emitter protruding from the second doping layer;

[0076] Step S4: depositing a first insulating layer on the cathode emitter, and etching the first insulating layer to form a gate and cathode preparation area;

[0077] Step S5: depositing a metal material on the first insulating layer, and etching the metal material to retain the metal material in the gate and cathode preparation regions, forming a gate in the gate preparation region, and forming a cathode in the cathode preparation region;

[0078] Step S6: depositing a second insulating layer on the cathode and the gate, the second insulating layer also covering the first insulating layer, and etching the second insulating layer to expose the top of the cathode;

[0079] Step S7: depositing a metal material on the side of the substrate away from the drift layer to form an anode.

[0080] The above-mentioned deposition process can be a preparation process of chemical vapor deposition or physical vapor deposition, but is not limited thereto. The annealing temperature can range from 900° C. to 1200° C., and the time can range from 30 minutes to several hours.

[0081] The prepared integrated gate-commutated thyristors are cut into individual chips and packaged to ensure the reliability and stability of the devices in practical applications. Electrical tests are also performed on the packaged devices to verify whether their withstand voltage and conduction loss meet the design requirements.

[0082] From the above description, it can be seen that the cell structure of the integrated gate-commutated thyristor provided by the present application achieves the following technical effects:

[0083] 1) The problem of large size and poor overall performance of the integrated gate-commutated thyristor is solved by setting a first doping layer on the drift layer of the cell structure of the integrated gate-commutated thyristor. The first doping layer includes a first sub-doping region and a second sub-doping region, and the contact area between the two is the depletion region of the thyristor. The contact area between the first sub-doping region and the second sub-doping region can generate a lateral electric field. Since the lateral electric field can share the voltage stress, the requirement of the thyristor on the drift layer to disperse the longitudinal voltage stress (voltage resistance) is reduced, and the thickness and width of the drift layer can be reduced, thereby reducing the size of the thyristor.

[0084] 2) As the thickness of the drift layer decreases, the on-resistance of the thyristor is reduced, and the switching speed of the thyristor is increased.

[0085] 3) A semi-super junction structure in which the first sub-doping region and the second sub-doping region are alternately arranged is formed above the drift layer. The depth of the semi-super junction structure in the longitudinal direction of the device is smaller than the depth of the super junction structure in the longitudinal direction of the device. In terms of the preparation process, the semi-super junction structure can easily achieve uniform doping and precise columnar structure.

[0086] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A cell structure of an integrated gate-commutated thyristor, characterized in that: include: a substrate having a first doping type; a drift layer, located on one side of the substrate, the drift layer having a first surface on a side facing away from the substrate, the drift layer having a second doping type, the first doping type being different from the second doping type; a first doping layer, located on the first surface, the first doping layer comprising a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region are alternately arranged along a first direction, the first sub-doping region has the first doping type, the second sub-doping region has the second doping type, and the first direction is perpendicular to a direction from the substrate to the drift layer; A second doping layer is located on a side of the first doping layer away from the substrate, a surface of the second doping layer away from the substrate is a second surface, and the second doping layer has the first doping type; a cathode structure, a portion of which is located in the second doped layer and another portion of which is located on the second surface; A plurality of gate electrodes are spaced apart and located on the second surface, and the plurality of gate electrodes are located on both sides of the cathode structure in the first direction.

2. The cellular structure according to claim 1, characterized in that: A contact surface between the first sub-doping region and the second sub-doping region is perpendicular to the first surface.

3. The cellular structure according to claim 1, characterized in that: The second doping layer includes a first sub-doping layer and a second sub-doping layer, wherein: The first sub-doped layer is located on a side of the first doped layer away from the substrate; The second sub-doping layer is located on a side of the first sub-doping layer away from the substrate, and the doping concentration of the second sub-doping layer is greater than the doping concentration of the first sub-doping layer.

4. The cellular structure according to claim 1, characterized in that: The width of the first sub-doping region and the second sub-doping region in the first direction is 1 μm-10 μm.

5. The cellular structure according to claim 1, characterized in that: The cathode structure comprises: a cathode emitter and a cathode, wherein: At least part of the cathode emitter is located in the second doped layer; The cathode is located at a side of the cathode emitter away from the drift layer, and the cathode is in contact with the cathode emitter.

6. The cellular structure according to claim 5, characterized in that: The cell structure further includes a plurality of first insulating layers, wherein the first insulating layers are located between the gate and the cathode structure, and the first insulating layers are in contact with the gate and the cathode and cover the side walls of the cathode emitter.

7. The cellular structure according to claim 6, characterized in that: The cell structure further includes a plurality of second insulating layers, wherein the second insulating layers cover the gate and the first insulating layer.

8. A method for preparing a cell structure of an integrated gate-commutated thyristor, characterized in that: A cell structure for preparing an integrated gate-commutated thyristor according to any one of claims 1 to 7, the preparation method comprising: providing a substrate having a first doping type; forming a drift layer on the substrate, wherein the drift layer has a first surface on a side facing away from the substrate, and the drift layer has a second doping type, wherein the first doping type is different from the second doping type; forming a first doping layer on the first surface, the first doping layer comprising a first sub-doping region and a second sub-doping region, the first sub-doping region and the second sub-doping region being alternately arranged along a first direction, the first sub-doping region having the first doping type, the second sub-doping region having the second doping type, and the first direction being parallel to the first surface and perpendicular to a direction from the substrate to the drift layer; forming a second doping layer on a side of the first doping layer away from the substrate, wherein a surface of the second doping layer on a side away from the substrate is a second surface, and the second doping layer has the first doping type; forming a cathode structure at least in the second doped layer; A plurality of gate electrodes are formed on the second surface and are distributed at intervals. The plurality of gate electrodes are located on both sides of the cathode structure in the first direction.

9. The preparation method according to claim 8, characterized in that: The step of forming a first doping layer on the first surface comprises: forming a first semiconductor layer on the first surface, wherein the first semiconductor layer has a plurality of first regions and a second region, and the second regions and the first regions are alternately arranged along the first direction; Performing a first ion implantation on the first region to form the first sub-doping region; A second ion implantation is performed on the second region to form the second sub-doping region, and the first sub-doping region and the second sub-doping region form the first doping layer.

10. An integrated gate-commutated thyristor, characterized in that: A cell structure comprising at least one integrated gate-commutated thyristor according to any one of claims 1 to 7.

Images