Back barrier integration scheme of GaN device

Abstract

The invention relates to a back barrier integration scheme for GaN devices. Various embodiments of the present disclosure disclose improved gallium nitride (GaN) power devices and methods of manufacturing such devices. A method of manufacturing a GaN device may include providing a semiconductor substrate having a first side and a second side. The semiconductor substrate includes a GaN material, a front-side barrier layer, and a back-side barrier layer. A pGaN landing portion is formed on a first region of a semiconductor substrate, and an ohmic contact is formed on a second region of the semiconductor substrate. The ohmic contact includes one or more via contact lands and one or more backside barrier contacts that are in direct contact with the backside barrier layer.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to the field of gallium nitride (GaN) devices, and more particularly to a back barrier integration scheme for GaN high electron mobility transistors (HEMTs). Background Art

[0002] Applicants have discovered many technical challenges and difficulties associated with GaN devices, such as GaN HEMTs. Through hard work, ingenuity, and innovation, Applicants have addressed the issues associated with dynamic drain-source resistance and other performance limitations of conventional GaN HEMT structures by developing solutions embodied in the present disclosure, which are described in detail below. Summary of the invention

[0003] Various embodiments described herein relate to systems, apparatus, products, and methods for making and using GaN devices.

[0004] In some embodiments, a method includes: providing a semiconductor substrate including a first side and a second side, wherein the semiconductor substrate includes a gallium nitride (GaN) material, the first side includes a front barrier layer, and the second side includes a back barrier layer; forming a pGaN landing on a first region of the first side of the semiconductor substrate; removing a portion of the front barrier layer on at least a portion of the second region of the first side of the semiconductor substrate to form an ohmic contact on the at least a portion of the second region; and removing one or more portions of the semiconductor substrate at one or more contact locations within the at least a portion of the second region to form one or more back barrier contacts.

[0005] In some embodiments, the method further includes forming a metal layer over the at least a portion of the second region, wherein the metal layer directly contacts the backside barrier layer at the one or more contact locations.

[0006] In some embodiments, the metal layer includes titanium (Ti), aluminum copper (AlCu), or titanium nitride (TiN) material.

[0007] In some embodiments, the method further includes forming one or more via contact landings on the metal layer at the one or more via locations.

[0008] In some embodiments, the one or more through-hole locations are separated from the one or more contact locations.

[0009] In some embodiments, the method includes forming a substrate layer over the metal layer.

[0010] In some embodiments, the substrate layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process.

[0011] In some embodiments, the substrate layer includes a silicon nitride (SiN) material.

[0012] In some embodiments, forming a pGaN landing portion includes etching a pGaN landing portion on a first region on a first side of a semiconductor substrate; forming an aluminum oxide (Al2O3) layer on a first region and a second region on the first side of the semiconductor substrate by an atomic layer deposition (ALD) process, wherein the Al2O3 layer covers the pGaN landing portion; forming a silicon oxide (SiO2) layer on the pGaN landing portion by a plasma enhanced chemical vapor deposition (PECVD) process; and forming a substrate layer on the first region and the second region on the first side of the semiconductor substrate, wherein the substrate layer covers the SiO2 layer.

[0013] In some embodiments, removing the portion of the front-side barrier layer on the second region further comprises removing an Al 2 O 3 layer, a SiO 2 layer, and a substrate layer.

[0014] In some embodiments, the one or more contact locations are based at least in part on a drain location, wherein the drain location indicates a location of the drain on the semiconductor substrate.

[0015] In some embodiments, the one or more contact locations are separated by at least a contact distance, wherein the contact distance is based at least in part on a drain distance between the one or more contact locations and a drain location.

[0016] In some embodiments, the method includes determining a drain distance; and determining a contact distance based at least in part on the drain distance, wherein the contact distance is within a threshold of the drain distance.

[0017] In some embodiments, the method includes forming a metal gate on the pGaN landing to form a pGaN gate, wherein the metal gate includes a titanium nitride (TiN) material.

[0018] In some embodiments, the method includes forming a gate contact dielectric over the pGAN gate by a plasma enhanced chemical vapor deposition (PECVD) process.

[0019] In some embodiments, a gallium nitride (GaN) device includes a semiconductor substrate having a first side and a second side, wherein the semiconductor substrate includes a GaN material, the first side includes an aluminum gallium nitride (AlGaN) layer, and the second side includes a back barrier layer; a pGaN landing on a first region of the first side of the semiconductor substrate; an ohmic contact on the second region of the first side of the semiconductor substrate; and one or more back barrier contacts at one or more contact locations in the second region.

[0020] In some embodiments, the GaN device is a GaN high electron mobility transistor (HEMT).

[0021] In some embodiments, the backside barrier layer includes a second AlGaN layer or a MgGaN layer.

[0022] In some embodiments, the GaN device includes a pGaN gate on a pGaN landing.

[0023] In some embodiments, the GaN device includes one or more via contact landings at one or more via locations within the second region, wherein the one or more via locations are separated from the one or more contact locations.

[0024] The above summary of the invention is only provided for summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it should be appreciated that the above embodiments are merely examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It should also be appreciated that the scope of the present disclosure also encompasses many potential embodiments in addition to the embodiments outlined here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Having thus generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0026] Figure 1 illustrates an example computing entity according to one or more embodiments of the present disclosure;

[0027] Figure 2A-2B illustrates an example cross section of a GaN device according to one or more embodiments of the present disclosure;

[0028] Figure 3 illustrates an example back barrier contact positioning scheme according to one or more embodiments of the present disclosure;

[0029] Figure 4 illustrates an example first stage of a GaN HEMT manufacturing process according to one or more embodiments of the present disclosure;

[0030] Figure 5A-Figure 5B illustrates an example second stage of a GaN HEMT manufacturing process according to one or more embodiments of the present disclosure;

[0031] Figure 6A-6B illustrates an example third stage of a GaN HEMT manufacturing process according to one or more embodiments of the present disclosure; and

[0032] Figure 7 A flow chart of an example method for fabricating a GaN device according to one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0033] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. Indeed, the various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. The same reference numerals represent the same elements throughout.

[0034] Various example embodiments of the present disclosure are directed to improved GaN devices and systems, apparatus, products, and methods for manufacturing improved GaN devices. The present disclosure describes, in some examples, a method for manufacturing a GaN heterostructure that reduces the dynamic drain-source resistance and R in a GaN device. on degradation to improve conventional GaN devices.

[0035] Traditionally, GaN heterostructures can be used for high power and high frequency field effect transistors. However, they are usually required to operate in the normally depleted mode rather than the enhanced mode (normally off). Enhancement mode devices are beneficial for safe operation and simplified driving circuits as well as reduced power consumption. A key issue for enhancement mode devices (especially GaN HEMT power structures) is the R after the OFF state condition. on There is a trade-off between degradation and off-state breakdown. To obtain reasonable vertical leakage values, it is necessary to compensate for the unintended n-doping of GaN by adding other elements such as iron (Fe) and carbon (C). However, the presence of these elements in the GaN HEMT power structure results in R on degradation and cause a significant increase in the resistance of the power device.

[0036] Some embodiments of the present disclosure describe a GaN heterostructure that reduces R on The GaN heterostructure design can replace conventional techniques to optimize off-state breakdown and R degradation while preventing off-state breakdown. This results in less resistance in the power device without device degradation over time. GaN heterostructures can be used to improve any power delivery device, including consumer-grade battery chargers to commercial electric vehicle chargers. Unique features of the present invention include (i) integrating back barriers in GaN heterostructure designs connected via multiple back-barrier contacts, and (ii) fabrication techniques for fabricating GaN heterostructures. GaN heterostructure designs can replace conventional techniques to optimize off-state breakdown and R degradation while preventing off-state breakdown. This results in less resistance in the power device without device degradation over time. GaN heterostructures can be used to improve any power delivery device, including consumer-grade battery chargers to commercial electric vehicle chargers. Unique features of the present invention include (i) integrating back barriers in GaN heterostructure designs connected via multiple back-barrier contacts, and (ii) fabrication techniques for fabricating GaN heterostructures. onThe trade-off between degradation, including the use of additional p-GaN regions grown on top of the aluminum gallium nitride (AlGaN) layer and connected to the drain, can be replaced and improved by implementing back barrier contacts within the ohmic region of the GaN heterostructure according to some GaN heterostructure designs of the present disclosure.

[0037] It should be readily appreciated that the embodiments of the systems, apparatus and methods described herein may be configured in a variety of additional and alternative ways besides those explicitly described herein.

[0038] Figure 1 An example computing system 100 according to one or more embodiments of the present disclosure is illustrated. In general, the term computing system, computer, system, device, entity and / or similar words (used interchangeably herein) may refer to, for example, one or more computers, computing entities, desktops, mobile phones, tablet computers, notebooks, laptops, distributed systems, kiosks, input terminals, servers or server networks, blades, gateways, switches, processing devices, processing entities, set-top boxes, relays, routers, network access points, base stations, etc. and / or any combination of devices or entities suitable for performing functions, operations and / or processes described herein. Such functions, operations and / or processes may include, for example, transmission, reception, operation, processing, display, storage, determination, creation / generation, monitoring, evaluation, comparison and / or similar terms (used interchangeably herein). In one embodiment, these functions, operations and / or processes may be performed on data, content, information and / or similar terms (used interchangeably herein).

[0039] The computing system 100 may include a computing device 110 and / or one or more computing entities 120 communicatively coupled to the computing device 110 using one or more wired and / or wireless communication technologies. The computing device 110 may include any computing device including, for example, one or more services, computing platforms, and / or the like that are specifically configured to perform one or more steps / operations of one or more manufacturing techniques described herein. In some embodiments, the computing device 110 may include (one or more) mobile devices, (one or more) desktop computers, (one or more) laptop computers, (one or more) servers, (one or more) cloud computing platforms, and / or the like, and / or be associated therewith. In some example embodiments, the computing device 110 may be configured to receive and / or provide power conversion instructions, data, and / or the like between one or more computing entities 120 to perform one or more steps / operations of one or more manufacturing techniques described herein.

[0040] In some embodiments, computing device 110 includes, is integrated with, and / or is otherwise associated with one or more computing entities 120. One or more computing entities 120 may include one or more semiconductor manufacturing equipment, such as one or more etching equipment 114 (e.g., ion etching equipment, chemical etching equipment, physical etching equipment, etc.), one or more material deposition equipment 112 (e.g., atomic layer deposition (ALD) equipment, plasma enhanced atomic layer deposition (PEALD) equipment, plasma enhanced chemical vapor deposition (PECVD) equipment, sputtering vapor deposition, thermal evaporation, arc vapor deposition, etc.), and / or the like. For example, computing device 110 may be configured to receive and / or provide one or more manufacturing instructions between one or more components of one or more computing entities 120. For example, computing entity 120 may include and / or be associated with one or more manufacturing systems that are configured to perform one or more manufacturing operations for manufacturing GaN and / or other power devices. For example, one or more manufacturing systems may be configured to manufacture one or more GaN HEMT power devices for use with one or more converters, inverters, power supplies, battery chargers, motor control systems, and / or the like.

[0041] Computing device 110 may include or be in communication with one or more processing elements 102 (also referred to as processors, processing circuitry, digital circuitry, and / or similar terms (used interchangeably herein)) that communicate with other elements within computing device 110 via, for example, a bus. As will be appreciated, processing element 102 may be implemented in a variety of different ways.

[0042] For example, processing element 102 may be implemented as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, co-processing entities, application specific instruction set processors (ASIPs), microcontrollers, and / or controllers. In addition, processing element 102 may be implemented as one or more other processing devices or circuit systems. The term circuit system may refer to a complete hardware embodiment or a combination of hardware and computer program products. Therefore, processing element 102 may be implemented as an integrated circuit, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, a digital circuit system, and / or the like.

[0043] Thus, as will be appreciated, processing element 102 may be configured for a particular purpose, or configured to execute instructions stored in a volatile or non-volatile medium or otherwise accessible to processing element 102. Thus, whether configured by hardware or a computer program product, or by a combination thereof, processing element 102, when configured accordingly, may be capable of performing steps or operations according to embodiments of the present disclosure.

[0044] In one embodiment, the computing device 110 may also include one or more memory elements 104, or communicate with one or more memory elements 104. The one or more memory elements 104 may include non-volatile and / or volatile media. For example, the memory element 104 may include non-volatile media (also referred to as non-volatile storage, memory, memory storage, memory circuitry, and / or similar terms (used interchangeably herein)). In one embodiment, the non-volatile storage or memory may include one or more non-volatile storage or memory media, including but not limited to a hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, NVRAM, MRAM, RRAM, SONOS, FJG RAM, Millipede memory, racetrack memory, and / or the like.

[0045] As will be appreciated, a non-volatile storage device or memory medium may store a database, a database instance, a database management system, data, an application, a program, a program module, a script, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like. The terms database, database instance, database management system, and / or similar terms (used interchangeably herein) may refer to a collection of records or data stored in a computer-readable storage medium using one or more database models, such as a hierarchical database model, a network model, a relational model, an entity-relationship model, an object model, a document model, a semantic model, a graph model, and / or the like.

[0046] Additionally or alternatively, the memory element 104 may include a volatile memory. For example, the computing device 110 may also include or communicate with a volatile medium (also referred to as volatile storage device memory, memory storage device, memory circuit system and / or similar terms (used interchangeably herein)). In one embodiment, the volatile storage device or memory may also include one or more volatile storage devices or memory media, including but not limited to RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory and / or the like.

[0047] As will be appreciated, volatile storage or memory media may be used to store at least a portion of a database, database instance, database management system, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like that is executed by, for example, processing element 102. Thus, a database, database instance, database management system, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like may be used to control certain aspects of the operation of computing device 110 with the assistance of processing element 102 and an operating system.

[0048] As indicated, in one embodiment, computing device 110 may also include one or more communication interfaces 108 for communicating with a variety of computing entities (including computing entity 120), such as by transmitting data, content, information, and / or similar terms (used interchangeably herein) that may be transmitted, received, manipulated, processed, displayed, stored, and / or the like. One or more communication interfaces 108 may, for example, include one or more wired peripherals (e.g., fiber optic interfaces, Ethernet ports, and / or the like), antennas, transmitters, receivers, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), modulators, demodulators, and / or the like. Such communications may be performed using a wired data transmission protocol (such as fiber distributed data interface (FDDI), digital subscriber line (DSL), Ethernet, asynchronous transfer mode (ATM), frame relay, data over cable service interface specification (DOCSIS), or any other wired transmission protocol). Similarly, the computing device 110 can be configured to communicate via a wireless external communication network using any of a variety of protocols, such as General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution Data Optimized (EVDO), High Speed ​​Packet Access (HSPA), High Speed ​​Downlink Packet Access (HSDPA), IEEE 802.9 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), Ultra Wideband (UWB), Infrared (IR) protocol, NFC protocol (such as NFC-A, NFC-B, NFC-F), Wibree, Bluetooth protocol, wireless Universal Serial Bus (USB) protocol and / or any other wireless protocol.

[0049] The computing device 110 may include input / output circuitry for communicating with one or more users. For example, the input / output circuitry may include one or more user interfaces for providing and / or receiving information from one or more users of the computing device 110. The input / output interfaces may include one or more tactile interfaces (e.g., keyboards, touch screens, etc.), one or more audio interfaces (e.g., microphones, speakers, etc.), visual interfaces (e.g., display devices, etc.), and / or the like. The input / output circuitry may be configured to receive user input from a user of the computing device 110 through one or more of the user interfaces, and to provide data to the user through one or more of the user interfaces.

[0050] Example embodiments of the present disclosure describe an improved GaN heterostructure that can be fabricated using an improved fabrication technique. The improved fabrication technique modifies a conventional GaN heterostructure by adding a back barrier contact, thereby reducing R on degradation and resistance of GaN devices, as well as having other advantages described herein.

[0051] Figure 2A-2B An example cross section of a GaN device according to one or more embodiments of the present disclosure is illustrated. The GaN device may include, for example, a GaN high electron mobility transistor (HEMT). In a first cross section 200, the GaN device may include a through-hole contact 324. In a second cross section 250, the GaN device may include a back barrier contact 252.

[0052] In some embodiments, reference Figure 2A , the GaN device includes a semiconductor substrate 202 having a first side 202A and a second side 202B. The first side 202A may include a front barrier layer 204. The front barrier layer 204 may include a conductive material layer, such as a first AlGaN layer. The second side 202B may include a back barrier layer 206. The back barrier layer 206 may include another conductive material layer, such as a second AlGaN layer. Additionally or alternatively, the back barrier layer 206 may include a magnesium GaN (MgGaN) layer.

[0053] In some examples, the semiconductor substrate 202 may include a GaN material disposed between a front barrier layer 204 and a back barrier layer 206. For example, the GaN material may be disposed between two AlGaN layers (e.g., on the first side 202A and the second side 202B, respectively). In some examples, the GaN device may include an insulating layer 208 disposed on the front barrier layer 204. The insulating layer 208 may include any insulating material. In some embodiments, the insulating layer 208 includes an aluminum oxide (Al2O3) layer.

[0054] In some embodiments, the GaN device includes a first region 220 and a second region 230 on the first side 202A of the semiconductor substrate 202. The second region 230 can be adjacent to the first region 220. In some examples, the first region 220 can include a gate region located between a drain region and a source region of the GaN device. In some examples, the second region 230 can include an ohmic source region. In some embodiments, the GaN device includes a drain region (not shown) separated from a source region (e.g., the second region 230) by a gate region (e.g., the first region 220).

[0055] In some embodiments, the first region 220 includes a pGaN structure. The pGaN structure includes a pGaN landing portion 210 located on the first region 220 of the first side 202A of the semiconductor substrate 202. The pGaN landing portion 210 may include a conductive material in direct contact with the front-side barrier layer 204 (e.g., the first AlGaN layer). In some examples, the pGaN structure may include a pGaN gate 212 disposed on the pGaN landing portion 210. In some examples, the pGaN gate 212 may include a metal gate. In some examples, the metal gate may be separated from the pGaN landing portion 210 by a portion of the insulating layer 208. The metal gate may include any metal material, such as titanium nitride (TiN) and / or the like.

[0056] In some embodiments, the first region 220 includes a field plate structure 214 and / or one or more substrate materials. For example, the field plate structure 214 may include a metal structure placed at the edge of the pGaN gate 212 to reduce the peak electric field at the gate edge. This can increase the breakdown voltage, weaken the strong field electron effect, suppress current collapse, and increase the output power of the GaN device. The field plate structure 214 may include any metal material, such as titanium nitride (TiN) and / or similar materials. In some examples, the field plate structure 214 may be the same material as the pGaN gate 212.

[0057] In some embodiments, one or more substrate materials may include a substrate layer 216 and an insulating pad 218. The substrate layer 216 may be disposed over one or more metal layers in the first region 220 and the second region 230 of the first side 202A of the semiconductor substrate 202. As described herein, on the first region 220, the substrate layer 216 may be initially disposed over the pGaN landing portion 210 and then removed to form the pGaN gate 212. The substrate layer 216 may include any insulating material. As an example, the substrate layer 216 may include a silicon nitride (SiN) material. The insulating pad 218 may include one or more portions of the same and / or different insulating materials. For example, the insulating pad 218 may include a silicon oxide (SiO2) material.

[0058] In some embodiments, the second region 230 includes an ohmic structure. The ohmic structure includes an ohmic contact 232 located on the second region 230 on the first side 202A of the semiconductor substrate 202. In some examples, the ohmic contact 232 can be disposed in direct contact with the semiconductor substrate 202. For example, the ohmic contact 232 can include a metal layer formed on the second region 230 on the first side 202A of the semiconductor substrate 202. The metal layer can include, for example, titanium (Ti), aluminum copper (AlCu), titanium nitride (TiN) and / or any other metal material. In some examples, the substrate layer 216 can be at least partially formed on the ohmic contact 232.

[0059] In some embodiments, in the first cross section 200 of the GaN device, the second region 230 includes a plurality of via contact landings 234. Each via contact landing 234 may include an insulating pad 218 and an opening in the substrate layer 216 to allow access to the ohmic contact 232.

[0060] refer to Figure 2B , in the second cross section 250 of the GaN device, the second region 230 may include one or more back barrier contacts 252. The back barrier contact 252 may include a hole in the semiconductor substrate 202 that allows the ohmic contact 232 to directly contact the back barrier layer 206. For example, the back barrier contact 252 may be made by removing one or more portions of the semiconductor substrate 202 below the one or more contact locations in the second region 230 to form one or more holes in the semiconductor substrate 202. The back barrier contact 252 may be formed by depositing a metal layer in the one or more holes so that the metal layer directly contacts the back barrier layer 206. In this manner, the ohmic contact 232 may include a continuous metal layer that is at least partially disposed on the first side 202A of the semiconductor substrate 202 and at least partially disposed on the second side 202B of the semiconductor substrate 202.

[0061] In some embodiments, the second region 230 may include a plurality of back barrier contacts 252 located at one or more contact locations. In some examples, the contact locations may be strategically placed to reduce the effect of one or more through-hole contact sizes on resistance. For example, reference will now be made to Figure 3 The back barrier contact positioning scheme is further described.

[0062] Figure 3An example back barrier contact positioning scheme 300 according to one or more embodiments of the present disclosure is illustrated. The back barrier contact positioning scheme 300 may include determining one or more contact positions 302A-302B for one or more back barrier contacts of a GaN device. In some examples, one or more contact positions 302A-302B may be based at least in part on a drain position 304. For example, the GaN device may include a drain electrode located opposite a second region of a semiconductor substrate. For example, the drain electrode may be located in a drain region separated from a second region by a first region including a pGaN gate.

[0063] In some embodiments, drain position 304 indicates the location of the drain on the semiconductor substrate. For example, the location can be a relative location relative to the second region of the semiconductor substrate. In some examples, one or more contact positions 302A-302B can be separated by at least a contact distance 306. The contact distance can be based at least in part on a drain distance 308 between one or more contact positions 302A-302B and the drain position 304. For example, the back barrier contact positioning scheme 300 can include determining the drain distance 308 and then determining the contact distance 306 based at least in part on the drain distance 308. In some examples, the contact distance 306 can be within a threshold of the drain distance 308. For example, the contact distance 306 (Lcc) can be approximated to the drain distance 308 (lcd) to optimize (e.g., reduce) the p-GaN resistance. For example, the P-GaN resistance can be expressed as:

[0064]

[0065] In some examples, the contact distance 306 (Lcc) can be set equal to the drain distance 308 (lcd) such that:

[0066]

[0067] It is approximately 12% and is not expected to significantly affect the operation of the buried p-GaN layer.For example, in some structures, the contact distance 306 (Lcc) may be fixed at 1.5um and the drain distance 308 (lcd) may be fixed at 3.35um.

[0068] In some examples, the contact locations 302A-302B can be utilized to generate a GaN heterostructure with multiple back barrier contacts to optimize the performance of the GaN HEMT device. The GaN heterostructure can be fabricated in a fabrication process that includes one or more fabrication stages. Reference will now be made to Figure 4 The first manufacturing stage is discussed in more detail.

[0069] Figure 4An example first stage 400 of a GaN HEMT manufacturing process according to one or more embodiments of the present disclosure is illustrated. The first stage 400 is illustrated using a top view 410 and a cross-sectional view 420 of a GaN device. During the first stage 400, a first region 220 on a first side 202A of a semiconductor substrate 202 is first fabricated. For example, the first stage 400 includes providing a semiconductor substrate 202. The semiconductor substrate 202 includes a first side 202A (e.g., a front side) and a second side 202B (e.g., a back side). As described herein, the semiconductor substrate 202 may include a GaN material.

[0070] In some embodiments, one or more barrier layers may be grown and / or deposited on the semiconductor substrate 202. For example, a front barrier layer 204 may be grown and / or deposited on a surface of the first side 202A of the semiconductor substrate 202. In this manner, the first side 202A may include the front barrier layer 204. In some examples, the front barrier layer 204 may include an AlGaN layer. Additionally or alternatively, a back barrier layer 206 may be grown and / or deposited on a surface of the second side 202B of the semiconductor substrate 202. In this manner, the second side 202B may include the back barrier layer 206. In some examples, the back barrier layer 206 may include the same material as the front barrier layer 204. For example, the back barrier layer 206 may include a second AlGaN layer. Additionally or alternatively, the back barrier layer 206 may include a different material, such as a MgGaN material.

[0071] In some embodiments, the pGaN landing portion 210 is formed on the first region 220 of the first side 202A of the semiconductor substrate 202. For example, the pGaN landing portion 210 can be etched (e.g., using resist stripping and / or tetraethyl orthosilicate (TEOS) removal) on the first region 220 of the first side 202A of the semiconductor substrate 202. For example, the pGaN landing portion 210 can be etched into the front-side barrier layer 204 (e.g., the first AlGaN layer, etc.).

[0072] In some embodiments, an insulating layer 208 is formed over the front barrier layer 204 and the pGaN landing portion 210. As described herein, the insulating layer 208 can include any insulating material, such as an Al2O3 layer. In some examples, the insulating layer 208 can be formed by an atomic layer deposition (ALD) process (e.g., 300 degrees Celsius based on H2O, etc.) to deposit the Al2O3 layer over the first region 220 and the second region (not shown) of the first side 202A of the semiconductor substrate 202. In some examples, the insulating layer 208 can be deposited after the pGaN landing portion 210 is formed, so that the insulating layer 208 covers the pGaN landing portion 210.

[0073] In some embodiments, a portion of the insulating pad 218 is formed over the first region 220. For example, the insulating pad 218 can be formed by a PECVD process to deposit a SiO2 layer over at least a portion of the first region 220 of the first side 202A of the semiconductor substrate 202. For example, the insulating pad 218 can be formed over at least a portion of the pGaN landing portion 210 and the insulating layer 208. In some examples, the insulating pad 218 can be applied by a sealing deposition PECVD to deposit SiH4-based SiO2. In some embodiments, the pGaN landing portion 210 can then be sealed on the insulating layer 208.

[0074] In some embodiments, a substrate layer 216 is formed over the first region 220 and / or the second region (not shown) of the first side 202A of the semiconductor substrate 202. The substrate layer 216 can cover the insulating pad 218 (e.g., a SiO2 layer) and / or the insulating layer 208. As described herein, the substrate layer 216 can include a SiN material. In some examples, the substrate layer 216 can be deposited using a PECVD process. In some examples, the substrate layer 216 can be deposited after the pGaN landing portion 210 is formed, so that the substrate layer 216 covers the pGaN landing portion 210.

[0075] Go to Figure 5A-Figure 5B , Figure 5A-Figure 5B An example second stage 500 of a GaN HEMT manufacturing process according to one or more embodiments of the present disclosure is illustrated. The second stage 500 is illustrated using a top view 510 of a GaN device and two cross-sectional views 520. The two cross-sectional views 520 illustrate one or more manufacturing operations on a first cross-section 200 and a second cross-section 250 of the GaN device. As described herein, the first cross-section 200 may correspond to a cross-section of the GaN device including one or more via landings, while the second cross-section 250 may include one or more base barrier contacts. In some examples, the second cross-section may correspond to one or more contact locations 502, as described herein.

[0076] During the second stage 500, the second region 230 on the first side 202A of the semiconductor substrate 202 is first fabricated. For example, the second stage 500 includes removing a first portion 504 of the front side barrier layer 204 on at least a portion of the second region 230 on the first side 202A of the semiconductor substrate 202 to form an ohmic contact on at least a portion of the second region 230. For example, the first portion 504 can be removed from the substrate layer 216, the insulating layer 208, and the front side barrier layer 204 to expose the surface of the first side 202A of the semiconductor substrate 202. For example, the first portion 504 can be removed by removing the Al2O3 layer, the SiO2 layer, and a portion of the substrate layer 216 corresponding to the contact location 502. In some examples, the first portion 504 can be removed by etching (e.g., using a resist stripping and / or polymer removal etching technique) the ohmic contact landing on the semiconductor substrate 202.

[0077] In some embodiments, in the second cross-section 250, one or more portions 506 of the semiconductor substrate 202 are further removed to form one or more back barrier contacts. For example, one or more portions 506 of the semiconductor substrate 202 located below the one or more contact locations 502 may be removed. The back barrier contacts may be formed by etching the ohmic contact landing portion (e.g., using resist stripping and / or polymer removal etching techniques) to expose the backside barrier layer 206.

[0078] Steering Figure 5B , the second stage 500 may include forming a metal layer within the etched surface. For example, the second stage 500 may include forming a metal layer over at least a portion of the second region 230. In the first cross-section 200, the metal layer may form an ohmic contact 232 that directly contacts the surface of the first side 202A of the semiconductor substrate 202. In the second cross-section 250, the metal layer may form an ohmic contact 232 that directly contacts the back barrier layer 206 through the semiconductor substrate 202. For example, in the second cross-section 250, the metal layer may directly contact the back barrier layer 206 at one or more contact locations 502. As described herein, the metal layer may include Ti, AlCu, TiN, and / or any other material suitable for an ohmic contact. In some examples, the ohmic contact 232 may be deposited using one or more deposition techniques, such as the techniques described herein.

[0079] In some embodiments, the second stage 500 includes forming a substrate layer 216 over the metal layer. For example, the substrate layer 216 may be formed by depositing a SiN layer (and / or a similar material thereof) over the ohmic contact 232 using a PECVD process. For example, at least a portion of the substrate layer 216 may be formed after forming the ohmic contact 232 such that the substrate layer 216 covers the ohmic contact 232. In some embodiments, the ohmic contact 232 may be annealed by an ohmic annealing process (e.g., thermal annealing, laser-based annealing, etc.).

[0080] Go to Figure 6A-6B , Figure 6A-6B An example third stage 600 of a GaN HEMT manufacturing process according to one or more embodiments of the present disclosure is illustrated. The third stage 600 is illustrated using a top view 610 of a GaN device and two cross-sectional views 620A-620B. The first cross-sectional view 620A illustrates one or more manufacturing operations on a first cross-section 200 of the GaN device. The second cross-sectional view 620B illustrates one or more manufacturing operations on a second cross-section 250 of the GaN device. As described herein, the first cross-section 200 may correspond to a cross-section of the GaN device including one or more via landings, while the second cross-section 250 may include one or more base barrier contacts. In some examples, the second cross-section 250 may correspond to one or more contact locations 502, as described herein.

[0081] In some embodiments, the third stage 600 includes forming a metal gate on the pGaN landing portion 210 to form a pGaN gate 212. As described herein, the metal gate may include a titanium nitride (TiN) material and / or similar materials. In some examples, the third stage 600 may include forming a gate contact dielectric on the pGaN gate 212 by a PECVD process. For example, a SiN etch landing portion may be formed on a portion of the insulating pad 218 (e.g., SiO2 material) (e.g., using resist stripping and / or polymer removal techniques). The field plate structure 214 may be formed by depositing a metal layer (such as a TiN material) at the edge of the pGaN landing portion 210 (e.g., using resist stripping and / or polymer removal techniques). The gate contact dielectric may be deposited, for example, using one or more PECVD and TEOS techniques. The gate contact and gate metal may be defined (e.g., using resist stripping and polymer removal, etc.) to form the pGaN gate 212.

[0082] In some embodiments, the third stage 600 includes forming one or more via contact landings 234 at one or more via locations 602 on the ohmic contact 232. As described herein, the one or more via locations 602 can be separated from the one or more contact locations 502. In some examples, the intermetallic dielectric can be formed by depositing the dielectric using PECVD TEOS and chemical mechanical planarization (CMP). The via contact landings 234 can be etched on the ohmic contact 232 (e.g., using resist stripping and / or polymer removal, etc.).

[0083] In some embodiments, the pGaN device is finally completed by forming a W-plug with metal deposition and definition, forming an inter-metal dielectric layer by depositing dielectric using PECVD TEOS and CMP, defining a plurality of vias, and finally forming an insulating pad 218 (e.g., by passivation deposition) and removing the pad opening 604 of the via.

[0084] Go to Figure 6B , one or more identical operations may be performed in the second cross-section 250 to form a pGaN gate 212 across each cross-section of the first region 220 of the GaN device.

[0085] Figure 7 A flowchart of an example method 700 for manufacturing GaN devices according to one or more embodiments of the present disclosure is illustrated. The flowchart illustrates manufacturing techniques for manufacturing improved GaN devices that overcome various performance limitations of conventional GaN devices. These techniques may be implemented by one or more computing devices, entities, and / or systems described herein. For example, via the various steps / operations of method 700, a computing device (such as computing device 110 described herein) may implement these techniques (e.g., via one or more control instructions to one or more computing entities 120) to improve the performance of GaN devices by reducing R on Degeneration is used to overcome various limitations of traditional GaN devices without increasing the source-to-drain resistance.

[0086] Figure 7 An example method 700 is illustrated for illustrative purposes. Although the example method 700 shows a specific order of steps / operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the steps / operations shown may be performed in parallel or in a different order without substantially affecting the functionality of the method 700. In other examples, different components of an example device or system implementing the method 700 may perform functions at substantially the same time or in a specific order.

[0087] According to some examples, method 700 includes providing a semiconductor substrate at step / operation 702. For example, method 700 may include providing a semiconductor substrate having a front barrier and a back barrier. For example, method 700 may include providing a semiconductor substrate including a first side and a second side. The semiconductor substrate may include a GaN material. The first side may include a front barrier layer. The second side may include a back barrier layer.

[0088] According to some examples, method 700 includes forming a pGaN landing portion on the front-side barrier at step / operation 704. For example, method 700 may include forming a pGaN landing portion on a first region of a first side of a semiconductor substrate. For example, method 700 may include etching a pGaN landing portion on a first region of a first side of a semiconductor substrate. Method 700 may include forming an Al2O3 layer over a first region and a second region of a first side of a semiconductor substrate by an ALD process. The Al2O3 layer may cover the pGaN landing portion. Method 700 may include forming a SiO2 layer over the pGaN landing portion by a PECVD process. The method may include forming a substrate layer over the first region and the second region of a first side of a semiconductor substrate. The substrate layer may cover the SiO2 layer.

[0089] In some examples, the method 700 may include forming a metal gate on the pGaN landing to form a pGaN gate. The metal gate may include a TiN material. In some examples, the method 700 may include forming a gate contact dielectric on top of the pGaN gate by a PECVD process.

[0090] According to some examples, method 700 includes removing a portion of the front-side barrier at step / operation 706. For example, method 700 may include removing the portion of the front-side barrier on at least a portion of the second region of the first side of the semiconductor substrate to form an ohmic contact on the at least a portion of the second region. In some examples, removing the front-side barrier may include removing an Al2O3 layer, a SiO2 layer, and / or a substrate layer.

[0091] According to some examples, method 700 includes removing a portion of the semiconductor substrate at step / operation 708. For example, method 700 may include removing one or more portions of the semiconductor substrate at one or more contact locations within at least a portion of the second region to form one or more back barrier contacts. In some examples, one or more contact locations may be based at least in part on a drain location. For example, the drain location may indicate a location of a drain on the semiconductor substrate. In some examples, one or more contact locations may be separated by at least a contact distance. For example, the contact distance may be based at least in part on a drain distance between one or more contact locations and a drain location.

[0092] For example, method 700 can include determining a drain distance and determining a contact distance based at least in part on the drain distance. The contact distance can be within a threshold of the drain distance.

[0093] According to some examples, method 700 includes forming an ohmic contact on the first region at step / operation 710. For example, method 700 may include forming a continuous ohmic contact across the first region of the semiconductor substrate. For example, method 700 may include forming a metal layer over at least a portion of the second region. The metal layer may directly contact the backside barrier layer at one or more contact locations. In some examples, the metal layer may include at least one of titanium (Ti), aluminum copper (AlCu), and / or titanium nitride (TiN) materials.

[0094] In some examples, method 700 may include forming a substrate layer on top of the metal layer. The substrate layer may be formed using a PECVD process. The substrate layer may include a SiN material.

[0095] According to some examples, method 700 includes forming a through-hole contact landing portion on the ohmic contact at step / operation 712. For example, method 700 may include forming one or more through-hole contact landing portions at one or more through-hole locations on the metal layer. In some examples, the one or more through-hole locations are separated from the one or more contact locations.

[0096] in conclusion

[0097] Many modifications and other embodiments of the disclosure described herein will occur to those skilled in the art after having benefited from the teachings presented in the above description and the associated drawings. Although the figures only show certain components of the apparatus and system described herein, it should be understood that a variety of other components can be used in conjunction with the system. Therefore, it should be understood that the disclosure is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, the steps in the above method do not necessarily occur in the order shown in the drawings, and in some cases, one or more of the steps shown may occur substantially simultaneously, or may involve additional steps. Although specific terms are used herein, they are used only in a general and descriptive sense, and not for limiting purposes.

[0098] Although various embodiments according to the principles disclosed herein have been shown and described above, those skilled in the art may modify them without departing from the spirit and teachings of the present disclosure. The embodiments described herein are representative only and are not intended to be limiting. Many variations, combinations, and modifications are possible and within the scope of the present disclosure. The disclosed embodiments are primarily directed to techniques for GaN power devices and for manufacturing GaN power devices, but those skilled in the art will recognize that these principles can be applied to any semiconductor device. Alternative embodiments produced by combining, integrating, and / or omitting features of (one or more) embodiments are also within the scope of the present disclosure. Therefore, the scope of protection is not limited by the above description.

[0099] Additionally, section headings are used herein to provide or otherwise provide an organizational cue for purposes of consistency with the provisions under 37 CFR 1.77. Such headings shall not limit or characterize the disclosure(s) set forth in any claim(s) that may issue from this disclosure.

[0100] The use of broader terms such as "comprising," "including," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting essentially of," and "consisting essentially of." The use of the terms "optionally," "may," "perhaps," "might," and the like with respect to any element of an embodiment means that the element is not required, or, alternatively, the element is required, both alternatives being within the scope of the embodiment(s). Furthermore, reference to examples is for illustrative purposes only and is not intended to be exclusive.

[0101] Although the detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements.For example, the appended claims may cover any form of semiconductor manufacturing.

[0102] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim.

Claims

1. A method comprising: Providing a semiconductor substrate including a first side and a second side, wherein the semiconductor substrate includes a gallium nitride (GaN) material, the first side includes a front-side barrier layer, and the second side includes a back-side barrier layer; forming a pGaN landing portion on a first region of a first side of a semiconductor substrate; removing a portion of the front-side barrier layer on at least a portion of a second region of the first side of the semiconductor substrate to form an ohmic contact on the at least a portion of the second region; as well as One or more portions of the semiconductor substrate at one or more contact locations within the at least a portion of the second region are removed to form one or more back barrier contacts. 2 . The method of claim 1 , further comprising forming a metal layer over the at least a portion of the second region, wherein the metal layer directly contacts the backside barrier layer at the one or more contact locations. 3 . The method of claim 2 , wherein the metal layer comprises titanium (Ti), aluminum copper (AlCu) or titanium nitride (TiN) material. 4 . The method of claim 2 , further comprising forming one or more via contact landings on the metal layer at one or more via locations.

5. The method of claim 4, wherein the one or more through-hole locations are separated from the one or more contact locations. The method of claim 2 , further comprising forming a substrate layer over the metal layer.

7. The method of claim 6, wherein the substrate layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process.

8. The method of claim 6, wherein the substrate layer comprises a silicon nitride (SiN) material.

9. The method of claim 1, wherein forming the pGaN landing portion comprises: etching a pGAN landing portion on a first region of a first side of a semiconductor substrate; forming an aluminum oxide (Al2O3) layer on the first region and the second region of the first side of the semiconductor substrate by an atomic layer deposition (ALD) process, wherein the Al2O3 layer covers the pGAN landing portion; forming a silicon oxide (SiO2) layer on the pGaN landing portion by a plasma enhanced chemical vapor deposition (PECVD) process; as well as A substrate layer is formed on the first region and the second region of the first side of the semiconductor substrate, wherein the substrate layer covers the SiO 2 layer.

10. The method of claim 9, wherein removing the portion of the front-side barrier layer on the second region further comprises removing an Al2O3 layer, a SiO2 layer, and a substrate layer.

11. The method of claim 1, wherein the one or more contact locations are based at least in part on a drain location, wherein the drain location indicates a location of the drain on a semiconductor substrate.

12. The method of claim 11, wherein the one or more contact locations are separated by at least a contact distance, wherein the contact distance is based at least in part on a drain distance between the one or more contact locations and a drain location.

13. The method of claim 12, further comprising: Determine the drain distance; as well as A contact distance is determined based at least in part on the drain distance, wherein the contact distance is within a threshold of the drain distance.

14. The method of claim 1, further comprising forming a metal gate on the pGaN landing portion to form a pGaN gate, wherein the metal gate comprises a titanium nitride (TiN) material.

15. The method of claim 14, forming the gate contact dielectric over the pGAN gate by a plasma enhanced chemical vapor deposition (PECVD) process.

16. A gallium nitride (GaN) device, comprising: a semiconductor substrate having a first side and a second side, wherein the semiconductor substrate comprises a GaN material, the first side comprises an aluminum gallium nitride (AlGaN) layer, and the second side comprises a backside barrier layer; a pGaN landing on a first region of a first side of a semiconductor substrate; an ohmic contact on the second region of the first side of the semiconductor substrate; as well as One or more back-barrier contacts at the one or more contact locations within the second region.

17. The GaN device of claim 16, wherein the GaN device is a GaN high electron mobility transistor (HEMT). 18 . The GaN device of claim 16 , wherein the backside barrier layer comprises a second AlGaN layer or a MgGaN layer.

19. The GaN device of claim 16, further comprising a pGaN gate on the pGaN landing portion.

20. The GaN device of claim 16, further comprising one or more via contact landings at one or more via locations within the second region, wherein the one or more via locations are separated from the one or more contact locations.

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