Low-loss trench gate silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method

Abstract

The invention provides a low-loss trench gate silicon carbide MOSFET device and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, an N + source region, a P + shielding region, a polycrystalline silicon gate, source metal and drain metal. According to the silicon carbide MOSFET device based on the asymmetric trench gate, a channel is formed in one side of a silicon carbide trench, and the other side of the silicon carbide trench is wrapped by P +. The integrated FinFET structure increases the channel density, and meanwhile, the extremely narrow Fin-shaped mesa weakens the electric field intensity and interface scattering at the channel, so that the mobility of the channel in the Fin-shaped mesa is increased. In addition, the P + structure wrapping the gate trench reduces the electric field of the gate oxide layer at the corner of the trench, so that the electric field intensity of the gate oxide layer of the device is within a safe working range after the FinFET structure is introduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a low-loss trench gate silicon carbide MOSFET device and a manufacturing method thereof. Background Art

[0002] As more and more applications put forward higher requirements on the withstand voltage and power consumption of power devices, the performance of power devices is facing greater and greater challenges. Silicon carbide materials have the advantages of high thermal conductivity, wide bandgap, high critical breakdown voltage, etc. Semiconductor devices made of silicon carbide are becoming increasingly advantageous in high-voltage and high-power applications. Silicon carbide MOSFET has the characteristics of high breakdown voltage, low specific on-resistance, low switching loss, etc., and has advantages in various application scenarios such as new energy vehicles. However, due to the limitations of the gate oxide process, there are a large number of interface traps at the interface of silicon carbide MOSFET. These traps make silicon carbide MOSFET have lower channel mobility and increase the specific on-resistance of silicon carbide MOSFET.

[0003] In order to reduce the specific on-resistance of SiC MOSFET, trench SiC MOSFET was proposed. The channel of trench SiC MOSFET is generally located at (11 _ 20) or (1 _ 100) crystal plane, with smaller interface traps and thus higher channel mobility. However, in order to protect the gate oxide layer, trench SiC MOSFETs often introduce a P-type shielding region, which introduces JFET region resistance and increases the cell size, thus failing to achieve a smaller specific on-resistance. Asymmetric trench SiC MOSFET is a classic SiC trench MOSFET structure, in which the channel is located at (112 _ 0) crystal plane. One side of the gate trench is wrapped by a P-type shielding structure, so the structure has good gate oxide layer reliability. However, the P-type shielding region introduces JFET resistance and increases the cell size.

[0004] Japanese scholars proposed and manufactured silicon carbide FinFET devices. When the Fin width is narrow enough, the device forms a "body inversion layer", the carrier distribution in the channel region is more uniform, and the channel mobility increases, which is called the "FinFET effect". At the same time, silicon carbide FinFET has a smaller cell size than trench gate silicon carbide MOSFET, and thus has a larger channel density. The above mechanism makes silicon carbide FinFET have a much lower specific on-resistance than trench silicon carbide MOSFET. However, the gate oxide layer electric field of the above silicon carbide FinFET is high under high voltage, exceeding the safe working electric field strength of silicon dioxide 3MV / cm.

[0005] The present invention integrates the FinFET structure into the gate trench of an asymmetric trench gate silicon carbide MOSFET device, and the Fin width is less than 300nm. The integrated FinFET structure sacrifices the channel located on the side wall of the trench and increases the channel located inside the Fin-shaped table, and the channel width inside the Fin-shaped table is greater than the channel width sacrificed by the side wall of the trench, so the overall channel density of the device is increased. At the same time, the extremely narrow Fin-shaped table allows the position far away from the interface to still have a higher carrier concentration, and the channel carriers are less affected by interface scattering, thereby increasing the channel mobility of the FinFET structure. Therefore, after the FinFET structure is integrated, the specific on-resistance of the asymmetric trench gate silicon carbide MOSFET is significantly reduced. The P-type shielding structure of the asymmetric trench gate silicon carbide MOSFET can protect the gate oxide layer of the FinFET structure integrated inside the trench, so the gate oxygen reliability of the entire device is not weakened. Summary of the invention

[0006] The purpose of the present invention is to provide a low-loss trench gate silicon carbide MOSFET device and a manufacturing method thereof. The device structure is based on an asymmetric trench gate silicon carbide MOSFET structure, in which the channel is located on one side of the gate trench, and the other side of the gate trench is wrapped by a P-type shielding structure. The present invention integrates a FinFET structure inside the gate trench to improve the device's specific on-resistance, and at the same time, the P-type shielding area protects the gate oxide layer of the FinFET structure, so that the device has a small specific on-resistance and good gate oxide layer reliability.

[0007] In order to achieve the above-mentioned invention object, the present invention adopts the following technical solutions:

[0008] A low-loss trench gate silicon carbide MOSFET device comprises: an N+ substrate 3, an N+ buffer layer 2 and an N-drift region 1 are sequentially arranged above the N+ substrate 3; a gate trench is arranged above the N-drift region 1, and a gate oxide layer 8 and a polysilicon gate 9 are arranged in the trench; a P-type well region 6 and an N+ source region 7 above the P-type well region 6 are arranged on one side of the gate trench, and the two form a channel located on the side wall of the trench; a P-type shielding region A4 and a P-type shielding region B5 are respectively arranged on the N-drift region 1, and the P-type shielding region A4 wraps the gate trench; a source metal A10 and a source metal B11 are arranged above the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7, and the source metal B11 forms an ohmic contact with the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7; a drain metal 12 is arranged at the bottom of the device to form an ohmic contact with the N+ substrate 3;

[0009] The FinFET structure is integrated in the gate trench, and the structure includes the N-drift region 1, N+ buffer layer 2, N+ substrate 3, P-type well region 6, polysilicon gate 9 and N+ source region 7; the N+ buffer layer 2 is located on the N+ substrate 3, the N-drift region 1 is located on the N+ buffer layer 2, there is a P-type well region 6 above the N-drift region 1, and an N+ source region 7 above the P-type well region 6, the gate trench passes through the N+ source region 7, the P-type well region 6 and the N-drift region 1, and there is a polysilicon gate 9 in the trench.

[0010] As a preferred embodiment, the FinFET structure integrated in the gate trench has a Fin width less than 300 nm.

[0011] As a preferred embodiment, the FinFET structure integrated in the gate trench is wrapped by a P-type shielding region A4.

[0012] The present invention also provides a method for manufacturing the low-loss trench gate silicon carbide MOSFET, comprising the following steps:

[0013] Step 1: Select silicon carbide material as the N+ substrate layer and epitaxially grow an N+ buffer layer on the N+ substrate;

[0014] Step 2: epitaxially grow an N-drift region on the N+ buffer layer;

[0015] Step 3: Form a P-type well region on the surface of the N-drift region by ion implantation of Al ions;

[0016] Step 4: Form an N-type source region by ion implantation of N ions on the surface of the P-type well region;

[0017] Step 5: Forming P-type shielding region A and P-type shielding region B on the surface of the N-drift region by ion implantation of Al;

[0018] Step 6: Form a gate trench in the N-drift region by etching;

[0019] Step 7: growing a gate oxide layer in the gate trench;

[0020] Step 8: depositing a polysilicon gate on the gate oxide layer;

[0021] Step 9: Deposit dielectric oxide layer;

[0022] Step 10: Form ohmic contacts on the upper and lower surfaces of the device.

[0023] The present invention integrates a FinFET structure on the basis of an asymmetric trench gate silicon carbide MOSFET device structure. The integrated FinFET structure sacrifices the channel located on the side wall of the trench and increases the channel located inside the Fin-shaped mesa, and the channel width inside the Fin-shaped mesa is greater than the channel width sacrificed by the trench side wall, so the overall channel density of the device is increased. At the same time, the Fin-shaped mesa with a width less than 300nm still has a higher carrier concentration at a position far away from the interface, and the channel carriers are less affected by interface scattering, thereby increasing the channel mobility of the FinFET structure. Therefore, after the FinFET structure is integrated, the specific on-resistance of the asymmetric trench gate silicon carbide MOSFET is significantly reduced. In addition, the P-type shielding area of ​​the asymmetric trench gate silicon carbide MOSFET structure protects the gate oxide layer, so that the oxide layer at the corner of the trench is not broken down in advance after the FinFET structure is introduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the present invention and are used together with the real-time examples of the present invention to explain the present invention, but do not constitute a limitation of the present invention:

[0025] Figure 1 It is a trench gate silicon carbide device structure with an integrated FinFET structure.

[0026] Figure 2 The structure of removing polysilicon and metal for integrating trench gate silicon carbide devices with FinFET structures.

[0027] Figure 3 A top view of a low-loss trench-gate SiC MOSFET ignoring metal, polysilicon, and dielectric layers.

[0028] Figure 4 To consider the metal, polysilicon and dielectric Figure 3 The cross-sectional view is taken along the AA' dashed line in FIG. 1 , where the AA' dashed line is a dashed line that points from the P-type shielding region B to the P-type shielding region A and passes through the N+ source region and the polysilicon gate.

[0029] Figure 5 After considering metal, polysilicon and dielectric Figure 3 The cross-sectional view is taken along the BB' dashed line in FIG. 8 , where the BB' dashed line is a dashed line pointing from a gate trench to another gate trench and passing through the N+ source region.

[0030] Figure 6 It is a schematic diagram of silicon carbide epitaxial wafer.

[0031] Figure 7 Schematic diagram of implanting a Pwell layer on an epitaxial wafer.

[0032] Figure 8 Schematic diagram of implanting N+ regions in the epitaxial layer.

[0033] Fig. 9 Schematic diagram of implanting P-type shielding regions in the epitaxial layer.

[0034] Fig.10 It is a schematic diagram of digging a gate trench in the epitaxial layer.

[0035] Fig.11 An oxide layer and polysilicon are formed in the gate trench, and metal contacts are formed on the upper and lower surfaces of the device.

[0036] Among them, 1-N-drift region, 2-N+ buffer layer, 3-N+ substrate, 4-P-type shielding region A, 5-P-type shielding region B, 6-P-type well region, 7-N+ source region, 8-gate oxide layer, 9-polysilicon gate, 10-source metal A, 11-source metal B, 12-drain metal. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] like Figure 1 and Figure 2 As shown, a low-loss trench gate silicon carbide MOSFET device comprises: an N+ substrate 3, an N+ buffer layer 2 and an N-drift region 1 are sequentially arranged above the N+ substrate 3; a gate trench is arranged above the N-drift region 1, and a gate oxide layer 8 and a polysilicon gate 9 are arranged in the trench; a P-type well region 6 and an N+ source region 7 above the P-type well region 6 are arranged on one side of the gate trench, and the two form a channel located on the side wall of the trench; a P-type shielding region A4 and a P-type shielding region B5 are respectively arranged on the N-drift region 1, and the P-type shielding region A4 wraps the gate trench; a source metal A10 and a source metal B11 are arranged above the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7, and the source metal B11 forms an ohmic contact with the P-type shielding region A4, the P-type shielding region B5 and the N+ source region 7; a drain metal 12 is arranged at the bottom of the device to form an ohmic contact with the N+ substrate 3. The FinFET structure is integrated in the gate trench, and the structure includes the N-drift region 1, N+ buffer layer 2, N+ substrate 3, P-type well region 6, polysilicon gate 9 and N+ source region 7; the N+ buffer layer 2 is located on the N+ substrate 3, the N-drift region 1 is located on the N+ buffer layer 2, there is a P-type well region 6 above the N-drift region 1, and an N+ source region 7 above the P-type well region 6, the gate trench passes through the N+ source region 7, the P-type well region 6 and the N-drift region 1, and there is a polysilicon gate 9 in the trench.

[0039] Figure 3 The top view of the low-loss trench-gate silicon carbide MOSFET ignoring the metal, polysilicon and dielectric layers includes a P-type shielding region A, a P-type shielding region B, an N+ source region, a gate trench and a gate oxide layer. The gate trenches are arranged alternately, and the adjacent gate trenches form a FinFET structure with the N+ source region, the P-type well region and the N-drift region.

[0040] Figure 4 To consider the metal, polysilicon and dielectric Figure 2 The cross-section along the AA' dashed line in the figure shows an asymmetric trench-gate SiC MOSFET device, which includes a gate trench, a channel located in the P-type well region on one side of the trench, and a P-type shield region A on the other side of the trench. The P-type shield regions A and B protect the gate oxide layer under high electric fields. The AA' dashed line is a dashed line from the P-type shield region B to the P-type shield region A and passes through the N+ source region and the polysilicon gate.

[0041] Figure 5 To consider the metal, polysilicon and dielectric Figure 2 The cross-section along the BB' dashed line in the figure shows a FinFET structure integrated in the trench, which consists of adjacent gate trenches, N+ source regions, P-type well regions Pwell and N- drift regions. The FinFET structure has a Fin-type table less than 300nm, and a "body inversion layer" channel is formed in the table. The channel carriers still have a high concentration at a position far away from the interface, so the channel carriers are less affected by interface scattering, thereby increasing the interface mobility of the FinFET structure, so the FinFET structure has a smaller channel resistance. At the same time, after the FinFET structure is integrated, the channel density of the device increases. All of the above factors have led to a significant reduction in the on-resistance of the low-loss trench gate silicon carbide MOSFET. The BB' dashed line is a dashed line pointing from the gate trench to another gate trench and passing through the N+ source region.

[0042] This embodiment also provides a method for manufacturing a low-loss trench gate silicon carbide MOSFET, comprising the following steps:

[0043] Step 1: Select silicon carbide material as the N+ substrate layer and epitaxially grow an N+ buffer layer on the N+ substrate;

[0044] Step 2: epitaxially grow an N-drift region on the N+ buffer layer, such as Figure 6 As shown;

[0045] Step 3: Form a P-type well region on the surface of the N-drift region by ion implantation of Al ions, such as Figure 7 As shown;

[0046] Step 4: Form an N-type source region by ion implantation of N ions on the surface of the P-type well region, such as Figure 8 As shown;

[0047] Step 5: Form P-type shielding region A and P-type shielding region B on the surface of the N-drift region by ion implantation of Al, such as Fig. 9 As shown;

[0048] Step 6: Form a gate trench in the N-drift region by etching, such as Fig.10 As shown;

[0049] Step 7: growing a gate oxide layer in the gate trench;

[0050] Step 8: depositing a polysilicon gate on the gate oxide layer;

[0051] Step 9: Deposit dielectric oxide layer;

[0052] Step 10: Form ohmic contacts on the upper and lower surfaces of the device, and finally obtain Fig.11 The device structure is shown.

[0053] The specific concentration and thickness of the N-drift region 1 are determined according to the voltage level of the device.

[0054] The concentration and depth of the P-type shielding region A4 and the P-type shielding region B5 are determined according to the electric field strength and the on-state voltage drop of the gate oxide layer.

[0055] The working principle of the present invention is:

[0056] The present invention proposes a low-loss trench gate silicon carbide MOSFET device. When the width of the Fin-shaped mesa is less than 300nm, the channel carriers still have a high concentration at a position far away from the interface, so the channel carriers are less affected by interface scattering, thereby increasing the interface mobility of the FinFET structure. In addition, the integrated FinFET structure sacrifices the channel located on the side wall of the trench and increases the channel located inside the Fin-shaped mesa. The channel width inside the Fin-shaped mesa is greater than the channel width of the sacrificed trench side wall. The integrated FinFET structure increases the channel density of the entire device. Due to the above reasons, the low-loss trench gate silicon carbide MOSFET has a smaller specific on-resistance than the asymmetric trench gate silicon carbide MOSFET. Secondly, the P-type shielding region that wraps the gate trench protects the gate oxide layer, so that the gate oxide layer of the device with the integrated FinFET structure is still protected.

[0057] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A low-loss trench gate silicon carbide MOSFET device, characterized in that: include: An N+ substrate (3), an N+ buffer layer (2) and an N-drift region (1) are sequentially arranged above the N+ substrate (3); a gate trench is arranged above the N-drift region (1), and a gate oxide layer (8) and a polysilicon gate (9) are arranged in the trench; a P-type well region (6) and an N+ source region (7) above the P-type well region (6) are arranged on one side of the gate trench, and the two form a channel located on the side wall of the trench; a P-type shielding region A (4) and a P-type source region (7) are respectively arranged on the N-drift region (1); A P-type shielding region B (5), wherein the P-type shielding region A (4) wraps the gate trench; a source metal A (10) and a source metal B (11) are arranged above the P-type shielding region A (4), the P-type shielding region B (5) and the N+ source region (7), wherein the source metal B (11) forms an ohmic contact with the P-type shielding region A (4), the P-type shielding region B (5) and the N+ source region (7); a drain metal (12) is arranged at the bottom of the device to form an ohmic contact with the N+ substrate (3); The gate trench integrates a FinFET structure, which includes the N-drift region (1), an N+ buffer layer (2), an N+ substrate (3), a P-type well region (6), a polysilicon gate (9) and an N+ source region (7); the N+ buffer layer (2) is located on the N+ substrate (3), the N-drift region (1) is located on the N+ buffer layer (2), there is a P-type well region (6) on the N-drift region (1), and an N+ source region (7) above the P-type well region (6), the gate trench passes through the N+ source region (7), the P-type well region (6) and the N-drift region (1), and there is a polysilicon gate (9) in the trench.

2. A low-loss trench gate silicon carbide MOSFET device according to claim 1, characterized in that: The FinFET structure integrated in the gate trench has a Fin width less than 300 nm.

3. A low-loss trench gate silicon carbide MOSFET device according to claim 1, characterized in that: The FinFET structure integrated in the gate trench is surrounded by a P-type shielding region A (4).

4. A method for manufacturing a low-loss trench gate silicon carbide MOSFET device according to any one of claims 1 to 3, characterized in that The following steps are involved: Step 1: Select silicon carbide material as the N+ substrate layer and epitaxially grow an N+ buffer layer on the N+ substrate; Step 2: epitaxially grow an N-drift region on the N+ buffer layer; Step 3: Form a P-type well region on the surface of the N-drift region by ion implantation of Al ions; Step 4: Form an N-type source region by ion implantation of N ions on the surface of the P-type well region; Step 5: Forming P-type shielding region A and P-type shielding region B on the surface of the N-drift region by ion implantation of Al; Step 6: Form a gate trench in the N-drift region by etching; Step 7: growing a gate oxide layer in the gate trench; Step 8: depositing a polysilicon gate on the gate oxide layer; Step 9: Deposit dielectric oxide layer; Step 10: Form ohmic contacts on the upper and lower surfaces of the device.

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