MOSFET device and chip

Abstract

The embodiment of the invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a chip. The MOSFET device comprises an N-type substrate; the N-type epitaxial layer is arranged on the other side of the N-type substrate; the N-type current expansion layer and the first P-type buried layer are arranged above the N-type epitaxial layer; the N-type current expansion layer is connected with the first P-type buried layer; the first N + region is arranged in a groove formed in the surface of the first P-type buried layer; the groove is formed above the N-type current expansion layer and the first P-type buried layer; and the source polycrystalline silicon region, the gate polycrystalline silicon region and the oxide layer are arranged in the groove, and the oxide layer covers the surfaces of the source polycrystalline silicon region and the gate polycrystalline silicon region. According to the embodiment of the invention, the channel diode is formed below the source polysilicon through the N-type current expansion layer and the first P-type buried layer, and when the device is in a reverse conduction state, the channel diode is conducted more importantly than a body diode, so that the problems of large follow current loss and bipolar degradation of the body diode when the device is in a reverse follow current working mode are avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOSFET device and a chip. Background Art

[0002] SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) is a high-performance power semiconductor device based on silicon carbide (SiC) material. However, when MOSFET is in reverse freewheeling mode, that is, when the source voltage of MOSFET is higher than the drain voltage, the body diode (parasitic diode) of MOSFET will be turned on, forming a reverse freewheeling path, and the current flows from the source to the drain through the body diode of MOSFET. The body diode of SiC MOSFET has a high conduction voltage drop, resulting in large conduction losses in reverse freewheeling mode. In addition, due to the conduction of the body diode, minority carriers (holes) inside the device accumulate, resulting in a phenomenon of device performance degradation. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a MOSFET device and a chip that overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a MOSFET device, the device comprising:

[0005] N-type substrate;

[0006] An N-type epitaxial layer is provided on the other side of the N-type substrate;

[0007] An N-type current spreading layer and a first P-type buried layer are disposed above the N-type epitaxial layer; the N-type current spreading layer is connected to the first P-type buried layer;

[0008] A first N+ region is provided in a groove formed on the surface of the first P-type buried layer;

[0009] A trench formed above the N-type current spreading layer and the first P-type buried layer;

[0010] A source polysilicon region, a gate polysilicon region and an oxide layer are arranged in the trench, the oxide layer covers the surfaces of the source polysilicon region and the gate polysilicon region; the source polysilicon region is connected to the first P-type buried layer, the first N+ region and the N-type current spreading layer through the oxide layer; the gate polysilicon region is connected to the N-type current spreading layer through the oxide layer; the gate polysilicon region is connected to the source polysilicon region through the oxide layer;

[0011] A P-type base region, disposed above the N-type current spreading layer, the P-type base region being connected to a side surface of the gate polysilicon region through the oxide layer;

[0012] A P+ region and a second N+ region are provided above the P-type base region, the second N+ region is connected to the side of the gate polysilicon region through the oxide layer, and the second N+ region and the P+ region are located in the same layer;

[0013] A source electrode is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region; a contact hole is provided in the oxide layer corresponding to the source polysilicon region to enable the source electrode to contact the source polysilicon region.

[0014] Optionally, the N-type current spreading layer is L-type.

[0015] Optionally, the oxide layer extends toward the second N+ region to cover a portion of the surface of the second N+ region.

[0016] Optionally, a barrier height formed by the N-type current spreading layer and the first P-type buried layer is smaller than a barrier height formed by the N-type current spreading layer and the P-type base region and a barrier height formed by the N-type epitaxial layer and the first P-type buried layer.

[0017] Optionally, the base materials of the N-type substrate and the N-type epitaxial layer are silicon carbide.

[0018] Optionally, the device further includes: a drain, disposed on one side of the N+ type substrate.

[0019] Optionally, the doping concentration of the N-type current spreading layer is greater than that of the N-type epitaxial layer.

[0020] Optionally, the N-type substrate is an N+ type substrate, the N-type epitaxial layer is an N-type epitaxial layer, and the doping concentration of the N-type epitaxial layer is lower than that of the N-type substrate.

[0021] Optionally, the drain is a back metal layer, and the source is a front metal layer.

[0022] Accordingly, an embodiment of the present invention provides a chip including the MOSFET device described above.

[0023] The embodiments of the present invention include the following advantages:

[0024] The MOSFET device of the embodiment of the present invention comprises an N-type substrate; an N-type epitaxial layer, which is arranged on the other side of the N-type substrate; an N-type current expansion layer and a first P-type buried layer, which are arranged above the N-type epitaxial layer; the N-type current expansion layer is connected to the first P-type buried layer; a first N+ region, which is arranged in a groove formed on the surface of the first P-type buried layer; a groove, which is formed above the N-type current expansion layer and the first P-type buried layer; a source polysilicon region, a gate polysilicon region and an oxide layer, which are arranged in the groove, and the oxide layer covers the surface of the source polysilicon region and the gate polysilicon region; the source polysilicon region is connected to the first P-type buried layer, the first N+ region and the N-type current expansion layer through the oxide layer ; The gate polysilicon region is connected to the N-type current spreading layer through an oxide layer; the gate polysilicon region is connected to the source polysilicon region through an oxide layer; the P-type base region is arranged above the N-type current spreading layer, and the P-type base region is connected to the side of the gate polysilicon region through an oxide layer; the P+ region and the second N+ region are arranged above the P-type base region, and the second N+ region is connected to the side of the gate polysilicon region through an oxide layer, and the second N+ region and the P+ region are located in the same layer; the source electrode is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region; the oxide layer corresponding to the source polysilicon region is provided with a contact hole to make the source electrode and the source polysilicon region. In the embodiment of the present invention, a channel diode is formed under the source polysilicon through an N-type current spreading layer and a first P-type buried layer. The channel diode is connected in parallel with the body diode. When the MOSFET device is in a reverse conduction state, the channel diode is turned on before the body diode, thereby avoiding the problem of large body diode freewheeling loss and bipolar degradation when the MOSFET is in a reverse freewheeling working mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of a MOSFET device according to an embodiment of the present invention;

[0026] Figure 2 It is a schematic structural diagram of a JFET region of a MOSFET device according to an embodiment of the present invention;

[0027] Figure 3 is a schematic structural diagram of another MOSFET device according to an embodiment of the present invention;

[0028] Figure 4 It is a schematic structural diagram of a body diode and a channel diode of a MOSFET device according to an embodiment of the present invention;

[0029] Figure 5 is an equivalent circuit diagram of a MOSFET device according to an embodiment of the present invention;

[0030] Figure 6 It is a local structure of a MOSFET device and a distribution diagram of the conduction band energy band at the cut-off line according to an embodiment of the present invention;

[0031] Figure 7 It is a schematic structural diagram of another MOSFET device according to an embodiment of the present invention.

[0032] Figure numerals: N-type substrate 101, N-type epitaxial layer 102, N-type current spreading layer 103, first P-type buried layer 104, first N+ region 105, source polysilicon region 106, gate polysilicon region 107, oxide layer 108, P-type base region 109, P+ region 110, second N+ region 111, source 112, drain 113, second P-type buried layer 114, first body diode 11, second body diode 12, channel diode 13. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] SiC MOSFET is a high-performance power semiconductor device based on silicon carbide (SiC) material. However, when MOSFET is in reverse freewheeling mode, that is, when the source voltage of MOSFET is higher than the drain voltage, the body diode (parasitic diode) of MOSFET will be turned on, forming a reverse freewheeling path, and the current flows from the source to the drain through the body diode of MOSFET. The body diode of SiC MOSFET has a high conduction voltage drop, resulting in large conduction losses in reverse freewheeling mode. In addition, due to the conduction of the body diode, minority carriers (holes) inside the device accumulate, resulting in a decrease in device performance.

[0035] One of the core concepts of the embodiments of the present invention is that a channel diode is formed under the source polysilicon through an N-type current spreading layer and a first P-type buried layer. The channel diode is connected in parallel with the body diode. When the MOSFET device is in a reverse conduction state, the channel diode is turned on before the body diode, thereby avoiding the problem of large body diode freewheeling loss and bipolar degradation when the MOSFET is in a reverse freewheeling working mode.

[0036] Reference Figure 1 , shows a schematic diagram of the structure of a MOSFET device according to an embodiment of the present invention, which may specifically include the following structure:

[0037] N-type substrate 101 .

[0038] The N-type substrate is formed by doping with donor impurities (such as phosphorus, nitrogen, etc.), and has a higher free electron concentration and a lower hole concentration. Characteristics of the N-type substrate: The N-type substrate is doped with donor impurities, so it has a higher free electron concentration. Electrons are majority carriers, and the concentration of free electrons determines the conductivity of the N-type substrate; due to the high electron concentration, the hole (positive charge carrier) concentration is relatively low, and it is a minority carrier. The low hole concentration makes the N-type substrate have a higher withstand voltage under reverse bias; due to the presence of free electrons, the N-type substrate has a higher conductivity and is suitable for application scenarios that require high conductivity. In MOSFET, the N-type substrate is used to construct the conductive channel of the device, to grow the epitaxial layer, and to quickly cut off the electric field, similar to the field stop layer of IGBT (Insulated Gate Bipolar Transistor).

[0039] The N-type epitaxial layer 102 is disposed on one side of the N-type substrate.

[0040] The N-type epitaxial layer is formed by epitaxially growing a layer of semiconductor material doped with donor impurities (such as phosphorus, nitrogen, etc.) on a substrate, and has a high free electron concentration and a low hole concentration. Characteristics of the N-type epitaxial layer: The N-type epitaxial layer is doped with donor impurities, so it has a high free electron concentration. Electrons are majority carriers, and the concentration of free electrons determines the conductivity of the N-type epitaxial layer; Due to the high electron concentration, the hole (positive charge carrier) concentration is relatively low, which is a minority carrier. The low hole concentration makes the N-type epitaxial layer have a higher withstand voltage under reverse bias; The resistivity of the N-type epitaxial layer can be precisely controlled by the doping concentration to meet the needs of different devices. The N-type epitaxial layer with a high doping concentration has a low resistivity and is suitable for conductive channels. The N-type epitaxial layer with a low doping concentration has a high resistivity and is suitable for withstand voltage structures; The epitaxial growth process can achieve high-quality lattice matching, reduce lattice defects, and improve the performance and reliability of the device. In MOSFET, the N-type epitaxial layer is used to construct the drift region of the device, which determines the breakdown voltage and on-resistance of the device, similar to the N-type drift region of IGBT.

[0041] The N-type current spreading layer 103 and the first P-type buried layer 104 are disposed above the N-type epitaxial layer 102 ; the N-type current spreading layer 103 is connected to the first P-type buried layer 104 .

[0042] N-type current spreading layer (CSL) is used to improve the uniform distribution of current on the device surface, thereby improving the efficiency and reliability of the device. The role of CSL: The main role of CSL is to make the current evenly distributed on the device surface, avoid current concentration in local areas, thereby improving the overall efficiency of the device. The uniform distribution of current can reduce local overheating and extend the service life of the device. In optoelectronic devices (such as LEDs and lasers), CSL can improve the diffusion of current and make the light-emitting area more uniform, thereby improving the light output efficiency. Uniform current distribution can reduce the non-uniformity of light intensity and improve the optical performance of the device. CSL can improve the diffusion of current and reduce the current density in local areas, thereby reducing the thermal resistance of the device. Reducing thermal resistance helps to improve the heat dissipation performance of the device and extend the service life of the device. Uniform current distribution can reduce stress concentration in local areas and improve the mechanical strength and reliability of the device. The current spreading layer is introduced to increase the doping concentration of the N drift region in the JFET region. The increased doping concentration of the N drift region will effectively reduce the depletion in the JFET region, while reducing the resistance of the JFET region and promoting the lateral expansion of current from the MOS channel to the drift region.

[0043] The P-type buried layer 104 forms a PN junction with the N-type epitaxial layer 102, which can adjust the internal electric field distribution of the device during withstand voltage, that is, its main function is to significantly reduce the electric field strength near the corner of the gate trench, thereby increasing the reliability of the device.

[0044] P-type buried layer (P Shielding Region, PSR), mainly used to optimize the electric field distribution, improve the voltage resistance and reliability of the device. The role of PSR: The main role of PSR is to optimize the electric field distribution of the device and reduce the local electric field concentration phenomenon by introducing a P-type doping layer. The optimization of the electric field distribution can increase the breakdown voltage of the device and extend the service life of the device; PSR can effectively disperse the electric field and reduce the maximum electric field strength, thereby improving the voltage resistance of the device. In high-voltage devices, PSR can significantly increase the breakdown voltage of the device, enabling it to withstand higher reverse voltages; PSR can improve the reverse characteristics of the device and reduce leakage current. By reducing the electric field concentration phenomenon, the leakage current under reverse bias is reduced; PSR can reduce the electric field concentration in the local area and improve the mechanical strength and reliability of the device. In high-voltage devices, PSR can reduce the stress concentration in the local area and improve the voltage resistance of the device.

[0045] The N-type current spreading layer 103 can reduce the JFET (Junction Field-Effect Transistor Effect) effect. The JFET effect refers to the phenomenon that the conductive properties of the device change due to the electric field of the PN junction in a semiconductor device. The JFET effect usually occurs in devices such as MOSFET and IGBT. Especially in high-voltage devices, the conductive properties of the device are affected by the PN junction electric field due to the uneven distribution of the electric field in the drift region. Principle of the JFET effect: The essence of the JFET effect is the influence of the electric field of the PN junction on the conductive properties of the device. Specifically, when there is a PN junction in the drift region of the device, the electric field of the PN junction will change the conductive properties of the drift region, resulting in an increase in the on-resistance of the device, affecting the efficiency and performance of the device. In high-voltage devices, the drift region is usually composed of lightly doped N-type or P-type materials with high resistivity. When the device operates under high voltage conditions, the electric field of the PN junction will act on the drift region, causing the conductivity of the drift region to change. Due to the electric field of the PN junction, the conductivity of the drift region is limited, resulting in an increase in the on-resistance of the device. The increase in on-resistance will lead to an increase in the conduction loss of the device, affecting the efficiency of the device. The electric field distribution is usually uneven, and the electric field intensity in local areas is high. Local high electric field areas will cause the JFET effect to be more significant, further increasing the on-resistance of the device.

[0046] Reference Figure 2 , showing a schematic structural diagram of a JFET region of a MOSFET device according to an embodiment of the present invention, Figure 2 by Figure 1 The left side is the mirror image of the symmetry axis. The JFET region is composed of two P-type doping layers and one N-type doping layer. The JFET region is composed of a P-type buried layer on the left, an N-type current spreading layer, and a P-type buried layer on the right. The resistance of the JFET region is the JFET resistance. The size of the JFET resistance is related to the length, doping, and width of the JFET region. The N-type current spreading layer 103 can reduce the JFET effect.

[0047] The first N+ region 105 is disposed in a groove formed on the surface of the first P-type buried layer 104 .

[0048] The first N+ region 105 provides electrons when the MOSFET is reversely conducted, that is, the drain is connected to a low level and the source is connected to a high level.

[0049] The N+ region is formed by doping with high concentrations of donor impurities (such as phosphorus, nitrogen, etc.) and has a low resistivity and a high free electron concentration. The N+ region is an N-type region formed by high concentration doping (such as phosphorus, nitrogen, etc.), and the doping concentration is much higher than that of the ordinary N-type region. The high doping concentration makes the conductivity of the N+ region very high, which is suitable for conductive channels or terminal structures; due to the high doping concentration, the resistivity of the N+ region is low, which can effectively reduce resistance losses. The low resistivity characteristics make the N+ region suitable for ohmic contacts or conductive channels; the N+ region has a high free electron concentration, and electrons are the majority carriers. The high free electron concentration makes the N+ region have good conductivity.

[0050] A trench is formed above the N-type current spreading layer 103 and the first P-type buried layer 104 .

[0051] The source polysilicon region 106, the gate polysilicon region 107 and the oxide layer 108 are arranged in the groove, and the oxide layer 108 covers the surface of the source polysilicon region 106 and the gate polysilicon region 107; the source polysilicon region 106 is connected to the first P-type buried layer 104, the first N+ region 105 and the N-type current spreading layer 103 through the oxide layer 108; the gate polysilicon region 107 is connected to the N-type current spreading layer 103 through the oxide layer 108; the gate polysilicon region 107 is connected to the source polysilicon region 106 through the oxide layer 108.

[0052] The source polysilicon region 106 is made of polysilicon material and is connected to the source metal in the layout design.

[0053] The gate polysilicon region 107 is made of polysilicon material and is connected to the gate metal in the layout design.

[0054] The oxide layer 108 serves as isolation and insulation.

[0055] The P-type base region 109 is disposed above the N-type current spreading layer 103 , and the P-type base region 109 is connected to the side surface of the gate polysilicon region 107 through the oxide layer 108 .

[0056] P-type base region (P-Body) 109, where the channel is formed, is formed by P-type doping, has a higher hole concentration and a lower electron concentration, and the P-type base region 109 is used to construct the base region of the device and form a PN junction, thereby controlling the on and off of the device. P-Body is the base region of the device, used to construct a PN junction, control the on and off of the device, and the P-Body forms a PN junction with the N-type source region to control the formation and disappearance of the conductive channel; the formation and disappearance of the conductive channel is controlled by the gate voltage, thereby controlling the flow of current. The gate voltage acts on the P-type base region through the gate oxide layer to form a conductive channel, thereby controlling the flow of current; the P-Body forms a PN junction with the N-type source region, which is used to control the on and off of the device, and the on and off of the PN junction is controlled by the gate voltage.

[0057] The P+ region 110 and the second N+ region 111 are disposed above the P-type base region 109 . The second N+ region 111 is connected to the side of the gate polysilicon region 107 through the oxide layer 108 . The second N+ region 111 and the P+ region 110 are located in the same layer.

[0058] The P+ region 110 is formed by doping with high concentration of acceptor impurities (such as aluminum), has low resistivity and high hole concentration, and is usually used to construct conductive channels, ohmic contacts or terminal structures of semiconductor devices. The characteristics of the P+ region are as follows: the P+ region is a P-type region formed by high concentration doping (such as aluminum), and the doping concentration is much higher than that of ordinary P-type regions. The high doping concentration makes the conductivity of the P+ region very high, which is suitable for conductive channels or terminal structures; due to the high doping concentration, the resistivity of the P+ region is low, which can effectively reduce resistance losses. The low resistivity characteristic makes the P+ region suitable for ohmic contacts or conductive channels; the P+ region has a high hole concentration, holes are the majority carriers, and the high hole concentration makes the P+ region have good conductivity.

[0059] The second N+ region 111 is formed by doping with high concentration of donor impurities (such as phosphorus, nitrogen, etc.), and has a lower resistivity and a higher free electron concentration. The N+ region is an N-type region formed by high concentration doping (such as phosphorus, nitrogen, etc.), and the doping concentration is much higher than that of the ordinary N-type region. The high doping concentration makes the conductivity of the N+ region very high, which is suitable for use in conductive channels or terminal structures; due to the high doping concentration, the resistivity of the N+ region is low, which can effectively reduce resistance loss, and the low resistivity characteristic makes the N+ region suitable for ohmic contact or conductive channels; the N+ region has a higher free electron concentration, and electrons are the majority carriers. The high free electron concentration makes the N+ region have good conductivity.

[0060] The second N+ region 111 provides electrons when the MOSFET is forward-conducted, that is, the drain is connected to a high level and the source is connected to a low level.

[0061] The source 112 is formed on the surface of the oxide layer 108, the first P-type buried layer 104, the first N+ region 105, the P+ region 110, and the second N+ region 111; the oxide layer 108 corresponding to the source polysilicon region 106 is provided with a contact hole so that the source 112 is in contact with the source polysilicon region 106.

[0062] The MOSFET device of the embodiment of the present invention comprises an N-type substrate; an N-type epitaxial layer, arranged on the other side of the N-type substrate; an N-type current spreading layer and a first P-type buried layer, arranged above the N-type epitaxial layer; the N-type current spreading layer is connected to the first P-type buried layer; a first N+ region, arranged in a groove formed on the surface of the first P-type buried layer; a groove, formed above the N-type current spreading layer and the first P-type buried layer; a source polysilicon region, a gate polysilicon region and an oxide layer, arranged in the groove, the oxide layer covering the surface of the source polysilicon region and the gate polysilicon region; the source polysilicon region is connected to the first P-type buried layer, the first N+ region and the N-type current spreading layer through the oxide layer; the gate ... The gate polysilicon region is connected to the source polysilicon region through the oxide layer; the P-type base region is arranged above the N-type current spreading layer, and the P-type base region is connected to the side of the gate polysilicon region through the oxide layer; the P+ region and the second N+ region are arranged above the P-type base region, and the second N+ region is connected to the side of the gate polysilicon region through the oxide layer, and the second N+ region and the P+ region are located in the same layer; the source electrode is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region; the oxide layer corresponding to the source polysilicon region is provided with a contact hole to short-circuit the source electrode with the source polysilicon region. In the embodiment of the present invention, a channel diode is formed under the source polysilicon through an N-type current spreading layer and a first P-type buried layer. The channel diode is connected in parallel with the body diode. When the MOSFET device is in a reverse conduction state, the channel diode is turned on before the body diode, thereby avoiding the problem of large body diode freewheeling loss and bipolar degradation when the MOSFET is in a reverse freewheeling working mode.

[0063] In the embodiment of the present invention, the N-type current spreading layer 103 is L-type. The first P-type buried layer 104 is connected to the lateral extension direction of the L-type N-type current spreading layer 103, and the thickness of the first P-type buried layer 104 is the same as the thickness of the L-type N-type current spreading layer 103 in the lateral extension direction.

[0064] In an embodiment of the present invention, the oxide layer extends toward the second N+ region, covering a portion of the surface of the second N+ region.

[0065] In the embodiment of the present invention, the doping concentration of the N-type current spreading layer 103 is greater than that of the N-type epitaxial layer 102 .

[0066] In the embodiment of the present invention, it further includes: a drain 112 disposed on one side of the N+ type substrate 101 .

[0067] Reference Figure 3 , shows a schematic structural diagram of another MOSFET device according to an embodiment of the present invention, wherein the MOSFET device further includes a drain 112 , which is disposed on the other side of the N+ type substrate 101 .

[0068] In an embodiment of the present invention, the barrier height formed by the N-type current spreading layer and the first P-type buried layer is smaller than the barrier height formed by the N-type current spreading layer and the P-type base region and the barrier height formed by the N-type epitaxial layer and the first P-type buried layer.

[0069] Reference Figure 4 , shows a schematic structural diagram of a body diode and a channel diode of a MOSFET device according to an embodiment of the present invention, including a first body diode 11, a second body diode 12, and a channel diode 13.

[0070] The body diode is a parasitic diode integrated in power devices such as MOSFET or IGBT, usually located between the source and drain of the device. The body diode is an inevitable parasitic effect in the device structure, and its characteristics directly affect the reverse recovery performance and switching loss of the device. The role of the body diode: The body diode will generate reverse recovery charge (Qrr) and reverse recovery time (trr) during the reverse recovery process, resulting in increased switching losses. The reverse recovery characteristics of the body diode directly affect the switching efficiency and reliability of the device; in some applications (such as motor drive, inverter, etc.), the body diode is used to provide a freewheeling path to maintain the continuity of the current. The conduction voltage drop and reverse recovery characteristics of the body diode directly affect the efficiency and reliability of the device; the body diode is a parasitic effect in the MOSFET structure and cannot be completely eliminated, but its characteristics can be improved by optimizing the device structure. The structure of the body diode: The body diode is a PN junction formed by the P-type base region (P-Body) and the N-type source region (N+Source). The P-type base region and the N-type source region form a PN junction to form a body diode.

[0071] The P-type base region 109 is connected to the N-type current spreading layer 103 up and down, and the P-type base region 109 and the N-type current spreading layer 103 form a PN junction to form a first body diode 11 .

[0072] The P-type buried layer 104 is connected to the N-type epitaxial layer 102 in a vertical manner, and the P-type buried layer 104 and the N-type epitaxial layer 102 form a PN junction to form a second body diode 12 .

[0073] The N-type current spreading layer 103 is connected to the P-type buried layer 104 on the left and right sides. The P-type buried layer 104 is located below the trench. The first N+ region 105 is arranged in a groove formed on the surface of the first P-type buried layer 104. A gate polysilicon region 107 is arranged in the trench. Figure 4 A trench diode 13 is formed in the middle dotted line frame.

[0074] The source polysilicon region 106 is connected to the source 112. When the gate polysilicon region 107 is grounded or negatively charged, the drain 113 is connected to a low level, and the source 112 is connected to a high level, that is, when the device is in a reverse conduction state, a channel diode 13 is integrated under the source polysilicon region 106, that is, Figure 4 The specific working principle is as follows: after a certain voltage is applied to the split gate (i.e., the source polysilicon region 106) connected to the source 112, a channel will be formed in the P-type buried layer 104 at the bottom of the split gate; after the channel is connected, the source 112 voltage is driven by a voltage, and the current flows from the drain 113-N-type epitaxial layer 102-N-type current expansion layer 103-P-type buried layer 104 channel-first N+ region 105-Anode (source 112).

[0075] Reference Figure 5 , shows an equivalent circuit diagram of a MOSFET device according to an embodiment of the present invention, and it can be seen that the integrated channel diode 13 of the embodiment of the present invention is connected in parallel with the first body diode 11 and the second body diode 12. There is a hole between the source polysilicon region 106 and the source 112, and the existence of the hole makes the two connected in parallel. Drift That is, the resistance of the N-type epitaxial layer 102, R Sub That is, the resistance of the N-type substrate 101, Figure 5 It is mainly used to explain why the channel diode 13 is turned on before the first body diode 11 and the second body diode 12 when the present invention is reversely conducted. When reversely conducted, the Source (source 112) is at a high level, and the conduction voltage drop of the channel diode 13 is lower than that of the first body diode 11 and the second body diode 12. Therefore, when the voltage applied to the Source (source 112) is greater than the channel diode 13 and less than the first body diode 11 and the second body diode 12, the entire SiC MOS is in a reverse conduction state.

[0076] Reference Figure 6 , shows a partial structure of a MOSFET device according to an embodiment of the present invention and a distribution diagram of the conduction band energy band at the cut-off point. It can be seen that when the device is in the reverse conduction state, when the electrons in the N-type current spreading layer 103 want to pass through the first P-type buried layer 104 and flow through the source 112, they need to cross the barrier height of a diode composed of the N-type current spreading layer 103 and the first P-type buried layer 104, that is, Figure 6In the interface between the first P-type buried layer 104 and the oxide layer 108, since the surface energy band is bent downward, the electrons only need to overcome a lower potential barrier to form a conductive channel and enter the source region, that is, Figure 6 A-A' in it. And at this time, the surface of the first P-type buried layer 104 is in a depletion state, and the hole density is very low, so an electronic current is formed, which is unipolar conduction. Therefore, the channel diode 13 will be turned on before the first body diode 11 and the second body diode 12. The second body diode 12 is a diode composed of the first P-type buried layer 104 and the N-type epitaxial layer 102. Since the doping of the N-type epitaxial layer 102 is lower than that of the N-type current expansion layer 103, the barrier height of the second body diode 12 is higher than the barrier height of the first body diode 11 composed of the N-type current expansion layer 103 and the first P-type buried layer 104. In addition, the conduction of the first body diode 11 and the second body diode 12 are both bipolar conduction. Due to the presence of stacking faults in the silicon carbide epitaxial wafer, electrons and holes recombine in the drift region, release energy and activate stacking faults, which will reduce the conduction ability and reliability of the device.

[0077] The depletion state means that the surface energy band bends downward, and electrons will accumulate at the place where the bottom of the conduction band bends downward, while holes will move away from that place; when the Source (source 112) increases the level, the downward bending degree of the surface energy band further increases, and more electrons will accumulate at the bending place.

[0078] Bipolar conduction refers to the conduction phenomenon in semiconductor devices where the injection and accumulation of minority carriers (holes or electrons) causes the device to conduct both electrons and holes in the on state. Bipolar conduction usually occurs in bipolar devices (such as IGBTs) and minority carrier devices (such as the body diode of MOSFETs), and its characteristics directly affect the conduction loss, switching speed, and reliability of the device. The effect of bipolar conduction: Bipolar conduction will increase the on-resistance of the device, thereby increasing the conduction loss, causing the switching speed of the device to decrease, affecting the dynamic performance of the device, and causing minority carriers (holes or electrons) to accumulate in the device, affecting the reliability of the device.

[0079] Stacking faults are a type of defect in the silicon carbide crystal structure, usually caused by irregular arrangement of atomic layers during crystal growth. Stacking faults introduce additional energy levels, affecting the recombination and migration of carriers. During bipolar conduction, electrons and holes recombine in the drift region, releasing energy (such as photons or thermal energy). The energy released during the recombination process may activate stacking faults, leading to the expansion and accumulation of defects. The activation of stacking faults will lead to further destruction of the crystal structure and increase the defect density of the material. The increase in defect density will reduce the conduction capability of the device and may cause device failure. The activation of stacking faults will increase the resistance of the drift region, thereby reducing the conduction capability of the device. The decrease in conduction capability will increase the conduction loss of the device and affect the efficiency of the device. The activation of stacking faults will increase the defect density of the device, resulting in a decrease in the reliability of the device. The increase in defect density may cause early failure of the device and affect the service life of the device.

[0080] For the second body diode 12, when the electrons in the N-type current spreading layer 103 want to flow through the P-type base region 109 and through the source 112, the potential barrier height that needs to be crossed is also higher than the potential barrier height at the interface (A-A') between the first P-type buried layer 104 and the source trench oxide layer 108. Therefore, the channel diode 13 will also be turned on before the second body diode 12.

[0081] In addition, when the gate Gate is grounded or negative voltage, the drain Drain is connected to a high level, and the source Source is grounded, that is, when the device is in a forward blocking state, the first P-type buried layer 104 connected to the source 112 will cause most of the drain's electric field lines to be cut off at this point, thereby reducing the electric field strength at the bottom of the gate trench and improving device reliability.

[0082] Forward blocking state: When the device is in the forward blocking state, a positive voltage is applied to the drain and the source is grounded. At this time, the PN junction of the device is in a reverse bias state, and the electric field is mainly concentrated in the drift region. In the forward blocking state, the electric field lines extend from the drain to the source and are concentrated at the bottom of the gate trench. The electric field strength at the bottom of the gate trench is high, which may cause local breakdown and affect the reliability of the device. The first P-type buried layer 104 is located near the bottom of the gate trench. The first P-type buried layer 104 is connected to the source 114 to form a low impedance path, attracting the electric field lines so that they are cut off at the first P-type buried layer 104. Due to the existence of the first P-type buried layer 104, the electric field lines are shielded at the first P-type buried layer 104, reducing the electric field strength at the bottom of the gate trench. The electric field strength at the bottom of the gate trench is reduced, reducing the risk of local breakdown, improving the voltage resistance of the device, and extending the service life of the device.

[0083] The split-gate SiC MOSFET structure with integrated trench diode in the embodiment of the present invention has the advantage that it integrates a trench diode with a lower turn-on voltage than the SiC MOSFET body diode, eliminating the bipolar degradation caused by the SiC MOSFET body diode during reverse conduction. In addition, the trench diode is integrated under the trench, so one of its components, the P-type buried layer, can adjust its internal electric field distribution when the device is reverse withstand voltage, further optimizing the reliability of the device.

[0084] In the embodiment of the present invention, the base materials of the N-type substrate 101 and the N-type epitaxial layer 102 are silicon carbide.

[0085] In the embodiment of the present invention, the N-type substrate 101 is an N+ type substrate, the N-type epitaxial layer 102 is an N− type epitaxial layer, and the doping concentration of the N-type epitaxial layer 102 is lower than that of the N-type substrate 101 .

[0086] In the embodiment of the present invention, the drain electrode 113 is a back metal layer, and the source electrode 112 is a front metal layer.

[0087] In an embodiment of the present invention, the device further includes:

[0088] The second P-type buried layer 114 is arranged above the N-type substrate 101, the second P-type buried layer 114 is connected to the N-type current spreading layer 103, the first P-type buried layer 104 and the second P-type buried layer 114 are respectively located on both sides of the N-type current spreading layer 103; the second P-type buried layer 114 extends to the P+ region 110 and is connected to the second N+ region 110, and the extended part is connected to the P-type base region 109.

[0089] Reference Figure 7 The device further includes a second P-type buried layer 114, which extends to the position of the P+ region 110, occupies the position of the P+ region 110, is connected to the second N+ region 110, and the extended portion is connected to the P-type base region 109. The structure of the double P-type buried layer, when the device is in forward blocking, the double P-type buried layer will attract more electric field lines, the electric field lines are cut off at this point, the electric field strength at the bottom of the gate trench is reduced, and the device reliability is improved.

[0090] The embodiment of the present invention aims at the problem that the body diode of SiC MOSFET has large freewheeling loss and bipolar degradation, and proposes a new structure of SiC MOSFET with improved third quadrant characteristics. The third quadrant characteristic refers to the working state of the semiconductor device in the reverse freewheeling mode. In this mode, the source voltage of the device is higher than the drain voltage, and the current flows from the source to the drain through the body diode of the device. The third quadrant characteristic directly affects the reverse recovery performance, switching loss and reliability of the device. In a DC circuit, the relationship between current and voltage can be expressed by four quadrants. The third quadrant indicates that both the current and voltage are negative, that is, the current flows from the source to the drain and the voltage is negative. In semiconductor devices, the third quadrant characteristic corresponds to the reverse freewheeling mode. When the source voltage of the device is higher than the drain voltage, the current flows from the source to the drain through the body diode of the device. The reverse freewheeling mode usually occurs after the device is turned off. The current in the inductor flows through the body diode to maintain the continuity of the current.

[0091] The new structure of the split-gate SiC MOSFET with integrated trench diode in the embodiment of the present invention has the advantage that it integrates a trench diode with a lower turn-on voltage than the SiC MOSFET body diode, eliminating the bipolar degradation caused by the SiC MOSFET body diode during reverse conduction. In addition, the trench diode is integrated under the trench, so one of its components, the P-type buried layer, can adjust its internal electric field distribution when the device is reverse withstand voltage, further optimizing the reliability of the device.

[0092] In an embodiment of the present invention, a chip is provided, comprising the MOSFET device as described above.

[0093] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0094] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0095] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0096] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0097] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0098] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0099] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0100] The MOSFET device and chip provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A MOSFET device, characterized in that: The device comprises: N-type substrate; An N-type epitaxial layer is provided on one side of the N-type substrate; An N-type current spreading layer and a first P-type buried layer are disposed above the N-type epitaxial layer; the N-type current spreading layer is connected to the first P-type buried layer; A first N+ region is provided in a groove formed on the surface of the first P-type buried layer; A trench formed above the N-type current spreading layer and the first P-type buried layer; A source polysilicon region, a gate polysilicon region and an oxide layer are arranged in the trench, the oxide layer covers the surfaces of the source polysilicon region and the gate polysilicon region; the source polysilicon region is connected to the first P-type buried layer, the first N+ region and the N-type current spreading layer through the oxide layer; the gate polysilicon region is connected to the N-type current spreading layer through the oxide layer; the gate polysilicon region is connected to the source polysilicon region through the oxide layer; A P-type base region, disposed above the N-type current spreading layer, the P-type base region being connected to a side surface of the gate polysilicon region through the oxide layer; A P+ region and a second N+ region are provided above the P-type base region, the second N+ region is connected to the side of the gate polysilicon region through the oxide layer, and the second N+ region and the P+ region are located in the same layer; A source electrode is formed on the surface of the oxide layer, the first P-type buried layer, the first N+ region, the P+ region, and the second N+ region; a contact hole is provided in the oxide layer corresponding to the source polysilicon region so that the source electrode contacts the source polysilicon region.

2. The MOSFET device according to claim 1, characterized in that The N-type current spreading layer is L-type.

3. The MOSFET device according to claim 1, characterized in that: The oxide layer extends toward the second N+ region and covers a portion of a surface of the second N+ region.

4. The MOSFET device according to claim 1, characterized in that: The barrier height formed by the N-type current spreading layer and the first P-type buried layer is smaller than the barrier height formed by the N-type current spreading layer and the P-type base region and the barrier height formed by the N-type epitaxial layer and the first P-type buried layer.

5. The MOSFET device according to claim 1, characterized in that: The base materials of the N-type substrate and the N-type epitaxial layer are silicon carbide.

6. The MOSFET device according to claim 1, characterized in that: Also includes: A second P-type buried layer is arranged above the N-type substrate, the second P-type buried layer is connected to the N-type current spreading layer, the first P-type buried layer and the second P-type buried layer are respectively located on both sides of the N-type current spreading layer; the second P-type buried layer extends to the P+ region and is connected to the second N+ region, and the extended part is connected to the P-type base region.

7. The MOSFET device according to claim 1, characterized in that: Also includes: The drain is arranged on the other side of the N+ type substrate.

8. The MOSFET device according to claim 1, characterized in that: The doping concentration of the N-type current spreading layer is greater than that of the N-type epitaxial layer.

9. The MOSFET device according to claim 1, characterized in that: The N-type substrate is an N+-type substrate, the N-type epitaxial layer is an N-type epitaxial layer, and the doping concentration of the N-type epitaxial layer is lower than that of the N-type substrate.

10. The MOSFET device according to claim 7, characterized in that: The drain is a back metal layer, and the source is a front metal layer.

11. A chip comprising the MOSFET device according to any one of claims 1 to 10.

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