Improved groove super-junction MOSFET and preparation method

Abstract

The invention provides an improved trench super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) which comprises an epitaxial N-type substrate layer, P columns, N columns, an interlayer insulating layer, a body region, a source region, a metal layer, grid polycrystalline silicon, a grid oxide dielectric layer and a dielectric isolation layer, wherein the P columns and the N columns are arranged on the epitaxial N-type substrate layer in a staggered manner; the grid polycrystalline silicon, the grid oxide dielectric layer and the dielectric isolation layer are arranged on the source region; and the P column is a combined P column formed by a P-type layer formed by deep trench injection and P-type epitaxial filling. According to the improved groove super-junction MOSFET provided by the invention, the mixed P column is formed by the bottom formed by injection and the P layer formed on the side wall and the subsequently filled P epitaxial layer, and the P column and the original N-type epitaxial layer form the PN junction, so that the original PN junction is reserved, the advantage that the groove is easy to fill is combined, the product stability is greatly weakened by the factors of process fluctuation, and the product quality is improved. The method is suitable for large-scale production of a production line, and the product cost performance is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved trench super junction MOSFET and a preparation method thereof. Background Art

[0002] At present, there are two main types of SJ MOSFET (super junction MOSFET) process structure designs. One type uses multiple epitaxial growth and multiple photolithography processes to form a P-pillar structure. The specific structure is as follows: Figure 1 As shown, the other type is to use deep trench filling to allow P-type epitaxy to form a P column structure. The specific structure is as follows Figure 2 shown.

[0003] The SJ processed with multi-layer epitaxial structure requires at least seven epitaxial growths, corresponding to seven P-column lithography and seven P-column and N-column injections. The process cycle is quite long and the processing cost is very high. The number of lithography layers required is more than 18 times. General production lines cannot produce in large quantities, and the product has poor cost performance.

[0004] Trench SJ is relatively simple to process, with approximately ten lithography layers and a short processing cycle. It requires only deep trenches to be dug and then filled with P-type epitaxial layers to form P-pillars. The conventional VDMOS process follows, making it the most commonly used SJ structure and process. However, while trench SJ processing has a shorter processing cycle than multi-layer epitaxial SJ, and any production line equipped with deep trench processing, P-type epitaxial filling, and the corresponding CMP process can complete trench SJ processing and manufacturing, it suffers from less stable processes and lower product performance compared to multi-layer epitaxial SJ. This is primarily due to the numerous unstable factors faced by trench SJ, such as the depth and morphology of the deep trenches, the resistivity fluctuations of the P-type epitaxial layers, and the numerous challenges in controlling the deep trench process, such as moisture in the trenches and oxide layer removal. These factors can lead to mismatching between the filled P-type epitaxial layers and the original N-type epitaxial layers, resulting in high product volatility and poor stability. Summary of the Invention

[0005] The primary purpose of this invention is to overcome the aforementioned shortcomings of the prior art and propose a vehicle tracking system and method based on an intelligent road stud array. This patent improves and optimizes the existing SJ trench system by forming a hybrid P-pillar structure with an implanted P-type structure on the trench walls and bottom, followed by a P-type epitaxial filler. This significantly mitigates process fluctuations and improves product stability and reliability.

[0006] The present invention adopts the following technical solutions:

[0007] An improved trench superjunction MOSFET comprises: an epitaxial N-type substrate layer, P columns and N columns arranged alternately on the epitaxial N-type substrate layer, an interlayer insulating layer, a body region, a source region, a metal layer, and a gate polysilicon, a gate oxide dielectric layer, and a dielectric isolation layer arranged on the source region. The P columns are formed by combining a P-type layer formed by deep trench implantation and a P-type epitaxial filling.

[0008] Specifically, the P-type layer formed by the deep trench implantation and the P-type layer formed on the bottom wall of the deep trench have a thickness of 0.5-2 μm;

[0009] Specifically, the P-type layer formed by the deep trench implantation and the P-type layer formed on the sidewall of the deep trench have a thickness of 0.1-0.5 um.

[0010] Specifically, the P-type layer formed by deep trench implantation is a P-type layer formed by deep trench implantation of boron ions.

[0011] Another embodiment of the present invention provides a method for preparing an improved trench super junction MOSFET, comprising:

[0012] S1: epitaxially growing and implanting N-type dopant ions on a silicon substrate to form an N-type substrate, and epitaxially growing an N-type epitaxial layer on the front side of the N-type substrate;

[0013] S2: forming a hard mask on the epitaxial layer, including a thermal oxide layer, a silicon nitride layer, and an LPTEOS layer, with each layer having a thickness between 1000Å and 20000Å;

[0014] S3: Trench lithography, hard mask etching, opening the trench, and then removing the photoresist;

[0015] S4: etching a hard mask to form a trench in a partial area of ​​the N-type epitaxial layer;

[0016] S5: sacrificial oxidation in the groove, with a thickness of 500 to 1000 Å, and then a certain dose of P-type dopant ions is injected to remove the sacrificial oxidation;

[0017] S6: P-type epitaxial growth and filling, using LP growth method, the thickness of P-type epitaxial is 5-15um;

[0018] S7: Chemical mechanical polishing to remove the P epitaxial layer and hard mask layer outside the trench, so that the original epitaxial layer and the filled P epitaxial layer are on the same level.

[0019] Specifically, the P-type doping ions are boron ions;

[0020] Specifically, the dosage of the P-type doping ions is 1 to 9E12.

[0021] Another aspect of an embodiment of the present invention provides a MOSFET device having a super junction structure, wherein the MOSFET device is manufactured according to any one of the above-mentioned methods for preparing an improved trench super junction MOSFET.

[0022] From the above description of the present invention, it can be seen that compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention proposes an improved trench superjunction MOSFET, comprising: an epitaxial N-type substrate layer; P-pillars and N-pillars arranged alternately on the epitaxial N-type substrate layer; an interlayer insulating layer; a body region; a source region; a metal layer; and a gate polysilicon layer, a gate oxide dielectric layer, and a dielectric isolation layer disposed on the source region. The P-pillars are a combination of a P-type layer formed by deep trench implantation and a P-type epitaxial fill layer. The improved trench superjunction MOSFET provided by the present invention forms a hybrid P-pillar with the P-layer formed at the bottom and sidewalls by implantation and the subsequently filled P-epitaxy layer. This P-pillar forms a PN junction with the original N-type epitaxial layer. This preserves the original PN junction while combining the advantages of easy trench filling. The product's stability is significantly less susceptible to process fluctuations, making it suitable for mass production and increased volume, and offering a high cost-effectiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of a SJ MOSFET with a multi-layer epitaxial structure in the prior art;

[0025] Figure 2 Schematic diagram of a SJ MOSFET with deep trench P epitaxial filling in the prior art;

[0026] Figure 3 A schematic diagram of the principle structure of an improved trench superjunction MOSFET provided by an embodiment of the present invention;

[0027] Figure 4 The present invention provides a 650V trench SJ product prepared by the method of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further described below through specific embodiments.

[0029] The improved trench super-junction MOSFET provided by the present invention forms a hybrid P column with the P layer formed at the bottom and sidewalls by injection and the P epitaxial layer filled later. This P column forms a PN junction with the original N-type epitaxial layer. This retains the original PN junction and combines the advantage of easy trench filling. The product stability is greatly reduced by process fluctuations, making it suitable for mass production and increased volume on the production line, and the product has a high cost-effectiveness.

[0030] like Figure 3An improved trench super-junction MOSFET includes: an epitaxial N-type substrate layer, P columns and N columns arranged alternately on the epitaxial N-type substrate layer, an interlayer insulating layer, a body region, a source region, a metal layer, and a gate polysilicon, a gate oxide dielectric layer, and a dielectric isolation layer arranged on the source region. The P column is a combined P column formed by a P-type layer formed by deep trench implantation and a P-type epitaxial filling.

[0031] Specifically, the P-type layer formed by the deep trench implantation and the P-type layer formed on the bottom wall of the deep trench have a thickness of 0.5-2 μm;

[0032] Specifically, the P-type layer formed by the deep trench implantation and the P-type layer formed on the sidewall of the deep trench have a thickness of 0.1-0.5 um.

[0033] Specifically, the P-type layer formed by deep trench implantation is a P-type layer formed by deep trench implantation of boron ions.

[0034] Another embodiment of the present invention provides a method for preparing an improved trench super junction MOSFET, comprising:

[0035] S1: epitaxially growing and implanting N-type dopant ions on a silicon substrate to form an N-type substrate, and epitaxially growing an N-type epitaxial layer on the front side of the N-type substrate, wherein the epitaxial layer has a resistivity of 1.0R to 1.5R and a thickness of 45 to 55 μm;

[0036] S2: forming a hard mask on the epitaxial layer, including a thermal oxide layer, a silicon nitride layer, and an LPTEOS layer, with each layer having a thickness between 1000Å and 20000Å;

[0037] S3: Trench lithography, hard mask etching, opening the trench, and then removing the photoresist;

[0038] S4: etching a hard mask to form a trench in a partial area of ​​the N-type epitaxial layer;

[0039] S5: Sacrificial oxidation in the trench, with a thickness of 500 to 1000A, and then a certain dose of P-type doped ions is injected to remove the sacrificial oxide (SAC-OX); after the deep trench is completed, sacrificial thin oxygen is grown in the trench, and then a certain dose of boron ions is reasonably injected. Since there is a thick hard mask barrier layer outside the trench, only impurities in the trench wall and the bottom of the trench can be injected. Since the trench is relatively straight, most of the boron ions are injected into the bottom of the trench. The amount of trench wall injection is related to the angle of the trench. Through simulation and actual flow verification, it is found that controlling the boron ion injection dose in the trench between 1 and 9E12 can have a good effect, which can greatly reduce the requirements for the resistivity of P epitaxial growth and greatly enhance the process stability. This is mainly because the local P column formed by the injection plays a perfect transition role.

[0040] S6: P-type epitaxial growth filling, using LP growth method, the P-type epitaxial thickness is 5-15um, generally 10um;

[0041] S7: Chemical mechanical polishing to remove the P epitaxial layer and hard mask layer outside the trench, so that the original epitaxial layer and the filled P epitaxial layer are on the same level.

[0042] The following are the usual steps;

[0043] S8: SAC-OX again, remove the SAC-OX layer, and formally grow the oxide layer for operation;

[0044] S9: JFET lithography and implantation, stripping;

[0045] S10: PBDY photolithography and implantation, stripping, followed by 1100°C annealing;

[0046] S11: field oxide growth, active area lithography and etching;

[0047] S12: Gate oxide growth and polycrystalline growth;

[0048] S13: Polycrystalline lithography and etching;

[0049] S14: Source region N+ photolithography and implantation;

[0050] S15: BPSG growth and reflow annealing;

[0051] S16: contact hole lithography and etching;

[0052] S17: front metal growth, metal lithography and etching, alloy annealing;

[0053] S18: Backside thinning and backside metallization;

[0054] S19: CP test and storage.

[0055] Specifically, the P-type doping ions are boron ions;

[0056] Specifically, the dosage of the P-type doping ions is 1 to 9E12.

[0057] Using the method of the present invention, a series of 650V trench SJ products have been successfully developed. The performance has reached the requirements of multi-layer epitaxial SJ, but the cost is much lower than that of multi-layer epitaxial. The product has a high cost performance. The specific product physical SEM cross-section is as follows: Figure 4 As shown, the cross section is very smooth and the P column morphology is in place.

[0058] The present invention proposes an improved trench superjunction MOSFET, comprising: an epitaxial N-type substrate layer; P-pillars and N-pillars arranged alternately on the epitaxial N-type substrate layer; an interlayer insulating layer; a body region; a source region; a metal layer; and a gate polysilicon layer, a gate oxide dielectric layer, and a dielectric isolation layer disposed on the source region. The P-pillars are a combination of a P-type layer formed by deep trench implantation and a P-type epitaxial fill layer. The improved trench superjunction MOSFET provided by the present invention forms a hybrid P-pillar with the P-layer formed at the bottom and sidewalls by implantation and the subsequently filled P-epitaxy layer. This P-pillar forms a PN junction with the original N-type epitaxial layer. This preserves the original PN junction while combining the advantages of easy trench filling. The product's stability is significantly less susceptible to process fluctuations, making it suitable for mass production and increased volume, and offering a high cost-effectiveness.

[0059] The above is only a specific implementation of the present invention, but the design concept of the present invention is not limited to this. Any non-substantial changes to the present invention using this concept shall be deemed as an infringement of the protection scope of the present invention.

Claims

1. An improved trench super junction MOSFET, comprising: An epitaxial N-type substrate layer, P columns and N columns arranged alternately on the epitaxial N-type substrate layer, an interlayer insulating layer, a body region, a source region, a metal layer, and a gate polysilicon, a gate oxide dielectric layer, and a dielectric isolation layer are arranged on the source region, characterized in that the P column is a combined P column formed by a P-type layer formed by deep trench injection and a P-type epitaxial filling.

2. The improved trench super junction MOSFET device according to claim 1, characterized in that: The P-type layer formed by the deep trench injection and the P-type layer formed on the bottom wall of the deep trench have a thickness of 0.5-2 um.

3. The improved trench super junction MOSFET device according to claim 1, characterized in that: The P-type layer formed by the deep trench injection and the P-type layer formed on the sidewall of the deep trench have a thickness of 0.1-0.5 um.

4. The improved trench super junction MOSFET device according to claim 1, characterized in that: The P-type layer formed by deep trench implantation is a P-type layer formed by deep trench implantation of boron ions.

5. A method for preparing an improved trench super junction MOSFET, characterized in that: S1: epitaxially growing and implanting N-type doping ions on a silicon substrate to form an N-type substrate, and epitaxially generating an N-type epitaxial layer on the front side of the N-type substrate; S2: forming a hard mask on the epitaxial layer, including a thermal oxide layer, a silicon nitride layer, and an LPTEOS layer, each layer having a thickness between 1000A and 20000A; S3: Trench lithography, hard mask etching, opening the trench, and then removing the photoresist; S4: etching a hard mask to form a groove in a partial area of ​​the N-type epitaxial layer; S5: sacrificial oxidation in the groove, with a thickness of 500 to 1000A, and then a certain dose of P-type doping ions is injected to remove the sacrificial oxidation; S6: P-type epitaxial growth filling, using LP growth method, the thickness of P-type epitaxial is 5-15um; S7: Chemical mechanical polishing to remove the P epitaxial layer and hard mask layer outside the trench, so that the original epitaxy and the filled P-type epitaxy are on the same level.

6. The method for preparing an improved trench super junction MOSFET according to claim 5, characterized in that: The P-type doping ions are boron ions.

7. The method for preparing an improved trench super junction MOSFET according to claim 6, characterized in that: The dosage of P-type doping ions is 1 to 9E12.

8. A MOSFET device having a super junction structure, characterized in that: The MOSFET device is manufactured according to the method according to any one of claims 5-7.

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