Planar silicon carbide MOSFET device and manufacturing method thereof

Abstract

The invention provides a planar silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The planar silicon carbide MOSFET device structurally comprises an N + substrate, an N-drift region, a P-well region with a buried layer, an N + source region, a P + source region, a current expansion layer, P-type polycrystalline silicon, a gate medium, an insulating medium, N-type polycrystalline silicon, a gate electrode, a source electrode and a drain electrode. A P-type buried layer connected with a source potential and P-type polycrystalline silicon are introduced on the basis of a traditional planar MOSFET, low third quadrant conduction voltage drop is realized through a silicon-silicon carbide heterojunction, and the saturation conduction current of the device is reduced and the short-circuit tolerance time is prolonged through an introduced JFET region. In addition, because the device adopts the split gate and comprises the P-type buried layer, the overlapping area of the gate and the drain is reduced, the Cgd of the device is reduced, and the switching speed of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide MOSFET device which suppresses the opening of a body diode of a silicon carbide device, reduces a third quadrant conduction voltage drop, and improves short-circuit tolerance. Background Art

[0002] As a third-generation semiconductor, compared with traditional silicon (Si) materials, silicon carbide (4H-SiC) materials have about 3 times the bandgap width, 10 times the critical breakdown electric field, 3 times the thermal conductivity, and a higher saturation drift velocity. The above advantages make silicon carbide-based power semiconductor devices show significant advantages in high temperature, high voltage, and high frequency applications.

[0003] In recent years, the market size of high-voltage silicon carbide power devices has increased significantly year by year, and the main market applications include photovoltaics, power supplies, electric / hybrid vehicles, charging piles, wind power, rail transit, and motor drives. Compared with silicon-based IGBT power devices, silicon carbide-based power devices have partially replaced the application scenarios of silicon-based IGBTs due to their higher operating frequency and smaller system volume. Against the backdrop of the continuous reduction in the cost of silicon carbide substrates, silicon carbide-based power devices are expected to replace silicon-based IGBTs in high-frequency and high-integration applications, thereby further promoting the development of power electronics technology.

[0004] However, there are still many problems to be solved in the application of silicon carbide power devices. Due to the high turn-on voltage of silicon carbide diodes, there is higher power consumption in the body diode freewheeling mode of silicon carbide-based MOSFET (metal oxide semiconductor field effect transistor), which reduces the working efficiency of silicon carbide power devices. At present, the main method to improve this problem is to integrate SBD (Schottky barrier diode) in silicon carbide MOSFET to suppress the opening of silicon carbide body diode. However, due to the high leakage of integrated SBD at high temperature, the short-circuit withstand time of the MOSFET is greatly reduced. In addition, since the critical breakdown electric field of silicon carbide material can be compared with the critical breakdown electric field of silicon dioxide (SiO2) dielectric layer, the gate oxide film of silicon carbide field effect device is in a high electric field environment for a long time, resulting in inevitable long-term reliability problems. Summary of the invention

[0005] In order to improve the silicon carbide metal oxide semiconductor field effect transistor in the above-mentioned prior art, the present invention proposes a silicon carbide MOSFET device and a manufacturing method thereof that suppresses the opening of the silicon carbide device body diode, reduces the third quadrant conduction voltage drop, and improves the short-circuit withstand capability. The invention of this structure achieves a low third quadrant conduction voltage drop through an integrated silicon-silicon carbide heterojunction, and reduces the saturation current of the device in the on state and improves the short-circuit withstand time through the introduction of the JFET region. In addition, since the device adopts a split gate and contains a P-type buried layer, the structure reduces the overlapping area of ​​the gate and the drain, and reduces the C gd Improves the switching speed of the device.

[0006] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0007] A planar silicon carbide MOSFET device comprises: an N+ substrate 11, an N-drift region 10 located above the substrate 11, a current spreading layer 6 located above the N-drift region 10, a P-well region 5 with a buried layer located above the N-drift region 10, a P+ source region 3 and an N+ source region 4 located in the P-well region 5 with a buried layer, a gate dielectric 8 located above the P-well region 5 with a buried layer, an N-type polysilicon 2 located above the gate dielectric 8, an insulating dielectric 9 located above and on both sides of the N-type polysilicon 2, a P-type polysilicon 7 located between the insulating dielectric 9 above the current spreading layer 6, a source metal 1 located above the P-polysilicon 7, the insulating dielectric 9, the P+ source region 3 and the N+ source region 4, and the source metal 1 simultaneously forms an ohmic contact with the P-polysilicon 7, the P+ source region 3 and the N+ source region 4, and a drain metal 12 located below the N+ substrate 11, and the drain metal 12 forms an ohmic contact with the N+ substrate 11.

[0008] As a preferred embodiment, the N-type polysilicon 2 is connected to the gate metal through the design on the layout, and is electrically connected to the polysilicon gate through a gate bus surrounding the active area.

[0009] As a preferred method, the P-well region 5 with a buried layer is formed by multiple injections, firstly forming a buried layer by an injection with a higher energy greater than 800keV, narrowing the injection window using a self-aligned process, and then forming an upper P-well region by an injection with a lower energy greater than 300keV and less than 500keV.

[0010] As a preferred embodiment, the width of the P-type polysilicon 7 is greater than the spacing of the P-well region 5 with the buried layer to form a JFET effect.

[0011] As a preferred manner, each doping type in the device can be changed to opposite doping, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time, so as to form a p-channel MOSFET device.

[0012] A second object of the present invention is to provide a method for manufacturing the planar silicon carbide MOSFET device, comprising the following steps:

[0013] Step 1: Clean the epitaxial wafer, and perform epitaxy or N-type ion implantation on the N-type drift region to form a current expansion layer;

[0014] Step 2: ion implantation forms a P-well region, firstly, a buried layer is formed by an implantation with a higher energy of more than 800keV, and then an upper P-well region is formed by an implantation with a lower energy of more than 300keV but less than 500keV after narrowing the implantation window using a self-aligned process;

[0015] Step 3: Ion implantation to form a P+ source region;

[0016] Step 4: N-type ion implantation to form an N+ source region;

[0017] Step 5: Dry oxygen oxidation to form a gate dielectric, followed by annealing in a nitrogen monoxide atmosphere, depositing N-type polysilicon, and etching a stripe pattern or a mesh pattern according to the layout;

[0018] Step 6: depositing an insulating dielectric and etching a window, depositing P-type polysilicon, and etching the P-type polysilicon to retain the polysilicon in the window;

[0019] Step 7: Etching source contact holes, depositing metal, and alloying; etching gate contact holes, depositing metal, and alloying; depositing metal on the back side and alloying.

[0020] The silicon-silicon carbide heterojunction diode is composed of P-type polysilicon 7 and current spreading layer 6, and has the following characteristics: the polysilicon is doped at a low concentration, which ensures low conduction loss, and due to the lower work function difference, its conduction voltage drop is less than 1.7V, which is much smaller than the conduction voltage drop of silicon carbide diode, and can effectively shield the silicon carbide body diode. Secondly, since the conduction principle of the silicon-silicon carbide heterojunction diode is unipolar conduction by electron tunneling, this reduces the reverse recovery of the device and improves the bipolar degradation of the silicon carbide device.

[0021] The JFET region is composed of a P-type polysilicon 7, a buried layer of a P-well region to form a gate, a current expansion layer 6 to form a channel, a source electrode to be the source electrode of a MOSFET, and a drain electrode to be the drain electrode of a MOSFET. In the short-circuit mode, the depletion of the JFET channel region exacerbates the decrease in the short-circuit saturation current. In addition, when the device is short-circuited and the temperature rises, the silicon side of the silicon-silicon carbide heterojunction will enter intrinsic excitation in advance, and due to the high drain voltage, band-bending electrons will accumulate at the silicon / silicon carbide interface, further exacerbating the depletion of the JFET channel region, reducing the saturation current and thus greatly improving the short-circuit tolerance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1is a cross-sectional view of a silicon carbide semiconductor device in an embodiment of the present invention.

[0023] Figure 2 Schematic diagram of the three-quadrant characteristics of a silicon carbide semiconductor device in an embodiment of the present invention.

[0024] Figure 3 Schematic diagram of short-circuit current and peak temperature of a silicon carbide semiconductor device in an embodiment of the present invention.

[0025] Figure 4 1 is a diagram illustrating the process of ion implantation in a current spreading layer of a silicon carbide semiconductor device according to an embodiment of the present invention.

[0026] Figure 5 It is a diagram illustrating the process of ion implantation in a P-type well region of a buried layer structure of a silicon carbide semiconductor device according to an embodiment of the present invention.

[0027] Figure 6 1 is a diagram illustrating the process of ion implantation in the P+ source region of a silicon carbide semiconductor device according to an embodiment of the present invention.

[0028] Figure 7 1 is a diagram illustrating the process of ion implantation in the N+ source region of a silicon carbide semiconductor device according to an embodiment of the present invention.

[0029] Figure 8 It is a diagram for explaining the process of forming gate oxide and gate polysilicon of a silicon carbide semiconductor device in an embodiment of the present invention.

[0030] Fig. 9 It is a diagram illustrating the process of forming the insulating medium and source polysilicon of the silicon carbide semiconductor device in an embodiment of the present invention.

[0031] Fig.10 It is a diagram illustrating the process of making contact with the source, gate, and drain of a silicon carbide semiconductor device in an embodiment of the present invention.

[0032] In the figure, 1-source metal, 2-N-type polysilicon, 3-P+ source region, 4-N+ ​​source region, 5-P-well region with buried layer, 6-current spreading layer, 7-P-type polysilicon, 8-gate dielectric, 9-insulating dielectric, 10-N-drift region, 11-N+ substrate, 12-drain metal. DETAILED DESCRIPTION

[0033] The principles and features of the present invention are described in detail below with reference to the accompanying drawings of the specific embodiments.

[0034] The same reference numerals in the drawings represent the same structure. The silicon carbide MOSFET device provided by the present invention can be an N-channel MOSFET device or a P-channel MOSFET device. The following description is based on the N-channel MOSFET device. The technicians in the relevant field can clearly understand the structure and working principle of the P-channel device based on the disclosure of the N-channel MOSFET device.

[0035] Example:

[0036] This embodiment provides a silicon carbide MOSFET device that suppresses the opening of the silicon carbide device body diode, reduces the third quadrant conduction voltage drop, and improves short-circuit tolerance. The cross-sectional view of the cell structure is as follows: Figure 1 As shown, it includes: an N+ substrate 11, an N-drift region 10 located above the substrate 11, a current spreading layer 6 located above the N-drift region 10, a P-well region 5 with a buried layer located above the N-type drift region 10, a P+ source region 3 and an N+ source region 4 located in the P-well region 5 with a buried layer, a gate dielectric 8 located above the P-well region 5 with a buried layer, an N-type polysilicon 2 located above the gate dielectric 8, an insulating dielectric 9 located above and on both sides of the N-type polysilicon 2, a P-type polysilicon 7 located between the insulating dielectrics 9 above the current spreading layer 6, a source metal 1 located above the P-polysilicon 7, the insulating dielectric 9, the P+ source region 3 and the N+ source region 4, and the source metal 1 simultaneously forms an ohmic contact with the P-polysilicon 7, the P+ source region 3 and the N+ source region 4, and a drain metal 12 located below the N+ substrate 11, and the drain metal 12 forms an ohmic contact with the N+ substrate 11.

[0037] As a preferred embodiment, the N-type polysilicon 2 is connected to the gate metal through the design on the layout, and is electrically connected to the polysilicon gate through a gate bus surrounding the active area.

[0038] As a preferred method, the P-well region 5 with a buried layer is formed by multiple injections, firstly forming a buried layer by an injection with a higher energy greater than 800keV, narrowing the injection window using a self-aligned process, and then forming an upper P-well region by an injection with a lower energy greater than 300keV and less than 500keV.

[0039] As a preferred embodiment, the width of the P-type polysilicon 7 is greater than the spacing of the P-well region 5 with the buried layer to form a JFET effect.

[0040] As a preferred manner, each doping type in the device can be changed to opposite doping, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time, so as to form a p-channel MOSFET device.

[0041] To achieve the above-mentioned purpose of the invention, the present invention also provides a method for manufacturing a silicon carbide MOSFET device that suppresses the opening of the body diode of the silicon carbide device, reduces the conduction voltage drop in the third quadrant, and improves the short-circuit withstand capability, comprising the following steps:

[0042] Step 1: If Figure 4 As shown, the epitaxial wafer is cleaned, and epitaxy or N-type ion implantation is performed on the N-type drift region to form a current spreading layer;

[0043] Step 2: If Figure 5 As shown, ion implantation forms a P-well region, firstly a buried layer is formed by implantation with a higher energy of more than 800keV, and then an upper P-well region is formed by implantation with a lower energy of more than 300keV but less than 500keV after narrowing the implantation window using a self-aligned process;

[0044] Step 3: If Figure 6 As shown, ion implantation forms a P+ source region;

[0045] Step 4: Figure 7 As shown, N-type ions are implanted to form an N+ source region;

[0046] Step 5: Figure 8 As shown, dry oxygen oxidation is performed to form a gate dielectric, followed by annealing in a nitrogen monoxide atmosphere, deposition of N-type polysilicon, and etching of a stripe pattern or a mesh pattern according to the layout;

[0047] Step 6: Fig. 9 As shown, an insulating dielectric is deposited and a window is etched, P-type polysilicon is deposited, and the P-type polysilicon is etched to retain the polysilicon in the window;

[0048] Step 7: Fig.10 As shown, the source contact hole is etched, metal is deposited, and alloying is performed; the gate contact hole is etched, metal is deposited, and alloying is performed; and metal is deposited on the back side and alloying is performed.

[0049] The gate polysilicon of the above device is the gate, the N-type silicon carbide substrate end is the drain, and the P+ source region, N+ source region and one end of the P-polysilicon are the source.

[0050] Taking N-type silicon carbide MOSFET as an example, the working principle of the device of the present invention is explained:

[0051] In order to suppress the opening of the silicon carbide MOSFET body diode and reduce the conduction voltage drop in the third quadrant, the invented silicon carbide MOSFET integrates a silicon-silicon carbide heterojunction diode composed of a P-type polysilicon 7 and a current expansion layer 6. Due to the lower work function difference, its conduction voltage drop is less than 1.7V, which is much smaller than the conduction voltage drop of the silicon carbide diode, and can effectively shield the silicon carbide body diode. Secondly, since the conduction principle of the silicon-silicon carbide heterojunction diode is electron tunneling for unipolar conduction, this reduces the reverse recovery of the device and improves the bipolar degradation of the silicon carbide device.

[0052] In order to achieve the purpose of improving the short-circuit tolerance time of silicon carbide MOSFET, the invented silicon carbide MOSFET introduces a JFET region, with a gate formed by a buried layer of P-type polysilicon 7 and a P-well region, a channel formed by a current expansion layer 6, a source electrode being the source electrode of the MOSFET, and a drain electrode being the drain electrode of the MOSFET. In the short-circuit mode, the depletion of the JFET channel region exacerbates the decrease in the short-circuit saturation current. In addition, when the device is short-circuited and the temperature rises, the silicon side of the silicon-silicon carbide heterojunction will enter intrinsic excitation in advance, and the high drain voltage forms a band-bending electron that accumulates at the silicon / silicon carbide interface, further exacerbating the depletion of the JFET channel region and reducing the saturation current, thereby greatly improving the short-circuit tolerance.

Claims

1. A planar silicon carbide MOSFET device, characterized in that: include: An N+ substrate (11), an N-drift region (10) located above the substrate (11), a current spreading layer (6) located above the N-drift region (10), a P-well region (5) with a buried layer located above the N-type drift region (10), a P+ source region (3) and an N+ source region (4) located in the P-well region (5) with a buried layer, a gate dielectric (8) located above the P-well region (5) with a buried layer, an N-type polysilicon (2) located above the gate dielectric (8), and insulating layers located above and on the left and right sides of the N-type polysilicon (2). The invention relates to a P-type polysilicon (7) located between an insulating medium (9) and an insulating medium (9) above a current spreading layer (6); a source metal (1) located above the P-type polysilicon (7), the insulating medium (9), a P+ source region (3) and an N+ source region (4), wherein the source metal (1) forms an ohmic contact with the P-type polysilicon (7), the P+ source region (3) and the N+ source region (4); and a drain metal (12) located below an N+ substrate (11), wherein the drain metal (12) forms an ohmic contact with the N+ substrate (11).

2. The planar silicon carbide MOSFET device according to claim 1, characterized in that: The N-type polysilicon (2) is connected to the gate metal through the design on the layout, and is electrically connected to the polysilicon gate through a gate bus surrounding the active area.

3. The planar silicon carbide MOSFET device according to claim 1, characterized in that: The P-well region (5) with buried layer is formed by multiple injections, firstly the buried layer is formed by injection with higher energy greater than 800keV, and then the upper P-well region is formed by injection with lower energy greater than 300keV and less than 500keV after narrowing the injection window using a self-alignment process.

4. The trench silicon carbide MOSFET device for suppressing switching oscillation according to claim 1, characterized in that: The width of the P-type polysilicon (7) is greater than the spacing of the P-well region (5) with the buried layer, so as to form a JFET effect.

5. The planar silicon carbide MOSFET device according to claim 1, characterized in that: Each doping type in the device can be changed to the opposite doping accordingly, that is, P-type doping is changed to N-type doping and N-type doping is changed to P-type doping at the same time, to form a p-channel MOSFET device.

6. The method for manufacturing a planar silicon carbide MOSFET device according to any one of claims 1 to 5, characterized in that The following steps are involved: Step 1: Clean the epitaxial wafer, and perform epitaxy or N-type ion implantation on the N-type drift region to form a current expansion layer; Step 2: ion implantation forms a P-well region, firstly, a buried layer is formed by an implantation with a higher energy of more than 800keV, and then an upper P-well region is formed by an implantation with a lower energy of more than 300keV but less than 500keV after narrowing the implantation window using a self-aligned process; Step 3: Ion implantation to form a P+ source region; Step 4: N-type ion implantation to form an N+ source region; Step 5: Dry oxygen oxidation to form a gate dielectric, followed by annealing in a nitrogen monoxide atmosphere, depositing N-type polysilicon, and etching a stripe pattern or a mesh pattern according to the layout; Step 6: depositing an insulating dielectric and etching a window, depositing P-type polysilicon, and etching the P-type polysilicon to retain the polysilicon in the window; Step 7: Etching source contact holes, depositing metal, and alloying; etching gate contact holes, depositing metal, and alloying; depositing metal on the back side and alloying.

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