Planar silicon carbide mosfet device and method of manufacturing the same
By introducing a silicon-silicon carbide heterojunction and a JFET region into silicon carbide MOSFET devices, the problems of high on-state voltage drop and insufficient short-circuit withstand capability of silicon carbide MOSFET devices are solved, achieving the effect of low on-state voltage drop and high short-circuit withstand capability.
CN119922954BActive Publication Date: 2026-06-02UNIV OF ELECTRONICS SCI & TECH OF CHINA
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2025-01-23
- Publication Date
- 2026-06-02
AI Technical Summary
Technical Problem
Silicon carbide MOSFET devices have a high on-state voltage drop in the third quadrant when the body diode is turned on, and insufficient short-circuit withstand capability, resulting in high power consumption and reliability issues.
Method used
It adopts a silicon-silicon carbide heterojunction structure, integrates the JFET region, and reduces the on-state voltage drop and improves short-circuit withstand capability through split gate and P-type buried layer design.
Benefits of technology
It achieves low on-state voltage drop and high short-circuit withstand capability, improving the device's operating efficiency and reliability.
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Smart Images
Figure CN119922954B_ABST
Abstract
The application provides a planar silicon carbide MOSFET device and a manufacturing method thereof, and the device structure comprises an N+ substrate, an N-drift region, a P-well region with a buried layer, an N+ source region, a P+ source region, a current spreading layer, P-type polysilicon, gate medium, insulating medium, N-type polysilicon, a gate, a source and a drain. On the basis of a traditional planar MOSFET, a P-type buried layer connected with the source potential and P-type polysilicon are introduced, a low third quadrant conduction voltage drop is realized through a silicon-silicon carbide heterojunction, and the saturation conduction current of the device is reduced and the short circuit resistance time is improved through the introduced JFET region. In addition, due to the fact that the device adopts split gate and contains a P-type buried layer, the area of the gate and the drain is reduced, the Cgd of the device is improved, and the switching speed of the device is improved.
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