Heterojunction-based air gap transistor with high switching ratio and rectification rate and preparation method of heterojunction-based air gap transistor

Abstract

The invention discloses a heterojunction-based air gap transistor with high switching ratio and rectification rate and a preparation method thereof, and belongs to the technical field of transistors. The heterojunction-based air gap transistor with the high switching ratio and the rectification rate comprises a conductive substrate, an insulating dielectric layer is arranged at the upper end of the conductive substrate, a source electrode is arranged at the upper end of the insulating dielectric layer, a first two-dimensional material layer is arranged at the upper end of the source electrode, and a second two-dimensional material layer is arranged on the first two-dimensional material layer and serves as a drain electrode; the first two-dimensional material layer is made of MoS2, the source electrode is made of platinum, the second two-dimensional material layer is made of graphene, and the MoS2 is in contact with the platinum to form a high Schottky barrier, so that the rectification capability can be improved; and the MoS2 is combined with the graphene, so that a heterojunction with higher carrier mobility can be formed, which is crucial for improving the switching speed of field effect transistors (FETs) and reducing the power consumption.

Description

Technical Field

[0001] The invention belongs to the technical field of transistors, and in particular relates to an air-gap transistor with a high switching ratio and rectification rate based on a heterojunction and a preparation method thereof. Background Art

[0002] In the research of modern transistor technology, two-dimensional materials have shown great application potential with their excellent physical properties such as high carrier mobility and adjustable band gap. However, in the process of transistor manufacturing, some process steps may cause damage to two-dimensional materials. Taking metal sputtering as an example, magnetron sputtering and electron beam evaporation are often used to deposit metal electrodes and other structures on the surface of two-dimensional materials. However, during the metal sputtering process, the impact of high-energy particles will damage extremely thin two-dimensional materials, which will cause direct damage such as lattice structure distortion and chemical bond breaking, thereby destroying the excellent physical properties of two-dimensional materials.

[0003] When two-dimensional materials are damaged by metal sputtering, the pin-piercing effect is a prominent problem. Due to the damage of the two-dimensional material, some irregular conductive channels appear inside it, which will cause abnormal leakage and fluctuation of the current, seriously interfering with the normal operation of the transistor. In addition, the interface state problem is also aggravated by the damage of the intermediate material of the two-dimensional material. The interface state in the transistor refers to a series of electronic states with special energy states that exist at the interface of different materials. When the two-dimensional material is damaged, the interface between it and the adjacent material becomes no longer flat and stable, and newly generated defects and impurities will accumulate at the interface. Reduce the carrier mobility of the transistor, thereby affecting the key performance indicators of the transistor such as switching speed and rectification capability. These defects caused by damage to two-dimensional materials greatly limit the application of transistors in high-performance electronic devices.

[0004] Although lamination technology can avoid the impact of metal sputtering on two-dimensional materials, it is still subject to process limitations. The lamination process usually requires high temperature, high pressure and other conditions, which may affect the performance of two-dimensional materials, such as changing their crystal structure, electrical properties, etc. For example, when preparing graphene-based composite materials, excessively high lamination temperatures may lead to an increase in graphene defects, thereby reducing its electrical properties.

[0005] Similarly, adding a protective layer to the two-dimensional material also has disadvantages. The added protective layer material itself may have defects, such as pores, impurities, etc. These defects may affect its protective effect on the two-dimensional material and may even cause interface reactions between the two-dimensional material and the protective layer, thereby damaging the two-dimensional material.

[0006] Faced with the above situation, there is an urgent need for a simple and effective preparation method that can avoid damage to two-dimensional materials as much as possible. Summary of the invention

[0007] In view of the deficiencies in the prior art, the present invention aims to provide an air-gap transistor with a high switching ratio and rectification rate based on a heterojunction and a preparation method thereof, thereby solving the problems in the prior art.

[0008] The purpose of the present invention can be achieved through the following technical solutions:

[0009] An air-gap transistor based on a heterojunction comprises: a conductive substrate, an insulating dielectric layer is arranged on the upper end of the conductive substrate, a source electrode is arranged on the upper end of the insulating dielectric layer, a first two-dimensional material layer is arranged on the upper end of the source electrode, and a second two-dimensional material layer is arranged on the first two-dimensional material layer as a drain electrode;

[0010] The first two-dimensional material layer is made of MoS2, the source electrode material is platinum, and the second two-dimensional material layer is made of graphene. MoS2 contacts platinum to form a high Schottky barrier.

[0011] Furthermore, the conductive substrate is made of silicon.

[0012] Furthermore, the insulating dielectric layer is made of silicon dioxide and has a thickness of 300 nm;

[0013] Furthermore, the width of the source electrode is 10 um; the thickness of the first two-dimensional material layer is 7.3 nm, and the thickness of the second two-dimensional material layer is 9.5 nm.

[0014] The above-mentioned method for preparing the air-gap transistor based on heterojunction comprises the following steps:

[0015] S1, after cleaning the silicon wafer, put it into a quartz boat, send it into the chamber of a high-temperature furnace, first introduce nitrogen to expel the air, then introduce oxygen and heat it, and perform dry oxygen oxidation and wet oxygen oxidation in sequence to obtain a silicon dioxide layer, i.e., an insulating dielectric layer;

[0016] S2, spin coating a layer of photoresist film on the surface of the insulating dielectric layer, forming an electrode pattern mask through exposure and development, and preparing a Pt electrode on the surface of the insulating dielectric layer by physical vapor deposition as a source electrode;

[0017] S3, using dry transfer method to prepare the first two-dimensional material layer MoS on the source electrode 2 ;

[0018] S4, preparing a second two-dimensional material layer on the first two-dimensional material layer using a dry transfer method.

[0019] Furthermore, in S1, the temperature of dry oxygen oxidation and wet oxygen oxidation is 1050° C.; the oxygen flow rate is 300 sccm.

[0020] Furthermore, in S2, the physical vapor deposition method is: using an electron beam evaporation device to evaporate Pt on the surface of the insulating dielectric layer, and the electron beam evaporation rate is 0.2 nm / s.

[0021] Furthermore, in S3, MoS is prepared by a dry transfer method. 2 The process is:

[0022] Use tape to glue MoS 2 Materials from MoS 2 The blocks were peeled off in layers and then bonded to PDMS;

[0023] Tear off the PDMS from the tape surface to peel off the MoS 2 Material;

[0024] Under a microscope, the MoS 2 The material PDMS is attached to the target position on the source electrode and heated;

[0025] Tear off the PDMS, MoS 2 The material remains at the target location, completing the MoS 2 transfer.

[0026] Furthermore, the heating temperature of the heat treatment is 130° C. and the heating time is 10 min.

[0027] A computer comprises the above-mentioned heterojunction-based air-gap transistor.

[0028] Beneficial effects of the present invention:

[0029] 1. The present invention selects graphene as the top electrode. Compared with the metal electrode contact with MoS2, the contact avoids damage to the extremely thin two-dimensional material, and avoids the occurrence of adverse reactions such as interface state destruction and pinning effect. In addition, combining MoS2 with graphene can form a heterojunction with higher carrier mobility, which is crucial to improving the switching speed of field effect transistors (FETs) and reducing power consumption.

[0030] 2. The present invention selects Pt as the bottom metal electrode, which can contact with MoS2 to form a higher Schottky barrier, which is significantly helpful for improving the rectification capability of the Schottky barrier transistor.

[0031] 3. The structure selected by the present invention is an air-gap transistor structure, which has the advantage of significantly improving the contact barrier on the air-gap side, thereby improving the electrical performance of the device, and combining with a high work function metal contact to improve the rectification ratio of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 It is a schematic diagram of the overall effective structure of the air-gap transistor of the present invention;

[0034] Figure 2 It is a schematic diagram of the physical structure of the present invention;

[0035] Figure 3 It is a schematic diagram of the preparation process of the air-gap transistor of the present invention;

[0036] Figure 4 is a physical diagram of the air-gap transistor of the present invention;

[0037] Figure 5 is a rectification characteristic diagram of an air-gap transistor of the present invention;

[0038] Figure 6 1 is a diagram showing the switching characteristics of the air-gap transistor of the present invention. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Example 1

[0041] like Figure 1 As shown, an air-gap transistor with a high switching ratio rectification rate based on a heterojunction includes: a conductive substrate, an insulating dielectric layer is arranged on the upper end of the conductive substrate, a source electrode is arranged on the upper end of the insulating dielectric layer, a first two-dimensional material layer is arranged on the upper end of the source electrode, and a second two-dimensional material layer is arranged on the first two-dimensional material layer as a drain electrode;

[0042] like Figure 2 As shown, in this embodiment, the conductive substrate is made of silicon; the insulating dielectric layer is made of silicon dioxide with a thickness of 300nm; the source electrode is made of platinum with a width of 10um; the first two-dimensional material layer is made of MoS2 with a thickness of 7.3nm, which can form a high Schottky barrier with the source electrode (platinum); the second two-dimensional material layer is made of graphene (Gr) with a thickness of 9.5nm.

[0043] Example 2

[0044] In this embodiment, the preparation method of the air-gap transistor in Embodiment 1 is introduced. Figure 3 As shown, the following steps are included:

[0045] S1, preparing an insulating dielectric layer on the upper end of a conductive substrate (silicon);

[0046] First, the silicon wafer was placed in glassware containing acetone and ethanol in turn, and ultrasonic cleaning was performed for 15 minutes each to remove oil and organic matter on the surface of the silicon wafer. The ultrasonic frequency was 40kHz and the power was 100W. Then the cleaned silicon wafer was placed in a quartz boat, and then the quartz boat was pushed into the constant temperature zone of the high-temperature furnace. The air inlet and outlet of the high-temperature furnace were closed, and nitrogen was first introduced at a flow rate of 500sccm (standard cubic centimeter per minute) for 15 minutes to remove the air in the reaction chamber. Then the nitrogen was closed, and oxygen was introduced at a flow rate of 300sccm to start the dry oxygen oxidation process. After the dry oxygen oxidation was carried out for 1 hour, the wet oxygen oxidation process was started. Water vapor was generated by deionized water heated to 95°C, and the water vapor was mixed with oxygen and introduced into the reaction chamber. The oxygen flow rate was maintained at 300sccm, and the water vapor flow rate was controlled at 100sccm by adjusting the temperature and pressure of the water vapor generator. The high-temperature furnace was heated from room temperature to 1050°C at a rate of 10°C / minute. At a temperature of 1050°C, dry oxygen oxidation and wet oxygen oxidation were performed for a total of 2 hours and 15 minutes, of which dry oxygen oxidation was performed for 1 hour and wet oxygen oxidation was performed for 1 hour and 15 minutes. After such an oxidation process, a silicon dioxide layer about 300nm thick can be grown on the surface of the silicon wafer.

[0047] S2, preparing a source electrode (Pt) on the insulating dielectric layer;

[0048] Take an appropriate amount of positive photoresist and drop it on the center of the sample where the insulating dielectric layer has been prepared to ensure that the photoresist can evenly cover the surface of the insulating dielectric layer.

[0049] Place the sample on the chuck of the spin coater, turn on the spin coater, set the spin coating speed to 4000 rpm, and the spin coating time to 60 seconds. During the spin coating process, the photoresist is evenly spread on the insulating dielectric layer under the action of centrifugal force to form a photoresist film with uniform thickness. Place the sample with the photoresist spun into the photolithography machine and perform alignment operations according to the pre-designed electrode pattern mask. Turn on the light source of the photolithography machine and expose the photoresist according to the set exposure dose and time. The exposure dose is 200mJ / cm 2 The exposure time is 10 seconds, so that the photoresist undergoes a photochemical reaction in the electrode pattern area, changing its solubility. The exposed sample is taken out from the photolithography machine and quickly transferred to the developing equipment.

[0050] Set the flow rate of tetramethylammonium hydroxide developer to 5 ml / s and the development time to 15 seconds. Spray the developer evenly on the sample surface. The photoresist in the unexposed area is gradually dissolved and washed away under the action of the developer, while the photoresist in the exposed area is retained, thereby forming an electrode pattern mask on the insulating dielectric layer. After the development is completed, rinse the sample surface with deionized water to remove the residual developer. The rinsing time is 30 seconds and the deionized water flow rate is 100 ml / s. Place the sample with the electrode pattern mask in the vacuum chamber of the electron beam evaporation machine and evacuate it to a vacuum degree of less than 5×10 -4 Pa.

[0051] Place a Pt metal source material with a purity of 99.99% at the evaporation source position, and adjust the power and scanning range of the electron beam so that the Pt metal can evaporate evenly. Set the electron beam evaporation rate to 0.2nm / s, and start evaporating Pt with a thickness of 50nm. During the evaporation process, the thickness of the Pt film is monitored in real time by a film thickness monitoring device to ensure that the evaporation thickness is accurately controlled at 50nm with an error within the range of ±1nm. After the evaporation is completed, remove the sample from the evaporator and place it in a glass container filled with acetone. The immersion time is 10 minutes, during which the glass container can be gently shaken so that the acetone can fully contact the sample surface, dissolve and remove the photoresist and the metal layer outside the electrode area.

[0052] After immersion, take out the sample with tweezers and rinse the sample surface with a large amount of deionized water to remove residual acetone and dissolved impurities. The rinsing time is 2 minutes and the deionized water flow rate is 200 ml / s.

[0053] Finally, the sample surface was dried with nitrogen to obtain a source electrode (Pt) prepared on the insulating dielectric layer.

[0054] S3, preparing the first two-dimensional material layer MoS2 on the source electrode;

[0055] The dry transfer technique is used. First, take a piece of tape of appropriate length and gently stick one end of it on the MoS 2 The surface of the bulk material ensures that the tape is in contact with the MoS 2 Have a good contact area. Slowly and steadily remove the tape from the MoS 2 Tear off the block and use the stickiness of the tape to make MoS 2 The layers are peeled off from the block under the adhesive force of the tape. Then it is laminated with PDMS (polydisiloxane methyl), and the bubbles are squeezed out with tweezers. After standing for a while, the PDMS is carefully peeled off from the surface of the tape, so that a small amount of MoS 2 Single crystal material. Then observe under a microscope and select the MoS on the PDMS to be bonded 2Single crystal, observe and select a suitable position on the oxidized silicon wafer where the platinum electrode has been prepared, and stick PDMS on the oxidized silicon wafer to make the target MoS 2 The single crystal was bonded to the target position of the source electrode on the oxidized silicon wafer and heated at 130°C for 10 minutes. After heating, the PDMS was slowly peeled off from the surface of the oxidized silicon wafer. 2 The material will remain at the target location on the platinum electrode, completing the MoS 2 The transfer process to silicon oxide wafer.

[0056] S4, preparing a second two-dimensional material layer on the first two-dimensional material layer;

[0057] This step also uses dry transfer technology, specifically:

[0058] First, take a piece of tape of appropriate length and gently stick one end of it on the surface of the graphene block material to ensure that the tape has a good contact area with the graphene. Slowly and steadily tear off the tape from the graphene block, and use the stickiness of the tape to make the graphene layer peel off from the block under the action of the adhesive force of the tape. Then fit it with PDMS (polydisiloxane methyl), squeeze out the bubbles with tweezers, let it stand for a while, and then carefully tear off the PDMS from the surface of the tape slowly, so that the PDMS peels off a little graphene single crystal material. Then observe and select the graphene single crystal on the PDMS to be bonded under a microscope, and observe and select the appropriate position on the oxidized silicon wafer where the platinum electrode has been prepared, and stick the PDMS on the oxidized silicon wafer, so that the target graphene single crystal is bonded to the target position of the source electrode on the oxidized silicon wafer and heat treated, the heating temperature is 120℃, and the heating time is 10min. After heating is completed, the PDMS is slowly torn off from the surface of the silicon oxide wafer. At this time, the graphene material will remain at the target position of the silicon oxide wafer, completing the transfer process of graphene to the silicon oxide wafer.

[0059] The transferred second 2D material layer partially contacts the first 2D material layer, and the second 2D material layer needs to be directly attached to other platinum electrodes. When selecting the test path, the bottom platinum electrodes that do not touch each other will be selected for testing. The two platinum electrodes are in contact with different 2D materials.

[0060] The actual picture of the prepared air gap transistor is as follows Figure 4 shown.

[0061] Example 3

[0062] In this embodiment, the rectification ratio and the switching ratio of the air-gap transistor described in Embodiment 1 are experimentally tested;

[0063] 1) The rectification ratio test process is:

[0064] Use the bottom platinum electrode as the source and the top graphene as the drain (the actual test pin is the platinum electrode connected under the graphene), set the voltage scanning range to -2V to 2V, the scanning step to 0.02V, take the absolute value of the current, and then obtain the logarithmic form of the current to more conveniently view its rectification ratio.

[0065] The rectification ratio test results are as follows: Figure 5 As shown, the black line part in the figure is I DS Take the logarithmic form, and the red line is the linear form of the test data. DS When the voltage is less than 0V, the device is in the on state and the maximum current is 3.49×10 -6 A; When the source-drain voltage V DS When it is greater than 0V, the device is in the cut-off state and the maximum current is 2.90×10 -12 A. Finally, the device rectification rate can be calculated to be 1.20×10 6 .

[0066] 2) The switch ratio test process is:

[0067] The bottom platinum electrode is used as the source, the top graphene is used as the drain (the actual test pin is the platinum electrode connected under the graphene), and the silicon metal at the bottom of the silicon wafer is used as the gate. The source-drain voltage V DS Set it to -1.5V, set the gate voltage scanning range to -50V to 50V, set the scanning step to 0.5V, take the absolute value of the current, and then obtain the logarithmic form of the current to more conveniently view its switching ratio.

[0068] The switch ratio test results are as follows: Figure 6 As shown in the figure, the test data is taken in logarithmic form. When V G When it is equal to -50V, the device is in the off state, and the off-state current is 7.41×10 -12 A; and when V G When it is equal to 50V, the device is in the on state, and the on-state current is 5.58×10 -5 A, the final calculated switching ratio of the device is 7.53×10 6 .

[0069] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0070] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. An air-gap transistor based on a heterojunction, characterized in that: include: A conductive substrate, an insulating dielectric layer is disposed on the upper end of the conductive substrate, a source electrode is disposed on the upper end of the insulating dielectric layer, a first two-dimensional material layer is disposed on the upper end of the source electrode, and a second two-dimensional material layer is disposed on the first two-dimensional material layer as a drain electrode; The first two-dimensional material layer is made of MoS2, the source electrode material is platinum, and the second two-dimensional material layer is made of graphene. MoS2 contacts platinum to form a high Schottky barrier.

2. The heterojunction-based air-gap transistor according to claim 1, characterized in that: The conductive substrate is made of silicon.

3. The heterojunction-based air-gap transistor according to claim 2, characterized in that: The insulating dielectric layer is made of silicon dioxide and has a thickness of 300 nm.

4. The heterojunction-based air-gap transistor according to claim 1, characterized in that: The width of the source electrode is 10 um; the thickness of the first two-dimensional material layer is 7.3 nm, and the thickness of the second two-dimensional material layer is 9.5 nm.

5. The method for preparing the heterojunction-based air-gap transistor according to claim 3, characterized in that: The following steps are involved: S1, after cleaning the silicon wafer, put it into a quartz boat, send it into the chamber of a high-temperature furnace, first introduce nitrogen to expel the air, then introduce oxygen and heat it, and perform dry oxygen oxidation and wet oxygen oxidation in sequence to obtain a silicon dioxide layer, i.e., an insulating dielectric layer; S2, spin coating a layer of photoresist film on the surface of the insulating dielectric layer, forming an electrode pattern mask through exposure and development, and preparing a Pt electrode on the surface of the insulating dielectric layer by physical vapor deposition as a source electrode; S3, preparing the first two-dimensional material layer MoS2 on the source electrode using a dry transfer method; S4, preparing a second two-dimensional material layer on the first two-dimensional material layer using a dry transfer method.

6. The method for preparing an air-gap transistor based on a heterojunction according to claim 5, characterized in that: In S1, the temperature of dry oxygen oxidation and wet oxygen oxidation is 1050°C; the oxygen flow rate is 300 sccm.

7. The method for preparing an air-gap transistor based on a heterojunction according to claim 5, characterized in that: In S2, the physical vapor deposition method is: using an electron beam evaporation device to evaporate Pt on the surface of the insulating dielectric layer, and the electron beam evaporation rate is 0.2 nm / s.

8. The method for preparing an air-gap transistor based on a heterojunction according to claim 5, characterized in that: In S3, the process of preparing MoS2 by dry transfer method is as follows: Use tape to peel the MoS2 material off from the MoS2 block in layers, and then bond it to PDMS; Tear off the PDMS from the tape surface to allow the PDMS to peel off the MoS2 material; Under a microscope, PDMS with MoS2 material is attached to the target position on the source electrode and heated; The PDMS is peeled off, and the MoS2 material remains at the target location, completing the transfer of MoS2.

9. The method for preparing an air-gap transistor based on a heterojunction according to claim 8, characterized in that: The heating temperature of the heating treatment is 130° C. and the heating time is 10 min.

10. A computer, characterized in that: The heterojunction-based air-gap transistor comprises the one described in any one of claims 1 to 4.

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