Normally open GaN HEMT integration on monolithic p-GaN integrated circuit

Abstract

Methods, systems, and apparatus are provided for normally open GaN high electron mobility transistor (HEMT) integration on a monolithic p-GaN integrated circuit (IC) platform. In particular, the integrated circuit platform may include both enhanced and depletion mode HEMT power devices in a monolithic integrated p-GaN power IC. An exemplary method may include treating at least one of the plurality of p-GaN gates with an in-situ plasma treatment to deactivate Mg in the treated p-GaN gate and deplete Mg of the p-GaN gate. The depleted p-GaN gate may be a gate of a normally-on HEMT in the IC. At least one of the p-GaN gates that is not exposed to the in-situ plasma pretreatment may be a gate of a normally off HEMT in the IC.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to high electron mobility transistors (HEMTs), including normally-on gallium nitride (GaN) HEMT integration on a monolithic p-GaN integrated circuit. Background Art

[0002] GaN is a normally-on technology. A p-GaN gate is used to implement a normally-off power device. GaN HEMTs are typically depletion mode transistors, which may be referred to as normally-on HEMTs. However, for some applications, an integrated circuit (IC) including an enhancement mode transistor, sometimes referred to as normally-off, is desired for safe operation and circuit simplification. The IC may use p-doped GaN to form a p-GaN gate for a normally-off HEMT (although it is not necessary to have undoped p-GaN, as p-GaN can also be etched), by etching the p-GaN to obtain a normally-on HEMT on the same platform. However, preparing an IC with both a normally-on HEMT and a normally-off HEMT may involve many operations, including the need for p-GaN etching to first define the gate structure. This p-GaN etch may increase the sheet resistance (RsH) of the completed power device.

[0003] The inventors have pointed out a number of improvements in the prior art and processes, which are the subject of the embodiments described herein. Through applied effort, ingenuity and innovation, many of these deficiencies, challenges and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Summary of the invention

[0004] Various embodiments described herein relate to high electron mobility transistors (HEMTs), including normally-on gallium nitride (GaN) HEMTs integrated on a monolithic normally-off p-GaN integrated circuit.

[0005] According to some embodiments of the present disclosure, an example method for manufacturing an integrated circuit platform is provided. The method for manufacturing an integrated circuit platform may include: providing a wafer, the wafer including an AlGaN layer having a first surface and a p-GaN layer on the first of the AlGaN layers; etching the p-GaN layer to form at least a first p-GaN gate and a second p-GaN gate; depositing a first silicon-based dielectric layer on the first p-GaN gate, the second p-GaN gate, and the AlGaN layer; etching the first silicon-based dielectric layer to expose the second p-GaN gate and a first portion of the AlGaN layer; treating the second p-GaN gate and the first portion of the AlGaN layer with an in-situ plasma treatment, wherein the in-situ plasma treatment inactivates magnesium in the second p-GaN gate to form a depleted p-GaN gate; and forming at least a first normally-off HEMT and at least a first normally-on HEMT, wherein the gate of the normally-off HEMT is the first p-GaN gate, and wherein the gate of the normally-on HEMT is the depleted p-GaN gate.

[0006] In some embodiments, forming the first normally-off HEMT includes forming a plurality of aluminum oxide layers; and forming the first normally-on HEMT includes a single aluminum oxide layer.

[0007] In some embodiments, the first silicon-based dielectric layer has a thickness of 70 nm.

[0008] In some embodiments, the in-situ plasma treatment includes diffusing hydrogen into the second p-GaN gate and the AlGaN layer.

[0009] In some embodiments, the in-situ plasma treatment deactivates magnesium in the first portion of the AlGaN layer.

[0010] In some embodiments, forming the first normally-off HEMT further includes depositing metallization layers associated with the first normally-off HEMT gate, the first normally-off HEMT source, and the first normally-off HEMT drain; and forming the first normally-on HEMT further includes depositing metallization layers associated with the first normally-on HEMT gate, the first normally-on HEMT source, and the first normally-on HEMT drain.

[0011] In some embodiments, forming the first normally-off HEMT further includes depositing at least a first metal shielding layer; and forming the first normally-on HEMT further includes depositing at least a second metal shielding layer.

[0012] In some embodiments, the depleted p-GaN gate of the first normally-on HEMT has a flat capacitance trend with increasing voltage.

[0013] In some embodiments, the p-GaN gate of the first normally-off HEMT has a Schottky capacitance trend that increases with voltage.

[0014] In some embodiments, providing the wafer further comprises providing a TiN layer covering the p-GaN layer; and the first p-GaN gate of the first normally-off HEMT is covered by a first portion of the TiN layer; and wherein the depleted p-GaN gate of the first normally-on HEMT is covered by a second TiN layer.

[0015] According to some embodiments of the present disclosure, an example integrated circuit platform is provided. The integrated circuit platform may include a normally-off HEMT and a normally-on HEMT; wherein the normally-off HEMT includes a p-doped GaN gate on an AlGaN layer; wherein the normally-on HEMT includes a depleted p-GaN gate depleted by in-situ plasma treatment on the AlGaN layer.

[0016] In some embodiments, the normally-off HEMT further includes multiple aluminum oxide layers; and the normally-on HEMT further includes a single aluminum oxide layer.

[0017] In some embodiments, the first silicon-based dielectric layer has a thickness of 70 nm.

[0018] In some embodiments, the depleted p-GaN gate includes Mg—H formed by diffusing hydrogen into the second p-GaN gate.

[0019] In some embodiments, the first portion of the AlGaN exposed to the in-situ plasma treatment includes deactivated magnesium.

[0020] In some embodiments, the normally-off HEMT further includes metallization layers associated with the normally-off HEMT gate, the normally-off HEMT source, and the normally-off HEMT drain; and the normally-on HEMT further includes metallization layers associated with the normally-on HEMT gate, the normally-on HEMT source, and the normally-on HEMT drain.

[0021] In some embodiments, the normally-off HEMT further includes at least a first metal shielding layer; and the normally-on HEMT further includes at least a second metal shielding layer.

[0022] In some embodiments, the depleted p-GaN gate of the normally-on HEMT has a flat capacitance trend with increasing voltage.

[0023] In some embodiments, the p-GaN gate of the normally-off HEMT has a Schottky capacitance trend that increases with voltage.

[0024] In some embodiments, the first p-GaN gate is covered by a first TiN layer; and wherein the depleted p-GaN gate is covered by a second TiN layer.

[0025] The above summary is provided only for the purpose of summarizing some example embodiments, to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above embodiments are only examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It will also be understood that in addition to those summarized here, the scope of the present disclosure also covers many potential embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Having thus generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0027] Figure 1 illustrates a first cross-sectional view of a block diagram of a first exemplary power device according to one or more embodiments of the present disclosure;

[0028] Figure 2 illustrates an example flow chart of operations for manufacturing a power device according to one or more embodiments of the present disclosure;

[0029] Figure 3A-Figure 3F illustrates an example block diagram associated with operations for manufacturing a power device according to one or more embodiments of the present disclosure;

[0030] Figure 4 illustrates a first capacitance versus voltage graph associated with an undoped p-GaN gate;

[0031] Figure 5 illustrates a first capacitance versus voltage graph associated with one or more embodiments of the present disclosure; and

[0032] Figure 6A-6B A current versus voltage graph associated with one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0033] Some embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. Indeed, the various embodiments of the present disclosure may be implemented in many different forms and should not be considered limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. The same reference numerals refer to the same elements throughout.

[0034] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and composed substantially of.

[0035] The phrases "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally mean that the specific feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0036] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0037] If the specification states that a component or feature "may", "can", "could", "should", "will", "preferably", "likely", "typically", "optionally", "for example", "often", "might" (or other such language) be included or have a feature, such a specific component or feature is not required to be included or have the feature. Such a component or feature may be optionally included in some embodiments or it may be excluded.

[0038] Overview

[0039] Various embodiments of the present disclosure are directed to integrating a normally-on GaN HEMT in a normally-off p-GaN. Specifically, the present disclosure includes obtaining both enhancement-mode (E-mode) HEMT power devices and depletion-mode (D-mode) HEMT power devices in a monolithically integrated p-GaN power IC.

[0040] For GaN HEMT devices, the undoped GaN device is normally-on because the GaN sets the device to be a normally-on device. To achieve a normally-off device, the GaN layer can be doped with magnesium (Mg) to form a p-GaN layer. The p-doped gate allows for the depletion of electrons to have a normally-off device. Normally-off HEMT power devices require a voltage applied to the gate to transition or switch the HEMT power device to the on state and conduct current.

[0041] The structure for an IC with a GaN HEMT includes a silicon substrate under a GaN buffer, which is under an AlGaN layer. The AlGaN layer can allow conduction between the source and gate of the HEMT.

[0042] This conduction originates from the electron concentration beneath the AlGaN layer. When a voltage is applied to the drain, then there will be conduction between the gate and the drain.

[0043] Co-integration of depletion-mode (D-mode) HEMTs on p-GaN-based GaN-on-silicon integrated circuit (IC) platforms enables the design of integrated circuits with greater functionality and enhanced performance. However, with p-GaN, the entire surface of the AlGaN of the D-mode HEMT is destroyed due to p-GaN etching. In addition, the gate metal for the D-mode HEMT is the same as the gate metal for the E-mode HEMT, thus limiting the tunability of the threshold voltage of the D-mode device.

[0044] An advantage of the present disclosure is that the D-type structure is integrated in a monolithic IC to avoid p-GaN etching that may cause surface damage to the AlGaN layer and also cause unstable voltage threshold (Vth). Embodiments of the present disclosure can allow Vth to be adapted by changing certain operations described herein. Additionally or alternatively, the normally-on power device can be manufactured on a single production line with the normally-off power device, which is different from the traditional method that requires different manufacturing operations and different production lines.

[0045] The power devices of the present disclosure may be used in a wide variety of applications. For example, various embodiments of the present disclosure may be used in DC-DC converter applications.

[0046] Example methods, systems, and devices

[0047] Figure 1 A first cross-sectional view of a block diagram of a first exemplary power device according to one or more embodiments of the present disclosure is illustrated. Figure 1 The example power device illustrated in FIG. 1 is after having completed fabrication operations of an example method, which is further described herein.

[0048] like Figure 1As shown, the power device 100 may include two p-GaN HEMTs. The normally-off p-GaN HEMT 102 is on the left of the figure, and the normally-on depleted p-GaN HEMT 104 is on the right of the figure. The normally-off p-GaN HEMT 102 and the normally-on depleted p-GaN HEMT 104 may be on top of a silicon substrate layer 110, which is located below a GaN layer 112, which is located below an AlGaN layer 114. Above the AlGaN layer is a p-GaN gate 120 and a depleted p-GaN gate 122. The p-GaN gate 120 and the depleted p-GaN gate 122 may initially be portions of a p-GaN layer that is etched to leave these two regions. As further described herein, the depleted p-GaN gate 122 is treated with plasma to form the depleted p-GaN gate 122 from associated portions of the p-GaN layer that remain after etching. The treatment with plasma is optional and can be performed by depleting Mg in this region by diffusing hydrogen into this region during the plasma treatment to deplete the p-GaN. Diffusion of hydrogen can also diffuse into the AlGaN layer 114 near the depleted p-GaN gate 122. The depleted p-GaN gate 122 as part of the depleted p-GaN gate allows for normally-off functionality.

[0049] The normally-off p-GaN HEMT 102 includes a gate, a source, and a drain. The metal contact to the gate of the normally-off p-GaN HEMT 102 is illustrated as metallization layer 150A. The metal contact to the source of the normally-off p-GaN HEMT 102 is illustrated as metallization layer 152A. The metal contact to the drain of the normally-off p-GaN HEMT 102 is illustrated as metallization layer 154A. The normally-off p-GaN HEMT 102 may also include one or more other metal shields 156 (e.g., 156A) that are used to control the electric field generated when the power device is operating.

[0050] The normally-on depleted p-GaN HEMT 104 includes a gate, a source, and a drain. The metal contact to the gate of the normally-on depleted p-GaN HEMT 104 is illustrated as metallization layer 150B. The metal contact to the source of the normally-on depleted p-GaN HEMT 104 is illustrated as metallization layer 152B. The metal contact to the drain of the normally-on depleted p-GaN HEMT 104 is illustrated as metallization layer 154B. The normally-on depleted p-GaN HEMT 104 may also include one or more other metal shields 156 (e.g., 156B) that are used to control the electric field generated when the power device is operating.

[0051] The power device may also include a plurality of aluminum oxide (Al2O3) layers (e.g., 130A, 130B, 130C) and a plurality of silicon-based dielectric (e.g., silicon oxide, silicon nitride, etc.) layers (e.g., 140A, 140B, 140C, 140D, 140E, 142A, 142B, 142C). The aluminum oxide layers and silicon-based dielectric layers may be deposited one layer at a time and etched to allow one or more surfaces to be exposed, thereby allowing more layers to be deposited in one or more layer portions removed by etching.

[0052] Figure 2 An example flow chart of operations for fabricating a power device according to one or more embodiments of the present disclosure is illustrated.

[0053] A wafer having an AlGaN layer covered by a p-GaN layer is provided at operation 200. The wafer may also include a GaN layer 112 beneath the AlGaN 114, and a silicon substrate layer 110 may be beneath the GaN layer 112. The p-GaN layer may be used to form a p-GaN gate 120 and also a region that will become a depleted p-GaN gate 122.

[0054] At operation 202, the p-GaN layer is etched to form a gate. Multiple gates can be etched from the p-GaN layer. In various embodiments, the first gate can be etched as the p-GaN gate 120, and the second gate can be etched as the gate that will become the depleted p-GaN gate 122. The p-GaN layer can be etched in Cl2 / O2. In various embodiments, there can also be a TiN layer above the p-GaN layer (e.g., a self-aligned gate method). The TiN layer can be etched with BCl3. In various embodiments, performing the etching can include wet etching the TiN side recess with SiN HM, removing the photoresist in O2 / N2 plasma, and removing the polymer in EKC265.

[0055] At operation 204, the exposed surfaces are cleaned. This cleaning operation will clean the exposed surfaces of the first and second gates and the AlGaN layer 114. In various embodiments, the cleaning may utilize hot HCl and / or HF.

[0056] At operation 206, a first aluminum oxide layer is deposited. The first aluminum oxide layer 130 may be deposited over the first gate 120 and the second gate 122A and the AlGaN layer 114. In various embodiments, the aluminum oxide layer may be Al2O3 up to a thickness of 5 nm and heated to 300° C. via thermal or plasma treatment. This thickness may vary. Other examples may include 2.5 nm to 7.5 nm.

[0057] At operation 208, a first silicon-based dielectric layer is deposited. In various embodiments, the first silicon-based dielectric layer 140 may be PECVD SiH4-based SiO2 at a thickness of 260 nm.

[0058] A diagram of the wafer after operation 208 is shown in FIG. Figure 3A middle.

[0059] In operation 210, the first silicon-based dielectric layer and the first aluminum oxide layer are etched to expose the second gate contact 122A. The etching of the first silicon-based dielectric layer 140 and the first aluminum oxide layer 130 can remove these layers on the first portion 310 of the wafer to expose the AlGaN layer 114 and the second gate 122A in this first portion 310. This etching can utilize CF4 EP on the AlGaN layer 114, remove photoresist with O2 / N2 plasma, and / or remove polymer in EKC 265.

[0060] At operation 212, an in-situ plasma treatment is performed. The in-situ plasma treatment may be used for the second gate 122A and the exposed first portion 310 of the AlGaN layer 114. The in-situ plasma treatment may utilize NH3 plasma treatment. The in-situ plasma treatment accelerates Mg deactivation by introducing hydrogen (H) formed by forming a Mg-H complex and this deactivates the Mg doped in the exposed p-GaN layer of the second gate 122A to form a depleted p-GaN gate 122, which may reduce the sheet resistance (RsH) of the AlGaN layer 114. The in-situ plasma treatment also deactivates some Mg in the AlGaN layer 114. The deactivation of Mg in p-GaN may enable an intrinsic GaN layer.

[0061] In various embodiments, in-situ plasma processing is performed on the wafer, for example, in a direct plasma chamber with NH3 / N2 flow and with a power range between 150 and 300 W. Additionally or alternatively, a temperature in the range of 300°C may accelerate the deactivation of Mg by the introduction of hydrogen. By modifying the conditions of operation 212 to diffuse additional hydrogen and / or deactivate a greater amount of Mg, then Vth may be further reduced.

[0062] A diagram of the wafer after operation 212 is shown in FIG. Figure 3B middle.

[0063] At operation 214, a second aluminum oxide layer is deposited. The second aluminum oxide layer 132 (Al2O3) is deposited. For the first portion 310 of the wafer, the second aluminum oxide layer 132 will cover the AlGaN layer 114 and the depleted p-GaN gate 122. Outside the first portion 310 of the wafer, the second aluminum oxide layer 132 is deposited on the first silicon-based dielectric layer 140.

[0064] In various embodiments, the second aluminum oxide layer 132 can have a different thickness than the previous aluminum oxide layer 130. This can be a second aluminum oxide layer 132 of a second aluminum oxide layer thickness, while the first aluminum oxide layer 130 has a first aluminum oxide layer thickness. The second aluminum oxide layer thickness can be, for example, 3 nm, 5 nm, 7 nm, etc. Variations in the thickness of the second aluminum oxide layer 132 can be associated with different gate leakage. Although the gate leakage will also depend on other aspects of the power device, including the profile of the p-GaN gate (e.g., 120). In various embodiments, the second aluminum oxide layer 132 can be an ALD Al2O3 deposition.

[0065] At operation 216, a second silicon-based dielectric layer is deposited. The second silicon-based dielectric layer 142 may be deposited. The second silicon-based dielectric layer 142 may be used to seal the depleted p-GaN gate 122. In various embodiments, the second silicon-based dielectric layer may be PECVD SiH4-based SiO2 at a thickness of 70 nm.

[0066] A diagram of the wafer after operation 216 is shown in FIG. Figure 3C middle.

[0067] At operation 218, the silicon-based dielectric layer(s) and the aluminum oxide layer(s) are etched to expose the second gate. The etching may be at a second portion 320 of the wafer, which is etched to remove the second silicon-based dielectric layer 142 and the second aluminum oxide layer 132 to expose the depleted p-GaN gate 122. This etching may utilize CF4 EP on the aluminum oxide layer 132, remove photoresist with O2 / N2 plasma, and / or remove polymer in EKC 265.

[0068] A diagram of the wafer after operation 218 is shown in FIG. Figure 3D middle.

[0069] At operation 220, the silicon-based dielectric layer(s) and the aluminum oxide layer(s) are etched to expose the first gate. The etching may be at a third portion 330 of the wafer, which is etched to remove the first silicon-based dielectric layer 140 and the second silicon-based dielectric layer 142 and the first aluminum oxide layer 130 and the second aluminum oxide layer 132 to expose the p-GaN gate 120. This etching may utilize CF4 EP, photoresist removal with O2 / N2 plasma, polymer removal in EKC 265, and / or pre-metal cleaning in HCl.

[0070] A diagram of the wafer after operation 220 is shown in FIG. Figure 3E middle.

[0071] At operation 222, metallization layers are deposited to form gate contacts. One or more metallization layers may be deposited to form a gate contact 150A for the p-GaN gate 120 and a gate contact 150B for the depleted p-GaN contact 122. This metallization layer deposition may utilize TiN / AlCu / TiN metallization and / or tapered etching. The gate contacts 150A, 150B may be self-aligned.

[0072] A diagram of the wafer after operation 222 is shown in FIG. Figure 3F middle.

[0073] At operation 224, a third silicon-based dielectric layer is deposited. In various embodiments, the third silicon-based dielectric layer 144 may be deposited. In various embodiments, the third silicon-based dielectric layer may be PECVD SiH4-based SiO2.

[0074] At operation 226, an ohmic contact is etched. The etch for the ohmic contact may include etching the silicon-based dielectric layer and / or the aluminum oxide layer to expose the AlGaN layer 114 for making the source contact 152 and the drain contact 154 of the power device. This etch may utilize CF4 EP on AlGaN, BCl3 recess, photoresist removal with O2 / N2 plasma, polymer removal in EKC 265, and / or pre-metal clean with HCl.

[0075] At operation 228, metallization layer(s) for ohmic contacts (and shields) are deposited. This metallization layer may be deposited to form source and drain contacts 152A and 154A for the normally-off p-GaN HEMT 102, and source and drain contacts 152B and 154B for the normally-on depleted p-GaN HEMT 104. In various embodiments, this metallization layer may also include one or more shield metal portions that are deposited. This metallization layer deposition may utilize TiN / AlCu / TiN metallization and / or tapered etching.

[0076] At operation 230, annealing is performed. The annealing may be an ohmic annealing. In various embodiments, the ohmic annealing may be performed at 560°C.

[0077] A diagram of the wafer after operation 230 is shown in FIG. Figure 1 middle.

[0078] In various embodiments, the operations following the in-situ plasma treatment may be referred to as forming the gate, source, and drain of the HEMT, as each of these operations forms one or more structures required for forming the HEMT power device 100 .

[0079] It will be appreciated that the above operations may be repeated, omitted or altered. For example, various embodiments may omit the deposition of one or more aluminum oxide layers.

[0080] Figure 3A-Figure 3F A block diagram associated with operations for manufacturing a power device according to one or more embodiments of the present disclosure is illustrated.

[0081] Figure 3A The wafer is illustrated after operation 208 has been performed.

[0082] Figure 3B The wafer is illustrated after operation 212 is performed.

[0083] Figure 3C The wafer is illustrated after operation 216 is performed.

[0084] Figure 3D The wafer is illustrated after operation 218 has been performed.

[0085] Figure 3E The wafer is illustrated after operation 220 has been performed.

[0086] Figure 3F The wafer is illustrated after operation 222 is performed.

[0087] It will be understood that various embodiments may include sole fabrication of a normally-on depleted p-GaN HEMT power device without one or more other power devices. Various embodiments may include fabrication of multiple power devices on one wafer, such as multiple normally-off p-GaN HEMT power devices and multiple normally-on depleted p-GaN HEMT power devices.

[0088] In various embodiments, the in-situ plasma treatment may be omitted and instead a wafer having a first portion of doped p-GaN (e.g., the portion containing gate 120) and a second portion of undoped GaN (e.g., the portion containing gate 122) may be provided. This may occur via one or more of the following operations: growing an undoped GaN layer, and then performing a selective ion implantation to selectively dope the first portion of this GaN layer with Mg while leaving the second portion of this GaN layer undoped. The undoped portion may then be used to form a normally-on HEMT.

[0089] Figure 4A first capacitance-versus-voltage graph associated with a doped p-GaN gate and an undoped GaN gate is illustrated. As described herein, a doped p-GaN gate can be used to form a normally-off HEMT power device. An undoped GaN gate can be used to conventionally form a normally-on HEMT power device. A first curve 410 is a capacitance-versus-voltage graph of a p-GaN gate, which depicts a Schottky capacitance trend. A second curve 420 is associated with an undoped GaN gate, which depicts a flat capacitance curve.

[0090] In the Schottky capacitance trend, the trend starts with a large rise with applied positive voltage bias, and then decreases as voltage increases. This trend depends on p-GaN activation, which depends on the Mg concentration and the composition of the p-GaN and AlGaN layers. In the undoped GaN gate of the normally-on device, it is normally on at 0 volts. Undoped GaN has a flat capacitance with increasing voltage.

[0091] Figure 5 A first capacitance versus voltage graph associated with one or more embodiments of the present disclosure is illustrated. Figure 5 A first curve 510 is illustrated that is associated with a doped p-GaN gate that can be used to form a normally-off HEMT power device as described herein. A second curve 520 is illustrated that is associated with a depleted p-GaN gate for a normally-on HEMT power device. The second curve 520 depicts a flat capacitance curve.

[0092] As can be seen from comparing curve 420 to curve 520 , the depleted p-GaN gate of the present disclosure can have the same flat capacitance curve as a conventional undoped GaN gate.

[0093] Figure 6A-6B A current versus voltage graph associated with one or more embodiments of the present disclosure is illustrated. Fig. 6A A semi-logarithmic scale is used for the current on the y-axis, while Figure 6B A linear scale is used for current on the y-axis. Curves 610A, 610B are associated with the p-GaN gate. Curves 620A, 620B are associated with the depleted p-GaN gate. In-situ plasma treatment allows the voltage threshold to drop, which is illustrated as a negative shift from 610A to 620A and from 610B to 620B.

[0094] It should be readily appreciated that, in addition to those explicitly described herein, the embodiments of the methods, systems, and devices described herein may also be configured in various additional and alternative ways. In various embodiments, this includes adding or omitting one or more operations. It should also be readily appreciated that the illustrations of the accompanying drawings herein are not drawn to scale, and therefore certain portions of the accompanying drawings may be different from those described.

[0095] in conclusion

[0096] The operations and / or functions of the present disclosure have been described herein, such as in flowcharts. The flowchart blocks support combinations of means for performing the specified operations and / or functions and combinations of operations and / or functions for performing the specified operations and / or functions.

[0097] Although this specification includes many specific embodiments and implementation details, these should not be understood as limitations on any disclosure or the scope of the requested protection, but as a description of the specific features of the specific disclosed embodiments. Certain features described herein in the context of different embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as acting in certain combinations, and even initially requested protection, one or more features from the requested combination may be excluded from the combination in some cases, and the requested combination may involve a variant of a sub-combination or a sub-combination.

[0098] Although operations and / or functions are illustrated in a particular order in the accompanying drawings, this should not be understood as requiring such operations and / or functions to be performed in the particular order shown or to be performed in sequence, or should not be understood as requiring that all illustrated operations be performed to achieve the desired results. In some cases, operations and / or functions in an alternative order may be advantageous. In some cases, the actions listed in the claims may be performed in a different order and still achieve the desired results. Therefore, although specific embodiments of the subject matter have been described, other embodiments are also within the scope of the following claims.

[0099] Although this detailed description has set forth some embodiments of the invention, the appended claims cover other embodiments of the invention according to various modifications and improvements that differ from the described embodiments.

[0100] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claim be interpreted under paragraph 6 of 35 USC §112.

Claims

1. A method for manufacturing an integrated circuit platform, comprising: Providing a wafer, the wafer comprising an AlGaN layer having a first surface and a p-GaN layer on the first surface of the AlGaN layer; etching the p-GaN layer to form at least a first p-GaN gate and a second p-GaN gate; depositing a first silicon-based dielectric layer on the first p-GaN gate, the second p-GaN gate, and the AlGaN layer; Etching the first silicon-based dielectric layer to expose a first portion of the AlGaN layer and the second p-GaN gate; treating the second p-GaN gate and the first portion of the AlGaN layer with an in-situ plasma treatment, wherein the in-situ plasma treatment deactivates magnesium in the second p-GaN gate to form a depleted p-GaN gate; as well as At least a first normally-off HEMT and at least a first normally-on HEMT are formed, wherein the gate of the first normally-off HEMT is the first p-GaN gate, and wherein the gate of the first normally-on HEMT is the depleted p-GaN gate.

2. The method of claim 1 , wherein forming the first normally-off HEMT comprises forming a plurality of aluminum oxide layers; and Wherein the first normally-on HEMT is formed to include a single aluminum oxide layer. The method according to claim 1 , wherein the first silicon-based dielectric layer has a thickness of 70 nm. 4 . The method of claim 1 , wherein the in-situ plasma treatment comprises diffusing hydrogen into the second p-GaN gate and the AlGaN layer. 5 . The method of claim 1 , wherein the in-situ plasma treatment deactivates magnesium in the first portion of the AlGaN layer.

6. The method of claim 1 , wherein forming the first normally-off HEMT further comprises depositing a metallization layer associated with a first normally-off HEMT gate, a first normally-off HEMT source, and a first normally-off HEMT drain; and Wherein forming the first normally-on HEMT further comprises depositing a metallization layer associated with a first normally-on HEMT gate, a first normally-on HEMT source, and a first normally-on HEMT drain.

7. The method of claim 6, wherein forming the first normally-off HEMT further comprises depositing at least a first metal shielding layer; and Wherein forming the first normally-on HEMT further comprises depositing at least a second metal shielding layer.

8. The method of claim 1, wherein the depleted p-GaN gate of the first normally-on HEMT has a flat capacitance trend with increasing voltage.

9. The method of claim 1, wherein the p-GaN gate of the first normally-off HEMT has a Schottky capacitance trend that increases with voltage.

10. The method of claim 1, wherein providing the wafer further comprises providing a TiN layer covering the p-GaN layer; and wherein the first p-GaN gate of the first normally-off HEMT is covered by a first portion of the TiN layer; and wherein the depleted p-GaN gate of the first normally-on HEMT is covered by a second TiN layer.

11. An integrated circuit platform, comprising: Normally-off HEMT and normally-on HEMT; wherein the normally-off HEMT comprises a p-doped GaN gate on an AlGaN layer; as well as The normally-on HEMT includes a depleted p-GaN gate on the AlGaN layer, wherein the depleted p-GaN gate is deactivated by an in-situ plasma treatment.

12. The integrated circuit platform of claim 11, wherein the normally-off HEMT further comprises a plurality of aluminum oxide layers; and The normally-on HEMT further comprises a single aluminum oxide layer. 13 . The integrated circuit platform of claim 11 , further comprising a first silicon-based dielectric layer, wherein the first silicon-based dielectric layer has a thickness of 70 nm.

14. The integrated circuit platform of claim 11, wherein the depleted p-GaN gate comprises Mg-H formed by diffusing hydrogen into the depleted p-GaN gate.

15. The integrated circuit platform of claim 11, further comprising a first portion of the AlGaN layer, wherein the first portion of the AlGaN layer comprises deactivated magnesium from exposure to the in-situ plasma treatment.

16. The integrated circuit platform of claim 11, wherein the normally-off HEMT further comprises a metallization layer associated with a normally-off HEMT gate, a normally-off HEMT source, and a normally-off HEMT drain; and The normally-on HEMT further includes a metallization layer associated with a normally-on HEMT gate, a normally-on HEMT source, and a normally-on HEMT drain.

17. The integrated circuit platform of claim 16, wherein the normally-off HEMT further comprises at least a first metal shield layer; and The normally-on HEMT further comprises at least a second metal shielding layer.

18. The integrated circuit platform of claim 11, wherein the depleted p-GaN gate of the normally-on HEMT has a flat capacitance trend with increasing voltage.

19. The integrated circuit platform of claim 11, wherein the p-doped GaN gate of the normally-off HEMT has a Schottky capacitance trend that increases with voltage.

20. The integrated circuit platform of claim 11, wherein the p-doped GaN gate is covered by a first TiN layer; and wherein the depleted p-GaN gate is covered by a second TiN layer.

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