Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first electrode, a second electrode, an insulating layer, a channel layer, a gate dielectric layer, a source electrode, and a drain electrode. The first electrode is arranged on the substrate. The second electrode is arranged on the first electrode. The insulating layer is arranged between the first electrode and the second electrode. And the channel layer is arranged on the second electrode. The gate dielectric layer is disposed between the channel layer and the second electrode. The source electrode is electrically connected with the first electrode and the channel layer. And the drain electrode is electrically connected with the channel layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and in particular to a semiconductor structure including a capacitor and a thin-film transistor (TFT). Background Art

[0002] With the expansion of application fields and the increase in the content of transmitted information, the technology and form of displays have gradually diversified, and consumers' requirements for displays have also increased. In some displays, thin film transistors and capacitors may be included. Generally speaking, thin film transistors and capacitors are arranged on a substrate and separated from each other, and are electrically connected to each other through a circuit layer. In this way, more layout area is occupied, resulting in the inability to reduce the size of the display. In addition, in some displays, thin film transistors and capacitors are stacked on a substrate, and the thin film transistors and capacitors are electrically connected to each other through a circuit structure. However, this technical means results in the thickness of the display being unable to be effectively reduced. Summary of the invention

[0003] The present invention is directed to a semiconductor structure, wherein the semiconductor structure comprises a capacitor and a thin film transistor stacked on a substrate, and the upper electrode of the capacitor can be used as a gate of the thin film transistor.

[0004] The present invention is directed to a method for manufacturing a semiconductor structure, wherein the semiconductor structure comprises a capacitor and a thin film transistor stacked on a substrate, and the upper electrode of the capacitor can be used as a gate of the thin film transistor.

[0005] The semiconductor structure of the present invention comprises a first electrode, a second electrode, an insulating layer, a channel layer, a gate dielectric layer, a source electrode and a drain electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The channel layer is disposed on the second electrode. The gate dielectric layer is disposed between the channel layer and the second electrode. The source electrode is electrically connected to the first electrode and the channel layer. The drain electrode is electrically connected to the channel layer.

[0006] In an embodiment of the semiconductor structure of the present invention, the second electrode and the insulating layer expose a portion of the first electrode.

[0007] In an embodiment of the semiconductor structure of the present invention, the channel layer and the gate dielectric layer expose a portion of the second electrode.

[0008] In an embodiment of the semiconductor structure of the present invention, a cap layer is further included, covering the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer.

[0009] In an embodiment of the semiconductor structure of the present invention, the material of the capping layer includes silicon nitride (SiN), silicon carbide nitride (SiCN) or silicon oxynitride (SiON).

[0010] In an embodiment of the semiconductor structure of the present invention, the second electrode is electrically connected to a transistor disposed on the substrate.

[0011] In an embodiment of the semiconductor structure of the present invention, a buffer layer is further included, which is disposed between the substrate and the first electrode.

[0012] In an embodiment of the semiconductor structure of the present invention, the material of the buffer layer includes silicon nitride, silicon carbide nitride or silicon oxynitride.

[0013] In an embodiment of the semiconductor structure of the present invention, the source electrode and the drain electrode are disposed on the channel layer.

[0014] In an embodiment of the semiconductor structure of the present invention, the source electrode and the drain electrode include doped regions disposed in the channel layer.

[0015] In one embodiment of the semiconductor structure of the present invention, the source electrode includes a first via connected to the first electrode, a second via connected to the channel layer, and a first circuit layer connecting the first via and the second via, and the drain electrode includes a third via connected to the channel layer and a second circuit layer connected to the third via.

[0016] The method for manufacturing a semiconductor structure of the present invention comprises the following steps: forming a first electrode on a substrate; forming an insulating layer on the first electrode; forming a second electrode on the insulating layer; forming a gate dielectric layer on the second electrode; forming a channel layer on the gate dielectric layer; forming a source electrode and a drain electrode, wherein the source electrode is electrically connected to the first electrode and the channel layer, and the drain electrode is electrically connected to the channel layer.

[0017] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the second electrode and the insulating layer expose a portion of the first electrode.

[0018] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the channel layer and the gate dielectric layer expose a portion of the second electrode.

[0019] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer comprises the following steps: forming a first electrode material layer, an insulating material layer, a second electrode material layer, a gate dielectric material layer and a channel material layer in sequence on the substrate; performing a first patterning process on the first electrode material layer, the insulating material layer, the second electrode material layer, the gate dielectric material layer and the channel material layer; performing a second patterning process on the channel material layer, the gate dielectric material layer, the second electrode material layer and the insulating material layer; and performing a third patterning process on the channel material layer and the gate dielectric material layer.

[0020] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, after forming the channel layer and before forming the source electrode and the drain electrode, it also includes forming a covering layer to cover the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer.

[0021] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, before forming the first electrode, the method further includes forming a buffer layer on the substrate.

[0022] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the source electrode and the drain electrode are formed on the channel layer.

[0023] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the source electrode and the drain electrode include doped regions formed in the channel layer.

[0024] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the source electrode includes a first conductive hole connected to the first electrode, a second conductive hole connected to the channel layer, and a first circuit layer connecting the first conductive hole and the second conductive hole, and the drain electrode includes a third conductive hole connected to the channel layer and a second circuit layer connected to the third conductive hole.

[0025] Based on the above, the semiconductor structure of the present invention includes a capacitor and a thin film transistor stacked on a substrate, and the upper electrode of the capacitor can be used as the gate of the thin film transistor. Therefore, the layout area occupied by the capacitor and the thin film transistor can be effectively reduced, and the total thickness of the stacked capacitor and the thin film transistor can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A to 1E is a cross-sectional schematic diagram of the manufacturing process of the semiconductor structure according to the first embodiment of the present invention;

[0027] Figure 2 is a schematic cross-sectional view of a semiconductor structure according to a second embodiment of the present invention;

[0028] Figure 3 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same components are indicated by the same symbols in the following description.

[0030] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

[0031] When the terms "first", "second", etc. are used to describe components, they are only used to distinguish these components from each other, and do not limit the order or importance of these components. Therefore, in some cases, the first component may also be referred to as the second component, and the second component may also be referred to as the first component, and this does not deviate from the scope of the present invention.

[0032] In addition, directional terms such as "upper", "lower", etc. mentioned herein are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when a component such as a layer or film is placed "on" another component, the component can be placed directly on the other component, or there can be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between the two.

[0033] In addition, the “material with a high dielectric constant” herein may refer to a dielectric material with a dielectric constant greater than 4 in the technical field.

[0034] Figures 1A to 1E 1 is a schematic cross-sectional view of the manufacturing process of the semiconductor structure of the first embodiment of the present invention. In this embodiment, the capacitor and the thin film transistor are stacked on the substrate, and the upper electrode of the capacitor can be used as the gate of the thin film transistor. In this way, the semiconductor structure of the present invention can include stacked capacitors and thin film transistors, and can have a smaller layout area and a smaller thickness. This embodiment will be described in detail below.

[0035] First, please refer to Figure 1A, providing a substrate 100. In the present embodiment, the substrate 100 includes a silicon substrate 100a and an interconnect structure layer 100b located on the silicon substrate 100a. The silicon substrate 100a may be a silicon chip. The interconnect structure layer 100b may include a dielectric layer, a circuit layer located in the dielectric layer, and vias connecting circuit layers of different layers. The detailed architecture and formation method of the interconnect structure layer 100b are well known to those skilled in the art and are not described separately here. In addition, the transistor TR is disposed on the surface of the silicon substrate 100 and is electrically connected to the interconnect structure layer 100b. In the present embodiment, the transistor TR may be a metal oxide semiconductor field effect transistor (MOSFET). Figure 1A In the embodiment, the structure of the interconnection structure layer 100 b and the structure and number of the transistors TR are merely exemplary, and the present invention is not limited thereto.

[0036] Next, please refer to Figure 1B , a buffer layer 102 may be formed on the substrate 100. In the present embodiment, the material of the buffer layer 102 is, for example, silicon nitride, silicon carbide, or silicon oxynitride. Thereafter, a first electrode material layer 104, an insulating material layer 106, a second electrode material layer 108, a gate dielectric material layer 110, and a channel material layer 112 are sequentially formed on the buffer layer 102. In other embodiments, the buffer layer 102 may be omitted depending on actual conditions.

[0037] The first electrode material layer 104 is used to form the lower electrode of the capacitor. In the present embodiment, the first electrode material layer 104 may be a metal layer or a composite layer composed of a metal layer and a metal nitride layer, but the present invention is not limited thereto. For example, the first electrode material layer 104 may be a titanium layer or a composite layer composed of a titanium layer and a titanium nitride layer.

[0038] The second electrode material layer 108 is used to form the upper electrode of the capacitor. The second electrode material layer 108 can be a metal layer or a composite layer composed of a metal layer and a metal nitride layer, but the present invention is not limited thereto. For example, the second electrode material layer 108 is a titanium layer or a composite layer composed of a titanium layer and a titanium nitride layer.

[0039] The insulating material layer 106 is used to form an insulator between the upper electrode and the lower electrode in the capacitor. The material of the insulating material layer 106 can be a dielectric material with a high dielectric constant. For example, the insulating material layer 106 is a composite layer composed of a zirconium oxide (ZrO2) layer, an aluminum oxide (Al2O3) layer and a zirconium oxide layer, but the present invention is not limited thereto.

[0040] The gate dielectric material layer 110 is used to form a gate dielectric layer in a thin film transistor. In the present embodiment, the material of the gate dielectric material layer 110 is, for example, silicon oxide, but the present invention is not limited thereto. The channel material layer 112 is used to form a channel (channel) layer in a thin film transistor. In the present embodiment, the material of the channel material layer 112 may be a metal oxide. For example, the material of the channel material layer 112 is, for example, indium gallium zinc oxide (InGaZnO, IGZO), but the present invention is not limited thereto.

[0041] In addition, in this embodiment, the capacitor and the thin film transistor share a conductive layer to serve as the electrode of the capacitor and the gate of the thin film transistor. In other words, the second electrode material layer 108 is used to form the gate of the thin film transistor in addition to forming the upper electrode of the capacitor.

[0042] Then, please refer to Figure 1C , a first patterning process is performed on the first electrode material layer 104, the insulating material layer 106, the second electrode material layer 108, the gate dielectric material layer 110, and the channel material layer 112 to remove a portion of the first electrode material layer 104, a portion of the insulating material layer 106, a portion of the second electrode material layer 108, a portion of the gate dielectric material layer 110, and a portion of the channel material layer 112 to define a region for forming a capacitor. After defining the region for forming a capacitor, a second patterning process is performed on the channel material layer 112, the gate dielectric material layer 110, the second electrode material layer 108, and the insulating material layer 106 to remove a portion of the channel material layer 112, a portion of the gate dielectric material layer 110, a portion of the second electrode material layer 108, and a portion of the insulating material layer 106.

[0043] In this way, a first electrode E1 formed by the first electrode material layer 104, an insulating layer 106a formed by the insulating material layer 106, a second electrode E2 formed by the second electrode material layer 108, a gate dielectric material layer 110a and a channel material layer 112a can be formed on the substrate 100, and the channel material layer 112a, the gate dielectric material layer 110a, the second electrode E2 and the insulating layer 106a expose a portion of the first electrode E1. In this embodiment, a portion of the first electrode E1 is exposed, but the present invention is not limited thereto. In other embodiments, some insulating material layer 106 may be retained on the above-exposed portion of the first electrode E1. The first electrode E1, the insulating layer 106a and the second electrode E2 may constitute a capacitor C having a metal-insulator-metal (MIM) structure in this embodiment.

[0044] Next, please refer to Figure 1D, the channel material layer 112a and the gate dielectric material layer 110a are subjected to a third patterning process to remove a portion of the channel material layer 112a and a portion of the gate dielectric material layer 110a. In this way, a gate dielectric layer 110b formed by the gate dielectric material layer 110 and a channel layer 112b formed by the channel material layer 112 can be formed on the capacitor C, and the channel layer 112b and the gate dielectric layer 110b expose a portion of the second electrode E2.

[0045] After forming the channel layer 112b and the gate dielectric layer 110b, a capping layer 114 may be formed on the substrate 100 to cover the first electrode E1, the insulating layer 106a, the second electrode E2, the gate dielectric layer 110b, and the channel layer 112b. In the present embodiment, the material of the capping layer 114 is, for example, silicon nitride, silicon carbide, or silicon nitride oxide, but the present invention is not limited thereto. The capping layer 114 may prevent the first electrode E1, the insulating layer 106a, the second electrode E2, the gate dielectric layer 110b, and the channel layer 112b from being damaged in subsequent processes. In other embodiments, the capping layer 114 may be omitted depending on actual conditions.

[0046] Afterwards, please refer to Figure 1E , a dielectric layer 116 is formed on the substrate 100. In the present embodiment, the dielectric layer 116 is formed on the capping layer 114 to cover the first electrode E1, the insulating layer 106a, the second electrode E2, the gate dielectric layer 110b and the channel layer 112b. The dielectric layer 116 serves as an inter-metal dielectric (IMD) in the semiconductor structure of the present embodiment. The material of the dielectric layer 116 is, for example, silicon oxide, but the present invention is not limited thereto. For example, the material of the dielectric layer 116 may be phosphoric silicate glass (PSG) or undoped silicate glass (USG). After the dielectric layer 116 is formed, a planarization process may be performed on the dielectric layer 116 according to actual needs to ensure that the dielectric layer 116 has a flat surface. The planarization process is, for example, a chemical mechanical polishing (CMP) process.

[0047] Then, a first conductive hole V1, a second conductive hole V2, a third conductive hole V3, a fourth conductive hole V4, a fifth conductive hole V5, a first circuit layer 118a, a second circuit layer 118b, and a second circuit layer 118c are formed in the dielectric layer 116. In the present embodiment, the first circuit layer 118a, the second circuit layer 118b, and the second circuit layer 118c are located at the same horizontal height, that is, the first circuit layer 118a, the second circuit layer 118b, and the second circuit layer 118c are the same conductive layer, but the present invention is not limited thereto. In other embodiments, the first circuit layer 118a, the second circuit layer 118b, and the second circuit layer 118c may be located at different horizontal heights.

[0048] The first via V1 is connected to the first circuit layer 118a, and extends downward through the cover layer 114 to connect to the first electrode E1. The second via V2 is connected to the first circuit layer 118a, and extends downward through the cover layer 114 to connect to the channel layer 112b. Therefore, the channel layer 112b and the first electrode E1 can be electrically connected to each other through the first circuit layer 118a, the first via V1, and the second via V2.

[0049] The third via V3 is connected to the second wiring layer 118 b and extends downward through the cover layer 114 to be connected to the channel layer 112 b .

[0050] The fourth via V4 is connected to the third circuit layer 118c, and extends downward through the cover layer 114 and the buffer layer 102 to be connected to the circuit layer in the interconnection structure layer 100b. The fifth via V5 is connected to the third circuit layer 118c, and extends downward through the cover layer 114 to be connected to the second electrode E2. Therefore, the second electrode E2 and the transistor TR can be electrically connected to each other through the third circuit layer 118c, the fourth via V4, the fifth via V5 and the interconnection structure layer 100b.

[0051] In this way, the semiconductor structure 10 of this embodiment is formed.

[0052] In the semiconductor structure 10 of the present embodiment, the first electrode E1, the insulating layer 106a and the second electrode E2 constitute a capacitor C having a metal-insulator-metal structure. In addition, the second electrode E2, the gate dielectric layer 110b, the channel layer 112b, the first circuit layer 118a, the second circuit layer 118b, the first via hole V1, the second via hole V2 and the third via hole V3 constitute a thin film transistor, wherein the second electrode E2 can be used as a gate electrode of the thin film transistor, the first via hole V1, the first circuit layer 118a and the second via hole V2 can be used as a source electrode of the thin film transistor, and the second circuit layer 118b and the third via hole V3 can be used as a drain electrode of the thin film transistor.

[0053] In this embodiment, the thin film transistor and the capacitor C are stacked on the substrate 100, and the thin film transistor and the capacitor C share a conductive layer as their respective gate and upper electrode. Therefore, the semiconductor structure 10 of this embodiment can have a smaller layout area and a smaller thickness.

[0054] In addition, in the semiconductor structure 10 of the present embodiment, the thin film transistor is electrically connected to the capacitor C through the first via hole V1, the first wiring layer 118a and the second via hole V2, and the capacitor C is electrically connected to the transistor TR through the fourth via hole V4, the third wiring layer 118c, the fifth via hole V5 and the interconnection structure layer 100b. Therefore, after applying voltage to the gate and drain of the transistor TR and applying voltage to the source electrode and the drain electrode of the thin film transistor, the thin film transistor can be operated and a capacitance can be generated at the capacitor C.

[0055] In this embodiment, the first via V1, the first wiring layer 118a and the second via V2 serve as the source electrode of the thin film transistor, and the second wiring layer 118b and the third via V3 serve as the drain electrode of the thin film transistor, but the present invention is not limited thereto. In other embodiments, the thin film transistor may have other types of source electrodes and drain electrodes.

[0056] Figure 2 FIG. 2 is a cross-sectional view of a semiconductor structure according to a second embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by identical reference symbols and will not be described again.

[0057] Please refer to Figure 2 In the semiconductor structure 20 of the present embodiment, the source electrode 200S and the drain electrode 200D are formed on the channel layer 112b and are separated from each other. The material of the source electrode 200S and the drain electrode 200D may be metal, but the present invention is not limited thereto.

[0058] In this embodiment, the source electrode 200S may be electrically connected to the capacitor C through the first via V1, the first wiring layer 118a and the second via V2, and the drain electrode 200D may be electrically connected to the external voltage source through the second wiring layer 118b and the third via V3.

[0059] Figure 3 FIG. 3 is a cross-sectional view of a semiconductor structure according to a third embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by identical reference symbols and will not be described again.

[0060] Please refer to Figure 3In the semiconductor structure 30 of the present embodiment, two doped regions separated from each other are formed in the channel layer 112b to serve as a source electrode 300S and a drain electrode 300D respectively. The source electrode 300S and the drain electrode 300D are formed by, for example, performing an ion implantation process on a specific region of the channel layer 112b.

[0061] In this embodiment, the source electrode 300S may be electrically connected to the capacitor C through the first via V1, the first wiring layer 118a and the second via V2, and the drain electrode 300D may be electrically connected to the external voltage source through the second wiring layer 118b and the third via V3.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A first electrode is disposed on the substrate; A second electrode, disposed on the first electrode; an insulating layer, disposed between the first electrode and the second electrode; A channel layer is disposed on the second electrode; a gate dielectric layer, disposed between the channel layer and the second electrode; a source electrode, electrically connected to the first electrode and the channel layer; as well as The drain electrode is electrically connected to the channel layer.

2. The semiconductor structure according to claim 1, characterized in that: The second electrode and the insulating layer expose a portion of the first electrode.

3. The semiconductor structure according to claim 1, characterized in that: The channel layer and the gate dielectric layer expose a portion of the second electrode.

4. The semiconductor structure according to claim 1, characterized in that: It also includes a covering layer, covering the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer.

5. The semiconductor structure according to claim 4, characterized in that: The material of the cover layer includes silicon nitride, silicon carbide nitride or silicon oxynitride.

6. The semiconductor structure according to claim 1, characterized in that The second electrode is electrically connected to a transistor disposed at the substrate.

7. The semiconductor structure according to claim 1, characterized in that: It also includes a buffer layer, which is arranged between the substrate and the first electrode.

8. The semiconductor structure according to claim 7, characterized in that: The material of the buffer layer includes silicon nitride, silicon carbide nitride or silicon oxynitride.

9. The semiconductor structure according to claim 1, characterized in that: The source electrode and the drain electrode are arranged on the channel layer.

10. The semiconductor structure according to claim 1, wherein: The source electrode and the drain electrode include doped regions disposed in the channel layer.

11. The semiconductor structure according to claim 1, characterized in that: The source electrode includes a first conductive hole connected to the first electrode, a second conductive hole connected to the channel layer, and a first circuit layer connecting the first conductive hole and the second conductive hole, and the drain electrode includes a third conductive hole connected to the channel layer and a second circuit layer connected to the third conductive hole.

12. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first electrode on a substrate; forming an insulating layer on the first electrode; forming a second electrode on the insulating layer; forming a gate dielectric layer on the second electrode; forming a channel layer on the gate dielectric layer; as well as A source electrode and a drain electrode are formed, wherein the source electrode is electrically connected to the first electrode and the channel layer, and the drain electrode is electrically connected to the channel layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The second electrode and the insulating layer expose a portion of the first electrode.

14. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The channel layer and the gate dielectric layer expose a portion of the second electrode.

15. The method for manufacturing a semiconductor structure according to claim 12, wherein: The method for forming the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer comprises: Sequentially forming a first electrode material layer, an insulating material layer, a second electrode material layer, a gate dielectric material layer and a channel material layer on the substrate; Performing a first patterning process on the first electrode material layer, the insulating material layer, the second electrode material layer, the gate dielectric material layer and the channel material layer; performing a second patterning process on the channel material layer, the gate dielectric material layer, the second electrode material layer and the insulating material layer; and A third patterning process is performed on the channel material layer and the gate dielectric material layer.

16. The method for manufacturing a semiconductor structure according to claim 12, wherein: After forming the channel layer and before forming the source electrode and the drain electrode, the method further includes forming a covering layer to cover the first electrode, the insulating layer, the second electrode, the gate dielectric layer and the channel layer.

17. The method for manufacturing a semiconductor structure according to claim 12, wherein: Before forming the first electrode, the method further includes forming a buffer layer on the substrate.

18. The method for manufacturing a semiconductor structure according to claim 12, wherein: The source electrode and the drain electrode are formed on the channel layer.

19. The method for manufacturing a semiconductor structure according to claim 12, wherein: The source electrode and the drain electrode include doped regions formed in the channel layer.

20. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The source electrode includes a first conductive hole connected to the first electrode, a second conductive hole connected to the channel layer, and a first circuit layer connecting the first conductive hole and the second conductive hole, and the drain electrode includes a third conductive hole connected to the channel layer and a second circuit layer connected to the third conductive hole.

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