Semiconductor device including dual contact structure on source / drain region

Abstract

There is provided a semiconductor device including: a first source / drain region; and a first contact structure on a first portion of the first source / drain region; and a second contact structure on a second portion of the first source / drain region, wherein at least one of the first contact structure and the second contact structure is configured to connect the first source / drain region to another circuit element or a voltage source for signal routing.

Description

Technical Field

[0001] Apparatuses and methods consistent with the present disclosure relate to three-dimensional stacked (3D stacked) semiconductor devices, also referred to as multi-stacked semiconductor devices, in which a double contact structure is formed on a lower source / drain region. Background Art

[0002] In response to the increasing demand for integrated circuits with high device density and performance, 3D stacked semiconductor devices have been introduced. The 3D stacked semiconductor device may include a first transistor at a first level and a second transistor at a second level above the first level, where each transistor may be a fin field effect transistor (FinFET), a nanosheet transistor, a forksheet transistor, or any other type of transistor.

[0003] FinFET has one or more horizontally arranged vertical fin structures as channel structures, at least three surfaces of the channel structure are surrounded by gate structures, and nanosheet transistors are characterized by one or more nanosheet layers stacked vertically on a substrate as channel structures, and gate structures surrounding all four surfaces of each nanosheet layer. Nanosheet transistors refer to gate all-around (GAA) transistors and multi-bridge channel field effect transistors (MBCFETs). Fork sheet transistors are a combination of two nanosheet transistors with an insulating trunk structure between them. The nanosheet layers of each nanosheet transistor are formed on each side of the insulating trunk structure and pass through a gate structure parallel to the trunk structure.

[0004] In a 3D stacked semiconductor device, the location of a contact structure connecting a source / drain region of a first transistor at a first level to a voltage source or another circuit element may affect power delivery performance or signal routing performance.

[0005] The information disclosed in this background technology section is known to the inventor or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0006] According to an aspect of an example embodiment, a semiconductor device is provided, which may include: a first source / drain region; and a first contact structure on a first portion of the first source / drain region; and a second contact structure on a second portion of the first source / drain region, wherein at least one of the first contact structure and the second contact structure is configured to connect the first source / drain region to another circuit element or voltage source for signal routing.

[0007] According to an aspect of example embodiments, the first contact structure and the second contact structure may be connected to each other through a metal line in a middle (MOL) layer or a back end of line (BEOL) layer.

[0008] According to an aspect of an example embodiment, a semiconductor device is provided, which may include: a first source / drain region for a first transistor; and a second source / drain region for a second transistor, the second source / drain region being vertically disposed above the first source / drain region, wherein in a channel width direction view, the second source / drain region has a width smaller than that of the first source / drain region, the channel width direction intersecting with a direction of current flow in each of the first transistor and the second transistor, and in a channel width direction view, a non-overlapping region in which the second source / drain region does not vertically overlap the first source / drain region is formed at each of the left and right sides of the second source / drain region.

[0009] According to an aspect of the example implementation, the 3D stacked semiconductor device may further include: a first contact structure on the first source / drain region, wherein the first contact structure passes through one of the non-overlapping regions; and a second contact structure on the first source / drain region, wherein the second contact structure passes through another of the non-overlapping regions.

[0010] According to an aspect of an example embodiment, a semiconductor device is provided, which may include: a first source / drain region; and a second source / drain region vertically above the first source / drain region, wherein two or more first contact structures are formed on the first source / drain region, and only one second contact structure is formed on the second source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figures 1A to 1C A 3D stacked semiconductor device is shown in accordance with one or more embodiments, wherein one contact structure is formed on each of source / drain regions at a first level and source / drain regions at a second level.

[0013] FIG. 2A to FIG. 2C A 3D stacked semiconductor device is shown in accordance with one or more embodiments, wherein two contact structures are formed on source / drain regions at a first level and one contact structure is formed on source / drain regions at a second level.

[0014] FIG. 3A to FIG. 3C A 3D stacked semiconductor device according to one or more embodiments is shown, wherein FIG. 2A to FIG. 2COnly one of the two contact structures of the 3D stacked semiconductor device shown in is formed on the source / drain region at a first level, and one contact structure is formed on the source / drain region at a second level.

[0015] FIG. 4A to FIG. 4C A 3D stacked semiconductor device is shown in which two contact structures are formed on source / drain regions at a first level and one contact structure is formed on source / drain regions at a second level according to one or more other embodiments.

[0016] FIG. 5A to FIG. 5C A 3D stacked semiconductor device is shown in which two contact structures are formed on source / drain regions at a first level and one contact structure is formed on source / drain regions at a second level according to one or more other embodiments.

[0017] Figure 6 is a schematic block diagram illustrating an electronic device including a semiconductor device in which two or more contact structures are formed on source / drain regions of the semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0018] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, even if the content described in a specific example or embodiment is not described in an example or embodiment different therefrom, these contents can also be understood as being related to or combined with different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described herein can be of different types and forms, as long as the present disclosure can be applied thereto.

[0019] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on," "over," "up," "below," "below," "under," "connected to," or "coupled to" another element of the semiconductor device, it may be directly on, over, over, under, under, under, connected to, or coupled to the other element, or there may be (multiple) intermediate elements. In contrast, when an element of a semiconductor device is referred to as being "directly on," "over," "up," "below," "below," "under," "directly connected to," or "directly coupled to" another element of the semiconductor device, there are no intermediate elements. Throughout this disclosure, the same reference numerals refer to the same elements.

[0020] For ease of description, spatially relative terms, such as "above", "above", "up", "upper", "below", "below", "below", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc., may be used herein to describe the relationship of one element to another (multiple) elements as shown in the figure. It will be understood that spatially relative terms are intended to cover different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figure. For example, if the semiconductor device in the figure is turned over, the element described as being "below" or "below" another element will be oriented to be "above" the other element. Therefore, the term "below" can cover both the upper and lower orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors are interpreted accordingly. As another example, elements referred to as "left" elements and "right" elements may also be "right" elements and "left" elements when the device or structure including these elements is oriented differently. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, with the necessary description to distinguish the two elements.

[0021] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0022] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this document, when the term "same" is used to compare the size of two or more elements, the term can cover "substantially the same" sizes.

[0023] It will also be understood that even if a certain step or operation of manufacturing a device or structure is described later than another step or operation, the step or operation may be performed earlier than the other step or operation unless the other step or operation is described as being performed before the step or operation.

[0024] Many embodiments are described herein with reference to cross-sectional views as schematic illustrations of embodiments (and intermediate structures). Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but rather include shape deviations, for example, caused by manufacturing. The various regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of the layers and regions may be exaggerated for clarity.

[0025] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and the materials forming them may or may not be described in detail herein. For example, when a certain isolation layer or structure of a semiconductor device is not related to the novel features of an embodiment, the layer or structure and the materials forming it may be omitted herein. In addition, when the materials forming the known structural elements of the semiconductor device are not related to the novel features of the embodiment, the description of those materials may be omitted herein. As used herein, the term "isolation" refers to electrical insulation or separation between structures, layers, components or regions in a corresponding device or structure.

[0026] Figures 1A to 1C A 3D stacked semiconductor device is shown in accordance with one or more embodiments, wherein a contact structure is formed on each of source / drain regions at a first level and source / drain regions at a second level.

[0027] Figure 1A is a top view of the 3D stacked semiconductor device 10, and Figure 1B and Figure 1C They are taken along lines I-I' and II-II' respectively. Figure 1A 3D stacked semiconductor device 10 is shown in FIG. Figure 1ATo illustrate the positional relationship between selected structural elements of the 3D stacked semiconductor device 10, Figure 1A Some structural elements are not shown, such as Figure 1B and Figure 1C The substrate 101 and the isolation structure 141 are shown in FIG.

[0028] like Figure 1A As shown in FIG. 1 , the D1 direction is the channel length direction in which current flows between two source / drain regions connected to each other through the channel structure, the D2 direction is the channel width direction intersecting the D1 direction, and the D3 direction is the vertical direction intersecting the D1 direction and the D2 direction which are horizontal directions. In addition, the channel width direction view is taken along the channel width direction (that is, the D2 direction). Figure 1A 0 is a cross-sectional view of a 3D stacked semiconductor device 10 shown in . The above description may be applied to other embodiments.

[0029] refer to Figures 1A to 1C , the 3D stacked semiconductor device 10 may include a plurality of nanosheet layers forming a first channel structure 110 at a first level above a substrate 101 and a plurality of nanosheet layers forming a second channel structure 120 at a second level above the first level. An intermediate isolation structure 115 may be formed between the first channel structure 110 and the second channel structure 120. The nanosheet layers of the channel structures 110 and 120 may have been epitaxially grown from the substrate 101. The first channel structure 110 may connect the first source / drain regions 135 to each other so that current flows between the first source / drain regions 135 under the control of the gate structure 125 surrounding the first channel structure 110. Similarly, the second channel structure 120 may connect the second source / drain regions 145 to each other so that current flows between the second source / drain regions 145 under the control of the gate structure 125 surrounding the second channel structure 120. The first source / drain region 135 may be epitaxially grown from the first channel structure 110 , and the second source / drain region 145 may be epitaxially grown from the second channel structure 120 .

[0030] Therefore, in the 3D stacked semiconductor device 10, the first channel structure 110 together with the first source / drain region 135 and the gate structure 125 can form a first transistor at a first level, which is a nanosheet transistor. In addition, the second channel structure 120 together with the second source / drain region 145 and the gate structure 125 can form a second transistor at a second level, which is also a nanosheet transistor. Here, as an example, the gate structure 125 can be a common gate structure shared by two transistors to form a complementary metal oxide semiconductor (CMOS) device structure (such as an inverter circuit).

[0031] The substrate 101 may be a silicon (Si) substrate. Additionally or alternatively, it may include other materials, such as silicon germanium (SiGe), silicon carbide (SiC), but is not limited thereto. Each nanosheet layer forming the channel structures 110 and 120 may be formed of silicon (Si) or silicon germanium (SiGe). The first source / drain region 135 and the second source / drain region 145 may also be formed of Si or SiGe. However, when the first source / drain region 135 is formed of Si and doped with n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc., the first transistor may be an n-type transistor. On the contrary, when the second source / drain region 145 is formed of SiGe and doped with impurities such as boron (B), gallium (Ga), indium (In), etc., the second transistor may be a p-type transistor.

[0032] A shallow isolation trench (STI) structure 103 may be formed on the upper left and upper right corners of the substrate 101, and an isolation structure 141 may be formed above the STI structure 103. The STI structure 103 and the isolation structure 141 may isolate the 3D stacked semiconductor device 10 from another 3D stacked semiconductor device or circuit element. The STI structure 103 and the isolation structure 141 may each be made of silicon oxide (SiO, SiO 2 The intermediate isolation structure 115 may be formed of silicon nitride (eg, SiN, SiBCN, SiCN, SiOCN, etc.).

[0033] The gate structure 125 may include a gate dielectric layer and a conductor layer. The gate dielectric layer may include a high-k material such as Hf, Al, Zr, La, Mg, Ba, Ti, Pb and / or a combination thereof, but not limited thereto, and the conductor layer may include a metal or a metal compound such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN or a combination thereof, but not limited thereto.

[0034] A gate contact structure CB may be formed on the gate structure 125 to receive a gate input signal through a metal line included in a back-end-of-line (BEOL) layer. A first contact structure CA1 may be formed on the first source / drain region 135, and a second contact structure CA2 may be formed on the second source / drain region 145. The first contact structure CA1 and the second contact structure CA2 may respectively connect the first source / drain region 135 and the second source / drain region 135 to another circuit element or one or more voltage sources for internal signal routing through corresponding metal lines included in the BEOL layer. For example, Figure 1CThe first contact structure CA1 is shown connected to the metal line M1 through the via structure V0 in the M1 layer. Each of the contact structures CB, CA1 and CA2, the metal line M1 and the via structure V0 may be formed of a metal or a metal compound such as Cu, W, Al, Ru, Mo, Co and / or a combination thereof, but is not limited thereto.

[0035] Meanwhile, the second channel structure 120 may be formed to have a smaller width in the D2 direction than the first channel structure 110. For example, although the left edge (or left side surface) of the second channel structure 120 is vertically aligned or coplanar with the left edge (or left side surface) of the first channel structure 110, the right edge (or right side surface) of the second channel structure 120 is not vertically aligned or coplanar with the right edge (or right side surface) of the first channel structure 110. Therefore, a non-overlapping region may be provided on the right side of the second channel structure 120 and above the first channel structure 110, wherein the second channel structure 120 does not vertically overlap with the first channel structure 110.

[0036] When the second channel structure 120 has a smaller width in the D2 direction than the first channel structure 110, the second source / drain region 145 epitaxially grown from the second channel structure 120 may also have a smaller width in the D2 direction than the first source / drain region 135 epitaxially grown from the first channel structure 110. For example, although the left edge of the second source / drain region 145 is vertically aligned or coplanar with the left edge of the first source / drain region 135, the right edge of the second source / drain region 145 is not vertically aligned or coplanar with the right edge of the first source / drain region 135. Therefore, the right side of the second source / drain region 145 and above the first source / drain region 135 may provide a non-overlapping region, wherein the second source / drain region 145 does not vertically overlap with the first source / drain region 135.

[0037] The aforementioned width difference between the source / drain regions is provided to form a first contact structure CA1 that extends straight downward from the metal line M1 and the via structure V0 through a non-overlapping area above the first source / drain region 135 and is formed on at least a portion of the top surface of the first source / drain region 135 in a limited area, as shown in FIG. Figure 1C . In addition, in order to avoid a possible short circuit risk with the second source / drain region 145 and the second contact structure CA2, the first contact structure CA1 may be formed to contact the upper right edge portion of the first source / drain region, which includes the upper right portion of its top surface. However, in this case, the contact area between the first source / drain region 135 and the first contact structure may be reduced, which may cause an increase in the contact resistance between the two structures, thereby adversely affecting the performance of the 3D stacked semiconductor device 10 in terms of power delivery or signal routing.

[0038] Therefore, the following embodiments are provided to address the reduced contact area between the first source / drain region 135 and the first contact structure.

[0039] FIG. 2A to FIG. 2C A 3D stacked semiconductor device is shown in accordance with one or more embodiments, wherein two contact structures are formed on source / drain regions at a first level and one contact structure is formed on source / drain regions at a second level.

[0040] Figure 2A is a top view of the 3D stacked semiconductor device 20, and Figure 2B and Figure 2C They are taken along lines I-I' and II-II' respectively. Figure 2A 3D stacked semiconductor device 20 is shown in FIG. Figure 2A To illustrate the positional relationship between selected structural elements of the 3D stacked semiconductor device 20, Figure 2A Some structural elements are not shown, such as Figure 2B and Figure 2C The substrate 101 and the isolation structure 141 are shown in FIG.

[0041] refer to FIG. 2A to FIG. 2C , the 3D stacked semiconductor device 20 has Figures 1A to 1C The 3D stacked semiconductor device 20 has the same structural configuration as the 3D stacked semiconductor device 10, except that the 3D stacked semiconductor device 20 has a different second channel structure 120' and a different second source / drain region 145' and an additional first contact structure CA11 and a via structure V01. Therefore, a repeated description thereof may be omitted herein, and instead, different aspects of the 3D stacked semiconductor device 20 are described below.

[0042] As in the 3D stacked semiconductor device 10, the 3D stacked semiconductor device 20 may also have a second channel structure 120' whose width in the D2 direction is smaller than the width of the first channel structure 110. However, the second channel structure 120' of the 3D stacked semiconductor device 20 may have a smaller width than the second channel structure 120 of the 3D stacked semiconductor device 10. For example, unlike the second channel structure 120, the second channel structure 120' may be formed so that the left edge (or left side surface) and the right edge (or right side surface) of the second channel structure 120' are not vertically aligned or coplanar with the left edge (or left side surface) and the right edge (or right side surface) of the first channel structure 110, respectively. Therefore, corresponding non-overlapping regions may be provided on both sides of the second channel structure 120 and above the first channel structure 110, wherein the second channel structure 120 does not vertically overlap with the first channel structure 110.

[0043] Therefore, the second source / drain region 145′ may be formed to have a smaller width than the second source / drain region 145 of the 3D stacked semiconductor device 10, so that the left edge (or left side surface) and the right edge (or right side surface) of the second source / drain region 145′ are not vertically aligned or coplanar with the left edge (or left side surface) and the right edge (or right side surface) of the first source / drain region 135, respectively. Therefore, corresponding non-overlapping regions may be provided on both sides of the second source / drain region 145′ and above the first source / drain region 135, wherein the second source / drain region 145′ does not vertically overlap with the first source / drain region 135.

[0044] By utilizing the non-overlapping regions above the first source / drain region 135 formed on both sides of the second source / drain region 145' and therebelow, two first contact structures CA11 and CA12 may be formed to connect the upper left edge portion and the upper right edge portion of the first source / drain region 135 to the metal line M1 through the via structures V01 and V02 in the M1 layer, respectively. For example, each of the first contact structures CA11 and CA12 formed on the upper left edge portion and the upper right edge portion, respectively, may pass through the non-overlapping regions to be connected to the metal line M1. The upper left edge portion and the upper right edge portion of the first source / drain region 135 include the upper left portion and the upper right portion of the top surface of the first source / drain region 135. In addition, the upper left edge portion and the upper right edge portion of the first source / drain region 135 may include the upper left side surface and the upper right side surface of the first source / drain region 135, as shown in FIG. Figure 2C The M1 layer may be included in the BEOL layer of the 3D stacked semiconductor device 20 .

[0045] The two first contact structures CA11 and CA12 may be connected by the metal line M1 so that the first source / drain region 135 may be connected to a voltage source or another circuit element through the two contact structures CA11 and CA12 to overcome the reduction in contact area and the increase in contact resistance.

[0046] Each of the contact structures CA11 and CA12 , the metal line M1 , and the via structures V01 and V02 may be formed of a metal or a metal compound such as Cu, W, Al, Ru, Mo, Co, and / or a combination thereof, but is not limited thereto.

[0047] FIG. 2A to FIG. 2CIt is shown that two contact structures CA11 and CA12 are formed at two opposite sides (that is, two non-overlapping areas) of the second source / drain region 145'. However, the present disclosure may not be limited thereto, and according to one or more other embodiments, two or more contact structures may be formed through at least one of the two opposite sides of the second source / drain region 145'. In addition, when it is expected that the route on the other side of the second source / drain region 145' is congested by another connection or contact structure, only one of the two contact structures CA11 and CA12 may be formed on the corresponding side of the second source / drain region 145'. In addition, according to one or more embodiments, although only one second contact structure CA2 is formed on the second source / drain region 145', two or more first contact structures including CA11 and CA12 may be formed on the first source / drain region 135, wherein at least two of the first contact structures may be connected to each other.

[0048] FIG. 3A to FIG. 3C A 3D stacked semiconductor device according to one or more embodiments is shown, wherein FIG. 2A to FIG. 2C Only one of the two contact structures of the 3D stacked semiconductor device shown in is formed on the source / drain region at a first level, and one contact structure is formed on the source / drain region at a second level.

[0049] Figure 3A is a top view of a 3D stacked semiconductor device 30, Figure 3B and Figure 3C They are taken along lines I-I' and II-II' respectively. Figure 3A 3D stacked semiconductor device 30 is shown in cross-sectional view. It should be understood that the Figure 3A To illustrate the positional relationship between selected structural elements of the 3D stacked semiconductor device 30, Figure 3A Some structural elements are not shown, such as Figure 3B and Figure 3C The substrate 101 and the isolation structure 141 are shown in FIG.

[0050] refer to FIG. 3A to FIG. 3C , the 3D stacked semiconductor device 30 has FIG. 2A to FIG. 2C The 3D stacked semiconductor device 20 has the same structural configuration as the 3D stacked semiconductor device 20, except that the first contact structure CA12 and the via structure V02 of the 3D stacked semiconductor device 20 are removed in the 3D stacked semiconductor device 30. Therefore, repeated descriptions thereof may be omitted herein, and instead, different aspects of the 3D stacked semiconductor device 30 are described below.

[0051] You can use FIG. 2A to FIG. 2CThe 3D stacked semiconductor device 20 is formed by removing the first contact structure CA12 formed on the upper right edge portion of the first source / drain region 135 and the via structure V02 formed on the first contact structure CA12 to form the 3D stacked semiconductor device 30. For example, when routing congestion is expected on the right side of the second source / drain region 145' and above the top surface of the first source / drain region 135 (that is, the non-overlapping area), these two structures can be removed. For example, when another connection structure or contact structure is routed through the non-overlapping area, the 3D stacked semiconductor device 30 can be configured to abandon the first contact structure CA12.

[0052] Therefore, the 3D stacked semiconductor device 30 may provide an additional space, that is, a non-overlapping region in which another circuit element other than the first contact structure CA11 may be formed, thereby increasing device density and freedom in circuit design including the 3D stacked semiconductor device 30 .

[0053] The design flexibility of the 3D stacked semiconductor device providing a non-overlapping region on each side of the second source / drain region at the second level as described above may be applied to various different embodiments as described below.

[0054] FIG. 4A to FIG. 4C A 3D stacked semiconductor device is shown in which two contact structures are formed on source / drain regions at a first level and one contact structure is formed on source / drain regions at a second level according to one or more other embodiments.

[0055] Figure 4A is a top view of a 3D stacked semiconductor device 40, and Figure 4B and Figure 4C They are taken along lines I-I' and II-II' respectively. Figure 4A 3D stacked semiconductor device 40 is shown in FIG. Figure 4A To illustrate the positional relationship between selected structural elements of the 3D stacked semiconductor device 40, Figure 4A Some structural elements are not shown, such as Figure 4B and Figure 4C The substrate 101 and the isolation structure 141 are shown in FIG.

[0056] refer to FIG. 4A to FIG. 4C , the 3D stacked semiconductor device 40 has FIG. 2A to FIG. 2C The 3D stacked semiconductor device 40 has the same structural configuration as the 3D stacked semiconductor device 20, except that the 3D stacked semiconductor device 40 includes another contact structure CM. Therefore, repeated description thereof may be omitted herein, and instead, different aspects of the 3D stacked semiconductor device 40 are described below.

[0057] The two first contact structures CA11 and CA12 are connected to each other through the metal line M1 and the via structures V01 and V02 in the BEOL layer. FIG. 2A to FIG. 2C Compared to the 3D stacked semiconductor device 20 of the present invention, the 3D stacked semiconductor device 40 may have two first contact structures CA11 and CA12 connected by another contact structure CM, which is a structural element formed in a middle of the line (MOL) process of manufacturing the 3D stacked semiconductor device 40. In other words, in the 3D stacked semiconductor device 40, the two first contact structures CA11 and CA12 as MOL structures may be connected by another MOL structure in the MOL layer below the BEOL layer. Unlike the metal wire M1 in the BEOL layer, a via structure such as via structures V01 and V02 is not formed to connect the first contact structures CA11 and CA12 to the contact structure CM.

[0058] This contact structure CM of the MOL layer may be formed when routing congestion in the BEOL layer is anticipated above the second source / drain region 145′ of the 3D stacked semiconductor device 40. For example, the circuit design including the 3D stacked semiconductor device 40 may not allow the formation of the metal line M1 and the via structures V01 and V02 to connect the two first contact structures CA11 and CA12 included in the 3D stacked semiconductor device 20. Therefore, another MOL structure such as the contact structure CM may be formed to connect the two first contact structures CA11 and CA12, so that the 3D stacked semiconductor device 40 can overcome the reduction in contact area and the increase in contact resistance.

[0059] The contact structure CM may be a metal line formed in the MOL layer and include the same or similar material forming the contact structures CA11 , CA12 , CA2 , CB , the via structures V01 , V02 , and the metal line M1 , such as Cu, W, Al, Ru, Mo, Co, and / or combinations thereof.

[0060] FIG. 5A to FIG. 5C A 3D stacked semiconductor device is shown in which two contact structures are formed on source / drain regions at a first level and one contact structure is formed on source / drain regions at a second level according to one or more other embodiments.

[0061] Figure 5A is a top view of a 3D stacked semiconductor device 50, and Figure 5B and Figure 5C They are taken along lines I-I' and II-II' respectively. Figure 5A 3D stacked semiconductor device 50 is shown in FIG. Figure 5A To illustrate the positional relationship between selected structural elements of the 3D stacked semiconductor device 50, Figure 5ASome structural elements are not shown, such as Figure 5B and Figure 5C The substrate 101 and the isolation structure 141 are shown in FIG.

[0062] refer to FIG. 5A to FIG. 5C , the 3D stacked semiconductor device 50 has FIG. 2A to FIG. 2C The 3D stacked semiconductor device 50 has the same structural configuration as the 3D stacked semiconductor device 20 , except that the 3D stacked semiconductor device 50 includes an additional BEOL structure. Therefore, repeated descriptions thereof may be omitted herein, and instead, different aspects of the 3D stacked semiconductor device 50 are described below.

[0063] The two first contact structures CA11 and CA12 are connected to each other through the metal line M1 in the M1 layer and the via structures V01 and V02. FIG. 2A to FIG. 2C Compared to the 3D stacked semiconductor device 20, the 3D stacked semiconductor device 50 may have two first contact structures CA11 and CA12 connected in the M2 layer above the M1 layer. For example, the first contact structure CA11 may be connected to the M2 metal wire in the M2 layer through the via structure V01 and the metal wire M11 in the M1 layer and the via structure V11 in the M2 layer. Similarly, the first contact structure CA12 may be connected to the M2 metal wire in the M2 layer through the via structure V02 and the metal wire M12 in the M1 layer and the via structure V12 in the M2 layer. Both the M1 layer and the M2 layer may be formed in the BEOL process of manufacturing the 3D stacked semiconductor device 50, and thus may be included in the BEOL layer.

[0064] When routing congestion in the MOL layer and the lower BEOL layer (i.e., the M1 layer) above the second source / drain region 145' of the 3D stacked semiconductor device 50 is anticipated, such connection of the two first contact structures CA11 and CA12 through the M2 metal line in the M2 layer may also be configured. However, the 3D stacked semiconductor device 50 may also overcome the problem of Figures 1A to 1C A reduction in contact area and an increase in contact resistance may occur in the 3D stacked semiconductor device 10 shown in FIG.

[0065] Each of the contact structures CA2, CA11, and CA12, the metal lines M11, M12, M2, and the via structures V01, V02, V11, and V12 may be formed of a metal or a metal compound such as Cu, W, Al, Ru, Mo, Co, and / or a combination thereof, but is not limited thereto.

[0066] In the above embodiments, the first transistor at the first level and the second transistor at the second level of each of the 3D stacked semiconductor devices 10-50 are described as nanosheet transistors. However, the present disclosure may not be limited thereto. According to one or more embodiments, at least one of the first transistor and the second transistor may be a different type of transistor, such as a FinFET, a fork-sheet transistor, etc.

[0067] In addition, in the 3D stacked semiconductor devices 20, 40 and 50, two contact structures CA11 and CA12 are formed on the first source / drain region of the first transistor at the first level. However, according to one or more other embodiments, multiple contact structures may also be formed on the source / drain region of the single stacked semiconductor device, depending on the circuit design considering the routing congestion of the semiconductor device.

[0068] Figure 6 is a schematic block diagram showing an electronic device including a semiconductor device according to one or more embodiments, in which two or more contact structures are formed on a source / drain region of the semiconductor device. According to one or more embodiments, the semiconductor device may be FIG. 2A to FIG. 2C to FIG. 5A to FIG. 5C One of the 3D stacked semiconductor devices 20 - 50 shown in FIG.

[0069] refer to Figure 6 , the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output module 1300, a storage device 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0070] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving input and at least one of a display, a speaker, etc. for generating an output signal processed by the processor 1100. The storage device 1400 may be implemented to store user data, output signals, etc. input through the input / output module 1300. The storage device 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS) device, etc.

[0071] The buffer RAM module 1500 may temporarily store data used for processing operations of the electronic device 1000. For example, the buffer RAM 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0072] although Figure 6 Although not shown in the figure, the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0073] According to one or more embodiments, at least one component in the electronic device 1000 may be formed based on a semiconductor device in which two or more contact structures are formed on source / drain regions of the semiconductor device.

[0074] The foregoing is a description of example embodiments and should not be construed as limiting the present disclosure. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above-described embodiments without materially departing from the present disclosure.

[0075] This application is based on and claims priority to U.S. Provisional Application No. 63 / 546,114 filed in the U.S. Patent and Trademark Office on October 27, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a first source / drain region; as well as a first contact structure on a first portion of the first source / drain region; as well as a second contact structure on a second portion of the first source / drain region, At least one of the first contact structure and the second contact structure is configured to connect the first source / drain region to another circuit element or a voltage source for signal routing. 2 . The semiconductor device according to claim 1 , wherein the first contact structure and the second contact structure are connected.

3. The semiconductor device according to claim 2, further comprising a metal line above the first source / drain region, The first contact structure and the second contact structure are connected through the metal wire.

4. The semiconductor device according to claim 3, further comprising a first via structure and a second via structure formed on the first contact structure and the second contact structure, respectively, Wherein the first via structure and the second via structure are connected to the metal line. 5 . The semiconductor device according to claim 3 , wherein no via structure is formed between each of the first contact structure and the second contact structure and the metal line.

6. The semiconductor device according to claim 1, further comprising a second source / drain region vertically above the first source / drain region, wherein the second source / drain region has a smaller width than the first source / drain region, in, forming a non-overlapping region at each of two opposite sides of the second source / drain region where the second source / drain region does not vertically overlap with the first source / drain region, and At least one of the first contact structure and the second contact structure is formed to pass through the non-overlapping region to be connected to the first source / drain region. 7 . The semiconductor device according to claim 6 , wherein the first contact structure and the second contact structure are formed to pass through the corresponding non-overlapping regions to be connected to the first source / drain region.

8. The semiconductor device according to claim 6, further comprising a metal line above the second source / drain region, The first contact structure and the second contact structure are connected through the metal wire.

9. The semiconductor device according to claim 8, further comprising a first via structure and a second via structure formed on the first contact structure and the second contact structure, respectively, Wherein the first via structure and the second via structure are connected to the metal line. 10 . The semiconductor device according to claim 1 , wherein the first portion is an upper left edge portion of the first source / drain region, and the second portion is an upper right edge portion of the first source / drain region.

11. A semiconductor device comprising: a first source / drain region for a first transistor; as well as a second source / drain region for a second transistor, the second source / drain region being vertically disposed above the first source / drain region, wherein the second source / drain region has a smaller width than the first source / drain region in a channel width direction view, the channel width direction intersecting with a direction in which current flows in each of the first transistor and the second transistor, Wherein a non-overlapping region where the second source / drain region does not vertically overlap with the first source / drain region is formed at each of the left and right sides of the second source / drain region in the channel width direction view.

12. The semiconductor device according to claim 11, further comprising a first contact structure on the first source / drain region, The first contact structure passes through one of the non-overlapping regions. 13 . The semiconductor device according to claim 12 , wherein the first contact structure is formed on an upper left edge portion or an upper right edge portion of the first source / drain region.

14. The semiconductor device according to claim 12, further comprising a second contact structure on the first source / drain region, Wherein the second contact structure passes through another one of the non-overlapping regions.

15. The semiconductor device according to claim 14, further comprising a metal line above the second source / drain region, The first contact structure and the second contact structure are connected through the metal wire. 16 . The semiconductor device according to claim 14 , wherein the first contact structure is formed on an upper left edge portion of the first source / drain region, and the second contact structure is formed on an upper right edge portion of the first source / drain region.

17. A semiconductor device comprising: a first source / drain region; as well as a second source / drain region vertically above said first source / drain region, wherein two or more first contact structures are formed on the first source / drain region, and Only one second contact structure is formed on the second source / drain region. 18 . The semiconductor device according to claim 17 , wherein at least one of the two or more first contact structures is formed at one side of the second source / drain region on a top surface of the first source / drain region. 19 . The semiconductor device according to claim 17 , wherein at least two of the two or more first contact structures are connected to each other. 20 . The semiconductor device of claim 19 , wherein the at least two first contact structures are connected to each other through a metal line in a middle of line (MOL) layer or a back end of line (BEOL) layer.

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