A wide band gap semiconductor composite chip structure and a method for manufacturing the same

Abstract

The application provides a wide-bandgap semiconductor composite chip structure and a preparation method thereof, and belongs to the technical field of semiconductor devices. The composite chip structure vertically integrates a wide-bandgap semiconductor voltage-resistant unit with a wide-bandgap semiconductor material as a main body and a switch control unit made on a traditional semiconductor material through a conductive plug, so that the composite chip structure has the voltage-resistant performance of the wide-bandgap semiconductor material, avoids various problems in the manufacture of the wide-bandgap semiconductor switch control device, and also avoids the problems of hetero-material interface defects and interface barriers in the existing integrated technology. The composite chip structure has a smaller chip area and better electrical performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a wide bandgap semiconductor composite chip structure and its fabrication method. Background Technology

[0002] Wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) have advantages over silicon (Si) in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Power devices made from wide-bandgap semiconductor materials, such as diodes, transistors, and power modules, have superior electrical characteristics, overcoming the limitations of silicon-based devices in meeting the requirements of high power, high voltage, high frequency, and high temperature applications. This is also one of the breakthrough paths to surpass Moore's Law, and therefore they are widely used in new energy fields (such as photovoltaics, energy storage, charging piles, and electric vehicles). However, various problems exist in the actual design, fabrication, and application of power devices. For example, silicon carbide MOSFET devices suffer from numerous gate oxide layer defects, threshold voltage drift, complex fabrication processes, and the need for special process equipment (including high-temperature annealing equipment). Furthermore, achieving P-type doping through ion implantation is relatively difficult for materials such as gallium nitride, gallium oxide, diamond, and aluminum nitride. Meanwhile, silicon power devices and processes are very mature, and there is mature industrial equipment and experience for device design, fabrication, and equipment. Therefore, integrating the switching control unit in traditional silicon power devices with the wide-bandgap semiconductor drift region, which serves as a voltage withstand unit, to create composite chips has become a research direction for researchers.

[0003] Existing technology CN118039634A discloses a composite device structure and fabrication method of a silicon control unit and a wide bandgap semiconductor unit. This device structure involves directly epitaxially or bonding a silicon single-crystal thin film layer to the surface of a wide bandgap semiconductor material layer, fabricating the MOSFET's channel switching control region within the silicon single-crystal thin film layer, and using the wide bandgap semiconductor material layer as a voltage-resistant unit. While this device structure successfully integrates the silicon control unit and the wide bandgap semiconductor voltage-resistant unit to obtain a composite device, solving problems related to the design, fabrication, and special equipment requirements of wide bandgap semiconductor devices, the composite device structure still has the following problems: the heterojunction interface between the wide bandgap semiconductor material and silicon material has interface defects such as oxide layers and amorphous layers; the heterojunction structure forms an interface barrier, preventing current from effectively conducting at the interface, thus forming a large interface capacitance and affecting the switching characteristics of the device. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a wide-bandgap semiconductor composite chip structure and its fabrication method. By vertically integrating the wide-bandgap semiconductor withstand voltage unit with the switch control unit through conductive plugs, the composite chip structure achieves a smaller area and superior electrical performance.

[0005] Specifically, in order to achieve the above objectives, the present invention adopts the following technical solution:

[0006] A wide bandgap semiconductor composite chip structure, wherein the cell structure of the composite chip structure includes, from bottom to top, a substrate, a drift layer, a first buried layer, and a switch control unit; the drift layer contains island-shaped distributed second buried layers; the second buried layer is connected to the first buried layer via connecting pillars; the first buried layer contains a first doped region penetrating the first buried layer and located above the second buried layer; on the upper surface of the first buried layer, in the area requiring electrical connection with the switch control unit, a first ohmic contact metal layer and a second ohmic contact metal layer are deposited; the second ohmic contact metal layer is located on the upper surface of the first doped region; the switch... The control unit includes a semiconductor material layer, a third ohmic contact metal layer and a fourth ohmic contact metal layer located on the upper surface of the semiconductor material layer; a plurality of conductive plugs are disposed in the semiconductor material layer, at least penetrating the semiconductor material layer; the first ohmic contact metal layer is electrically connected to the third ohmic contact metal layer through the conductive plugs; the second ohmic contact metal layer is electrically connected to the fourth ohmic contact metal layer through the conductive plugs; the substrate, the drift layer, the first doped region, and the semiconductor material layer are doped of a first type, and the first buried layer, the second buried layer, and the connecting pillar are doped of a second type.

[0007] In a preferred embodiment, a bonding interface layer is provided on the upper surface of the first buried layer, and the semiconductor material layer is located on the upper surface of the bonding interface layer.

[0008] In a preferred embodiment, the substrate is made of at least one of single-crystal SiC, polycrystalline SiC, and Si.

[0009] In a preferred embodiment, the material of the drift layer is at least one of SiC, GaN, Ga2O3, and AlN.

[0010] In a preferred embodiment, the drift layer has a dimension of 1000 nm to 150 μm along the direction from the substrate to the first buried layer.

[0011] In a preferred embodiment, the dimension of the first buried layer along the direction from the substrate to the first buried layer is 10 nm to 500 nm.

[0012] In a preferred embodiment, the material of the bonding interface layer is silicon dioxide or BCB.

[0013] In a preferred embodiment, the semiconductor material layer is made of at least one of silicon, GaN, and 3C-SiC.

[0014] In a preferred embodiment, the dimension of the bonding interface layer along the direction from the substrate to the bonding interface layer is 1 nm to 10 μm.

[0015] In a preferred embodiment, the size of the semiconductor material layer along the direction from the substrate to the semiconductor material layer is 100 nm to 10 μm.

[0016] In a preferred embodiment, the switch control unit is any one of a MOSFET device, a HEMT device, an NPN transistor, a PNP transistor, a JFET switch control unit, or a diode.

[0017] In a preferred embodiment, the conductive plug is made of at least one of titanium, titanium nitride, tungsten, aluminum, and copper.

[0018] The present invention also provides a method for fabricating the composite chip structure described in any of the above embodiments, comprising the following steps:

[0019] S1. The drift layer is formed on the surface of one side of the substrate; a first buried layer is formed on the top layer or the upper surface of the drift layer;

[0020] S2. Form the second buried layer and the connecting pillar in an island-like distribution in the drift layer, form the first doped region in the first buried layer, and anneal;

[0021] S3. Deposit ohmic contact metal on the upper surface of the first buried layer and etch it to retain the area that needs to be electrically connected to other devices, to obtain the first ohmic contact metal layer and the second ohmic contact metal layer, and anneal it; to obtain a wide bandgap semiconductor voltage withstand cell.

[0022] S4. Bond the semiconductor material layer to the upper surface of the wide bandgap semiconductor voltage withstand unit;

[0023] S5. The switch control unit is fabricated in the semiconductor material layer;

[0024] S6. In the corresponding area where the switch control unit and the wide bandgap semiconductor withstand voltage unit need to be electrically connected, a through hole that penetrates at least through the semiconductor material layer is etched; a first dielectric layer is deposited on the sidewall of the through hole, and then a conductive material is deposited on the upper surface of the semiconductor material layer and inside the through hole, and etched to obtain the conductive plug.

[0025] In a preferred embodiment, the fabrication method further includes the following steps: fabricating an isolation layer, a gate, and a source on the upper surface of the device structure obtained in step S6, wherein the isolation layer isolates the gate and the source; and fabricating a drain on the surface of the substrate opposite to the drift layer.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] (1) The wide bandgap semiconductor composite chip structure provided by the present invention combines the high voltage and high power characteristics of wide bandgap semiconductor materials with the mature process platform of traditional semiconductor material switch control unit, realizing the vertical integration of wide bandgap semiconductor voltage-resistant unit with wide bandgap semiconductor material as drift layer and traditional semiconductor material switch control unit, so that the composite chip structure has both high voltage resistance and smaller chip area.

[0028] (2) This invention avoids the problems of interface defects and interface barriers caused by the direct integration of silicon-based switch control units and wide-bandgap semiconductor voltage withstand units through heterogeneous materials in the prior art. In this invention, conductive plugs are used to realize the electrical connection between traditional semiconductor material switch control units and wide-bandgap semiconductor voltage withstand units, which effectively overcomes the problems of current not being able to flow effectively due to interface barriers and the formation of large interface capacitance affecting the switching characteristics of the device. Attached Figure Description

[0029] Figure 1 A schematic diagram of a wide bandgap semiconductor composite chip structure provided by the present invention;

[0030] Figure 2 A schematic diagram of another wide bandgap semiconductor composite chip structure provided by the present invention;

[0031] Figure 3 A schematic diagram of another wide bandgap semiconductor composite chip structure provided by the present invention;

[0032] Figure 4 for Figure 1 The structure above is a top view of the upper surface of the first buried layer. The area within the red dashed line in the figure is the second buried layer.

[0033] Figure 5 for Figure 1 Top view of the structure at section AA';

[0034] Figures 6-8 This is a schematic diagram of the structure obtained in steps S1 to S3 of the present invention for preparing a wide bandgap semiconductor composite chip structure;

[0035] Figure 9 , Figure 10This is a schematic diagram of the structure obtained by using different bonding methods between the semiconductor material layer and the wide bandgap semiconductor voltage-resistant unit in step S4 of the present invention for preparing a wide bandgap semiconductor composite chip structure;

[0036] Figures 11-13 These are schematic diagrams of different device structures obtained in step S5 of the present invention for preparing a wide bandgap semiconductor composite chip structure;

[0037] Figures 14-16 This is a schematic diagram of different device structures obtained in step S6 of the present invention for preparing a wide bandgap semiconductor composite chip structure.

[0038] In the figure: 1. Wide bandgap semiconductor breakdown voltage cell; 101. Substrate; 102. Drift layer; 103. First buried layer; 104. Second buried layer; 105. Connecting pillar; 106. First doped region; 107. First ohmic contact metal layer; 108. Second ohmic contact metal layer; 2. Bonding interface layer; 3. Switch control unit; 301. Semiconductor material layer; 302. Via; 303. First dielectric layer; 304. Well region; 305. Second doped region; 306. Third ohmic contact metal layer; 307. Fourth ohmic contact metal layer; 308. Isolation layer; 309. AlGaN layer; 310. p-GaN layer; 4. Conductive plug; 5. Gate; 6. Source; 7. Drain. Detailed Implementation

[0039] The following description, in conjunction with embodiments, clearly and completely describes the technical solutions of this application, so that those skilled in the art can fully understand this application. Obviously, the described embodiments are merely some preferred embodiments of this application, and not all embodiments. Any equivalent modifications or substitutions made by those skilled in the art to the following embodiments without creative effort are within the protection scope of this application.

[0040] The directional terms described in this application, such as "upper," "lower," "inner," "outer," "bottom," and "upper surface," indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings or the orientations or positional relationships commonly used when the product is in use. These terms are used solely for the purpose of describing and understanding the product structure and should not be construed as limitations on this application. In this application, unless otherwise explicitly defined, expressions such as "upper," "above," "above," and "upper surface" for the first feature and the second feature indicate that the first and second features may be in direct contact or indirectly in contact through an intermediate medium; the first feature may be directly above or diagonally above the second feature, or simply indicate that the first feature is at a higher horizontal level than the second feature. Expressions such as "lower," "below," "below," and "lower surface" for the first feature and the second feature indicate that the first and second features may be in direct contact or indirectly in contact through an intermediate medium; the first feature may be directly below or diagonally below the second feature, or simply indicate that the first feature is at a lower horizontal level than the second feature. Ordinal numbers used in this application, such as "first" and "second," are for descriptive purposes only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Methods not described in detail in the following embodiments are conventional methods well-known to those skilled in the art.

[0041] The full names of the abbreviations used in the following examples are as follows:

[0042] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor;

[0043] HEMT: High Electron Mobility Transistors;

[0044] MOCVD: Metal-organic Chemical Vapor Deposition;

[0045] JFET: Junction Field-Effect Transistor;

[0046] MBE: Molecular beam epitaxy;

[0047] CVD: Chemical Vapor Deposition;

[0048] ALD: Atomic layer deposition;

[0049] BCB: Benzocyclobutene.

[0050] Example 1

[0051] A wide-bandgap semiconductor composite chip structure, composed of several cell structures. (Refer to...) Figures 1-5 Each cell structure, from bottom to top, includes a substrate 101, a drift layer 102, a first buried layer 103, and a switch control unit 3. Island-shaped second buried layers 104 are distributed in the drift layer 102, located below the first buried layer 103. The second buried layer 104 is connected to the first buried layer 103 via connecting posts 105 to prevent the second buried layer 104 from floating. A first doped region 106 is disposed in the first buried layer 103, penetrating the first buried layer 103 and located above the second buried layer 104. A first ohmic contact metal layer 107 and a second ohmic contact metal layer 108 are deposited on the upper surface of the first buried layer 103 in the area requiring electrical connection with the switch control unit 3. The second ohmic contact metal layer 108 is located on the upper surface of the first doped region 106. The switch control unit 3 includes a semiconductor material layer 301, a third ohmic contact metal layer 306, and a fourth ohmic contact metal layer 307 located on the upper surface of the semiconductor material layer 301 (i.e., the surface of the semiconductor material layer 301 away from the first buried layer 103). A plurality of conductive plugs 4, each penetrating at least through the semiconductor material layer 301, are disposed in the semiconductor material layer 301. The first ohmic contact metal layer 107 is electrically connected to the third ohmic contact metal layer 306 via the conductive plugs 4. The second ohmic contact metal layer 108 is electrically connected to the fourth ohmic contact metal layer 307 via the conductive plugs 4. The substrate 101, drift layer 102, first doped region 106, and semiconductor material layer 301 are doped using the first type of doping, while the first buried layer 103, second buried layer 104, and connecting pillar 105 are doped using the second type of doping.

[0052] In the above scheme, the drift layer 102, the first buried layer 103, the second buried layer 104, the connecting post 105, the first ohmic contact metal layer 107, and the second ohmic contact metal layer 108 constitute a wide bandgap semiconductor withstand voltage unit 1. The first ohmic contact metal layer 107 of the wide bandgap semiconductor withstand voltage unit 1 is electrically connected to the third ohmic contact metal layer 306 of the switch control unit 3 through a conductive plug 4. The second ohmic contact metal layer 108 of the wide bandgap semiconductor withstand voltage unit 1 is electrically connected to the fourth ohmic contact metal layer 307 of the switch control unit 3 through a conductive plug 4. By vertically integrating the wide bandgap semiconductor withstand voltage unit 1 with the switch control unit 3, a composite chip structure is obtained. This wide bandgap semiconductor withstand voltage unit 1 enables the composite chip structure to have excellent lateral withstand voltage turn-off performance and good forward conduction characteristics under reverse bias voltage. Because the first buried layer 103 contains a first doped region 106 serving as a current path, when a reverse bias voltage is applied to the composite chip structure, the island-shaped distributed second buried layer 104 can completely block the first doped region 106, shielding it from the high electric field in the reverse direction. Simultaneously, the island-shaped distribution (see...) Figure 4 and Figure 5 The second buried layer 104 is connected to the first buried layer 103 via connecting pillars 105 periodically arranged in the drift layer 102, preventing the second buried layer 104 from being in a floating state. This allows the reverse depletion of the PN junction to be recovered in time during dynamic switching, reducing the switching capacitance and achieving a good reverse electric field masking effect during continuous switching. The second ohmic contact metal layer 108 located on the upper surface of the first doped region 106 is electrically connected to the fourth ohmic contact metal layer 307 in the switch control unit 3 via a conductive plug 4, allowing current to flow between the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3.

[0053] In some specific embodiments, the substrate 101, drift layer 102, first doped region 106, and semiconductor material layer 301 are all N-type doped, while the first buried layer 103, second buried layer 104, and connecting pillar 105 are all P-type doped. In other specific embodiments, the substrate 101, drift layer 102, first doped region 106, and semiconductor material layer 301 are all P-type doped, while the first buried layer 103, second buried layer 104, and connecting pillar 105 are all N-type doped.

[0054] As an example, the material of substrate 101 is at least one of single-crystal SiC, polycrystalline SiC, and Si.

[0055] As an example, the material of the drift layer 102 is at least one of SiC, GaN, Ga2O3, and AlN.

[0056] As an example, the thickness of the drift layer 102 (the dimension along the direction from the substrate 101 to the first buried layer 103 or along the direction from the first buried layer 103 to the substrate 101) is 1000nm to 150μm; for example, the thickness of the substrate 101 is 1000nm, 1001nm, 1002nm, 1005nm, 1010nm, 1015nm, 1020nm, 1025nm, 1030nm, 1040nm, 1050nm...2000nm, 2100nm, 2200nm, 2300nm, 2400nm, 2500nm, 2600nm, 2800nm...10μm, 11μm, 12μm, 13μm, 14μm...150μm, preferably 10μm.

[0057] As an example, the thickness of the first buried layer 103 (the dimension along the direction from the substrate 101 to the first buried layer 103 or along the direction from the first buried layer 103 to the substrate 101) is 10nm to 500nm; for example, the thickness of the first buried layer 103 is 10nm, 11nm, 12nm, 15nm, 20nm, 22nm, 25nm, 30nm, 35nm, 40nm, 50nm...500nm, preferably 100nm.

[0058] As an example, the material of the first ohmic contact metal layer 107 is nickel or a titanium-nickel-aluminum alloy.

[0059] As an example, the material of the second ohmic contact metal layer 108 is nickel or a titanium-nickel-aluminum alloy.

[0060] In some specific implementations, the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3 are combined through the interface layer 2 to form a complete composite chip cell structure (e.g., Figure 1 and Figure 2 (As shown).

[0061] As an example, the material of the bonding interface layer 2 is silicon dioxide and / or BCB; silicon dioxide is preferred. For example, when the material of the semiconductor material layer 301 is silicon, a layer of silicon dioxide is deposited on the upper surface of the first buried layer 103 as the bonding interface layer 2 by CVD, ALD, or spin coating. The semiconductor material layer 301 is deposited on the upper surface of the silicon dioxide dielectric layer. The switch control unit 3 and the wide bandgap semiconductor withstand voltage unit 1 are bonded together as a whole through the silicon dioxide dielectric layer.

[0062] As an example, the thickness of the bonding interface layer 2 (the dimension along the direction from the substrate 101 to the bonding interface layer 2) is 1 nm to 10 μm; for example, the thickness of the bonding interface layer 2 is 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 10 nm, 12 nm, 15 nm...300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 380 nm...1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm...10 μm, preferably 300 nm.

[0063] In other specific embodiments, the wide-bandgap semiconductor withstand voltage unit 1 and the switch control unit 3 are constructed into a complete composite chip cell structure by epitaxially growing a semiconductor material layer 301 on the upper surface of the first buried layer 103 (e.g., using MOCVD, MBE, or other methods). Figure 3 As shown, when the material of the drift layer 102 is silicon carbide, a GaN layer is directly heteroepitaxially grown on the upper surface of the first buried layer 103 to obtain a semiconductor material layer 301, and an AlGaN layer 309 is grown on the upper surface of the GaN layer.

[0064] As an example, the switch control unit 3 can be any one of a MOSFET device, a HEMT device, an NPN transistor, a PNP transistor, a JFET switch control unit, or a diode.

[0065] like Figure 1 As shown, when the switch control unit 3 is a MOSFET device, it includes a semiconductor material layer 301, a well region 304 disposed in the semiconductor material layer 301, a second doped region 305 disposed in the semiconductor material layer 301, a third ohmic contact metal layer 306 and a fourth ohmic contact metal layer 307 located on the upper surface of the semiconductor material layer 301, a gate 5, a source 6, and a drain 7; the gate 5 and the source 6 are separated by an isolation layer 308; the second doped region 305 serves as the source doped region. The doping type of the well region 304 is opposite to that of the semiconductor material layer 301, while the doping type of the second doped region 305 is the same as that of the semiconductor material layer 301. The first buried layer 103 is connected to the source 6 through the first ohmic contact metal layer 107 and the conductive plug 4 located on its upper surface, forming a lateral equipotential field plate. During reverse breakdown, it can work with the island-shaped second buried layer 104 to achieve reverse depletion pinch-off of the PN junction in the drift layer 102, thereby achieving a more reliable reverse breakdown capability. When the switch control unit 3 is a MOSFET device, when the device is turned on (i.e., a positive voltage is applied to the gate 5 relative to the source 6, and a positive voltage is also applied to the drain 7 relative to the source 6), the current conduction path of the composite chip structure is as follows: Figure 1The direction indicated by the green dashed arrow is shown. When the device is turned off (i.e., a negative voltage or 0V is applied to the gate 5 relative to the source 6, and the drain 7 is at a positive high voltage relative to the source 6), the first buried layer 103 and the second buried layer 104 connected to the first buried layer 103 via the connecting post 105, together with the drift layer 102, form a PN junction that is depleted by reverse bias. The depletion region expands and pinches off the channel of the drift layer 102 (e.g., ...). Figure 1 As shown by the red dashed line above), an effective reverse withstand voltage is formed; at the same time, the island-shaped second buried layers 104 will also be depleted due to the reverse bias of the PN junction formed with the drift layer 102, and the depletion region expands to cut off the channel of the drift layer 102 (as shown by the red dashed line above). Figure 1 (As shown by the red dotted line above), which helps to improve pressure resistance.

[0066] like Figure 2 and Figure 3 As shown, the drift layer 102 is made of silicon carbide, and the switch control unit 3 is a p-GaN HEMT device. The switch control unit 3 includes a semiconductor material layer 301 (the semiconductor material layer 301 is made of GaN), an AlGaN layer 309 deposited on the upper surface of the semiconductor material layer 301, a p-GaN layer 310 located on the upper surface of the AlGaN layer 309, and a gate 5, a source 6, and a drain 7 located on the upper surface of the p-GaN layer 310; the gate 5 and the source 6 are separated by an isolation layer 308. When the switch control unit 3 is a p-GaN HEMT switch control unit, the advantages of different wide bandgap semiconductor materials can be combined and complemented. When the upper switch control unit is a p-GaN HEMT cell structure constructed with a GaN material layer, the high mobility of the two-dimensional electron gas between AlGaN and GaN, and the relatively stable threshold turn-on characteristics of the p-GaN gate, can be used to construct faster switching characteristics, while retaining the high voltage withstand and high heat dissipation performance of silicon carbide.

[0067] As an example, the thickness of the semiconductor material layer 301 (the dimension along the direction from the substrate 101 to the semiconductor material layer 301 or along the direction from the semiconductor material layer 301 to the substrate 101) is 100 nm to 10 μm; for example, the thickness of the semiconductor material layer 301 is 100 nm, 101 nm, 102 nm, 103 nm, 105 nm, 110 nm, 115 nm, 125 nm, 130 nm, 140 nm, 150 nm...200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 280 nm...1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm...10 μm, preferably 600 nm.

[0068] As an example, the semiconductor material layer 301 is made of at least one of silicon, GaN, and 3C-SiC.

[0069] As an example, the third ohmic contact metal layer 306 is nickel or a titanium-nickel-aluminum alloy.

[0070] As an example, the fourth ohmic contact metal layer 307 is nickel or a titanium-nickel-aluminum alloy.

[0071] As an example, the material of the isolation layer 308 is SiO2.

[0072] As an example, the material of the conductive plug 4 is at least one of titanium, titanium nitride, tungsten, aluminum, and copper.

[0073] As an example, the material of gate 5 is aluminum and / or copper.

[0074] As an example, the material of source electrode 6 is aluminum and / or copper.

[0075] As an example, the material of drain 7 is aluminum and / or copper.

[0076] Example 2

[0077] Reference Figures 6-16 A method for fabricating a wide-bandgap semiconductor composite chip structure includes the following steps:

[0078] S1. A wide bandgap semiconductor material layer is epitaxially or bonded to the surface of one side of the substrate 101 to obtain a drift layer 102. A first buried layer 103 is formed on the top layer of the drift layer 102 by ion implantation or epitaxial growth.

[0079] S2. A second buried layer 104 with an island-like distribution is formed in the drift layer 102 by ion implantation. A connecting pillar 105 is formed in the drift layer 102 by ion implantation. A first doped region 106 is formed in the first buried layer 103 by ion implantation. Annealing is then performed. The first doped region 106 penetrates the first buried layer 103 and is located above the second buried layer 104.

[0080] S3. Deposit ohmic contact metal on the upper surface of the first buried layer 103 and etch it to retain the area that needs to be electrically connected to other devices, to obtain the first ohmic contact metal layer 107 and the second ohmic contact metal layer 108. Anneal the layer to form ohmic contacts between the drift layer 102 and the first ohmic contact metal layer 107 and the second ohmic contact metal layer 108; to obtain the wide bandgap semiconductor withstand voltage unit 1.

[0081] S4. Bond the semiconductor material layer 301 to the upper surface of the wide bandgap semiconductor voltage-resistant unit 1 (e.g., Figure 9 and Figure 10 (As shown).

[0082] S5. A switch control unit 3 is fabricated in the semiconductor material layer 301 using CMOS technology (e.g., Figures 11-13 (As shown).

[0083] S6. In the corresponding region where the switch control unit 3 and the wide bandgap semiconductor withstand voltage unit 1 need to be electrically connected, a via 302 penetrating at least through the semiconductor material layer 301 is etched. A first dielectric layer 303 is deposited on the sidewall of the via 302. Then, a conductive material is deposited on the upper surface of the semiconductor material layer 301 and inside the via 302, and etched to obtain a conductive plug 4. This completes the vertical integration of the wide bandgap semiconductor withstand voltage unit 1 and the switch control unit 3.

[0084] In some specific embodiments, the annealing conditions in step S2 are: annealing at a temperature of 400℃~1100℃ for 5~300s. For example, the annealing temperature is 400℃, 405℃, 410℃, 420℃, 430℃, 450℃, 500℃, 550℃, 600℃...1100℃; the annealing time is 5s, 6s, 7s, 8s, 9s, 10s, 12s, 15s, 20s, 30s, 40s, 60s, 100s...300s.

[0085] In some specific implementations, the annealing conditions in step S3 are: XXX is annealed at a temperature of 400℃-1100℃ for 5~300s. For example, the annealing temperature is 400℃, 402℃, 408℃, 410℃, 415℃, 425℃, 480℃, 520℃, 580℃, 600℃...1100℃; the annealing time is 5s, 8s, 10s, 15s, 20s, 30s, 35s, 50s, 70s, 75s, 90s...300s.

[0086] In some specific embodiments, the bonding of the semiconductor material layer 301 to the upper surface of the wide bandgap semiconductor voltage withstand unit 1 in step S4 is performed as follows: a bonding interface layer 2 is deposited on the upper surface of the wide bandgap semiconductor voltage withstand unit 1 using CVD, ALD, or spin coating processes. A semiconductor material layer 301 is then bonded to the upper surface of the bonding interface layer 2 using a wafer-level bonding process. The via 302 in step S6 penetrates both the semiconductor material layer 301 and the bonding interface layer 2.

[0087] In some other specific embodiments, in step S4, a semiconductor material layer 301 is directly epitaxially grown on the upper surface of the wide bandgap semiconductor voltage withstand unit 1 by MOCVD or MBE method, thereby bonding the semiconductor material layer 301 to the upper surface of the wide bandgap semiconductor voltage withstand unit 1.

[0088] Reference Figure 10 , Figure 13 and Figure 1Taking a MOSFET switch control unit as an example, in step S5, a well region 304 is first formed in the source region of the semiconductor material layer 301 by ion implantation, and then a second doped region 305 with spacing is formed in the top layer of the semiconductor material layer 301 by ion implantation. A portion of the second doped region 305 is located in the well region 304 as a source doped region. Ohmic contact metal is deposited on the upper surface of the semiconductor material layer 301 and etched, retaining the ohmic contact metal in the area that needs to be electrically connected to the wide bandgap semiconductor voltage-resistant unit 1, to obtain a third ohmic contact metal layer 306 and a fourth ohmic contact metal layer 307. Annealing (annealing conditions are the same as in step S3) forms ohmic contacts between the semiconductor material layer 301 and both the third ohmic contact metal layer 306 and the fourth ohmic contact metal layer 307. An insulating material is deposited on the upper surface of the semiconductor material layer 301 and etched to obtain a gate dielectric layer, and a gate 5 is fabricated on the upper surface of the gate dielectric layer. Then, an insulating material is deposited and etched on the surface of the obtained device to obtain an interlayer dielectric layer. The gate dielectric layer and the interlayer dielectric layer are collectively referred to as the isolation layer 308. Metal is deposited and etched on the upper surface of the obtained device structure to obtain the source 6; metal is deposited on the surface of the substrate 101 away from the drift layer 102 to obtain the drain 7.

[0089] Reference Figure 12 , Figure 13 , Figure 15 , Figure 16 , Figure 2 and Figure 3 Taking a p-GaN HEMT switch control unit as an example, in step S5, the semiconductor material layer 301 is a GaN layer. An AlGaN layer 309 is deposited on the upper surface of the GaN layer. A p-type GaN layer 310 is deposited and etched on the upper surface of the AlGaN layer 309. A conductive material is deposited and etched on the upper surface of the p-GaN layer 310 to obtain the gate 5. An insulating material is deposited and etched on the surface of the obtained device structure to obtain an interlayer dielectric layer. The interlayer dielectric layer serves as an isolation layer 308 to isolate the gate 5 from the subsequently fabricated source 6. Metal is deposited and etched on the upper surface of the obtained device structure to obtain the source 6. Metal is deposited on the surface of the substrate 101 away from the drift layer 102 to obtain the drain 7.

[0090] The embodiments described above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by anyone skilled in the art. Any simple equivalent changes and modifications made based on the scope of protection of this application and the content of the specification should be included within the scope of protection of this application.

Claims

1. A wide bandgap semiconductor composite chip structure, characterized in that, The cellular structure of the composite chip includes, from bottom to top, a substrate, a drift layer, a first buried layer, and a switch control unit; the drift layer contains island-shaped distributed second buried layers; the second buried layer is connected to the first buried layer via connecting pillars; the first buried layer contains a first doped region penetrating the first buried layer and located above the second buried layer; on the upper surface of the first buried layer, in the area where electrical connection with the switch control unit is required, a first ohmic contact metal layer and a second ohmic contact metal layer are deposited; the second ohmic contact metal layer is located on the upper surface of the first doped region; The switch control unit includes a semiconductor material layer, a third ohmic contact metal layer and a fourth ohmic contact metal layer located on the upper surface of the semiconductor material layer; a plurality of conductive plugs are disposed in the semiconductor material layer, which at least penetrate the semiconductor material layer; the first ohmic contact metal layer is electrically connected to the third ohmic contact metal layer through the conductive plugs; The second ohmic contact metal layer is electrically connected to the fourth ohmic contact metal layer through the conductive plug; The substrate, the drift layer, the first doped region, and the semiconductor material layer are of the first type of doping, while the first buried layer, the second buried layer, and the connecting pillar are of the second type of doping.

2. The composite chip structure according to claim 1, characterized in that, A bonding interface layer is provided on the upper surface of the first buried layer, and the semiconductor material layer is located on the upper surface of the bonding interface layer.

3. The composite chip structure according to claim 2, characterized in that, The material of the bonding interface layer is silicon dioxide or BCB.

4. The composite chip structure according to claim 2, characterized in that, The dimensions of the bonding interface layer along the direction from the substrate to the bonding interface layer are 1 nm to 10 μm.

5. The composite chip structure according to claim 1, characterized in that, The substrate is made of at least one of single-crystal SiC, polycrystalline SiC, and Si; or / and the drift layer is made of at least one of SiC, GaN, Ga2O3, and AlN; or / and the semiconductor material layer is made of at least one of silicon, GaN, and 3C-SiC.

6. The composite chip structure according to claim 1, characterized in that, The drift layer has a dimension of 1000 nm to 150 μm along the direction from the substrate to the first buried layer; or / and the first buried layer has a dimension of 10 nm to 500 nm along the direction from the substrate to the first buried layer; or / and the semiconductor material layer has a dimension of 100 nm to 10 μm along the direction from the substrate to the semiconductor material layer.

7. The composite chip structure according to claim 1, characterized in that, The switch control unit is any one of MOSFET device, HEMT device, NPN transistor, PNP transistor, JFET switch control unit or diode.

8. The composite chip structure according to claim 1, characterized in that, The conductive plug is made of at least one of titanium, titanium nitride, tungsten, aluminum, and copper.

9. The method for preparing the composite chip structure according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1. The drift layer is formed on the surface of one side of the substrate; a first buried layer is formed on the top layer or the upper surface of the drift layer; S2. Form the second buried layer and the connecting pillar in an island-like distribution in the drift layer, form the first doped region in the first buried layer, and anneal; S3. Deposit ohmic contact metal on the upper surface of the first buried layer and etch it to retain the area that needs to be electrically connected to other devices, to obtain the first ohmic contact metal layer and the second ohmic contact metal layer, and anneal it. A wide-bandgap semiconductor voltage-resistant cell was obtained; S4. Bond the semiconductor material layer to the upper surface of the wide bandgap semiconductor voltage withstand unit; S5. The switch control unit is fabricated in the semiconductor material layer; S6. In the corresponding area where the switch control unit and the wide bandgap semiconductor withstand voltage unit need to be electrically connected, a through hole that penetrates at least through the semiconductor material layer is etched; a first dielectric layer is deposited on the sidewall of the through hole, and then a conductive material is deposited on the upper surface of the semiconductor material layer and inside the through hole, and etched to obtain the conductive plug.

10. The preparation method according to claim 9, characterized in that, Includes the following steps: An isolation layer, a gate, and a source are fabricated on the upper surface of the device structure obtained in step S6, wherein the isolation layer isolates the gate and the source. A drain electrode is fabricated on the surface of the substrate opposite to the drift layer.

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