Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device, the array substrate comprises a substrate, the substrate comprises a plurality of sub-pixel areas, and each sub-pixel area comprises an opening area; the at least one gate insulation layer and the at least one passivation layer are arranged in a stacked mode, and at least one layer of the gate insulation layer and / or at least one layer of the passivation layer are / is arranged in the opening area in a hollowed-out mode.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation and easy to carry. It has been rapidly developed in recent years and has gradually replaced the traditional cathode ray tube display (CRT) and has occupied a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small sized products, covering almost all major electronic products in today's information society, such as LCD TV, high-definition digital TV, computer (desktop and notebook), mobile phone, tablet computer, navigation system, car display, projection display, video camera, digital camera, electronic watch, calculator, electronic instrument, meter, public display and virtual display, etc. Summary of the invention

[0003] The present disclosure provides an array substrate, a display panel and a display device, and the specific scheme is as follows:

[0004] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0005] A base substrate, the base substrate comprising a plurality of sub-pixel regions, and the sub-pixel regions comprising an opening region;

[0006] At least one gate insulating layer and at least one passivation layer are stacked, wherein at least one gate insulating layer and / or at least one passivation layer is hollowed out in the opening area.

[0007] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, all of the gate insulation layer is hollowed out in the opening area.

[0008] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the gate insulation layer is a multilayer, and the gate insulation layer includes a first gate insulation layer and a second gate insulation layer located on the side of the first gate insulation layer away from the base substrate, and one of the first gate insulation layer and the second gate insulation layer is hollowed out in the opening area, and the other covers the opening area.

[0009] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the material of the first gate insulating layer includes silicon nitride, and the thickness of the first gate insulating layer is The material of the second gate insulating layer includes silicon oxide, and the thickness of the second gate insulating layer is

[0010] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, all of the passivation layers cover the opening areas respectively.

[0011] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, all of the gate insulation layers respectively cover the opening areas.

[0012] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, all of the passivation layer is hollowed out in the opening area.

[0013] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the passivation layer is a multilayer, and the passivation layer includes a first passivation layer and a second passivation layer located on the side of the first passivation layer away from the base substrate, and one of the first passivation layer and the second passivation layer is hollowed out in the opening area, and the other covers the opening area.

[0014] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the material of the first passivation layer includes silicon oxide, and the thickness of the first passivation layer is The material of the second passivation layer includes silicon nitride, and the thickness of the second passivation layer is

[0015] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes an organic insulating layer located on a side of the passivation layer away from the gate insulating layer, and the organic insulating layer covers the opening area.

[0016] On the other hand, an embodiment of the present disclosure further provides a display panel, comprising the array substrate provided by the embodiment of the present disclosure, and an opposite substrate disposed opposite to the array substrate.

[0017] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by the embodiment of the present disclosure, and a backlight module located on the light incident side of the display panel, wherein the backlight module comprises a quantum dot light-emitting device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic structural diagram of a sub-pixel region in the related art;

[0019] Figure 2 For along Figure 1 Schematic diagram of the cross-sectional structure along line a-a';

[0020] Figure 3A schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure;

[0021] Figure 4 for Figure 3 A schematic diagram of the structure of a sub-pixel area;

[0022] Figure 5 For along Figure 4 A schematic diagram of a cross-sectional structure of b-b';

[0023] Figure 6 For along Figure 4 Schematic diagram of the cross-sectional structure of c-c'-c";

[0024] Figure 7 For along Figure 4 Schematic diagram of the cross-sectional structure of d-d'-d";

[0025] Figure 8 For along Figure 4 Schematic diagram of the cross-sectional structure along line e-e';

[0026] Fig. 9 for Figure 5 A flowchart of the manufacturing process of the laminated structure shown;

[0027] Fig.10 for Figure 6 A flowchart of the manufacturing process of the laminated structure shown;

[0028] Fig.11 for Figure 7 A flowchart of the manufacturing process of the laminated structure shown;

[0029] Fig.12 For along Figure 4 Another schematic diagram of the cross-sectional structure of b-b';

[0030] Fig.13 For along Figure 4 Another schematic diagram of the cross-sectional structure of b-b';

[0031] Fig.14 for Fig.12 A flowchart of the manufacturing process of the laminated structure shown;

[0032] Fig.15 for Fig.13 A flowchart of the manufacturing process of the laminated structure shown;

[0033] Fig.16 For along Figure 4 Another schematic diagram of the cross-sectional structure of b-b';

[0034] Fig.17 For along Figure 4 Another schematic diagram of the cross-sectional structure of b-b';

[0035] Fig.18 for Fig.16 A flowchart of the manufacturing process of the laminated structure shown;

[0036] Fig.19 for Fig.17 A flowchart of the manufacturing process of the laminated structure shown;

[0037] Fig. 20 For along Figure 4 Another schematic diagram of the cross-sectional structure of b-b';

[0038] Fig.21 for Fig. 20 A flowchart of the manufacturing process of the laminated structure shown;

[0039] Fig. 22 For along Figure 4 Another schematic diagram of the cross-sectional structure of b-b';

[0040] Fig.23 for Fig. 22 A flowchart of the manufacturing process of the laminated structure shown;

[0041] Fig.24 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0042] Fig.25 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thickness of the layers, films, panels, regions, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes do not reflect the exact shape of the illustrated areas, do not reflect the true proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0044] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0045] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] Figure 1 is a pixel unit structure in the related art, comprising Figure 1 It can be seen that the pixel electrode 104 is disposed in the area surrounded by the gate line GL and the data line DL. The pixel electrode 104 can form an electric field with the common electrode (Com) to control the rotation of the liquid crystal, so that the backlight passes through the liquid crystal to realize the picture display. Figure 2 For along Figure 1 The schematic diagram of the cross-sectional structure of the a-a' line is shown in Figure 1. Figure 2It can be seen that there are gate insulating layer 102 and passivation layer 103 between pixel electrode 104 and substrate 101. Therefore, in the actual picture display process, before the backlight is irradiated to the liquid crystal through pixel electrode 104, it needs to penetrate gate insulating layer 102 and passivation layer 103. However, due to the difference in refractive index between adjacent layers in gate insulating layer 102, the difference in refractive index between adjacent layers in passivation layer 103, the difference in refractive index between adjacent gate insulating layer 102 and passivation layer 103, and the uniformity of single-layer film thickness in gate insulating layer 102 and single-layer film thickness in passivation layer 103, etc., the penetrating colored light will produce constructive or destructive interference, causing color deviation, such as red, green, blue, uneven color at a large viewing angle, and other color deviation anomalies that are difficult to handle later. In addition, when quantum dot (QD) backlight is used, the gate insulating layer 102 and passivation layer 103 will have the effect of enhanced light wave interference with the spectrum of the backlight, so the color unevenness anomaly is more obvious.

[0047] In order to improve the above technical problems existing in the related art, the present disclosure provides an array substrate, such as Figures 3 to 7 As shown, it includes: a base substrate 101, the base substrate 101 includes a plurality of sub-pixel areas SPX (including but not limited to red sub-pixel areas, green sub-pixel areas and blue sub-pixel areas) defined by a plurality of gate lines GL and a plurality of data lines DL, optionally, the sub-pixel area SPX includes an opening area O for passing backlight, optionally, the opening area includes an area defined by the data lines DL and the gate lines GL, a pixel electrode 104 covers the opening area O, and the pixel electrode 104 is coupled to the first electrode D (for example, the source or drain) of the transistor TFT; the array substrate also includes at least one layer of gate insulating layer 102 and at least one layer of passivation layer 103 stacked, wherein at least one layer of the gate insulating layer 102 and / or at least one layer of the passivation layer 103 is hollowed out in the opening area O, in other words, at least one layer of the gate insulating layer 102 and / or at least one layer of the passivation layer 103 has no pattern in the opening area O.

[0048] In the above-mentioned array substrate provided in the embodiment of the present disclosure, by hollowing out at least one layer of the gate insulation layer 102 and / or at least one layer of the passivation layer 103 in the opening area O, on the one hand, the problem of color deviation caused by inconsistent penetration of light of different colors due to the uniformity of film thickness of at least one layer of the gate insulation layer 102 and / or at least one layer of the passivation layer 103 can be reduced; on the other hand, the number of film layers with different refractive indices is reduced, thereby reducing the constructive or destructive interference of light of different colors caused by the difference in refractive indices of adjacent insulation layers, thereby reducing color unevenness abnormalities.

[0049] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, Figures 4 to 7It can be seen that the entire gate insulating layer 102 is hollowed out in the opening region O, and the entire passivation layer 103 covers the opening region O (that is, the entire passivation layer 103 is not hollowed out in the opening region O). Figures 4 to 7 It is shown that the gate insulating layer 102 includes two layers, a first gate insulating layer 1021 and a second gate insulating layer 1022, and the first gate insulating layer 1021 and the second gate insulating layer 1022 are both hollowed out in the opening area O; the passivation layer 103 includes two layers, a first passivation layer 1031 and a second passivation layer 1032, and the first passivation layer 1031 and the second passivation layer 1032 both cover the opening area O. It should be understood that in other embodiments, the gate insulating layer 102 and the passivation layer 103 may also be a single film layer structure, and the present disclosure is described by taking the example that the gate insulating layer 102 includes the first gate insulating layer 1021 and the second gate insulating layer 1022, and the passivation layer 103 includes the first passivation layer 1031 and the second passivation layer 1032.

[0050] See also Figure 4 and Figure 8 It can be known that in the array substrate provided by the present disclosure, the first electrode D of the transistor TFT is coupled to the pixel electrode 104, the second electrode S of the transistor TFT is integrally arranged with the data line DL, a part of the gate line GL serves as the gate G of the transistor TFT, and a layer where the gate G is located (equivalent to the layer where the gate line GL is located), a first gate insulating layer 1021, a second gate insulating layer 1022, an active layer AC, a layer where the first electrode D and the second electrode S are located (equivalent to the layer where the data line DL is located), a first passivation layer 1031, a second passivation layer 1032, an organic insulating layer 105 and a layer where the pixel electrode 104 is located are sequentially arranged on the base substrate 101.

[0051] Among them, the first gate insulating layer 1021 and the second gate insulating layer 1022 can prevent water vapor from corroding the layer where the gate G is located (equivalent to the layer where the gate line GL is located), and the organic insulating layer 105, the first passivation layer 1031 and the second passivation layer 1032 can prevent the liquid crystal, the orientation layer (PI), and water vapor from corroding the layer where the first pole D and the second pole S are located (equivalent to the layer where the data line DL is located). In some embodiments, the organic insulating layer 105 may not be provided, that is, only the first passivation layer 1031 and the second passivation layer 1032 are used to protect the layer where the first pole D and the second pole S are located (equivalent to the layer where the data line DL is located). In the present disclosure, the array substrate including the organic insulating layer 105 is used as an example for description.

[0052] In some embodiments, in order to achieve a better protection effect against water vapor, etc., in the present disclosure, the material of the first gate insulating layer 1021 includes silicon nitride SiNx, which can be formed by ammonia NH 3 and silane SiH 4 Formation, specific, NH 3 :SiH 4=2:1~4:1, for example, NH 3 :SiH 4 is 2:1, 3:1, 4:1, etc., and the thickness of the first gate insulating layer 1021 is For example, the thickness of the first gate insulating layer 1021 is The material of the second gate insulating layer 1022 includes silicon oxide SiOx, which can be made of nitrous oxide N 2 O and silane SiH 4 Formation, specific, N 2 O:SiH 4 =20:1~40:1, for example, N 2 O:SiH 4 is 20:1, 30:1, 40:1, etc., and the thickness of the second gate insulating layer 1022 is For example, the thickness of the second gate insulating layer 1022 is etc.; the material of the first passivation layer 1031 includes silicon oxide SiOx, which can be made of nitrous oxide N 2 O and silane SiH 4 Formation, specific, N 2 O:SiH 4 =30:1~70:1, for example, N 2 O:SiH 4 is 30:1, 40:1, 50:1, 60:1, 70:1, etc., and the thickness of the first passivation layer 1031 is For example, the thickness of the first passivation layer 1031 is The material of the second passivation layer 1032 includes silicon nitride SiNx, which can be made of ammonia NH 3 and silane SiH 4 Formation, specific, NH 3 :SiH 4 =2:1~4:1, for example NH 3 :SiH 4 is 2:1, 3:1, 4:1, etc., and the thickness of the second passivation layer 1032 is For example, the thickness of the second passivation layer 1032 is The material of the organic insulating layer 105 may include at least one of polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy acrylic resin, and the thickness of the organic insulating layer 105 is For example, the thickness of the organic insulating layer 105 is wait.

[0053] In some embodiments, the coupling between the first electrode D of the transistor TFT and the pixel electrode 104 can be achieved by the following steps. The first step is to use a first mask to realize the production of the layer where the gate G is located (equivalent to the layer where the gate line GL is located); the second step is to form a first gate insulating layer 1021 and a second gate insulating layer 1022 on the layer where the gate line GL is located; the third step is to use a second mask process on the second gate insulating layer 1022 to realize the production of the active layer AC; the fourth step is to use a third mask process on the active layer AC to realize the production of the layer where the first electrode D and the second electrode S are located (equivalent to the layer where the data line DL is located), and the first electrode D and the second electrode S are ohmically connected to the active layer AC respectively; the fifth step is to use a second mask process on the active layer AC to realize the production of the first electrode D and the second electrode S. The layer where the first pole D and the second pole S are located (equivalent to the layer where the data line DL is located) forms the first passivation layer 1031, the second passivation layer 1032 and the organic insulating layer 105 in sequence, and the fourth mask process is used to form a through hole penetrating the first passivation layer 1031, the second passivation layer 1032 and the organic insulating layer 105; in the sixth step, the layer where the pixel electrode 104 is located is formed on the organic insulating layer 105 by the fifth mask process, and the pixel electrode 104 is coupled to the first pole D through the through hole penetrating the first passivation layer 1031, the second passivation layer 1032 and the organic insulating layer 105.

[0054] It is worth noting that for Figure 8 The arrangement scheme of the insulating layer in the opening area O shown in FIG. Figure 5 Specifically, after performing the second step and before performing the third step, as shown in the figure, the insulating layer in the opening region O can be provided. Fig. 9 As shown, a mask process can be added to expose, develop, and etch the first gate insulation layer 1021 and the second gate insulation layer 1022 in the opening area O, so that the first gate insulation layer 1021 and the second gate insulation layer 1022 in the opening area O are etched away; then the above-mentioned third to sixth steps can be carried out normally.

[0055] like Figure 4 , Figure 6 and Fig.10 As shown, cc' represents the section line at the position of the data line DL, and c'-c" represents the section line along the direction of cc' and located at the opening area O; Fig.10(A) in the figure shows a schematic diagram of the structure of the first gate insulating layer 1021 and the second gate insulating layer 1022 after film formation; (B) shows a schematic diagram of the cross-sectional structure of the first gate insulating layer 1021 and the second gate insulating layer 1022 along the c-c'-c" section line after exposure and development, in which the photoresist PR covers the c-c' region (i.e., the metal region of the data line DL), and at the same time, the photoresist PR exposes the c'-c" region (i.e., the opening region O); (C) shows an etching process, in which, after etching, the c-c' region is covered by the photoresist PR, so the first gate insulating layer 1021 and the second gate insulating layer 1022 in the c-c' region are retained, and the c'-c" region is not. There is a photoresist PR covering, so the first gate insulating layer 1021 and the second gate insulating layer 1022 in the c'-c" area are etched away; (D) represents the production of the data line DL located in the c-c' area; (E) represents the stacked structure of the c-c'-c" cross section after the transistor TFT is produced, wherein the stacked structure in the c-c' area includes the first gate insulating layer 1021, the second gate insulating layer 1022, the data line DL, the first passivation layer 1031, the second passivation layer 1032 and the organic insulating layer 105 arranged in sequence, and the stacked structure in the c'-c" area includes the first passivation layer 1031, the second passivation layer 1032 and the organic insulating layer 105 arranged in sequence.

[0056] like Figure 4 , Figure 7 and Fig.11 As shown, d-d' represents the section line at the position of the gate line GL, and d'-d" represents the section line along the direction of d-d' and located in the opening area O; Fig.11(A) in the figure shows a schematic diagram of the structure after the gate line GL is made; (B) shows a schematic diagram of the structure after the first gate insulating layer 1021 and the second gate insulating layer 1022 are formed; (C) shows a schematic diagram of the cross-sectional structure of the first gate insulating layer 1021 and the second gate insulating layer 1022 along the d-d'-d" section line after exposure and development, the photoresist PR will cover the d-d' area (i.e., the metal area of ​​the gate line GL), and the photoresist PR will expose the d'-d" area (i.e., the opening area O); (D) shows the etching process, after etching, the d-d' area is covered by the photoresist PR, so the first gate insulating layer 1021 and the second gate insulating layer 1022 in the d-d' area are The gate insulating layer 1022 is retained, and the d'-d" region is not covered by the photoresist PR, so the first gate insulating layer 1021 and the second gate insulating layer 1022 in the d'-d" region are etched away; (E) represents the stacked structure of the d-d'-d" cross section after the transistor TFT is manufactured, wherein the stacked structure in the d-d' region includes the gate line GL, the first gate insulating layer 1021, the second gate insulating layer 1022, the first passivation layer 1031, the second passivation layer 1022 and the organic insulating layer 105 arranged in sequence, and the stacked structure in the d'-d" region includes the first passivation layer 1031, the second passivation layer 1032 and the organic insulating layer 105 arranged in sequence.

[0057] In the above array substrate provided in the embodiment of the present disclosure, in addition to the above configuration that the first gate insulating layer 1021 and the second gate insulating layer 1022 are both hollowed out in the opening area O, Figure 4 , Fig.12 and Fig.13 As shown, one of the first gate insulating layer 1021 and the second gate insulating layer 1022 may be hollowed out in the opening region O, and the other may cover the opening region O, for example, Figure 4 and Fig.12 In the embodiment, the second gate insulating layer 1022 is hollowed out in the opening region O, and the first gate insulating layer 1021 covers the opening region O. Figure 4 and Fig.13 In the embodiment, the first gate insulating layer 1021 is hollowed out in the opening area O, and the second gate insulating layer 1022 covers the opening area O. As the thickness of the film increases, the uniformity of the film thickness decreases, the interference between the film layer and the light increases, and the color deviation is more likely to occur. In the present disclosure, the thickness of the first gate insulating layer 1021 is The thickness of the second gate insulating layer 1022 is Therefore, the uniformity of the thickness of the first gate insulating layer 1021 is not as good as that of the second gate insulating layer 1022. Based on this, the solution disclosed in the present invention that the first gate insulating layer 1021 is hollowed out in the opening area O and the second gate insulating layer 1022 with better uniformity of thickness is retained in the opening area O can better improve the poor color deviation compared with the solution that the second gate insulating layer 1022 is hollowed out in the opening area O and the first gate insulating layer 1021 with slightly worse uniformity of thickness is retained in the opening area O.

[0058] In some embodiments, Figure 4 and Fig.12 The film layer stacking structure in the opening area O shown in the present disclosure can be adopted Fig.14 Specifically, after forming the first gate insulating layer 1021 and the second gate insulating layer 1022, a mask process can be added to expose, develop, and etch the second gate insulating layer 1022 in the opening area O, so that the second gate insulating layer 1022 is hollowed out in the opening area O, and the first gate insulating layer 1021 is retained in the opening area O; the film layers, the first passivation layer 1031, the second passivation layer 1032, the organic insulating layer 105, and the pixel electrode 104 of the crystalline TFT can be manufactured according to the relevant process, which will not be described in detail here. In addition, for Figure 4 and Fig.13 The film layer stacking structure in the opening area O shown in the present disclosure can be adopted Fig.15 Specifically, after forming the first gate insulating layer 1021, a mask process may be added to expose, develop and etch the first gate insulating layer 1021 in the opening area O, so that the first gate insulating layer 1021 is hollowed out in the opening area O. The second gate insulating layer 1022, the film layers of the crystalline TFT, the first passivation layer 1031, the second passivation layer 1032, the organic insulating layer 105 and the pixel electrode 104 may be manufactured according to relevant processes, which will not be elaborated here.

[0059] In some embodiments, Figure 4 , Fig.16 and Fig.17 As shown, the present disclosure may also configure all the passivation layers 103 (e.g., the first passivation layer 1031 and the second passivation layer 1032) to be hollowed out in the opening area O, or a layer of the passivation layer 103 (e.g., the first passivation layer 1031 or the second passivation layer 1032) to be hollowed out in the opening area O. Fig.17 Specifically, the first passivation layer 1031 is hollowed out in the opening area O. The thickness of the first passivation layer 1031 in the present disclosure is The thickness of the second passivation layer 1032 is Therefore, the thickness of the first passivation layer 1031 is greater than that of the second passivation layer 1032 . The first passivation layer 1031 has a greater influence on the color deviation than the second passivation layer 1032 . By hollowing out the first passivation layer 1031 in the opening area O, the color deviation can be improved better.

[0060] In some embodiments, Figure 4 and Fig.16 The film layer stacking structure in the opening area O shown in the present disclosure can be adopted Fig.18 Specifically, after forming the first gate insulating layer 1021, the second gate insulating layer 1022, the first passivation layer 1031 and the second passivation layer 1032, a mask process can be added to expose, develop and etch the first passivation layer 1031 and the second passivation layer 1032 in the opening area O, so that the first passivation layer 1031 and the second passivation layer 1032 are hollowed out in the opening area O, and the first gate insulating layer 1021 and the second gate insulating layer 1022 are retained in the opening area O; the film layers, the organic insulating layer 105 and the pixel electrode 104 of the crystalline TFT can be manufactured according to the relevant process, which will not be described in detail here. In addition, for Figure 4 and Fig.17 The film layer stacking structure in the opening area O shown in the present disclosure can be adopted Fig.19 The process shown is carried out for production. Specifically, after forming the first gate insulating layer 1021, the second gate insulating layer 1022, the first passivation layer 1031 and the second passivation layer 1032, a mask process can be added to expose, develop and etch the second passivation layer 1032 in the opening area O, so that the second passivation layer 1032 is hollowed out in the opening area O, and the first passivation layer 1031, the first gate insulating layer 1021 and the second gate insulating layer 1022 are retained in the opening area O; the various film layers, the organic insulating layer 105 and the pixel electrode 104 of the crystalline TFT can be produced according to relevant processes, which will not be described in detail here.

[0061] In some embodiments, Figure 4 and Fig. 20 As shown, the present disclosure can also set all the passivation layers 103 (such as the first passivation layer 1031 and the second passivation layer 1032) and a layer of the gate insulation layer 102 (such as the second gate insulation layer 1022) to be hollowed out in the opening area O. Figure 4 and Fig. 20It can be seen that after the first passivation layer 1031, the second passivation layer 1032, and the second gate insulating layer 1022 are removed from the opening area O, only the first gate insulating layer 1021 and the organic insulating layer 105 are retained. Therefore, the color deviation caused by the different refractive indices of adjacent film layers is greatly reduced. Based on the same principle, in some embodiments, the present disclosure can also set all gate insulating layers 102 (such as the first gate insulating layer 1021 and the second gate insulating layer 1022) and a passivation layer 103 (such as the first passivation layer 1031 or the second passivation layer 1032) to be hollowed out in the opening area O, which is not limited here.

[0062] In some embodiments, Figure 4 and Fig. 20 The film layer stacking structure in the opening area O shown in the present disclosure can be adopted Fig.21 The process shown is carried out for production. Specifically, after forming the first gate insulating layer 1021, the second gate insulating layer 1022, the first passivation layer 1031 and the second passivation layer 1032, a mask process can be added to expose, develop and etch the first passivation layer 1031, the second passivation layer 1032 and the second gate insulating layer 1022 in the opening area O, so that the first passivation layer 1031, the second passivation layer 1032 and the second gate insulating layer 1022 are hollowed out in the opening area O, and the first gate insulating layer 1021 is retained in the opening area O; the various film layers, the organic insulating layer 105 and the pixel electrode 104 of the crystalline TFT can be produced according to relevant processes, which will not be described in detail here.

[0063] In some embodiments, Figure 4 and Fig. 22 As shown, the present disclosure may further include a passivation layer 103 (eg, a first passivation layer 1031) and a gate insulating layer 102 (eg, a first gate insulating layer 1022) which are hollowed out in the opening region O. Figure 4 and Fig. 22 It can be seen that after removing the first passivation layer 1031 and the first gate insulating layer 1021 in the opening area O, the three insulating layers of the second gate insulating layer 1022, the second passivation layer 1032 and the organic insulating layer 105 are retained, thereby reducing the color deviation caused by the different refractive indices of adjacent film layers to a certain extent.

[0064] In some embodiments, Figure 4 and Fig. 22 The film layer stacking structure in the opening area O shown in the present disclosure can be adopted Fig.23The process shown is used for production. Specifically, after forming the first gate insulating layer 1021, a mask process can be added to expose, develop and etch the first gate insulating layer 1021 in the opening area O, so that the first gate insulating layer 1021 is hollowed out in the opening area O; then, a second gate insulating layer 1022 and a first passivation layer 1031 are formed on the first gate insulating layer 1021, and another mask process is added to expose, develop and etch the first passivation layer 1031 in the opening area O, so that the first passivation layer 1031 is hollowed out in the opening area O; the film layers, the second passivation layer 1032, the organic insulating layer 105 and the pixel electrode 104 of the crystalline TFT can be manufactured according to relevant processes, which will not be repeated here.

[0065] It is worth noting that Figure 5 , Fig.12 , Fig.13 , Fig.16 , Fig.17 , Fig. 20 and Fig. 22 As shown, in the present disclosure, one, two or three layers of the first gate insulating layer 1021, the second gate insulating layer 1022, the first passivation layer 1031 and the second passivation layer 1032 are retained between the base substrate 101 and the pixel electrode 104. This is because the first gate insulating layer 1021, the second gate insulating layer 1022, the first passivation layer 1031 and the second passivation layer 1032 are all inorganic insulating layers with good adhesion to the base substrate 101. Compared with the solution in which the pixel electrode 104 directly contacts the base substrate 101, it can effectively prevent the pixel electrode 104 from abnormally falling off due to weak adhesion.

[0066] In addition, the present disclosure only etches and removes at least one layer of the first gate insulating layer 1021, the second gate insulating layer 1022, the first passivation layer 1031, and the second passivation layer 1032 in the opening area O, and does not etch and remove the organic insulating layer 105 in the opening area O. This is because the thickness of the organic insulating layer 105 is In the process of etching the thick organic insulating layer 105, there is a problem of etching uniformity. Of course, in some embodiments, the organic insulating layer 105 in the opening area O may also be etched away, which is not limited here.

[0067] In addition, Fig.12 , Fig.13 , Fig.16 , Fig.17 , Fig. 20 and Fig. 22 Under the different film layer stacking structures of the opening area O shown in FIG. Figure 4 The cross-sectional structure at c-c') and the gate line GL (ie Figure 4 The cross-sectional structure at d-d') can be seen in Figure 6 The cross-sectional structure of c-c' shown, and Figure 7 The cross-sectional structure of d-d' is not described in detail here.

[0068] It can be seen from the above content that the present disclosure adds one or several mask processes in the process of manufacturing the array substrate to etch the insulating film layer in the opening area O, wherein the insulating film layer includes but is not limited to the gate insulating layer 102, the passivation layer 103, the organic insulating layer 105, etc., so as to achieve the purpose of flexibly adjusting the structure and thickness of the insulating film layer in the opening area O; in the specific implementation process, it can be used for single-layer etching of the gate insulating layer 102, the passivation layer 103, the organic insulating layer 105, etc., and can also be used for cross-layer etching of the gate insulating layer 102, the passivation layer 103, the organic insulating layer 105, or only a part of a specific film layer of the gate insulating layer 102, the passivation layer 103, the organic insulating layer 105 can be etched, or a new film can be formed after etching, which is not specifically limited here.

[0069] It should be noted that in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process such as deposition, photoresist coating, mask template masking, exposure, development, etching, photoresist stripping, etc., but also other process, which is subject to the graphics of the required composition formed in the actual manufacturing process, and is not limited here. For example, a post-baking process may also be included after development and before etching. Among them, the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here; the mask used in the mask process may be a half-tone mask (Half Tone Mask), a single slit diffraction mask (Single Slit Mask) or a gray tone mask (Gray Tone Mask), which is not limited here; etching may be dry etching or wet etching, which is not limited here.

[0070] Based on the same inventive concept, the embodiment of the present disclosure provides a display panel, such as Fig.24 As shown, it includes the above-mentioned array substrate 001 provided for the embodiment of the present disclosure, and an opposite substrate 002 arranged opposite to the array substrate 001.

[0071] Alternatively, if Fig.24 As shown, the counter substrate 002 includes a common electrode 201, and the common electrode 201 is disposed on the entire surface of the display area AA. In some embodiments, the common electrode 201 can also be disposed on the array substrate, which is not limited here. The present disclosure is described by taking the common electrode 201 disposed on the counter substrate 002 as an example. Fig.24It can be known that the counter substrate 002 may further include a black matrix 202, which is a grid-like structure. Optionally, the orthographic projection of the gate line GL on the base substrate 101 is located within the orthographic projection of the black matrix 202 on the base substrate 101, and the orthographic projection of the data line DL on the base substrate 101 is located within the orthographic projection of the black matrix 202 on the base substrate 101. In some embodiments, the counter substrate 002 may further include a color resist 203 and a substrate 204. Optionally, the color resist 203 includes a red color resist corresponding to a red sub-pixel region, a blue color resist corresponding to a blue sub-pixel region, and a green color resist corresponding to a green sub-pixel region; the substrate 204 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or other materials.

[0072] In some embodiments, Fig.24 As shown, the display panel provided by the embodiment of the present disclosure may also include a liquid crystal layer 003 between the array substrate 001 and the counter substrate 002. In some embodiments, a first polarizer may be provided on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer may be provided on the side of the counter substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer. Other essential components of the display panel should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.

[0073] Based on the same inventive concept, the present disclosure provides a display device, such as Fig.25 As shown, it includes the above-mentioned display panel PN provided by the embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PN. The backlight module BLU can be a direct-type backlight module or an edge-entry backlight module. Optionally, the edge-entry backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., which are stacked, and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film, which are stacked on the light-emitting side of the matrix light source, and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices. Since the gate insulating layer 102 and the passivation layer 103 will have the effect of enhancing the interference of light waves with the spectrum of the backlight after using quantum dot (QD) backlight, the color unevenness abnormality is more obvious. The present disclosure can reduce the interference between the QD backlight and the insulating layer by removing at least one layer of the gate insulating layer 102 and / or at least one layer of the passivation layer 103 in the opening region O, thereby effectively improving color unevenness.

[0074] In some embodiments, the lamp beads can also be micro-light-emitting devices (such as Mini LED, Micro LED), etc. Submillimeter or even micron-level micro-light-emitting devices are self-luminous devices like organic light-emitting devices (OLED). Like organic light-emitting devices, it has a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, it has the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting devices based on organic matter. And when the micro-light-emitting device is used as a backlight source, a more precise dynamic backlight effect can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare phenomenon caused by traditional dynamic backlight between the bright and dark areas of the screen, and optimize the visual experience.

[0075] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip may also include a memory, and may also include a power module, and the like, and realize power supply and signal input and output functions through additionally provided wires, signal lines, and the like. For example, the control chip may also include a hardware circuit and a computer executable code, and the like. The hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, and the like. In addition, those skilled in the art will appreciate that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0076] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0077] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein: include: A base substrate, the base substrate comprising a plurality of sub-pixel regions, and the sub-pixel regions comprising an opening region; At least one gate insulating layer and at least one passivation layer are stacked, wherein at least one gate insulating layer and / or at least one passivation layer is hollowed out in the opening area.

2. The array substrate according to claim 1, wherein: The entire gate insulation layer is hollowed out in the opening area.

3. The array substrate according to claim 1, wherein: The gate insulating layer is a multilayer layer, comprising a first gate insulating layer and a second gate insulating layer located on a side of the first gate insulating layer away from the substrate, one of the first gate insulating layer and the second gate insulating layer is hollowed out in the opening area, and the other covers the opening area.

4. The array substrate according to claim 3, wherein: The material of the first gate insulating layer includes silicon nitride, and the thickness of the first gate insulating layer is The material of the second gate insulating layer includes silicon oxide, and the thickness of the second gate insulating layer is 5. The array substrate according to any one of claims 2 to 4, wherein: All of the passivation layers cover the opening areas respectively.

6. The array substrate according to claim 1, wherein: All of the gate insulation layers cover the opening areas respectively.

7. The array substrate according to any one of claims 1 to 4 and 6, wherein: The entire passivation layer is hollowed out in the opening area.

8. The array substrate according to any one of claims 1 to 4 and 6, wherein: The passivation layer is a multilayer layer, including a first passivation layer and a second passivation layer located on a side of the first passivation layer away from the substrate. One of the first passivation layer and the second passivation layer is hollowed out in the opening area, and the other covers the opening area.

9. The array substrate according to claim 8, wherein: The material of the first passivation layer includes silicon oxide, and the thickness of the first passivation layer is The material of the second passivation layer includes silicon nitride, and the thickness of the second passivation layer is 10. The array substrate according to any one of claims 1 to 9, wherein: It also includes an organic insulating layer located on a side of the passivation layer away from the gate insulating layer, and the organic insulating layer covers the opening area.

11. A display panel, wherein: It comprises the array substrate according to any one of claims 1 to 10, and an opposite substrate arranged opposite to the array substrate.

12. A display device, wherein: It comprises the display panel as claimed in claim 11, and a backlight module located on the light incident side of the display panel, wherein the backlight module comprises a quantum dot light emitting device.

Images