Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a substrate, a first metal layer arranged on one side of the substrate in an insulating mode, a second metal layer arranged on the side, away from the substrate, of the first metal layer in an insulating mode, and a third metal layer arranged on the side, away from the first metal layer, of the second metal layer in an insulating mode. The third metal layer comprises a reset signal line and a first power signal line which are arranged at an interval, and the reset signal line and the first power signal line extend in the first direction and are arranged in the second direction perpendicular to the first direction. According to the invention, the layout of the signal wires is optimized, and the arrangement of all the signal wires can be realized only through three metal layers, so that the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] For a long time, with the development of display technology, users have been pursuing high-resolution, high-brightness, and low-power display panels. However, as the resolution of display panels continues to increase, the number of pixel units in the display area increases, resulting in increasing signal line delay (loading), and thus increasing power consumption. Summary of the invention

[0003] An object of the present invention is to provide an array substrate and a display panel to solve the problem of signal line delay in the prior art.

[0004] To achieve the above object, the present invention provides an array substrate, the array substrate comprising a substrate, a first metal layer insulated on one side of the substrate, a second metal layer insulated on a side of the first metal layer away from the substrate, and a third metal layer insulated on a side of the second metal layer away from the first metal layer. The third metal layer comprises a reset signal line and a first power signal line, the reset signal line and the first power signal line both extend in a first direction and are arranged in a second direction perpendicular to the first direction. The reset signal line is spaced apart from the first power signal line.

[0005] Furthermore, the second metal layer includes a second power signal line in a mesh structure. Preferably, the reset signal line and the first power line are alternately arranged along the second direction.

[0006] Further, the second metal layer includes a first signal connection line extending along the second direction. The first signal connection line is connected to the reset signal line. Preferably, the first signal connection line is insulated from other signal lines in the second metal layer.

[0007] Further, the reset signal line includes a first reset line and a second reset line. The first reset line extends along the first direction and is arranged along the second direction. The second reset line intersects with the first reset line and is connected to the first signal connection line. Preferably, the orthographic projection of the first signal connection line on the substrate is located between the orthographic projection of the first reset line on the substrate and the orthographic projection of the first power signal line on the substrate. Preferably, the shape of the first reset line is the same as that of the first power signal line.

[0008] Furthermore, the first metal layer includes a first electrode plate, and the second metal layer also includes a second electrode plate, the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and a storage capacitor is formed between the first electrode plate and the second electrode plate. Preferably, the second electrode plate is connected to the second power signal line.

[0009] Furthermore, the third metal layer further includes a second signal connection line, the second signal connection line is insulated from the reset signal line and the first power signal line, one end of the second signal connection line is connected to the reset transistor, and the other end of the second signal connection line is connected to the drive transistor.

[0010] Further, the materials of the first metal layer, the second metal layer and the third metal layer include at least one metal material. Preferably, the materials of the second metal layer and the materials of the third metal layer include at least two metal materials respectively. Preferably, the metal materials include at least one or more of molybdenum, aluminum, titanium, silver, copper and nickel. Preferably, the array substrate further includes a semiconductor layer, the semiconductor layer is arranged on one side of the substrate, and the first metal layer is insulated and arranged on a side of the semiconductor layer away from the substrate.

[0011] Furthermore, the third metal layer further comprises a data signal line, the data signal line extends along the first direction and is arranged along the second direction. Preferably, one data signal line is provided between the reset signal line and an adjacent first power signal line.

[0012] Further, the first metal layer includes a scan signal line and a light-emitting control signal line, the scan signal line and the light-emitting control signal line both extend along the second direction and are arranged along the first direction. Preferably, the orthographic projection of the second power signal line on the substrate is located between the orthographic projection of the scan signal line and the orthographic projection of the light-emitting control signal line on the substrate.

[0013] The present invention further provides a display panel, which includes the array substrate as described above.

[0014] The advantages of the present invention are: in an array substrate and a display panel of the present invention, the layout of the signal lines is optimized, so that one metal layer can be removed on the basis of four metal layers, and the arrangement of all signal lines can be realized by only three metal layers, which can reduce the production cost while realizing the lightweight and thinning of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a schematic top view of an array substrate in an embodiment of the present invention;

[0017] Figure 2 is a wiring diagram of an array substrate in an embodiment of the present invention;

[0018] Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure of the array substrate at the AA' line;

[0019] Figure 4 It is a schematic diagram of wiring of the semiconductor layer and the first metal layer in an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of wiring of a semiconductor layer, a first metal layer, and a second metal layer in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of wiring of the first metal layer in an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of wiring of the second metal layer in an embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram of wiring of the third metal layer in an embodiment of the present invention;

[0024] Fig. 9 FIG. 4 is a circuit diagram of a pixel driving circuit in an embodiment of the present invention.

[0025] The components in the figure are shown as follows:

[0026] Array substrate 1; First sub-pixel 11;

[0027] Second sub-pixel 12; Substrate 100;

[0028] Semiconductor layer 200; First metal layer M1;

[0029] Scan signal line Scan; First scan line Scan1;

[0030] A second scanning line Scan2; a light emitting control signal line EM;

[0031] A second metal layer M2; A second power signal line VDD;

[0032] A first power supply line VDD1; A second power supply line VDD2;

[0033] A first signal connection line S1; A third metal layer M3;

[0034] Data signal line Data; First power signal line VSS;

[0035] Reset signal line Vi; First reset line Vi1;

[0036] A second reset line Vi2; A second signal connection line S2;

[0037] Insulating film layer 300; Storage capacitor Cst;

[0038] The first electrode plate C1; The second electrode plate C2. DETAILED DESCRIPTION

[0039] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0040] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0041] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0042] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted on" or "connected to" another component, the two may be understood to be directly "mounted on" or "connected", or one component may be indirectly "mounted on" or "connected to" another component via an intermediate component.

[0043] In the relevant display technology, a 7T1C (7 thin film transistors and 1 capacitor) type pixel driving circuit is usually used to drive the display panel, that is, a single light-emitting unit has 7 thin film transistors and 1 capacitor to drive it to emit light. However, the 7T1C type array substrate usually uses 4 layers of metal for routing design. The inventors of this application found that more metal layers are not conducive to reducing production costs. In addition, the inventors of this application also found that the power signal line VDD in the relevant display technology is usually a unidirectional extension structure with a large resistance, which is prone to signal loading, thereby generating signal delay (Loading), which will eventually affect the screen display effect of the panel.

[0044] Based on the above research findings of the inventors, an array substrate 1 is provided in an embodiment of the present invention. The array substrate 1 realizes the layout of display signal lines by only three metal layers, which reduces one metal layer compared to the array substrate 1 in the related display technology. Specifically, Figure 3 As shown, the array substrate 1 includes a substrate 100, a semiconductor layer 200, a first metal layer M1, a second metal layer M2 and a third metal layer M3 which are stacked in sequence. The substrate 100 may be a flexible substrate 100 or a rigid substrate 100, the semiconductor layer 200 is arranged on the surface of the substrate 100, the first metal layer M1 is insulated and arranged on a side of the semiconductor layer 200 away from the substrate 100, the second metal layer M2 is insulated and arranged on a side of the first metal layer M1 away from the semiconductor layer 200, and the third metal layer M3 is insulated and arranged on a side of the second metal layer M2 away from the first metal layer M1. Furthermore, the array substrate 1 also includes an insulating film layer 300 arranged between any two metal layers, and the insulating film layer 300 may be at least one of an organic insulating film layer or an inorganic insulating film layer such as an interlayer dielectric layer, a passivation layer, and a flat layer, which is used to insulate and protect the corresponding metal layer. The third metal layer M3 includes a first power signal line VSS and a reset signal line Vi, both of which extend along a first direction X and are arranged along a second direction Y, wherein the first power signal line VSS and the reset signal line Vi are spaced apart. The present application optimizes the layout of the signal lines to achieve a simplified arrangement of all signal lines, thereby achieving a thinner panel and reducing production costs.

[0045] The first metal layer M1, the second metal layer M2 and the third metal layer M3 are respectively provided with a plurality of signal wirings, and these signal wirings are combined to form a Figure 1 The pixel circuit shown in FIG. 1 is provided with a plurality of array-arranged sub-pixels in the array substrate 1, and the sub-pixels include a first sub-pixel column and a second sub-pixel column arranged at intervals in the second direction Y. The first sub-pixel column is provided with a plurality of first sub-pixels 11 arranged along the first direction X, and the second sub-pixel column is provided with a plurality of second sub-pixels 12 arranged along the first direction X. The first direction X is perpendicular to the second direction Y.

[0046] like Figure 2 , Figure 4 , Figure 5 as well as Figure 6 As shown in the figure, the first metal layer M1 includes a scan signal line Scan and a light-emitting control signal line EM, and the scan signal line Scan includes a first scan line Scan1 and a second scan line Scan2. The first scan line Scan1, the second scan line Scan2 and the light-emitting control signal line EM are insulated from each other, and all extend along the second direction Y and are arranged along the first direction X. The first scan line Scan1, the second scan line Scan2 and the light-emitting control signal line EM extend from the first sub-pixel 11 to the second sub-pixel 12, and each row of sub-pixels has the first scan line Scan1, the second scan line Scan2 and the light-emitting control signal line EM. In the same sub-pixel, a first scan line Scan1 and a light-emitting control signal line EM are arranged alternately, and a second scan line Scan2 is arranged on the side of the light-emitting control signal line EM away from the first scan line Scan1, that is, in the same sub-pixel, the light-emitting control line EM is located between the first scan line Scan1 and the second scan line Scan2.

[0047] like Figure 2 , Figure 5 as well as Figure 7As shown in , the second metal layer M2 includes a second power signal line VDD, and the second power signal line VDD is in a mesh structure. Specifically, the second power signal line VDD includes a plurality of first power lines VDD1 and second power lines VDD2 that are arranged to intersect. The first power line VDD1 extends along the first direction X and is arranged along the second direction Y, and the second power line VDD2 extends along the second direction Y and is arranged along the first direction X. Each column of sub-pixels has a first power line VDD1, and each row of sub-pixels also has a second power line VDD2. Each sub-pixel has an intersection point between the first power line VDD1 and the corresponding second power line VDD2, thereby forming a second power signal line VDD with a mesh structure. Compared with the power signal line with a unidirectional routing structure in the related display technology, the impedance of the second power signal line VDD with a mesh structure in the embodiment of the present invention is lower, thereby preventing the occurrence of signal load in the second power signal line VDD, thereby solving the delay (Loading) problem of the display panel.

[0048] Furthermore, if Figure 2 , Figure 4 and Figure 7 As shown in , the first metal layer M1 and the second metal layer M2 also include a first electrode plate C1 and a second electrode plate C2, respectively. The first electrode plate C1 is located in the first metal layer M1, and the second electrode plate C2 is located in the second metal layer M2. Each sub-pixel has a first electrode plate C1 and a second electrode plate C2, and the orthographic projection of the first electrode plate C1 on the substrate 100 overlaps with the orthographic projection of the second electrode plate C2 on the substrate 100 at least partially, so as to form a storage capacitor Cst between the first electrode plate C1 and the second electrode plate C2. Among them, the first electrode plate C1 can be connected to the driving transistor in the array substrate 1, and the second electrode plate C2 is connected to the second power signal line VDD. Further, in the same sub-pixel, the orthographic projection of the first electrode plate C1, the second electrode plate C2 and the second power signal line VDD2 on the substrate 100 is located between the orthographic projection of the first scan line Scan1 and the light emitting control signal line EM on the substrate 100.

[0049] like Figure 2 , Figure 5 as well as Figure 8As shown in , the third metal layer M3 includes a data signal line Data, a first power signal line VSS and a reset signal line Vi, the data signal line Data, the first power signal line VSS and the reset signal line Vi all extend along the first direction X and are arranged along the second direction Y, and the data signal line Data, the first power signal line VSS and the reset signal line Vi are insulated from each other and do not intersect. Among them, the first power signal line VSS and the reset signal line Vi are arranged alternately with each other, and each column of sub-pixels has only one first power signal line VSS or one reset signal line Vi, and a data signal line Data is also arranged between the reset signal line Vi and the adjacent first power signal line VSS; that is: each column of sub-pixels has a data signal line Data, each column of the first sub-pixels has a first power signal line VSS, and each column of the second sub-pixels has a reset signal line Vi.

[0050] Specifically, the second metal layer M2 also includes a first signal connection line S1 extending along the second direction Y. The first signal connection line S1 is arranged between two adjacent first power lines VDD1 and is insulated from the second power signal line VDD. One end of the first signal connection line S1 is located in the first sub-pixel 11, and the other end thereof is located in the second sub-pixel 12. Among them, one end of the first signal connection line S1 located in the first sub-pixel 11 is electrically connected to the reset transistor, and one end thereof located in the second sub-pixel 12 is electrically connected to the reset signal line Vi. The reset signal line Vi transmits the reset signal to the reset transistor in the first sub-pixel 11 through the first signal connection line S1. The arrangement of the first signal connection line S1 adds a connection channel (i.e., the first signal connection line S1) in another direction on the basis of the reset signal line Vi extending in one direction, so that a grid-like structure can be formed while realizing a single reset signal line controlling multiple columns of sub-pixels, thereby preventing the phenomenon of signal load in the reset signal line Vi, thereby solving the signal delay (Loading) problem.

[0051] Further, the reset signal line Vi includes a first reset line Vi1 and a second reset line Vi2. The first reset line Vi1 extends along the first direction X and is arranged along the second direction Y, and the second reset line Vi2 extends along the second direction Y and is arranged along the first direction X, so that the first reset line Vi1 and the second reset line Vi2 are intersected and connected. Preferably, the shape of the first reset line Vi1 is the same as the shape of the first power signal line VSS. The same routing shape can simplify the routing layout design in the third metal layer M3 and reduce the difficulty of production. The orthographic projection of the first signal connection line S1 on the substrate 100 is located between the orthographic projection of the first reset line Vi1 and the first power signal line VSS on the substrate 100, and the orthographic projection of the first signal connection line S1 on the substrate 100 does not overlap with the orthographic projection of the first reset line Vi1 and the first power signal line VSS on the substrate 100, thereby preventing the first signal connection line S1 from affecting other conductive structures (such as transistors) located below the first reset line Vi1. The orthographic projection of one end of the first signal connection line S1 located in the second sub-pixel 12 on the substrate 100 at least partially overlaps with the orthographic projection of the second reset line Vi2 on the substrate 100, so that the second reset line Vi2 can be electrically connected to the first signal connection line S1 through the via, and the first signal connection line S1 can be electrically connected to the reset signal line Vi through the auxiliary connection of the second reset line Vi2.

[0052] Furthermore, the third metal layer M3 also includes a second signal connection line S2 extending along the first direction X, and each sub-pixel has a second signal connection line S2. In the first sub-pixel 11, the second signal connection line S2 is located between the data signal line Data and the first power signal line VSS. In the second sub-pixel 12, the second signal connection line S2 is located between the data signal line Data and the reset signal line Vi. In the same sub-pixel, one end of the second signal connection line S2 is connected to the driving transistor, and the other end thereof is connected to the node. In other embodiments of the present invention, the node is also connected to the reset transistor, the compensation transistor and the storage capacitor Cst, which is not limited in the embodiments of the present invention.

[0053] In related display technologies, the reset signal line is generally set in a separate layer, but in the embodiment of the present invention, the reset signal line Vi is set in the third metal layer M3, and the second electrode plate in the same layer as the reset signal line in the related display technology is set in the second metal layer M2, so that the metal layer used to set the reset signal line and the second electrode plate in the related display technology can be removed. Therefore, compared with the array substrate with 4 metal layers in the related display technology, the array substrate 1 provided in the embodiment of the present invention only needs 3 metal layers to realize the arrangement of all signal routings. While reducing one metal layer, the insulating film layer for insulating and protecting the corresponding metal layer can also be reduced, which is conducive to realizing lightweight display and can also reduce the production cost of the product.

[0054] The materials of the first metal layer M1, the second metal layer M2 and the third metal layer M3 all contain at least one metal material with excellent electrical conductivity, such as at least one or more of molybdenum (Mo), aluminum (Al), titanium (Ti), silver (Ag), copper (Cu) and nickel (Ni). Preferably, the material of the first metal layer M1 includes a metal material, such as molybdenum; the materials of the second metal layer M2 and the third metal layer M3 all include at least two metal materials, for example, the second metal layer M2 and the third metal layer M3 can be a metal stacked structure of titanium / aluminum / titanium. Among them, the signal routing in the second metal layer M2 and the third metal layer M3 adopts a multi-layer metal stacked structure, which can greatly reduce the impedance of the signal routing, thereby further reducing the probability of signal loading, and then solving the problem of signal delay (Loading).

[0055] Furthermore, the pixel circuit structure provided in the embodiment of the present invention can be applied to a 7T1C type pixel driving circuit. The circuit diagram of the 7T1C type pixel driving circuit is shown in FIG. Fig. 9As shown in . In the 7T1C type pixel driving circuit, the first electrode and the second electrode of the driving transistor T1 are indirectly electrically connected to the second power signal line VDD and the light-emitting unit OLED respectively, and driven by the storage capacitor Cst, the driving transistor T1 provides a driving current to the light-emitting unit. The first electrode and the second electrode of the data writing transistor T2 are connected to the data signal line Data and the driving transistor T1 respectively, and its gate is connected to the first scanning line Scan1. The data writing transistor T2 transmits the data signal transmitted by the data signal line Data to the driving transistor T1 according to the scanning signal received by its gate, thereby realizing selective conduction of the data transmission channel. At the same time, the first scanning line Scan1 is also connected to the gate of the compensation transistor T3, the first electrode of the compensation transistor T3 is connected to the storage capacitor Cst, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1. The compensation transistor T3 compensates the threshold voltage of the driving transistor T1 according to the scanning signal transmitted by the first scanning line Scan1. The gates of the light-emitting control transistors T5 and T6 are connected to the light-emitting control signal line EM, the first and second electrodes of the light-emitting control transistor T5 are respectively connected to the second power supply signal line VDD and the first electrode of the driving transistor T1, and the first and second electrodes of the light-emitting control transistor T6 are respectively connected to the second electrode of the driving transistor T1 and the light-emitting unit OLED. The light-emitting control transistors T5 and T6 selectively turn on the light-emitting unit OLED according to the light-emitting signal, so as to cause the light-emitting unit OLED to emit light. The second scanning line Scan2 is connected to the gate of the reset transistor T4, the first and second electrodes of the reset transistor M4 are respectively connected to the reset signal line Vi and the gate of the driving transistor M1, and the reset signal is selectively transmitted to the driving transistor T1 according to the scanning signal transmitted by the second scanning line Scan2. At the same time, the second scanning line Scan2 is also connected to the gate of the initialization transistor T7, the first and second electrodes of the initialization transistor T7 are respectively connected to the anode of the light-emitting unit OLED and the reset signal line Vi, and the initialization transistor T7 is used to selectively transmit the initialization signal to the light-emitting unit OLED. The cathode of the light-emitting unit OLED is connected to the first power supply signal line VSS.

[0056] In an embodiment of the present invention, a display panel is further provided, and the display panel may be an OLED (Organic Light-Emitting Diode) display panel, which includes the array substrate 1 as described above and a light-emitting layer, an encapsulation layer, etc. arranged on the array substrate. The display panel may be arranged on any terminal device with a display function, such as a mobile phone, a laptop computer, a tablet computer, etc.

[0057] In the array substrate and display panel provided in the embodiment of the present invention, by setting the reset signal line and the electrode plate of the storage capacitor in other metal layers respectively, one metal layer can be removed on the basis of the existing four metal layers, and the arrangement of all signal lines can be realized by only three metal layers, which can reduce the production cost while realizing the panel lightness and thinness. At the same time, in the embodiment of the present invention, the second power signal line is designed as a mesh structure, which can greatly reduce the impedance in the line compared with the unidirectional power signal line in the related art, thereby preventing the phenomenon of signal load, and thus solving the problem of delay in the display panel.

[0058] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. An array substrate, characterized in that: include: substrate; A first metal layer, insulated and disposed on one side of the substrate; A second metal layer, insulated and arranged on a side of the first metal layer away from the substrate; a third metal layer, insulated and arranged on a side of the second metal layer away from the first metal layer; The third metal layer includes a reset signal line and a first power signal line, wherein the reset signal line and the first power signal line both extend along a first direction and are arranged along a second direction perpendicular to the first direction; The reset signal line is spaced apart from the first power signal line.

2. The array substrate according to claim 1, characterized in that: The second metal layer includes a second power signal line in a mesh structure. Preferably, the reset signal lines and the first power signal lines are alternately arranged along the second direction.

3. The array substrate according to claim 1, characterized in that: The second metal layer comprises: a first signal connection line, the first signal connection line extending along the second direction and connected to the reset signal line; Preferably, the first signal connection line is insulated from other signal lines in the second metal layer.

4. The array substrate according to claim 3, characterized in that: The reset signal line comprises: first reset lines extending along the first direction and arranged along the second direction; A second reset line intersecting the first reset line and connected to the first signal connection line; Preferably, the orthographic projection of the first signal connection line on the substrate is located between the orthographic projection of the first reset line and the first power signal line on the substrate; Preferably, a shape of the first reset line is the same as a shape of the first power signal line.

5. The array substrate according to claim 2, characterized in that: The first metal layer includes a first electrode plate, and the second metal layer also includes a second electrode plate, the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and a storage capacitor is formed between the first electrode plate and the second electrode plate; Preferably, the second electrode plate is connected to the second power signal line.

6. The array substrate according to claim 4, characterized in that: The third metal layer further comprises: a second signal connection line, insulated from the reset signal line and the first power signal line; One end of the second signal connection line is connected to the reset transistor, and the other end of the second signal connection line is connected to the drive transistor.

7. The array substrate according to claim 1, wherein: The materials of the first metal layer, the second metal layer and the third metal layer include at least one metal material; preferably, the material of the second metal layer and the material of the third metal layer include at least two metal materials respectively; Preferably, the metal material includes at least one or more of molybdenum, aluminum, titanium, silver, copper and nickel; Preferably, the array substrate further comprises a semiconductor layer, the semiconductor layer is arranged on one side of the substrate, and the first metal layer is insulated and arranged on a side of the semiconductor layer facing away from the substrate.

8. The array substrate according to claim 1, wherein: The third metal layer further comprises: Data signal lines extending along the first direction and arranged along the second direction; Preferably, one data signal line is provided between the reset signal line and an adjacent first power signal line.

9. The array substrate according to claim 2, characterized in that: The first metal layer comprises: Scan signal lines extending along the second direction and arranged along the first direction; Light-emitting control signal lines extending along the second direction and arranged along the first direction; Preferably, the orthographic projection of the second power signal line on the substrate is located between the orthographic projections of the scanning signal line and the light emitting control signal line on the substrate.

10. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 9.

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