Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, including: a substrate, a first gate, and a second gate. The substrate includes an active region, and a plurality of grooves are formed in the active region and arranged along a first direction. Both the first gate and the second gate extend along the first direction. A first part of the first gate is located on the active region, a second part of the first gate covers the sidewalls and the bottom of the grooves, the first part and the second part are connected, and the second gate is located on the active region. The present invention realizes the reduction of the area of the semiconductor device and improves the integration degree of the semiconductor device in the integrated circuit design.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the design of integrated circuits, a semiconductor IP core refers to a reusable pre-designed module that can be used to build more complex chip systems. The Power Performance Area (PPA) evaluation is a key step in determining the efficiency and applicability of an IP core in a specific application. Higher performance, lower power consumption, and smaller area are the directions for continuous optimization of the IP core. The occupied area refers to the physical space occupied by the IP core on the chip. A smaller IP core area can provide higher integration, enabling more functional modules to be accommodated on the same chip. Therefore, area optimization is highly competitive for IP cores.

[0003] Figure 1 FIG. is a three-dimensional schematic diagram of an OTP device in the prior art. Please refer to Figure 1 , Figure 1 shows a partial structure of an OTP (One Time Programmable) device. The OTP device generally includes an NMOS transistor and a MOS capacitor. The OTP device defaults to read "0", and the gate oxide is partially broken down by applying a voltage to the gate of the MOS capacitor. After programming, it reads "1". The substrate 10 includes an active region 12 and a trench isolation structure 14. The first gate 21 and the second gate 22 serve as the gate of the NMOS transistor and the gate of the MOS capacitor, respectively. The first gate 21 and the second gate 22 both extend along the first direction D1 and are spaced apart along the second direction D2. The first gate 21 and the second gate 22 are both located on the active region 12. Since the size of the first gate 21 along the first direction D1 is related to the size of the active region 12, that is, it is necessary to ensure the contact area between the first gate 21 and the active region 12 to ensure the electrical performance of the OTP device (it is not necessary to ensure the contact area between the gate of the MOS capacitor (the second gate 22) and the active region 12). Since the first gate 21 is located on the active region 12, in order to obtain a larger contact area between the first gate 21 and the active region 12, generally, the size of the first gate 21 along the first direction D1 and the size S1 of the active region 12 are relatively large, resulting in difficulty in reducing the area of the OTP device and difficulty in obtaining higher integration in the design of integrated circuits. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to reduce the area of the semiconductor device and improve the integration of the semiconductor device in the design of integrated circuits.

[0005] To achieve the above object, the present invention provides a semiconductor device, including:

[0006] A substrate, an active region is included in the substrate, a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along a first direction;

[0007] A first gate and a second gate, both extending along the first direction, a first part of the first gate is located on the active region, a second part of the first gate covers sidewalls and a bottom of the groove, the first part and the second part are connected, and the second gate is located on the active region.

[0008] Optionally, a depth of the groove is less than a depth of the active region.

[0009] Optionally, a thickness of the first gate is less than the depth of the groove.

[0010] Optionally, a size of the groove along a second direction is less than or equal to a size of the first gate along the second direction, and the first direction and the second direction intersect perpendicularly.

[0011] Optionally, a size of the groove along the first direction is less than a size of the active region along the first direction.

[0012] Optionally, the plurality of grooves are arranged in a strip shape, and the first gate and the second gate are both in a strip shape.

[0013] Optionally, a first doping region, a second doping region and a third doping region are further included, the first doping region and the second doping region are respectively located in the active region on two sides of the first gate, the second doping region is located in the active region between the first gate and the second gate, and the second doping region and the third doping region are respectively located in the active region on two sides of the second gate.

[0014] Optionally, a trench isolation structure is further included, located in the substrate and extending along the first direction, and the groove, the first doping region, the second doping region and the third doping region are all located between adjacent trench isolation structures.

[0015] Optionally, the semiconductor device is an OTP device.

[0016] The present invention further provides a method for manufacturing a semiconductor device, including:

[0017] Providing a substrate, an active region is included in the substrate, a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along a first direction;

[0018] The first gate and the second gate both extend along the first direction. A first part of the first gate is located on the active region. A second part of the first gate covers the sidewall and the bottom of the groove. The first part and the second part are connected. The second gate is located on the active region.

[0019] In the semiconductor device and its manufacturing method provided by the present invention, the substrate includes an active region, and a plurality of grooves are formed in the active region and arranged along a first direction. The first gate and the second gate both extend along the first direction. A first part of the first gate is located on the active region. A second part of the first gate covers the sidewall and the bottom of the groove. The first part and the second part are connected. The second gate is located on the active region. By arranging a plurality of grooves in the active region, the plurality of grooves are arranged along the first direction, and the first gate extends along the first direction, and the arrangement direction of the grooves is the same as the extension direction of the first gate, so that a part of the first gate covers the sidewall and the bottom of the groove, which can increase the contact area between the first gate and the active region, thereby reducing the size of the active region along the first direction, realizing the reduction of the area of the semiconductor device, and improving the integration degree of the semiconductor device in the integrated circuit design. Description of the Drawings

[0020] Figure 1 It is a three-dimensional schematic diagram of an OTP device in the prior art.

[0021] Figure 2 It is a three-dimensional schematic diagram of a semiconductor device provided by an embodiment of the present invention.

[0022] Figure 3 For Figure 2 The three-dimensional schematic diagram along the section line C1C2 in

[0023] Figure 4 For Figure 2 The sectional schematic diagram along the section line A1A2 in

[0024] Figure 5 For Figure 2 The sectional schematic diagram along the section line B1B2 in

[0025] Figure 6 For Figure 2 The sectional schematic diagram along the section line C1C2 in

[0026] Figure 7 It is a three-dimensional schematic diagram after providing a substrate in the manufacturing method of a semiconductor device provided by an embodiment of the present invention.

[0027] Figure 8 It is a three-dimensional schematic diagram after forming grooves in the manufacturing method of a semiconductor device provided by an embodiment of the present invention.

[0028] Figure 9 ForFigure 8 Schematic cross-sectional view along the section line C1C2.

[0029] Figure 10 3D schematic view after forming a polysilicon layer in the method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0030] Among them, the reference numerals are:

[0031] 10, 100 - substrate; 12, 120 - active region; 14, 140 - trench isolation structure; 160 - groove; 21, 210 - first gate; 22, 220 - second gate; 200 - polysilicon layer. Detailed implementation manners

[0032] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in extremely simplified forms and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different focuses, and sometimes different scales are used.

[0033] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", and in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] Figure 2 3D schematic view of the semiconductor device provided in this embodiment, Figure 3 is Figure 2 3D schematic view along the section line C1C2, Figure 4 is Figure 2 Schematic cross-sectional view along the section line A1A2, Figure 5 is Figure 2 Schematic cross-sectional view along the section line B1B2, Figure 6 is Figure 2 Schematic cross-sectional view along the section line C1C2, Figure 2 Part of the structure of the semiconductor device is schematically shown, where the section line C1C2 is a section along the edge of the first gate 210 so as to be able to schematically show the specific structures of the first gate 210 and the groove 160. Please refer toFigure 2 , this embodiment provides a semiconductor device, which is an OTP device, including a substrate 100, a first gate 210 and a second gate 220. The substrate 100 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate. The substrate 100 includes an active region 120. The active region 120 has a first dimension extending along a first direction D1 and a second dimension extending along a second direction D2. The first direction D1 and the second direction D2 are perpendicular to each other. The first dimension of the active region 120 is related to the dimension of the first gate 210 extending along the first direction D1. Specifically, the first dimension of the active region 120 is related to the contact area between the first gate 210 and the active region 120. Generally, the larger the contact area between the first gate 210 and the active region 120, the larger the dimension of the first gate 210 extending along the first direction D1, and the larger the first dimension of the active region 120. A trench isolation structure 140 is formed in the substrate 100. The trench isolation structure 140 extends along the first direction D1 and is arranged along the second direction D2. The first gate 210 and the second gate 220 are located on the active region 120 between adjacent trench isolation structures 140.

[0035] Please refer to Figure 3 and Figure 6 , a plurality of grooves 160 are formed in the active region 120, and the plurality of grooves 160 are arranged along the first direction D1 and are arranged in a strip shape. The number of grooves 160 is at least one. In this embodiment, the depth of the groove 160 is less than the depth of the active region 120 to prevent the groove 160 from penetrating the active region 120; the depths of the plurality of grooves 160 are preferably the same, which is conducive to forming the plurality of grooves 160 in the same manufacturing process; the dimension of the groove 160 along the first direction D1 is less than the dimension of the active region 120 along the first direction D1, so that a part of the first gate 210 is located on the active region 120.

[0036] Please refer to Figure 2 , both the first gate 210 and the second gate 220 extend along the first direction D1, both the first gate 210 and the second gate 220 are in a strip shape, and the second gate 220 is located on the active region 120; please refer to Figure 4 , a first part of the first gate 210 is located on the active region 120; please refer to Figure 5 and Figure 6 , a second part of the first gate 210 covers the side wall and the bottom of the groove 160, and the first part and the second part are connected to form a complete first gate 210. In this embodiment, the thickness of the first gate 210 is less than the depth of the groove 160 (see Figure 5), such that the first gate 210 does not completely fill the groove 160, but covers the sidewalls and the bottom of the groove 160; the thicknesses of the first gate 210 and the second gate 220 are preferably the same, which is beneficial to forming the first gate 210 and the second gate 220 in the same manufacturing process. In this embodiment, the size of the groove 160 along the second direction D2 is less than or equal to the size of the first gate 210 along the second direction D2. In Figure 5 it is shown that the size of the groove 160 along the second direction D2 is equal to the size of the first gate 210 along the second direction D2, such that in one cross-section (see Figure 5 ), the first gate 210 covers the bottom of the groove 160 in the second direction D2 and does not extend to cover a part of the surface of the active region 120. When the size of the groove 160 along the second direction D2 is less than the size of the first gate 210 along the second direction D2, in one cross-section (not shown in the figure), the first gate 210 covers the bottom of the groove 160 in the second direction D2 and extends to cover a part of the surface of the active region 120.

[0037] Furthermore, the semiconductor device further includes a first doped region, a second doped region, and a third doped region (not shown in the figure). The first doped region and the second doped region are respectively located in the active region 120 on both sides of the first gate 210. The second doped region is located in the active region 120 between the first gate 210 and the second gate 220. The second doped region and the third doped region are respectively located in the active region 120 on both sides of the second gate 220. The groove 160, the first doped region, the second doped region, and the third doped region are all located between adjacent trench isolation structures 140; the first doped region, the second doped region, and the third doped region serve as source regions or drain regions, and the doping types of the first doped region, the second doped region, and the third doped region are the same. A lightly doped region (not shown in the figure) is further formed in the active region 160, and the first doped region, the second doped region, and the third doped region are located in the lightly doped region.

[0038] In this embodiment, the OTP device includes an NMOS transistor and a MOS capacitor. To ensure the electrical performance of the OTP device, it is necessary to ensure that the gate of the NMOS transistor has a large contact area with the active region, and it is not necessary to ensure the contact area between the gate of the MOS capacitor and the active region. Among them, the first gate 210 is the gate of the NMOS transistor, and the second gate 220 is the gate of the MOS capacitor. Therefore, it is necessary to ensure that the first gate 210 has a large contact area with the active region 120, and it is not necessary to change the morphology of the second gate 220. In this embodiment, by providing a plurality of grooves 160 in the active region 120, the plurality of grooves 160 are arranged along the first direction D1, and the first gate 210 extends along the first direction D1. The arrangement direction of the grooves 160 is the same as the extension direction of the first gate 210, so that a part of the first gate 210 (the second part of the first gate 210) covers the side walls and the bottom of the grooves 160, which can increase the contact area between the first gate 210 and the active region 120, thereby reducing the size of the active region 120 along the first direction D1, realizing the reduction of the area of the semiconductor device, and improving the integration degree of the semiconductor device in the integrated circuit design. For example, please refer to Figure 1 and Figure 2 , Figure 2 in which the size of the first gate 210 along the first direction D1 and the size S2 of the active region 120 are less than Figure 1 in which the size of the first gate 21 along the first direction D1 and the size S1 of the active region 12, thereby reducing the size of the active region 120 along the first direction D1, and realizing the reduction of the area of the semiconductor device.

[0039] This embodiment also provides a method for manufacturing a semiconductor device for manufacturing the above semiconductor device. The semiconductor device is an OTP device, including:

[0040] Step S1: Provide a substrate, the substrate includes an active region, and a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along the first direction;

[0041] Step S2: Form a first gate and a second gate both extending along the first direction. The first part of the first gate is located on the active region, the second part of the first gate covers the side walls and the bottom of the grooves, the first part and the second part are connected, and the second gate is located on the active region.

[0042] Figure 7 is a three-dimensional schematic diagram after providing the substrate in the method for manufacturing the semiconductor device provided in this embodiment, Figure 8 is a three-dimensional schematic diagram after forming the grooves in the method for manufacturing the semiconductor device provided in this embodiment, Figure 9 is Figure 8 the cross-sectional schematic diagram along the section line C1C2 in Figure 10 is a three-dimensional schematic diagram after forming the polysilicon layer in the method for manufacturing the semiconductor device provided in this embodiment. The following is combined with Figures 7 - 10A detailed description is given of the method for manufacturing the semiconductor device provided in this embodiment.

[0043] Perform step S1: Refer to Figure 7 , provide a substrate 100, where the substrate 100 includes an active region 120. The active region 120 has a first dimension extending along a first direction D1 and a second dimension extending along a second direction D2. The first direction D1 and the second direction D2 intersect perpendicularly. A trench isolation structure 140 is formed in the substrate 100. The trench isolation structure 140 extends along the first direction D1 and is arranged along the second direction D2. Refer to Figure 8 and Figure 9 , Figure 9 For Figure 8 is a schematic cross-sectional view along the section line C1C2 in

[0044] , where the section line C1C2 is a section along the edge of the groove 160. Etch the substrate 100 to form a plurality of grooves 160 in the active region 120, and the plurality of grooves 160 are arranged in a strip shape along the first direction D1. The structure and dimensions of the grooves 160 are as described above.

[0044] Perform step S2: Refer to Figure 10 , form a polysilicon layer 200 to cover the active region 120 and the sidewalls and bottom of the grooves 160; Refer to Figure 2 , perform patterning on the Figure 10 polysilicon layer 200 in

[0045] to form a first gate 210 and a second gate 220. Both the first gate 210 and the second gate 220 extend along the first direction D1. Both the first gate 210 and the second gate 220 are in a strip shape. The second gate 220 is located on the active region 120. The first part of the first gate 210 is located on the active region 120. The second part of the first gate 210 covers the sidewalls and bottom of the groove 160. The first part and the second part are connected to form a complete first gate 210.

[0045] Furthermore, a lightly doped region is formed in the active region 160, and a first doped region, a second doped region, and a third doped region are formed in the lightly doped region. The first doped region and the second doped region are respectively located in the active region 120 on both sides of the first gate 210. The second doped region is located in the active region 120 between the first gate 210 and the second gate 220. The second doped region and the third doped region are respectively located in the active region 120 on both sides of the second gate 220. The groove 160, the first doped region, the second doped region, and the third doped region are all located between adjacent trench isolation structures 140; The first doped region, the second doped region, and the third doped region serve as source regions or drain regions.

[0046] In summary, in the semiconductor device and its manufacturing method provided by the present invention, the substrate includes an active region, and a plurality of grooves are formed in the active region, and the plurality of grooves are arranged along a first direction; both the first gate and the second gate extend along the first direction, a first part of the first gate is located on the active region, a second part of the first gate covers the sidewalls and the bottom of the grooves, the first part and the second part are connected, and the second gate is located on the active region. By providing a plurality of grooves in the active region, the plurality of grooves are arranged along the first direction, the first gate extends along the first direction, and the arrangement direction of the grooves is the same as the extension direction of the first gate, so that a part of the first gate covers the sidewalls and the bottom of the grooves, which can increase the contact area between the first gate and the active region, thereby reducing the size of the active region along the first direction, realizing the reduction of the area of the semiconductor device, and improving the integration degree of the semiconductor device in the integrated circuit design.

[0047] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A semiconductor device, the semiconductor device being an OTP device, characterized in that, Comprising: A substrate, the substrate including an active region, a plurality of grooves being formed in the active region, and the plurality of grooves being arranged along a first direction; A first gate and a second gate, both extending along the first direction, the size of the groove along a second direction being less than or equal to the size of the first gate along the second direction, the first direction and the second direction intersecting perpendicularly, a first portion of the first gate being located on the active region, a second portion of the first gate covering the sidewalls and the bottom of the groove, the first portion and the second portion being connected, and the second gate being located on the active region.

2. The semiconductor device according to claim 1, wherein, The depth of the groove is less than the depth of the active region.

3. The semiconductor device according to claim 2, wherein, The thickness of the first gate is less than the depth of the groove.

4. The semiconductor device according to claim 1, wherein, The size of the groove along the first direction is less than the size of the active region along the first direction.

5. The semiconductor device according to claim 1, wherein The plurality of grooves are arranged in a strip shape, and the first gate and the second gate are both in a strip shape.

6. The semiconductor device according to claim 1, wherein, It further includes a first doping region, a second doping region, and a third doping region. The first doping region and the second doping region are respectively located in the active region on both sides of the first gate, the second doping region is located in the active region between the first gate and the second gate, and the second doping region and the third doping region are respectively located in the active region on both sides of the second gate.

7. The semiconductor device according to claim 6, wherein It further includes a trench isolation structure, which is located in the substrate and extends along the first direction, and the groove, the first doping region, the second doping region, and the third doping region are all located between adjacent trench isolation structures.

8. A method for manufacturing a semiconductor device, the semiconductor device being an OTP device, characterized in that, Comprising: Providing a substrate, the substrate including an active region, a plurality of grooves being formed in the active region, and the plurality of grooves being arranged along a first direction; Forming a first gate and a second gate both extending along the first direction, the size of the groove along a second direction being less than or equal to the size of the first gate along the second direction, the first direction and the second direction intersecting perpendicularly, a first portion of the first gate being located on the active region, a second portion of the first gate covering the sidewalls and the bottom of the groove, the first portion and the second portion being connected, and the second gate being located on the active region.

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