Preparation method of N-type TOPCon battery

Abstract

The invention provides a preparation method of an N-type TOPCon battery. The preparation method comprises the following steps: S100, forming a textured structure on a silicon wafer; s200, forming a PN junction on the silicon wafer; s300, growing a tunneling oxide layer and a poly-si layer on the silicon wafer; s400, phosphorus diffusion is carried out on the silicon wafer, and then cleaning is carried out; s500, scribing and splitting the silicon wafer to obtain a plurality of silicon wafer slices; s600, aluminum oxide deposition is carried out on the front face and the cutting face of the silicon slice; s700, performing silicon nitride deposition on the front surface and the cutting surface of the silicon slice; s800, performing silicon nitride deposition on the back surface and the cutting surface of the silicon slice; and S900, carrying out metallization processing on the silicon wafer slices. The invention provides a preparation method of an N-type TOPCon battery, and aims to solve the problem that in the prior art, a high-precision passivation device needs to be adopted to perform passivation treatment on a cutting surface after slicing, so that the production cost is increased.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and more specifically, relates to a method for preparing an N-type TOPCon cell. Background Art

[0002] N-type TOPCon cell, namely Tunnel Oxide Passivated Contact cell, is a solar cell technology based on N-type silicon wafer. The structure of TOPCon cell is to form a passivated contact structure by preparing a tunnel oxide layer and a polysilicon layer on the back of the cell on an N-type silicon substrate. This structure can effectively reduce the recombination current on the back of the cell, increase the open circuit voltage and short circuit current of the cell, and thus improve the conversion efficiency of the cell. Compared with traditional P-type cells, N-type TOPCon cells have higher conversion efficiency, with a theoretical conversion efficiency of up to 28.7%. It has a stronger ability to absorb and utilize light, especially in weak light environments, and can maintain good power generation performance. At the same time, N-type TOPCon cells have a lower temperature coefficient, more stable performance in high temperature environments, and stronger resistance to light-induced degradation, which can ensure the power generation efficiency of the battery during long-term use.

[0003] At present, more and more manufacturers have adopted half-cut cell technology. Cutting is a key step in the manufacture of N-type TOPCon cells. Generally, the whole silicon wafer is cut before metallization, and then the cut surface is passivated, metallized and other subsequent processes are carried out. In order to achieve high-quality cut passivation, some high-precision equipment is required, such as chemical vapor deposition (CVD) equipment, atomic layer deposition (ALD) equipment, etc. These equipment are not only expensive, but also have high maintenance costs, which increases the equipment investment and operating costs of enterprises. Summary of the invention

[0004] The purpose of the present invention is to provide a method for preparing an N-type TOPCon battery, aiming to solve the problem in the prior art that high-precision passivation equipment is needed to passivate the cut surface after slicing, and the passivation equipment is expensive, resulting in increased production costs.

[0005] The technical solution adopted by the present invention is: Provided is a method for preparing an N-type TOPCon battery, comprising: S100, forming a velvet structure on the front and back sides of the silicon wafer by chemical etching or laser texturing to increase light absorption efficiency; S200, forming a PN junction on the front side of the silicon wafer by a boron diffusion process, and then cleaning the front side and the back side of the silicon wafer; S300, growing a tunneling oxide layer and a poly-Si layer on the back side of the silicon wafer; S400, diffusing phosphorus on the side of the silicon wafer where the tunnel oxide layer and the poly-Si layer are formed, and then cleaning the silicon wafer; S500, scribing and splitting the silicon wafer to obtain a plurality of silicon wafer slices; S600, performing aluminum oxide deposition on the front surface and the cut surface of the silicon wafer slice respectively; S700, depositing silicon nitride on the front side and the cut side of the silicon wafer slice respectively; S800, depositing silicon nitride on the back side and the cut side of the silicon wafer slice respectively; S900, performing metallization processing on the silicon wafer slices.

[0006] In a possible implementation, the S600 specifically includes: S610, depositing silicon oxide on the front surface and the cut surface of the silicon wafer slice to form a silicon oxide layer; S620, depositing aluminum oxide on the silicon oxide layer of the silicon wafer slice, so that a first aluminum oxide layer is formed on the front side and the cut side of the silicon wafer slice, respectively.

[0007] In a possible implementation manner, the S610 specifically includes: S611, the temperature in the first high temperature furnace is maintained at 300°C, and the nitrogen flow rate is 10 sccm; S612, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a first high-temperature furnace; S613, the flow rate of nitrous oxide is 1200 sccm, and the time is maintained for 5 seconds. Silicon oxide is deposited on the front side and the cut side of the silicon wafer slice to form a silicon oxide layer. The thickness of the silicon oxide layer is 1nm-2nm.

[0008] In a possible implementation manner, the S620 specifically includes: S621, trimethylaluminum flow rate is 1800sccm, water flow rate is 1300sccm, time is maintained for 5s, and cycled 33 times; S622, depositing aluminum oxide on the silicon oxide layer of the silicon wafer slices, so that the front cut surfaces of the silicon wafer slices respectively form a first aluminum oxide layer, and the thickness of the first aluminum oxide layer is 5-10 nm; S623, taking the quartz boat out of the first high temperature furnace.

[0009] In a possible implementation manner, the S700 specifically includes: S710, depositing silicon nitride on the front surface and the cut surface of the silicon wafer slice to form a silicon nitride layer; S720, depositing silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer.

[0010] In a possible implementation manner, the S710 specifically includes: S711, the temperature in the second high temperature furnace is maintained at 460°C, and the nitrogen flow rate is 10slm; S712, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a second high-temperature furnace; S713, maintaining the second high temperature furnace in a vacuum state, and checking the sealing of the second high temperature furnace; S714, when the sealing in the second high-temperature furnace is qualified, the monosilane flow rate in the second high-temperature furnace is 2800sccm, the ammonia flow rate is 10000sccm, the time is maintained for 750s, and silicon nitride is deposited on the front and cut surfaces of the silicon wafer slices to form a silicon nitride layer, and the thickness of the silicon nitride layer is 70-90nm.

[0011] In a possible implementation manner, the S720 specifically includes: S721, silane flow rate is 14000sccm, ammonia flow rate is 5000sccm, and the time is maintained for 400s. S722, maintaining a vacuum state in the second high temperature furnace; S723, depositing silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer, wherein the thickness of the silicon oxynitride layer is 1-10 nm; S724, taking the quartz boat out of the second high temperature furnace.

[0012] In a possible implementation, in S800, after silicon nitride is deposited on the back side and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed, and the second silicon nitride layer includes one or more layers of silicon nitride films.

[0013] In a possible implementation, in S800, the second silicon nitride layer includes multiple layers of silicon nitride films, and the thicknesses and refractive indices of the multiple layers of silicon nitride films are different.

[0014] In a possible implementation manner, the S800 specifically includes: S810, the temperature in the third high temperature furnace is maintained at 500°C, and the nitrogen flow rate is 10slm; S820, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a third high-temperature furnace; S830, maintaining the third high temperature furnace in a vacuum state, and checking the sealing of the third high temperature furnace; S840, after depositing silicon nitride on the back side and the cut surface of the silicon wafer slice, forming a second silicon nitride layer, wherein the second silicon nitride layer includes one or more layers of silicon nitride thin films, and the thickness of the second silicon nitride layer is 60-80 nm; S850, taking the quartz boat out of the third high temperature furnace.

[0015] The beneficial effect of the preparation method of the N-type TOPCon cell provided by the present invention is that: compared with the prior art, in the early process, a velvet structure is first formed on the front and back sides of the silicon wafer to increase the light absorption efficiency, and then a boron diffusion process is used to form a PN junction on the front side of the silicon wafer through a diffusion process, and then the front and back sides of the silicon wafer are cleaned, and a tunneling oxide layer and a poly-si layer are grown on the back side and phosphorus is diffused, which effectively optimizes the transmission and collection efficiency of carriers and reduces the composite loss. Different from the traditional process, the present invention performs slicing and splitting after the preparation of the back tunneling oxide passivation layer is completed, and then uses an aluminum oxide deposition device and a silicon nitride deposition device to deposit a composite film layer on the cut surface of the silicon wafer slice to achieve passivation of the cut surface of the silicon wafer slice. This method does not require the use of dedicated passivation equipment, which reduces costs and improves the passivation effect. In addition, by depositing a composite film on the cut surface of the silicon wafer slice, compared with the existing technology of only forming a single aluminum oxide passivation film on the cut surface, chemical passivation and physical passivation can be achieved simultaneously, which significantly improves the passivation effect of the silicon wafer, thereby improving the open circuit voltage and conversion efficiency of the battery, providing an efficient and economical solution for the preparation of N-type TOPCon batteries. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic structural diagram of a method for preparing an N-type TOPCon battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] In the claims, specification and the above drawings of the present invention, unless otherwise clearly defined, the terms "first", "second" or "third" are used to distinguish different objects, rather than to describe a specific order. Unless otherwise specified, other directional words, such as "vertical", "clockwise", "counterclockwise", etc., indicating directions or positional relationships are based on the directions and positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, so it cannot be understood as limiting the specific protection scope of the present invention. In the claims, specification and the above drawings of the present invention, unless otherwise clearly defined, the terms "fixed connection" or "fixed connection" should be understood in a broad sense, that is, any connection method without a displacement relationship and relative rotation relationship between the two, that is, including non-detachable fixed connection, detachable fixed connection, integrated connection and fixed connection through other devices or elements. In the claims, specification and the above drawings of the present invention, the terms "including", "having" and their variations are used, and the intention is to "include but not limited to".

[0020] See also Figure 1 The preparation method of the N-type TOPCon battery provided by the present invention is now described. The preparation method of the N-type TOPCon battery comprises: S100, forming a velvet structure on the front and back sides of the silicon wafer by chemical etching or laser texturing to increase light absorption efficiency; S200, forming a PN junction on the front side of the silicon wafer by a boron diffusion process, and then cleaning the front side and the back side of the silicon wafer; S300, growing a tunneling oxide layer and a poly-Si layer on the back side of the silicon wafer; S400, diffusing phosphorus on the side of the silicon wafer where the tunnel oxide layer and the poly-Si layer are formed, and then cleaning the silicon wafer; S500, scribing and splitting the silicon wafer to obtain a plurality of silicon wafer slices; S600, performing aluminum oxide deposition on the front side and the cut side of the silicon wafer slice respectively; S700, depositing silicon nitride on the front side and the cut side of the silicon wafer slice respectively; S800, depositing silicon nitride on the back side and the cut side of the silicon wafer slice respectively; S900, metallizing the silicon wafer slices.

[0021] Compared with the prior art, the preparation method of the N-type TOPCon cell provided by the present invention first forms a velvet structure on the front and back sides of the silicon wafer in the early process to increase the light absorption efficiency, and then uses a boron diffusion process to form a PN junction on the front side of the silicon wafer, and then cleans the front and back sides of the silicon wafer, tunnels through the oxide layer and the poly-si layer and diffuses phosphorus, effectively optimizing the transmission and collection efficiency of carriers and reducing the composite loss. Different from the traditional process, the present invention performs slicing and splitting after the preparation of the back tunneling oxide passivation layer is completed, and then uses an aluminum oxide deposition device and a silicon nitride deposition device to deposit a composite film layer on the cut surface of the silicon wafer slice to passivate the cut surface of the silicon wafer slice. This method does not require the use of dedicated passivation equipment, which reduces costs and improves the passivation effect. In addition, by depositing a composite film on the cut surface of the silicon wafer slice, compared with the existing technology of only forming a single aluminum oxide passivation film on the cut surface, chemical passivation and physical passivation can be achieved simultaneously, which significantly improves the passivation effect of the silicon wafer, thereby improving the open circuit voltage and conversion efficiency of the battery, providing an efficient and economical solution for the preparation of N-type TOPCon batteries.

[0022] It should be noted that silicon nitride is deposited twice on the cut surface, once together with the front side of the silicon wafer, and once together with the back side of the silicon wafer. The thickness of the two silicon nitride depositions is different, which can achieve a better passivation effect.

[0023] In some embodiments, see Figure 1 , S600 specifically includes: S610, depositing silicon oxide on the front side and the cut side of the silicon wafer slice to form a silicon oxide layer; S620, depositing aluminum oxide on the silicon oxide layer of the silicon wafer slice, so that a first aluminum oxide layer is formed on the front side and the cut side of the silicon wafer slice, respectively.

[0024] The deposition of the silicon oxide layer provides a good substrate for the subsequent growth of the first aluminum oxide layer. At the same time, silicon oxide itself has excellent insulation properties and chemical stability, which can effectively passivate the surface of the silicon wafer, reduce surface defects and recombination centers, thereby improving the life of carriers and the efficiency of the battery. In addition, the deposition of the first aluminum oxide layer further enhances the surface passivation effect, especially aluminum oxide has excellent negative charge fixing ability, which can effectively inhibit the recombination of minority carriers on the surface, further improving the open circuit voltage and conversion efficiency of the battery. In addition, the first aluminum oxide layer also has good anti-reflection properties, which can reduce the reflection loss of light and enhance the absorption efficiency of light. By forming silicon oxide and aluminum oxide layers on the front and cut surfaces respectively, not only the electrical performance of the battery is optimized, but also its mechanical stability and environmental durability are improved. In summary, the implementation of the S600 step significantly improves the surface passivation effect, light absorption capacity and overall performance of the battery, laying an important foundation for the preparation of high-efficiency N-type TOPCon batteries.

[0025] In some embodiments, see Figure 1 , S610 specifically includes: S611, the temperature in the first high temperature furnace is maintained at 300°C, and the nitrogen flow rate is 10 sccm; S612, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a first high-temperature furnace; S613, the flow rate of nitrous oxide is 1200 sccm, and the time is maintained for 5 seconds. Silicon oxide is deposited on the front side and the cut side of the silicon wafer slice to form a silicon oxide layer with a thickness of 1nm-2nm.

[0026] The temperature of the first high-temperature furnace was stabilized at 300 ° C and nitrogen was introduced to provide a stable reaction environment for the deposition of silicon oxide, ensuring the controllability and consistency of the process. Then, nitrous oxide was used as the reaction gas to achieve uniform deposition of an ultra-thin silicon oxide layer with a thickness of only 1nm-2nm in a short time (5s). Silicon oxide can chemically passivate the dangling bonds and various defect states on the surface, and the band gap of silicon oxide is wider, which improves the field passivation effect. In addition, this ultra-thin structure can minimize the obstruction to carrier transport, thereby improving the electrical performance of the battery. The silicon oxide layer has good insulation properties and chemical stability, and can provide an ideal substrate for the subsequent deposition of the aluminum oxide layer, further enhancing the surface passivation effect. By precisely controlling the gas flow, temperature and time, this step achieves the reproducible preparation of high-quality silicon oxide layers, laying a solid foundation for the successful implementation of subsequent process steps. In summary, the implementation of the S610 step significantly optimizes the surface passivation effect, improves the carrier life and overall efficiency of the battery, and ensures the efficiency and stability of the process.

[0027] In some embodiments, see Figure 1, S620 specifically includes: S621, trimethylaluminum flow rate is 1800sccm, water flow rate is 1300sccm, time is maintained for 5s, and cycled 33 times; S622, depositing aluminum oxide on the silicon oxide layer of the silicon wafer slice, so that the front cut surfaces of the silicon wafer slice respectively form a first aluminum oxide layer, and the thickness of the first aluminum oxide layer is 5-10 nm; S623, taking the quartz boat out of the first high temperature furnace.

[0028] The process in this embodiment ensures the high quality and consistency of the aluminum oxide layer, giving it excellent surface passivation performance. The first aluminum oxide layer can not only effectively fix negative charges and inhibit the recombination of minority carriers on the surface, but also significantly improve the open circuit voltage and conversion efficiency of the battery. The combination of the first aluminum oxide layer and the silicon oxide layer further enhances the surface passivation effect. At the same time, aluminum oxide also has good anti-reflection properties, which can reduce the reflection loss of light and improve the absorption efficiency of light. In addition, by removing the quartz boat from the high-temperature furnace, the controllability and safety of the process are ensured, and the potential impact of overheating on the performance of the silicon wafer is avoided. The steps in S620 optimize the surface passivation effect, light absorption capacity and electrical properties of the battery, providing important guarantees for the preparation of high-efficiency N-type TOPCon batteries.

[0029] In some embodiments, see Figure 1 , S700 specifically includes: S710, depositing silicon nitride on the front side and the cut side of the silicon wafer slice to form a silicon nitride layer; S720, depositing silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer.

[0030] Silicon nitride has a high refractive index and good anti-reflection properties, which can reduce the reflection loss of light, enhance the light absorption efficiency, and further improve the photoelectric conversion performance of the battery. Depositing a silicon oxynitride layer on the silicon nitride layer further optimizes the surface passivation effect. At the same time, the silicon oxynitride layer has good insulation properties and chemical stability, which can effectively protect the silicon wafer surface from the influence of the external environment and enhance the durability and reliability of the battery. In addition, the introduction of the silicon oxynitride layer can also adjust the interface band structure, improve the transmission and collection efficiency of carriers, and thus improve the overall performance of the battery.

[0031] In some embodiments, see Figure 1 , S710 specifically includes: S711, the temperature in the second high temperature furnace is maintained at 460°C, and the nitrogen flow rate is 10slm; S712, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a second high temperature furnace; S713, maintaining the second high temperature furnace in a vacuum state, and checking the sealing of the second high temperature furnace; S714, when the sealing in the second high temperature furnace is qualified, the monosilane flow rate in the second high temperature furnace is 2800sccm, the ammonia flow rate is 10000sccm, the time is maintained for 750s, silicon nitride is deposited on the front and cut surfaces of the silicon wafer slices respectively to form a silicon nitride layer with a thickness of 70-90nm.

[0032] The temperature of the second high-temperature furnace is stabilized at 460°C and nitrogen is introduced to provide a stable reaction environment for the deposition of silicon nitride, ensuring the controllability and consistency of the process. Maintaining a vacuum state in the second high-temperature furnace and checking the sealing ensures the purity of the reaction environment and the reliability of the process, and avoids the impact of impurity contamination on the quality of the silicon nitride layer. Then, by controlling the monosilane flow rate to 2800sccm and the ammonia flow rate to 10000sccm, and depositing the silicon nitride layer within 750s, a uniform silicon nitride layer with a thickness of 70-90nm was prepared. The silicon nitride layer has an excellent surface passivation effect, which can effectively reduce surface defects and recombination centers, thereby improving the life of carriers and the efficiency of the battery. In addition, the hydrogen in the silicon nitride layer can passivate various defects in the silicon wafer and has a good physical passivation effect.

[0033] In some embodiments, see Figure 1 , S720 specifically includes: S721, silane flow rate is 14000sccm, ammonia flow rate is 5000sccm, and the time is maintained for 400s. S722, maintaining a vacuum state in the second high temperature furnace; S723, depositing silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer, wherein the thickness of the silicon oxynitride layer is 1-10 nm; S724, taking the quartz boat out of the second high temperature furnace.

[0034] This ultra-thin silicon oxynitride layer can not only further optimize the surface passivation effect, but also effectively adjust the interface band structure, improve the transmission and collection efficiency of carriers, and thus improve the open circuit voltage and conversion efficiency of the battery. Maintaining a vacuum state in the second high-temperature furnace ensures the purity of the reaction environment and the stability of the process, and avoids the impact of impurity contamination on the quality of the silicon oxynitride layer. The silicon oxynitride layer has good insulation properties and chemical stability, which can effectively protect the surface of the silicon wafer from the influence of the external environment and enhance the durability and reliability of the battery. In addition, silicon oxynitride can not only passivate various defects in the silicon wafer, but also work synergistically with the silicon nitride layer to further improve the anti-reflection performance and light absorption efficiency. Finally, by removing the quartz boat from the high-temperature furnace, the controllability and safety of the process are ensured, and the potential impact of overheating on the performance of the silicon wafer is avoided.

[0035] In some embodiments, see Figure 1 In S800, after silicon nitride is deposited on the back side and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed, and the second silicon nitride layer includes one or more layers of silicon nitride films.

[0036] The second silicon nitride layer can be designed as one or more layers of silicon nitride film. This multilayer structure can further optimize the optical and electrical properties of the back side. The deposition of the second silicon nitride layer provides excellent surface passivation for the back side of the silicon wafer, which can effectively reduce defects and recombination centers on the back side surface, thereby improving the carrier life and battery efficiency.

[0037] In some embodiments, see Figure 1 In S800, the second silicon nitride layer includes multiple silicon nitride films, and the thicknesses and refractive indices of the multiple silicon nitride films are different. Multilayer silicon nitride films can achieve better anti-reflection effects, reduce light reflection losses, and enhance light absorption efficiency by adjusting the thickness and refractive index of each layer. In addition, the silicon nitride layer also has good chemical stability and mechanical strength, which can effectively protect the back of the silicon wafer from the influence of the external environment and enhance the durability and reliability of the battery.

[0038] In some embodiments, see Figure 1 , S800 specifically includes: S810, the temperature in the third high temperature furnace is maintained at 500°C, and the nitrogen flow rate is 10slm; S820, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a third high temperature furnace; S830, maintaining the third high temperature furnace in a vacuum state, and checking the sealing of the third high temperature furnace; S840, after silicon nitride is deposited on the back side and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed, the second silicon nitride layer includes one or more layers of silicon nitride thin films, and the thickness of the second silicon nitride layer is 60-80 nm; S850, taking the quartz boat out of the third high temperature furnace.

[0039] By stabilizing the temperature of the third high-temperature furnace at 500°C and introducing nitrogen, a stable reaction environment is provided for the deposition of silicon nitride, ensuring the controllability and consistency of the process. Maintaining a vacuum state in the high-temperature furnace and checking the sealing ensures the purity of the reaction environment and the reliability of the process, and avoids the influence of impurity contamination on the quality of the silicon nitride layer. Silicon nitride is deposited on the back of the silicon wafer to form a second silicon nitride layer with a thickness of 60-80nm, which can be designed as one or more layers of silicon nitride film. The multi-layer silicon nitride film structure can further optimize the optical and electrical properties of the back side, and achieve better anti-reflection effects by adjusting the thickness and refractive index of each layer, reduce the reflection loss of light, and enhance the absorption efficiency of light. In addition, the silicon nitride layer has an excellent surface passivation effect, which can effectively reduce the defects and recombination centers on the back surface, thereby improving the life of carriers and the efficiency of the battery. The silicon nitride layer also has good chemical stability and mechanical strength, which can effectively protect the back of the silicon wafer from the influence of the external environment and enhance the durability and reliability of the battery. Finally, by removing the quartz boat from the high-temperature furnace, the controllability and safety of the process are ensured, avoiding the potential impact of overheating on silicon wafer performance.

[0040] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing an N-type TOPCon battery, characterized in that: include: S100, forming a velvet structure on the front and back sides of the silicon wafer by chemical etching or laser texturing to increase light absorption efficiency; S200, forming a PN junction on the front side of the silicon wafer by a boron diffusion process, and then cleaning the front side and the back side of the silicon wafer; S300, growing a tunneling oxide layer and a poly-Si layer on the back side of the silicon wafer; S400, diffusing phosphorus on the side of the silicon wafer where the tunnel oxide layer and the poly-Si layer are formed, and then cleaning the silicon wafer; S500, scribing and splitting the silicon wafer to obtain a plurality of silicon wafer slices; S600, performing aluminum oxide deposition on the front surface and the cut surface of the silicon wafer slice respectively; S700, depositing silicon nitride on the front side and the cut side of the silicon wafer slice respectively; S800, depositing silicon nitride on the back side and the cut side of the silicon wafer slice respectively; S900, performing metallization processing on the silicon wafer slices.

2. The method for preparing an N-type TOPCon battery according to claim 1, characterized in that: The S600 specifically includes: S610, depositing silicon oxide on the front surface and the cut surface of the silicon wafer slice to form a silicon oxide layer; S620, depositing aluminum oxide on the silicon oxide layer of the silicon wafer slice, so that a first aluminum oxide layer is formed on the front side and the cut side of the silicon wafer slice, respectively.

3. The method for preparing an N-type TOPCon battery according to claim 2, characterized in that: The S610 specifically includes: S611, the temperature in the first high temperature furnace is maintained at 300°C, and the nitrogen flow rate is 10 sccm; S612, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a first high-temperature furnace; S613, the flow rate of nitrous oxide is 1200 sccm, and the time is maintained for 5 seconds. Silicon oxide is deposited on the front side and the cut side of the silicon wafer slice to form a silicon oxide layer. The thickness of the silicon oxide layer is 1nm-2nm.

4. The method for preparing an N-type TOPCon battery according to claim 3, characterized in that: The S620 specifically includes: S621, trimethylaluminum flow rate is 1800sccm, water flow rate is 1300sccm, time is maintained for 5s, and cycled 33 times; S622, depositing aluminum oxide on the silicon oxide layer of the silicon wafer slices, so that the front cut surfaces of the silicon wafer slices respectively form a first aluminum oxide layer, and the thickness of the first aluminum oxide layer is 5-10 nm; S623, taking the quartz boat out of the first high temperature furnace.

5. The method for preparing an N-type TOPCon battery according to claim 1, characterized in that: The S700 specifically includes: S710, depositing silicon nitride on the front surface and the cut surface of the silicon wafer slice to form a silicon nitride layer; S720, depositing silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer.

6. The method for preparing an N-type TOPCon battery according to claim 5, characterized in that: The S710 specifically includes: S711, the temperature in the second high temperature furnace is maintained at 460°C, and the nitrogen flow rate is 10slm; S712, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a second high-temperature furnace; S713, maintaining the second high temperature furnace in a vacuum state, and checking the sealing of the second high temperature furnace; S714, when the sealing in the second high-temperature furnace is qualified, the monosilane flow rate in the second high-temperature furnace is 2800sccm, the ammonia flow rate is 10000sccm, the time is maintained for 750s, and silicon nitride is deposited on the front and cut surfaces of the silicon wafer slices to form a silicon nitride layer, and the thickness of the silicon nitride layer is 70-90nm.

7. The method for preparing an N-type TOPCon battery according to claim 5, characterized in that: The S720 specifically includes: S721, silane flow rate is 14000sccm, ammonia flow rate is 5000sccm, and the time is maintained for 400s. S722, maintaining a vacuum state in the second high temperature furnace; S723, depositing silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer, wherein the thickness of the silicon oxynitride layer is 1-10 nm; S724, taking the quartz boat out of the second high temperature furnace.

8. The method for preparing an N-type TOPCon battery according to claim 1, characterized in that: In the S800, after silicon nitride is deposited on the back side and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed, and the second silicon nitride layer includes one or more layers of silicon nitride films.

9. The method for preparing an N-type TOPCon battery according to claim 8, characterized in that: In the S800, the second silicon nitride layer includes multiple layers of silicon nitride films, and the thicknesses and refractive indices of the multiple layers of silicon nitride films are different.

10. The method for preparing an N-type TOPCon battery according to claim 1, characterized in that: The S800 specifically includes: S810, the temperature in the third high temperature furnace is maintained at 500°C, and the nitrogen flow rate is 10slm; S820, placing the silicon wafer slices into a quartz boat, and sending the quartz boat into a third high-temperature furnace; S830, maintaining the third high temperature furnace in a vacuum state, and checking the sealing of the third high temperature furnace; S840, after depositing silicon nitride on the back side and the cut surface of the silicon wafer slice, forming a second silicon nitride layer, wherein the second silicon nitride layer includes one or more layers of silicon nitride thin films, and the thickness of the second silicon nitride layer is 60-80 nm; S850, taking the quartz boat out of the third high temperature furnace.

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