Preparation Method of N-Type TOPCon Battery

Abstract

The present invention provides a preparation method for an N-type TOPCon battery, including: S100, forming a textured structure on a silicon wafer; S200, forming a PN junction on the silicon wafer; S300, growing a tunneling oxide layer and a poly-si layer on the silicon wafer; S400, performing phosphorus diffusion on the silicon wafer and then cleaning; S500, dicing and cleaving the silicon wafer to obtain a plurality of silicon wafer slices; S600, depositing aluminum oxide on the front and cut surfaces of the silicon wafer slices; S700, depositing silicon nitride on the front and cut surfaces of the silicon wafer slices; S800, depositing silicon nitride on the back and cut surfaces of the silicon wafer slices; S900, performing metallization treatment on the silicon wafer slices. The preparation method for the N-type TOPCon battery provided by the present invention aims to solve the problem in the prior art that after slicing, a high-precision passivation device is required to passivate the cut surface, resulting in an increase in production cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and more specifically, relates to a preparation method for N-type TOPCon cells. Background Art

[0002] The N-type TOPCon cell, namely the Tunnel Oxide Passivated Contact cell, is a solar cell technology based on N-type silicon wafers. The structure of the TOPCon cell is to form a passivated contact structure by preparing a tunneling oxide layer and a polysilicon layer on the back of the cell on an N-type silicon substrate. This structure can effectively reduce the recombination current on the back of the cell, increase the open-circuit voltage and short-circuit current of the cell, thereby improving the conversion efficiency of the cell. Compared with traditional P-type cells, N-type TOPCon cells have higher conversion efficiency, and the theoretical conversion efficiency can reach 28.7%. Its ability to absorb and utilize light is stronger, especially in low-light environments, it can also maintain good power generation performance. At the same time, the temperature coefficient of N-type TOPCon cells is lower, the performance is more stable in high-temperature environments, and the ability to resist light-induced degradation is also stronger, which can ensure the power generation efficiency of the cells during long-term use.

[0003] Currently, more and more manufacturers have adopted the half-cell technology. Slicing is a key step in the manufacturing of N-type TOPCon cells. Generally, the whole silicon wafer is sliced before metallization, and then subsequent processes such as passivation of the cut surface and metallization are carried out. In order to achieve high-quality slicing passivation, some high-precision equipment is required, such as chemical vapor deposition (CVD) equipment, atomic layer deposition (ALD) equipment, etc. These equipment are not only expensive but also have high maintenance costs, increasing the equipment investment and operating costs of enterprises. Summary of the Invention

[0004] The purpose of the present invention is to provide a preparation method for N-type TOPCon cells, aiming to solve the problem in the prior art that after slicing, high-precision passivation equipment is required for passivation treatment of the cut surface, and the passivation equipment is expensive, resulting in an increase in production costs.

[0005] The technical solution adopted by the present invention is:

[0006] Provide a preparation method for N-type TOPCon cells, including:

[0007] S100. By means of chemical etching or laser texturing, form a textured structure on the front and back of the silicon wafer respectively to increase the light absorption efficiency;

[0008] S200. Form a PN junction on the front side of the silicon wafer using a boron diffusion process, and then clean the front and back sides of the silicon wafer;

[0009] S300. Grow a tunneling oxide layer and a poly-si layer on the back side of the silicon wafer;

[0010] S400. Perform phosphorus diffusion on the side of the silicon wafer where the tunneling oxide layer and the poly-si layer are formed, and then clean the silicon wafer;

[0011] S500. Slice and break the silicon wafer to obtain multiple silicon wafer slices;

[0012] S600. Deposit alumina on the front side and the cut surface of the silicon wafer slice respectively;

[0013] S700. Deposit silicon nitride on the front side and the cut surface of the silicon wafer slice respectively;

[0014] S800. Deposit silicon nitride on the back side and the cut surface of the silicon wafer slice respectively;

[0015] S900. Perform metallization on the silicon wafer slice.

[0016] In a possible implementation manner, the S600 specifically includes:

[0017] S610. Deposit silicon oxide on both the front side and the cut surface of the silicon wafer slice to form a silicon oxide layer;

[0018] S620. Deposit alumina on the silicon oxide layer of the silicon wafer slice, so that a first alumina layer is formed on the front side and the cut surface of the silicon wafer slice respectively.

[0019] In a possible implementation manner, the S610 specifically includes:

[0020] S611. Keep the temperature in the first high-temperature furnace at 300 °C, and the nitrogen flow rate is 10 sccm;

[0021] S612. Place the silicon wafer slice into a quartz boat and send the quartz boat into the first high-temperature furnace;

[0022] S613. The nitrous oxide flow rate is 1200 sccm, and the time is kept for 5 s. Deposit silicon oxide on both the front side and the cut surface of the silicon wafer slice to form a silicon oxide layer, and the thickness of the silicon oxide layer is 1 nm - 2 nm.

[0023] In a possible implementation manner, the S620 specifically includes:

[0024] S621. The flow rate of trimethylaluminum is 1800 sccm, the flow rate of water is 1300 sccm, the time is maintained for 5 s, and the cycle is 33 times;

[0025] S622. Deposit aluminum oxide on the silicon dioxide layer of the silicon wafer slice, so that a first aluminum oxide layer is respectively formed on the front cutting surface of the silicon wafer slice, and the thickness of the first aluminum oxide layer is 5 - 10 nm;

[0026] S623. Take out the quartz boat from the first high-temperature furnace.

[0027] In a possible implementation manner, the S700 specifically includes:

[0028] S710. Deposit silicon nitride on the front and cutting surfaces of the silicon wafer slice respectively to form a silicon nitride layer;

[0029] S720. Deposit silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer.

[0030] In a possible implementation manner, the S710 specifically includes:

[0031] S711. The temperature in the second high-temperature furnace is maintained at 460 °C, and the nitrogen flow rate is 10 slm;

[0032] S712. Put the silicon wafer slice into the quartz boat and send the quartz boat into the second high-temperature furnace;

[0033] S713. Keep the second high-temperature furnace in a vacuum state and check the airtightness in the second high-temperature furnace;

[0034] When the airtightness in the second high-temperature furnace is qualified, the flow rate of silane in the second high-temperature furnace is 2800 sccm, the flow rate of ammonia is 10000 sccm, the time is maintained for 750 s, deposit silicon nitride on the front and cutting surfaces of the silicon wafer slice respectively to form a silicon nitride layer, and the thickness of the silicon nitride layer is 70 - 90 nm.

[0035] In a possible implementation manner, the S720 specifically includes:

[0036] S721. The flow rate of silane is 14000 sccm, the flow rate of ammonia is 5000 sccm, and the time is maintained for 400 s,

[0037] S722. Keep the second high-temperature furnace in a vacuum state;

[0038] S723. Deposit silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer, and the thickness of the silicon oxynitride layer is 1 - 10 nm;

[0039] S724. Take out the quartz boat from the second high-temperature furnace.

[0040] In a possible implementation, in the S800, after depositing silicon nitride on the back and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed, and the second silicon nitride layer includes one or more silicon nitride thin films.

[0041] In a possible implementation, in the S800, the second silicon nitride layer includes multiple silicon nitride thin films, and the thicknesses and refractive indexes of the multiple silicon nitride thin films are all different.

[0042] In a possible implementation, the S800 specifically includes:

[0043] S810. The temperature in the third high-temperature furnace is maintained at 500 °C, and the nitrogen flow rate is 10 slm.

[0044] S820. Place the silicon wafer slice into a quartz boat and send the quartz boat into the third high-temperature furnace.

[0045] S830. Keep the inside of the third high-temperature furnace in a vacuum state and check the airtightness of the inside of the third high-temperature furnace.

[0046] S840. After depositing silicon nitride on the back and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed. The second silicon nitride layer includes one or more silicon nitride thin films, and the thickness of the second silicon nitride layer is 60 - 80 nm.

[0047] S850. Take out the quartz boat from the third high-temperature furnace.

[0048] The beneficial effects of the method for preparing an N-type TOPCon battery provided by the present invention are as follows: Compared with the prior art, in the early process, a textured structure is first formed on the front and back of the silicon wafer to increase the light absorption efficiency. Subsequently, a PN junction is formed on the front of the silicon wafer through a boron diffusion process, and then the front and back of the silicon wafer are cleaned, and a tunneling oxide layer and a poly-si layer are grown on the back and phosphorus diffusion is performed, effectively optimizing the carrier transport and collection efficiency and reducing the recombination loss. Different from the traditional process, in the present invention, scribing and breaking are performed after the back tunneling oxidation passivation layer is prepared, and then a composite film layer is deposited on the cut surface of the silicon wafer slice by using an alumina deposition device and a silicon nitride deposition device to achieve passivation of the cut surface of the silicon wafer slice. This method does not require a dedicated passivation device, which not only reduces the cost but also improves the passivation effect. In addition, by depositing a composite film on the cut surface of the silicon wafer slice, compared with only forming a single alumina passivation film on the cut surface in the prior art, chemical passivation and physical passivation can be achieved simultaneously, significantly improving the passivation effect of the silicon wafer, thereby improving the open-circuit voltage and conversion efficiency of the battery, and providing an efficient and economical solution for the preparation of N-type TOPCon batteries. Brief Description of the Drawings

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0050] Figure 1 It is a schematic structural diagram of a method for preparing an N-type TOPCon battery provided by an embodiment of the present invention. Detailed Embodiments

[0051] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0052] In the claims, the description and the above-mentioned drawings of the present invention, unless otherwise clearly defined, when using terms such as "first", "second" or "third", etc., are used to distinguish different objects and are not used to describe a specific order. Unless otherwise stated, the remaining orientation terms, such as "vertical", "clockwise", "counterclockwise", etc., indicate the orientation and positional relationship based on the orientation and positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, so it cannot be understood as limiting the specific protection scope of the present invention. In the claims, the description and the above-mentioned drawings of the present invention, unless otherwise clearly defined, when using terms such as "fixed connection" or "fixedly connected", should be understood in a broad sense, that is, any connection method without displacement relationship and relative rotation relationship between the two, that is, including non-detachable fixed connection, detachable fixed connection, being integrated as one body, and being fixedly connected through other devices or elements. In the claims, the description and the above-mentioned drawings of the present invention, when using terms such as "comprising", "having" and their variants, are intended to mean "including but not limited to".

[0053] Please refer to Figure 1 , and now a method for preparing an N-type TOPCon battery provided by the present invention will be described. The method for preparing an N-type TOPCon battery includes:

[0054] S100. By means of chemical etching or laser texturing, a textured structure is respectively formed on the front and back surfaces of the silicon wafer to increase the light absorption efficiency;

[0055] S200. Form a PN junction on the front side of the silicon wafer using a boron diffusion process, and then clean the front and back sides of the silicon wafer;

[0056] S300. Grow a tunneling oxide layer and a poly-si layer on the back side of the silicon wafer;

[0057] S400. Perform phosphorus diffusion on the side of the silicon wafer where the tunneling oxide layer and the poly-si layer are formed, and then clean the silicon wafer;

[0058] S500. Dice and break the silicon wafer to obtain multiple silicon wafer slices;

[0059] S600. Deposit alumina on the front side and the cut surface of the silicon wafer slice respectively;

[0060] S700. Deposit silicon nitride on the front side and the cut surface of the silicon wafer slice respectively;

[0061] S800. Deposit silicon nitride on the back side and the cut surface of the silicon wafer slice respectively;

[0062] S900. Metallize the silicon wafer slice.

[0063] Compared with the prior art, the preparation method of the N-type TOPCon battery provided by the present invention forms a textured structure on the front and back sides of the silicon wafer in the early process to increase the light absorption efficiency. Subsequently, a PN junction is formed on the front side of the silicon wafer using a boron diffusion process, and then the front and back sides of the silicon wafer are cleaned, as well as the tunneling oxide layer and the poly-si layer, and phosphorus diffusion is carried out, effectively optimizing the carrier transport and collection efficiency and reducing the recombination loss. Different from the traditional process, in the present invention, dicing and breaking are carried out after the back tunneling oxide passivation layer is prepared, and then a composite film layer is deposited on the cut surface of the silicon wafer slice using an alumina deposition device and a silicon nitride deposition device to achieve passivation of the cut surface of the silicon wafer slice. This method does not require a dedicated passivation device, which not only reduces the cost but also improves the passivation effect. In addition, by depositing a composite film on the cut surface of the silicon wafer slice, compared with only forming a single alumina passivation film on the cut surface in the prior art, chemical passivation and physical passivation can be achieved simultaneously, significantly improving the passivation effect of the silicon wafer, thereby enhancing the open-circuit voltage and conversion efficiency of the battery, providing an efficient and economical solution for the preparation of N-type TOPCon batteries.

[0064] It should be noted that silicon nitride is deposited twice on the cut surface. One time, silicon nitride is deposited together with the front side of the silicon wafer, and on the other side, silicon nitride is deposited together with the back side of the silicon wafer. The thicknesses of the two silicon nitride depositions are different, which can achieve a better passivation effect.

[0065] In some embodiments, please refer to Figure 1 , S600 specifically includes:

[0066] S610. Deposit silicon oxide on both the front side and the cut surface of the silicon wafer slice to form a silicon oxide layer;

[0067] S620. Deposit aluminum oxide on the silicon oxide layer of the silicon wafer slice to form a first aluminum oxide layer on the front side and the cut surface of the silicon wafer slice respectively.

[0068] The deposition of the silicon oxide layer provides a good substrate for the subsequent growth of the first aluminum oxide layer. At the same time, silicon oxide itself has excellent insulation performance and chemical stability, which can effectively passivate the surface of the silicon wafer, reduce surface defects and recombination centers, thereby improving the lifetime of carriers and the efficiency of the battery. In addition, the deposition of the first aluminum oxide layer further enhances the surface passivation effect. Especially, aluminum oxide has excellent negative charge fixing ability, which can effectively inhibit the recombination of minority carriers on the surface and further improve the open circuit voltage and conversion efficiency of the battery. Moreover, the first aluminum oxide layer also has good antireflection performance, which can reduce the reflection loss of light and enhance the light absorption efficiency. By forming silicon oxide and aluminum oxide layers on the front side and the cut surface respectively, not only the electrical performance of the battery is optimized, but also its mechanical stability and environmental durability are improved. In summary, the implementation of step S600 significantly improves the surface passivation effect, light absorption ability and overall performance of the battery, laying an important foundation for the preparation of high-efficiency N-type TOPCon batteries.

[0069] In some embodiments, refer to Figure 1 , S610 specifically includes:

[0070] S611. Keep the temperature in the first high-temperature furnace at 300 °C and the nitrogen flow rate at 10 sccm;

[0071] S612. Place the silicon wafer slice in a quartz boat and send the quartz boat into the first high-temperature furnace;

[0072] S613. Keep the flow rate of dinitrogen monoxide at 1200 sccm for 5 s, deposit silicon oxide on both the front side and the cut surface of the silicon wafer slice to form a silicon oxide layer, and the thickness of the silicon oxide layer is 1 nm - 2 nm.

[0073] The temperature of the first high-temperature furnace was stabilized at 300 °C and nitrogen was introduced, providing a stable reaction environment for the deposition of silicon oxide, ensuring the controllability and consistency of the process. Then, nitrous oxide was used as the reaction gas, and a uniform deposition of an ultra-thin silicon oxide layer with a thickness of only 1 nm - 2 nm was achieved within a short time (5 s). The silicon oxide can chemically passivate the dangling bonds and various defect states on the surface, and the silicon oxide has a wider bandgap, improving the field passivation effect. In addition, this ultra-thin structure can also minimize the hindrance to carrier transport, thereby improving the electrical performance of the battery. The silicon oxide layer has good insulation properties and chemical stability, and can provide an ideal substrate for the subsequent deposition of the aluminum oxide layer, further enhancing the surface passivation effect. By precisely controlling the gas flow rate, temperature, and time, this step achieved the reproducible preparation of a high-quality silicon oxide layer, laying a solid foundation for the successful implementation of subsequent process steps. In summary, the implementation of step S610 significantly optimized the surface passivation effect, improved the carrier lifetime and overall efficiency of the battery, while ensuring the high efficiency and stability of the process.

[0074] In some embodiments, refer to Figure 1 , S620 specifically includes:

[0075] S621. The flow rate of trimethylaluminum is 1800 sccm, the flow rate of water is 1300 sccm, the time is maintained for 5 s, and it is cycled 33 times;

[0076] S622. Deposit aluminum oxide on the silicon oxide layer of the silicon wafer slice, so that a first aluminum oxide layer is formed on the front cutting surface of the silicon wafer slice, and the thickness of the first aluminum oxide layer is 5 - 10 nm;

[0077] S623. Take out the quartz boat from the first high-temperature furnace.

[0078] The process in this embodiment ensures the high quality and consistency of the aluminum oxide layer, making it have excellent surface passivation performance. The first aluminum oxide layer can not only effectively fix negative charges, inhibit the recombination of minority carriers on the surface, but also significantly improve the open-circuit voltage and conversion efficiency of the battery. The combination of the first aluminum oxide layer and the silicon oxide layer further enhances the surface passivation effect. At the same time, aluminum oxide also has good antireflection performance, which can reduce the reflection loss of light and improve the light absorption efficiency. In addition, by taking out the quartz boat from the high-temperature furnace, the controllability and safety of the process are ensured, avoiding the potential impact of overheating on the performance of the silicon wafer. The steps in S620 optimize the surface passivation effect, light absorption ability, and electrical performance of the battery, providing an important guarantee for the preparation of high-efficiency N-type TOPCon batteries.

[0079] In some embodiments, refer to Figure 1 , S700 specifically includes:

[0080] S710. Deposit silicon nitride on the front and cut surfaces of the silicon wafer slice to form a silicon nitride layer;

[0081] S720. Deposit silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer.

[0082] Silicon nitride has a high refractive index and good antireflection performance, which can reduce the reflection loss of light, enhance the light absorption efficiency, and further improve the photovoltaic conversion performance of the battery. Depositing a silicon oxynitride layer on the silicon nitride layer further optimizes the surface passivation effect. At the same time, the silicon oxynitride layer has good insulation performance and chemical stability, which can effectively protect the surface of the silicon wafer from the influence of the external environment and enhance the durability and reliability of the battery. In addition, the introduction of the silicon oxynitride layer can also adjust the interface energy band structure, improve the carrier transport and collection efficiency, and thus improve the overall performance of the battery.

[0083] In some embodiments, refer to Figure 1 , S710 specifically includes:

[0084] S711. Keep the temperature in the second high-temperature furnace at 460 °C and the nitrogen flow rate at 10 slm;

[0085] S712. Place the silicon wafer slice in a quartz boat and send the quartz boat into the second high-temperature furnace;

[0086] S713. Keep the second high-temperature furnace in a vacuum state and check the airtightness in the second high-temperature furnace;

[0087] S714. When the airtightness in the second high-temperature furnace is qualified, the flow rate of silane in the second high-temperature furnace is 2800 sccm, the flow rate of ammonia is 10000 sccm, and the time is kept for 750 s. Deposit silicon nitride on the front and cut surfaces of the silicon wafer slice to form a silicon nitride layer, and the thickness of the silicon nitride layer is 70 - 90 nm.

[0088] Stabilizing the temperature of the second high-temperature furnace at 460 °C and introducing nitrogen provide a stable reaction environment for the deposition of silicon nitride, ensuring the controllability and consistency of the process. Keeping the second high-temperature furnace in a vacuum state and checking the airtightness ensure the purity of the reaction environment and the reliability of the process, avoiding the influence of impurity contamination on the quality of the silicon nitride layer. Then, by controlling the silane flow rate at 2800 sccm and the ammonia flow rate at 10000 sccm, and depositing the silicon nitride layer within 750 s, the preparation of a uniform silicon nitride layer with a thickness of 70 - 90 nm is achieved. The silicon nitride layer has excellent surface passivation effect, which can effectively reduce surface defects and recombination centers, thus improving the carrier lifetime and the efficiency of the battery. In addition, the hydrogen in the silicon nitride layer can passivate various defects in the silicon wafer and has a good physical passivation effect.

[0089] In some embodiments, refer toFigure 1 , S720 specifically includes:

[0090] S721, the flow rate of silane is 14000 sccm, the flow rate of ammonia is 5000 sccm, and the time is maintained for 400 s.

[0091] S722, maintain a vacuum state in the second high-temperature furnace;

[0092] S723, deposit silicon oxynitride on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer, and the thickness of the silicon oxynitride layer is 1 - 10 nm;

[0093] S724, take out the quartz boat from the second high-temperature furnace.

[0094] This ultra-thin silicon oxynitride layer can not only further optimize the surface passivation effect, but also effectively adjust the interface energy band structure, improve the carrier transport and collection efficiency, thereby enhancing the open-circuit voltage and conversion efficiency of the battery. Maintaining a vacuum state in the second high-temperature furnace ensures the purity of the reaction environment and the stability of the process, avoiding the influence of impurity contamination on the quality of the silicon oxynitride layer. The silicon oxynitride layer has good insulation performance and chemical stability, can effectively protect the surface of the silicon wafer from the external environment, and enhance the durability and reliability of the battery. In addition, silicon oxynitride can not only passivate various defects in the silicon wafer, but also cooperate with the silicon nitride layer to further improve the antireflection performance and light absorption efficiency. Finally, by taking out the quartz boat from the high-temperature furnace, the controllability and safety of the process are ensured, avoiding the potential influence of overheating on the performance of the silicon wafer.

[0095] In some embodiments, please refer to Figure 1 , in S800, after depositing silicon nitride on the back and cutting surface of the silicon wafer slice, a second silicon nitride layer is formed, and the second silicon nitride layer includes one or more silicon nitride thin films.

[0096] The second silicon nitride layer can be designed as one or more silicon nitride thin films, and this multi-layer structure can further optimize the optical and electrical properties of the back surface. The deposition of the second silicon nitride layer provides excellent surface passivation effect for the back surface of the silicon wafer, can effectively reduce the defects and recombination centers on the back surface, thereby enhancing the carrier lifetime and the efficiency of the battery.

[0097] In some embodiments, please refer to Figure 1 , in S800, the second silicon nitride layer includes multiple silicon nitride thin films, and the thickness and refractive index of the multiple silicon nitride thin films are all different.

[0098] The multi-layer silicon nitride film can achieve a better antireflection effect, reduce the reflection loss of light, and enhance the light absorption efficiency by adjusting the thickness and refractive index of each layer. In addition, the silicon nitride layer also has good chemical stability and mechanical strength, which can effectively protect the back of the silicon wafer from the influence of the external environment and enhance the durability and reliability of the battery.

[0099] In some embodiments, refer to Figure 1 , S800 specifically includes:

[0100] S810. The temperature in the third high-temperature furnace is maintained at 500 °C, and the nitrogen flow rate is 10 slm;

[0101] S820. Place the silicon wafer slice into the quartz boat and send the quartz boat into the third high-temperature furnace;

[0102] S830. Keep the third high-temperature furnace in a vacuum state and check the airtightness inside the third high-temperature furnace;

[0103] S840. After depositing silicon nitride on the back and cutting surface of the silicon wafer slice, form a second silicon nitride layer. The second silicon nitride layer includes one or more layers of silicon nitride films, and the thickness of the second silicon nitride layer is 60 - 80 nm;

[0104] S850. Take out the quartz boat from the third high-temperature furnace.

[0105] By stabilizing the temperature of the third high-temperature furnace at 500 °C and introducing nitrogen, a stable reaction environment is provided for the deposition of silicon nitride, ensuring the controllability and consistency of the process. Keeping the high-temperature furnace in a vacuum state and checking the airtightness ensure the purity of the reaction environment and the reliability of the process, avoiding the influence of impurity contamination on the quality of the silicon nitride layer. Depositing silicon nitride on the back of the silicon wafer forms a second silicon nitride layer with a thickness of 60 - 80 nm, which can be designed as one or more layers of silicon nitride films. The multi-layer silicon nitride film structure can further optimize the optical and electrical properties of the back. By adjusting the thickness and refractive index of each layer, a better antireflection effect can be achieved, reducing the reflection loss of light and enhancing the light absorption efficiency. In addition, the silicon nitride layer has an excellent surface passivation effect, which can effectively reduce the defects and recombination centers on the back surface, thereby improving the carrier lifetime and the efficiency of the battery. The silicon nitride layer also has good chemical stability and mechanical strength, which can effectively protect the back of the silicon wafer from the influence of the external environment and enhance the durability and reliability of the battery. Finally, by taking out the quartz boat from the high-temperature furnace, the controllability and safety of the process are ensured, avoiding the potential impact of overheating on the performance of the silicon wafer.

[0106] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. Preparation method of N-type TOPCon battery, characterized in that, Including: S100. By means of chemical etching or laser texturing, a textured structure is respectively formed on the front and back surfaces of the silicon wafer to increase the light absorption efficiency; S200. A PN junction is formed on the front surface of the silicon wafer by using a boron diffusion process, and then the front and back surfaces of the silicon wafer are cleaned; S300. A tunneling oxide layer and a poly-si layer are grown on the back surface of the silicon wafer; S400. Phosphorus diffusion is carried out on the side of the silicon wafer where the tunneling oxide layer and the poly-si layer are formed, and then the silicon wafer is cleaned; S500. The silicon wafer is scribed and cleaved to obtain a plurality of silicon wafer slices; S600. Alumina is deposited on the front surface and the cut surface of the silicon wafer slice respectively; S700. Silicon nitride is deposited on the front surface and the cut surface of the silicon wafer slice respectively; S800. Silicon nitride is deposited on the back surface and the cut surface of the silicon wafer slice respectively; S900. Metallization treatment is carried out on the silicon wafer slice; S600 specifically includes: S610. Silicon oxide is deposited on both the front surface and the cut surface of the silicon wafer slice to form a silicon oxide layer; S620. Alumina is deposited on the silicon oxide layer of the silicon wafer slice, so that a first alumina layer is respectively formed on the front surface and the cut surface of the silicon wafer slice.

2. The preparation method of the N-type TOPCon battery according to claim 1, characterized in that, The S610 specifically includes: S611. The temperature in the first high-temperature furnace is maintained at 300 °C, and the nitrogen flow rate is 10 sccm; S612. The silicon wafer slice is placed in a quartz boat, and the quartz boat is sent into the first high-temperature furnace; S613. The flow rate of nitrous oxide is 1200 sccm, and the time is maintained for 5 s. Silicon oxide is deposited on both the front surface and the cut surface of the silicon wafer slice to form a silicon oxide layer, and the thickness of the silicon oxide layer is 1 nm - 2 nm.

3. The preparation method of the N-type TOPCon battery according to claim 2, wherein, The S620 specifically includes: S621. The flow rate of trimethylaluminum is 1800 sccm, the flow rate of water is 1300 sccm, the time is maintained for 5 s, and the cycle is 33 times; S622. Alumina is deposited on the silicon oxide layer of the silicon wafer slice, so that a first alumina layer is respectively formed on the front cut surface of the silicon wafer slice, and the thickness of the first alumina layer is 5 - 10 nm; S623. The quartz boat is taken out of the first high-temperature furnace.

4. The preparation method of the N-type TOPCon battery according to claim 1, characterized in that The S700 specifically includes: S710. Silicon nitride is respectively deposited on the front surface and the cut surface of the silicon wafer slice to form a silicon nitride layer; S720. Silicon oxynitride is deposited on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer.

5. The preparation method of the N-type TOPCon battery according to claim 4, wherein, The S710 specifically includes: S711. The temperature in the second high-temperature furnace is maintained at 460 °C, and the nitrogen flow rate is 10 slm; S712. The silicon wafer slice is placed in a quartz boat, and the quartz boat is sent into the second high-temperature furnace; S713. The second high-temperature furnace is kept in a vacuum state, and the airtightness in the second high-temperature furnace is checked; S714. When the airtightness in the second high-temperature furnace is qualified, the flow rate of silane in the second high-temperature furnace is 2800 sccm, the flow rate of ammonia is 10000 sccm, and the time is maintained for 750 s. Silicon nitride is respectively deposited on the front surface and the cut surface of the silicon wafer slice to form a silicon nitride layer, and the thickness of the silicon nitride layer is 70 - 90 nm.

6. The preparation method of the N-type TOPCon battery according to claim 4, characterized in that, The S720 specifically includes: S721. The flow rate of silane is 14000 sccm, the flow rate of ammonia is 5000 sccm, and the time is maintained for 400 s. S722. The second high-temperature furnace is kept in a vacuum state. S723. Silicon oxynitride is deposited on the silicon nitride layer of the silicon wafer slice to form a silicon oxynitride layer, and the thickness of the silicon oxynitride layer is 1 - 10 nm. S724. Take out the quartz boat from the second high-temperature furnace.

7. The preparation method of the N-type TOPCon battery according to claim 1, wherein, In S800, after silicon nitride deposition is performed on the back surface and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed, and the second silicon nitride layer includes one or more silicon nitride thin films.

8. The preparation method of the N-type TOPCon battery according to claim 7, wherein, In S800, the second silicon nitride layer includes multiple silicon nitride thin films, and the thicknesses and refractive indices of the multiple silicon nitride thin films are all different.

9. The preparation method of the N-type TOPCon battery according to claim 1, characterized in that, S800 specifically includes: S810. The temperature in the third high-temperature furnace is maintained at 500 °C, and the nitrogen flow rate is 10 slm. S820. Place the silicon wafer slice into the quartz boat and send the quartz boat into the third high-temperature furnace. S830. Keep the third high-temperature furnace in a vacuum state and check the airtightness in the third high-temperature furnace. S840. After silicon nitride deposition is performed on the back surface and the cut surface of the silicon wafer slice, a second silicon nitride layer is formed, and the second silicon nitride layer includes one or more silicon nitride thin films, and the thickness of the second silicon nitride layer is 60 - 80 nm. S850. Take out the quartz boat from the third high-temperature furnace.

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