Display device

Abstract

The invention provides a display device. A display device according to an embodiment includes: a substrate; a plurality of pixels arranged in a matrix in the display region on the substrate along a first direction and a second direction that intersect each other; a control signal line that supplies a control signal to each of the plurality of pixels; and a power supply line that supplies an initialization voltage to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit composed of a plurality of transistors, and a light emitting element driven by the pixel circuit. The plurality of transistors constituting the pixel circuit include a first transistor that is disposed between the power supply line and the light-emitting element and is turned on based on a control signal. The control signal lines extend so as to be connected to the plurality of pixels arranged in the first direction, and are arranged side by side in the second direction. The power supply lines extend so as to be connected to the plurality of pixels disposed in the second direction, and are arranged side by side in the first direction.

Description

[0001] This application is based on Japanese Patent Application No. 2023-185594 (filing date: October 30, 2023) and claims priority from the present application, and the present application incorporates all the contents of the application by reference. Technical Field

[0002] Embodiments of the present invention relate to a display device. Background Art

[0003] In recent years, display devices using organic light emitting diodes (OLEDs), which are light emitting elements that function as display elements, have been put into practical use.

[0004] In such a display device, a light emitting element is driven by a pixel circuit. However, when a short circuit occurs between the anode and cathode of the light emitting element, the display quality is degraded starting from a dark spot caused by the short circuit. Summary of the invention

[0005] An object of the present invention is to provide a display device capable of suppressing a decrease in display quality.

[0006] The display device of the embodiment comprises: a substrate; a plurality of pixels arranged in a matrix in a display area on the substrate along a first direction and a second direction intersecting each other; a control signal line that supplies a control signal to each of the plurality of pixels; and a power line that supplies an initialization voltage to each of the plurality of pixels. Each of the plurality of pixels includes a pixel circuit composed of a plurality of transistors and a light-emitting element driven by the pixel circuit. The plurality of transistors constituting the pixel circuit include a first transistor that is arranged between the power line and the light-emitting element and becomes conductive based on the control signal. The control signal line extends in a manner connected to the plurality of pixels arranged in the first direction and is arranged in the second direction. The power line extends in a manner connected to the plurality of pixels arranged in the second direction and is arranged in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a diagram showing a configuration example of a display device according to an embodiment.

[0008] Figure 2 A diagram showing an example of a layout of a plurality of sub-pixels included in a pixel.

[0009] Figure 3 FIG. 2 is a diagram showing another example of the layout of a plurality of sub-pixels included in a pixel.

[0010] Figure 4 It is along Figure 2A schematic cross-sectional view of the display device taken along line AA in FIG.

[0011] Figure 5 It is a schematic enlarged cross-sectional view of the partition wall.

[0012] Figure 6 This is a schematic cross-sectional view for explaining a light-emitting element formed using partition walls.

[0013] Figure 7 This is a schematic cross-sectional view for explaining a light-emitting element formed using partition walls.

[0014] Figure 8 This is a schematic cross-sectional view for explaining a light-emitting element formed using partition walls.

[0015] Fig. 9 This is a diagram for explaining an example of a circuit configuration of a pixel circuit.

[0016] Fig.10 This is a diagram for explaining an example of the operation of a pixel circuit.

[0017] Fig.11 This is a diagram schematically showing various wirings connected to a pixel circuit in a comparative example of the present embodiment.

[0018] Fig.12 This is a diagram for explaining a case where a short circuit occurs between the anode and the cathode of a light-emitting element in a comparative example of the present embodiment.

[0019] Fig.13 This is a diagram showing an example of horizontal stripes generated in a display area in a comparative example of the present embodiment.

[0020] Fig.14 Schematic diagram of various wirings connected to the pixel circuit in this embodiment.

[0021] Fig.15 A diagram showing an example of a layout of a pixel circuit in this embodiment.

[0022] Fig.16 This is a diagram for explaining a case where a short circuit occurs between the anode and the cathode of a light-emitting element in this embodiment.

[0023] Fig.17 This is a diagram for explaining the brightness variation of the light-emitting element occurring in this embodiment.

[0024] Fig.18 FIG. 1 is a diagram showing an example of vertical stripes generated in the display area in this embodiment.

[0025] The reference numerals are described as follows:

[0026] DSP display device, DA display area, NDA non-display area, PX pixel,

[0027] SP, SP1, SP2, SP3 sub-pixel, AP, AP1, AP2, AP3 opening, LE, LE1,

[0028] LE2, LE3 lower electrode, UE, UE1, UE2, UE3 upper electrode, OR, OR1, OR2,

[0029] OR3 organic layer, SE, SE1, SE2, SE3 sealing layer, Tr1 to Tr7 transistors, Cst holding capacitor, 5 rib, 6 partition wall, 10 substrate, 11 insulating layer, 12 circuit layer, 13 insulating layer, 14 resin layer, 15 sealing layer, 16 resin layer, 20 light emitting element, 61 lower part, 62 upper part, 100 pixel circuit DETAILED DESCRIPTION

[0030] An embodiment will be described with reference to the drawings.

[0031] The present disclosure is only an example, and appropriate changes that maintain the main purpose of the invention and that are easily conceivable by those skilled in the art are of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part of the drawings are sometimes schematically shown compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same figure mark is sometimes used to mark the constituent elements that perform the same or similar functions as the constituent elements described in the drawings that appeared in the previous text, and repeated detailed descriptions are appropriately omitted.

[0032] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are described as needed for ease of understanding. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Observing various elements parallel to the third direction Z is referred to as a top view.

[0033] The display device of this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element (light emitting element), and is mounted on a television, a notebook computer, a portable terminal, a mobile phone, and the like.

[0034] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the present embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0035] In the present embodiment, the shape of the substrate 10 in plan view is a rectangle, but the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0036] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y that intersect each other. The pixel PX includes a plurality of sub-pixels SP. In an example, the plurality of sub-pixels SP include a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. It should be noted that the plurality of sub-pixels SP may include sub-pixels of other colors such as white together with the sub-pixels SP1, SP2, and SP3. In addition, the plurality of sub-pixels SP may also include sub-pixels of other colors instead of any one of the sub-pixels SP1, SP2, and SP3.

[0037] It should be noted that, as will be described in detail later, each of the plurality of sub-pixels SP includes a pixel circuit and a light-emitting element driven by the pixel circuit. The pixel circuit is composed of, for example, a plurality of transistors (switching elements composed of thin film transistors). The light-emitting element is the above-mentioned organic light-emitting diode. For example, the sub-pixel SP1 has a light-emitting element that emits light in a red wavelength range, the sub-pixel SP2 has a light-emitting element that emits light in a green wavelength range, and the sub-pixel SP3 has a light-emitting element that emits light in a blue wavelength range.

[0038] Figure 2 An example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in a pixel PX is shown. Here, four pixels PX will be described.

[0039] The sub-pixels SP1, SP2, and SP3 constituting one pixel PX are respectively formed in a substantially rectangular shape extending in the second direction Y, and are arranged in the first direction X. If the two pixels PX arranged in the first direction X are focused on, the colors displayed in the sub-pixels SP adjacent to each other in the first direction X are different from each other. In addition, if the two pixels PX arranged in the second direction Y are focused on, the colors displayed in the sub-pixels SP adjacent to each other in the second direction Y are the same. It should be noted that the area of ​​each of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0040] Figure 3 Another example of the layout of the plurality of sub-pixels SP ( SP1 , SP2 , and SP3 ) included in the pixel PX is shown.

[0041] Sub-pixels SP1 and SP2 constituting one pixel PX are arranged in the second direction Y, sub-pixels SP1 and SP3 are arranged in the first direction X, and sub-pixels SP2 and SP3 are arranged in the first direction X. Sub-pixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and sub-pixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of ​​sub-pixel SP2 is larger than that of sub-pixel SP1, and the area of ​​sub-pixel SP3 is larger than that of sub-pixel SP2. It should be noted that the shape and area of ​​sub-pixel SP1 may be the same as those of sub-pixel SP2.

[0042] If the focus is on two pixels PX arranged in the first direction X, in the region where sub-pixels SP1 and SP3 are alternately arranged, and in the region where sub-pixels SP2 and SP3 are alternately arranged, the colors displayed in the sub-pixels SP adjacent to each other in the first direction X are different from each other. On the other hand, if the focus is on two pixels PX arranged in the second direction Y, in the region where sub-pixels SP1 and SP2 are alternately arranged, the colors displayed in the sub-pixels SP adjacent to each other in the second direction Y are different from each other. In addition, in the region where a plurality of sub-pixels SP3 are arranged, the colors displayed in the sub-pixels SP adjacent to each other in the second direction are the same.

[0043] It should be noted that Figure 2 as well as Figure 3 The outer shapes of the sub-pixels SP1, SP2, and SP3 shown correspond to the outer shapes of the regions displaying colors (that is, light-emitting regions) in the sub-pixels SP, but the outer shapes are shown in a simplified manner and do not necessarily reflect the actual shapes.

[0044] Here, the display area DA in the present embodiment is provided with ribs and partitions, the details of which will be described later. The ribs have openings in the sub-pixels SP1, SP2, and SP3, respectively. The partitions are provided at the boundaries of adjacent sub-pixels SP, and overlap with the ribs when viewed from above. Specifically, the partitions are provided between the adjacent openings (sub-pixels SP) in the first direction X, and between the adjacent openings (sub-pixels SP) in the second direction Y. Thus, the partitions as a whole have a lattice shape formed in a manner of dividing the sub-pixels SP1, SP2, and SP3. In other words, the partitions, like the ribs, can also be said to have openings in the sub-pixels SP1, SP2, and SP3.

[0045] Figure 4 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AA in FIG. In the display device DSP, an insulating layer 11 called a primer layer is disposed on a light-transmitting substrate 10 such as glass (on the side where the light-emitting element is disposed).

[0046] The insulating layer 11 has a three-layer stacked structure including, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). It should be noted that the insulating layer 11 is not limited to a three-layer stacked structure. The insulating layer 11 may have a stacked structure having more than three layers, or may have a single-layer structure or a two-layer stacked structure.

[0047] The circuit layer 12 is disposed on the insulating layer 11 . The circuit layer 12 has a pixel circuit (various circuits and wirings) for driving the light-emitting element included in each of the sub-pixels SP1 , SP2 , and SP3 as described above. The circuit layer 12 is covered with the insulating layer 13 .

[0048] The insulating layer 13 functions as a planarizing film that planarizes the unevenness generated by the circuit layer 12. Figure 4 Although not shown in the figure, a contact hole for connecting the lower electrode LE to the pixel circuit is provided in the insulating layer 13 .

[0049] The lower electrodes LE (LE1, LE2, and LE3) are arranged on the insulating layer 13. The ribs 5 are arranged on the insulating layer 13 and the lower electrodes LE. The end portions (parts) of the lower electrodes LE are covered by the ribs 5.

[0050] The partition wall 6 has a lower portion 61 disposed on the rib 5, and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a greater width than the lower portion 61 in the first direction X and the second direction Y. Thus, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. This shape of the partition wall 6 can be called an overhanging shape.

[0051] The organic layer OR (OR1, OR2, and OR3) and the upper electrodes UE (UE1, UE2, and UE3) together with the lower electrodes LE (LE1, LE2, and LE3) constitute a light emitting element included in the sub-pixel SP.

[0052] like Figure 4 As shown, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b separated from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b separated from each other. The first organic layer OR1a passes through the opening AP1 (the opening of the rib 5 in the sub-pixel SP1) and contacts the lower electrode LE1, and covers a part of the rib 5. The second organic layer OR1b is located above the upper portion 62. The first upper electrode UE1a is opposite to the lower electrode LE1 and covers the first organic layer OR1a. Moreover, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0053] In addition, if Figure 4As shown, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b separated from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b separated from each other. The first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 (the opening of the rib 5 in the sub-pixel SP2) and covers a portion of the rib 5. The second organic layer OR2b is located above the upper portion 62. The first upper electrode UE2a is opposite to the lower electrode LE2 and covers the first organic layer OR2a. Moreover, the first upper electrode UE2a contacts the side of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0054] In addition, if Figure 4 As shown, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b separated from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b separated from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 (the opening of the rib 5 in the sub-pixel SP3) and covers a portion of the rib 5. The second organic layer OR3b is located above the upper portion 62. The first upper electrode UE3a is opposite to the lower electrode LE3 and covers the first organic layer OR3a. Moreover, the first upper electrode UE3a contacts the side of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0055] exist Figure 4 In the illustrated example, the sub-pixels SP1 , SP2 , and SP3 include cover layers CP1 , CP2 , and CP3 (optical path adjustment layers) for adjusting optical characteristics of light emitted from the light emitting layers of the organic layers OR1 , OR2 , and OR3 .

[0056] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b which are separated from each other. The first cap layer CP1a is located at the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0057] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b which are separated from each other. The first cap layer CP2a is located at the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0058] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b which are separated from each other. The first cap layer CP3a is located at the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0059] Sealing layers SE1, SE2 and SE3 are respectively arranged in sub-pixels SP1, SP2 and SP3. Sealing layer SE1 continuously covers the components of sub-pixel SP1 including the first cap layer CP1a, the partition wall 6 and the second cap layer CP1b. Sealing layer SE2 continuously covers the components of sub-pixel SP2 including the first cap layer CP2a, the partition wall 6 and the second cap layer CP2b. Sealing layer SE3 continuously covers the components of sub-pixel SP3 including the first cap layer CP3a, the partition wall 6 and the second cap layer CP3b.

[0060] exist Figure 4 In the example shown, the second organic layer OR1b, the second upper electrode UE1b, the second cover layer CP1b, and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the partition wall 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the partition wall 6 between the sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, the second cover layer CP3b, and the sealing layer SE3 on the partition wall 6.

[0061] The sealing layers SE1 , SE2 , and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15 . Furthermore, the sealing layer 15 is covered with a resin layer 16 .

[0062] The insulating layer 13 and the resin layers 14 and 16 are formed of an organic material. The ribs 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are formed of an inorganic material such as silicon nitride (SiNx).

[0063] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may also be formed of a conductive oxide such as ITO.

[0064] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE is equivalent to the anode (electrode) and the upper electrode UE is equivalent to the cathode (electrode). In addition, when the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE is equivalent to the anode (electrode) and the lower electrode LE is equivalent to the cathode (electrode).

[0065] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. For example, the organic layer OR has a structure in which a hole injection layer, a hole input layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order.

[0066] The cap layer CP (CP1, CP2 and CP3) is formed, for example, by a multilayer body of multiple transparent thin films. The multilayer body may also include a thin film formed of an inorganic material and a thin film formed of an organic material as multiple thin films. In addition, these multiple thin films have different refractive indices from each other. The material of the thin film constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. It should be noted that the cap layer CP may also be omitted.

[0067] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surface of the lower portion 61. The pixel voltage is supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 included in each of the sub-pixels SP (SP1, SP2, and SP3).

[0068] If a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in a red wavelength range. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in a green wavelength range. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in a blue wavelength range.

[0069] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may also emit light of the same color (for example, white). In this case, the display device DSP may also include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0070] Figure 5 6 is a schematic enlarged cross-sectional view of the partition wall 6. Figure 5 In FIG. 1 , elements other than the ribs 5, the partitions 6, the insulating layer 13, and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE corresponds to any one of the lower electrodes LE1, LE2, and LE3 described above.

[0071] exist Figure 5In the example shown, the lower portion 61 of the partition wall 6 includes a blocking layer (bottom portion) 611 disposed on the rib portion 5, and a metal layer (shaft portion) 612 disposed on the blocking layer 611. The blocking layer 611 is formed of a material different from that of the metal layer 612, for example, a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN). The metal layer 612 is formed thicker than the blocking layer 611. The metal layer 612 may be a single-layer structure or a stacked structure of different metal materials. As an example, the metal layer 612 is formed of, for example, aluminum (Al) or an aluminum alloy.

[0072] The upper portion (top portion) 62 is thinner than the lower portion 61. Figure 5 In the example shown, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is formed of titanium (Ti), and the second layer 622 is formed of ITO.

[0073] exist Figure 5 In the example shown, the width of the lower portion 61 decreases as it approaches the upper portion 62. That is, the side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the direction Z. The upper portion 62 includes an end 62a protruding from the side surface 61a and an end 62b protruding from the side surface 61b.

[0074] The protrusion amount D of the end portions 62a and 62b from the side surfaces 61a and 61b (hereinafter, referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. The protrusion amount D of the partition wall 6 in the present embodiment corresponds to the distance between the lower end (blocking layer 611) of the side surfaces 61a and 61b and the end portions 62a and 62b in the width direction (first direction X or second direction Y) orthogonal to the third direction Z of the partition wall 6.

[0075] It should be noted that in Figure 5 In the example shown, the side surface of the blocking layer 611 is aligned with the side surface of the metal layer 612 to form a plane without steps, but for example, the side surface of the blocking layer 611 may be slightly retreated relative to the side surface of the metal layer 612, or may protrude relative to the side surface of the metal layer 612. Figure 5 In the embodiment, the side surfaces of the blocking layer 611 and the metal layer 612 (that is, the side surfaces 61a and 61b of the lower portion 61) are inclined relative to the third direction Z, but the side surfaces may also be parallel to the third direction Z.

[0076] The structure of the partition wall 6 and the material of each part of the partition wall 6 can be appropriately selected in consideration of, for example, the method of forming the partition wall 6 .

[0077] Here, in this embodiment, the partition wall 6 is formed to divide the sub-pixel SP in a plan view. The organic layer OR is formed by, for example, an anisotropic or directional vacuum deposition method. However, when an organic material for forming the organic layer OR is deposited on the entire substrate 10 with the partition wall 6 disposed, the partition wall 6 has Figure 4 as well as Figure 5 Since the shape shown is shown, the organic layer OR is hardly formed on the side surface of the partition wall 6. Thus, the organic layer OR (light-emitting element) partitioned for each sub-pixel SP can be formed by the partition wall 6.

[0078] Figure 6 to Figure 8 FIG. 6 is a schematic cross-sectional view for explaining a light emitting element formed by using the partition wall 6. Figure 6 to Figure 8 In the figure, the substrate 10, the insulating layer 11 and the circuit layer 12 are omitted. Figure 6 to Figure 8 The sub-pixels SPα, SPβ, and SPγ shown correspond to any of the sub-pixels SP1, SP2, and SP3.

[0079] First, as described above, in the state where the partition wall 6 is arranged, Figure 6 As shown, an organic layer OR, an upper electrode UE, a cap layer CP, and a sealing layer SE are sequentially formed by evaporation relative to the entire substrate 10. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. The organic layer OR is separated into a first organic layer ORa that passes through the opening AP and contacts the lower electrode LE and a second organic layer Orb on the partition wall 6 by a suspended partition wall 6, the upper electrode UE is separated into a first upper electrode UEa that covers the first organic layer Ora and a second upper electrode UEb that covers the second organic layer Orb, and the cap layer CP is separated into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa contacts the lower portion 61 of the partition wall 6. The sealing layer SE continuously covers the first cap layer CPa, the partition wall 6, and the second cap layer CPb.

[0080] Next, if Figure 7 As shown in FIG. 1 , a resist R is formed on the sealing layer SE. The resist R covers the sub-pixel SPα. That is, the resist R is arranged directly above the first organic layer ORa, the first upper electrode UEa, and the first cover layer CPa located in the sub-pixel SPα. The resist R is also located directly above the second organic layer ORb, the second upper electrode UEb, and the second cover layer CPb on the partition wall 6 between the sub-pixel SPα and the sub-pixel SPβ, which are close to the sub-pixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0081] Furthermore, by etching with the resist R as a mask, as Figure 8As shown, the exposed portions of the organic layer OR, the upper electrode UE, the cover layer CP, and the sealing layer SE from the resist R are removed. As a result, a light-emitting element including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cover layer CPa is formed in the sub-pixel SPα. On the other hand, in the sub-pixels SPβ and SPγ, the lower electrode LE is exposed. It should be noted that the above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cover layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0082] As described above, when the light-emitting element of the sub-pixel SPα is formed, the resist R is removed, and the light-emitting elements of the sub-pixels SPβ and SPγ are sequentially formed in the same manner as the sub-pixel SPα.

[0083] As exemplified for the above sub-pixels SPα, SPβ, and SPγ, the light-emitting elements of the sub-pixels SP1, SP2, and SP3 are formed, and the resin layer 14, the sealing layer 15, and the resin layer 16 are further formed, thereby achieving Figure 4 The structure of the display device DSP is shown.

[0084] Here, as described above, each of the plurality of sub-pixels SP includes a pixel circuit for driving a light-emitting element. Fig. 9 An example of the circuit configuration of a pixel circuit is described below. Fig. 9 The pixel circuit 100 shown is a 7Tr1C pixel circuit composed of seven transistors Tr1 to Tr7 and one holding capacitor Cst.

[0085] In the following description, Fig. 9 In each of the transistors Tr1 to Tr7 shown in the figure, one of the source / drain terminals is set as the first terminal, and the other is set as the second terminal. Fig. 9 One terminal of the storage capacitor Cst (capacitance element realizing the storage capacitor Cst) shown is set as a first terminal, and the other terminal is set as a second terminal.

[0086] The first terminal of transistor Tr1 is connected to the first terminal of transistor Tr2 and the second terminal of transistor Tr5 via node n3. The second terminal of transistor Tr1 is connected to a data signal line for supplying data signal Data. Data signal Data is equivalent to a signal (pixel signal) written to a pixel. In addition, transistor Tr1 is, for example, an n-channel transistor.

[0087] The transistor Tr2 is equivalent to a driving transistor (DRT) that supplies current to the light-emitting element 20 included in the sub-pixel SP (that is, the light-emitting element 20 driven by the pixel circuit 100). The first terminal of the transistor Tr2 is connected to the first terminal of the transistor Tr1 and the second terminal of the transistor Tr5 via the node n3. The second terminal of the transistor Tr2 is connected to the second terminal of the transistor Tr3, the first terminal of the transistor Tr4, and the first terminal of the transistor Tr7 via the node n1. In addition, the transistor Tr2 is, for example, an n-channel transistor.

[0088] The first terminal of transistor Tr3 is connected to the gate terminal of transistor Tr2 and the second terminal of holding capacitor Cst via node n2. The second terminal of transistor Tr3 is connected to the second terminal of transistor Tr2, the first terminal of transistor Tr4 and the first terminal of transistor Tr7 via node n1. In addition, transistor Tr3 is, for example, an n-channel transistor.

[0089] The first terminal of transistor Tr4 is connected to the second terminal of transistor Tr2, the second terminal of transistor Tr3, and the first terminal of transistor Tr7 via node n1. The second terminal of transistor Tr4 is connected to a power line supplying power supply voltage VDDEL. Transistor Tr4 is, for example, a p-channel transistor.

[0090] The first terminal of transistor Tr5 is connected to the first terminal of transistor Tr6, the first terminal of holding capacitor Cst and the anode terminal of light emitting element 20 via node n4. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr1 and the first terminal of transistor Tr2 via node n3. It should be noted that transistor Tr5 is, for example, a p-channel transistor.

[0091] The first terminal of transistor Tr6 is connected to the first terminal of transistor Tr5, the first terminal of storage capacitor Cst and the anode terminal of light emitting element 20 via node n4. The second terminal of transistor Tr6 is connected to a power supply line for supplying initialization voltage Vini. Transistor Tr6 is, for example, an n-channel transistor.

[0092] The first terminal of transistor Tr7 is connected to the second terminal of transistor Tr2, the second terminal of transistor Tr3, and the first terminal of transistor Tr4 via node n1. The second terminal of transistor Tr7 is connected to a power line supplying power supply voltage VSH. Transistor Tr7 is, for example, an n-channel transistor.

[0093] In addition, if Fig. 9As shown, the gate terminal of transistor Tr1 is connected to the gate signal line supplied with gate signal Scan2. The gate terminal of transistor Tr3 is connected to the gate signal line supplied with gate signal Scan1. The gate terminals of transistors Tr4 to Tr6 are connected to the control signal line supplied with control signal EM. The gate terminal of transistor Tr7 is connected to the gate signal line supplied with gate signal Scan3.

[0094] The first terminal of the storage capacitor Cst is connected to the first terminal of the transistor Tr5, the first terminal of the transistor Tr6 and the anode terminal of the light emitting element 20 via the node n4. The second terminal of the storage capacitor Cst is connected to the gate terminal of the transistor Tr2 and the first terminal of the transistor Tr3 via the node n2.

[0095] The anode terminal of the light emitting element 20 is connected to the first terminal of the transistor Tr5, the first terminal of the transistor Tr6, and the first terminal of the holding capacitor Cst via the node n4. The cathode terminal of the light emitting element 20 is connected to a power line that supplies the power supply voltage VSSEL. The power supply voltage VDDEL is equivalent to the anode voltage supplied to the light emitting element 20, and the power supply voltage VSSEL is equivalent to the cathode voltage supplied to the light emitting element 20.

[0096] Below, refer to Fig.10 , briefly explain the above Fig. 9 An example of the operation of the pixel circuit 100 (7Tr1C pixel circuit) is shown. Fig.10 1 is a timing chart showing an output example of the gate signals Scan1 to Scan3 and the control signal EM to the pixel circuit 100 (including the sub-pixel SP of the pixel circuit 100 ).

[0097] It should be noted that the plurality of transistors constituting the pixel circuit 100 include n-channel transistors and p-channel transistors, but the n-channel transistor is a switch element that becomes an off state (non-conducting state) when a low (level) signal is supplied to the gate terminal, and becomes a conducting state (conducting state) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switch element that becomes an off state (non-conducting state) when a high (level) signal is supplied to the gate terminal, and becomes a conducting state (conducting state) when a low (level) signal is supplied to the gate terminal.

[0098] exist Fig.10 In the illustrated period t0 , the control signal EM is at a low level. Therefore, among the seven transistors included in the pixel circuit 100 , the transistor Tr4 and the transistor Tr5 are in an on state, and the transistor Tr6 is in an off state.

[0099] Furthermore, in the period t0 , the gate signals Scan1 to Scan3 are at a low level, and therefore the transistors Tr1 , Tr3 , and Tr7 are in an off state.

[0100] Thus, a current controlled by the gate voltage of the transistor Tr2 (voltage supplied to the gate terminal of the transistor Tr2 based on the data signal Data of the previous frame) flows to the light emitting element 20 (OLED), and the light emitting element 20 is kept emitting light.

[0101] It should be noted that, at the timing when the period t0 ends, the control signal EM is switched from the low level to the high level.

[0102] Next, Fig.10 The period t1 shown corresponds to the reset period. During the period t1, the control signal EM is at a high level, so the transistors Tr4 and Tr5 are in the off state, and the transistor Tr6 is in the on state. In this case, the initialization voltage Vini is supplied to the node n4 via the transistor Tr6, but the initialization voltage Vini is set to a value at which no current flows through the light emitting element 20, so no current flows through the light emitting element 20 during the period t1.

[0103] In addition, at the timing of the start of period t1, the gate signal Scan1 is switched from a low level to a high level. Therefore, during period t1, transistor Tr3 is turned on. Moreover, after the end of period t0 and before the start of period t1, the gate signal Scan3 is switched from a low level to a high level. Therefore, during period t1, transistor Tr7 is turned on. As a result, the power supply voltage VSH is supplied to the gate terminal of transistor Tr2 via transistor Tr7 and transistor Tr3. In this case, a voltage of VSH-Vini is applied to the holding capacitor Cst (between the first and second terminals), and the information of the previous frame is reset.

[0104] It should be noted that, at the timing when the period t1 ends, the gate signal Scan3 is switched from the high level to the low level.

[0105] Next, Fig.10 The period t2 shown corresponds to the sampling period. At the timing when the period t2 starts, the gate signal Scan2 is switched from a low level to a high level. Therefore, during the period t2, the transistor Tr1 is turned on. In addition, during the period t2, the gate signal Scan3 is at a low level, so the transistor Tr7 is turned off.

[0106] In this case, the data signal Data (voltage Vdata corresponding to the signal) and the threshold voltage Vth of the second transistor Tr2 (that is, a voltage equivalent to Vdata+Vth) are supplied to the gate terminal of the transistor Tr2 via the transistor Tr1, the transistor Tr2, and the transistor Tr3. Thus, a voltage of Vdata+Vth-Vini is applied to the holding capacitor Cst, and information related to Vdata and Vth is written into the holding capacitor Cst (that is, the voltage controlling the current supplied by the transistor Tr2 to the light emitting element 20 is held by the holding capacitor Cst).

[0107] It should be noted that, at the timing when the period t2 ends, the gate signal Scan1 is switched from the high level to the low level.

[0108] Next, Fig.10 The period t3 shown corresponds to the light-emitting period. During the period t3, the gate signal Scan1 is at a low level, so the transistor Tr3 is in an off state. In addition, before the start of the period t3, the gate signal Scan2 is switched from a high level to a low level, so the transistor Tr1 is in an off state. Moreover, at the timing of the start of the period t3, the control signal EM is switched from a high level to a low level. Therefore, the transistors Tr4 and Tr5 are in an on state, and the transistor Tr6 is in an off state.

[0109] Here, if the first terminal of transistor Tr2 is set as the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n2 to node n3) of transistor Tr2 becomes the voltage (Vdata+Vth-Vini) of the holding capacitor Cst. In this case, transistor Tr2 becomes conductive, and current flows from the power line (power line supplying the power supply voltage VDDEL) connected to the second terminal of transistor Tr4 to node n4. Along with this, the potential of node n4 begins to rise, and when the potential exceeds the threshold of the light-emitting element 20 (OLED), the circuit begins to flow to the light-emitting element 20, and the light-emitting element 20 begins to emit light. Finally, when the current Ioled flowing to the light-emitting element 20 reaches the output current (the output current in the saturation region of transistor Tr2) Idrt given by transistor Tr2, the potential of node n4 stops rising, and the light-emitting element 20 becomes a stable light-emitting state.

[0110] Here, when the voltage Vgs=Vdata+Vth-Vini between the gate terminal and the source terminal of the transistor Tr2 is substituted into the TFT saturation formula, Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 When Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini) 2In addition, Cox is the gate electrostatic capacitance per unit area, μ is the carrier mobility, W is the channel width of the transistor Tr2, and L is the channel length of the transistor Tr2.

[0111] It can be seen from this that Idrt is a value that does not depend on the threshold voltage Vth of the transistor Tr2 (that is, a current that does not depend on the threshold voltage Vth of the transistor Tr2 flows through the light emitting element 20 ), and the influence of the variation in the threshold voltage Vth on Idrt can be eliminated.

[0112] That is, we can say Fig. 9 The pixel circuit 100 (7Tr1C pixel circuit) shown has a function of correcting the variation of the threshold voltage Vth of the transistor Tr2 (Vth correction function).

[0113] Here, Fig.11 Schematically shows various wirings connected to the pixel circuit 100 included in each of the plurality of sub-pixels SP arranged in the display area DA of the display device DSP according to the comparative example of the present embodiment. Fig.11 , a gate signal line for supplying gate signals Scan1 to Scan3 , a control signal line for supplying a control signal EM, a power supply line for supplying an initialization voltage Vini, and a data signal line for supplying a data signal Data are shown among a plurality of wirings connected to the pixel circuit 100 .

[0114] like Fig.11 As shown, in the comparative example of the present embodiment, the gate signal lines for supplying the gate signals Scan1 to Scan3, the control signal lines for supplying the control signal EM, and the power supply lines for supplying the initialization voltage Vini extend in the first direction X, and are connected to the pixel circuit 100 included in each of the plurality of sub-pixels SP arranged in the first direction X. In addition, for each row consisting of the plurality of sub-pixels SP arranged in the first direction X in the display area DA, the gate signal lines for supplying the gate signals Scan1 to Scan3, the control signal lines for supplying the control signal EM, and the power supply lines for supplying the initialization voltage Vini are arranged in the second direction Y.

[0115] On the other hand, the data signal line for supplying the data signal Data extends in the second direction Y and is connected to the pixel circuit 100 included in each of the plurality of sub-pixels SP arranged in the second direction Y. In addition, for each column of the sub-pixels SP arranged in the second direction Y in the display area DA, the data signal line for supplying the data signal Data is arranged in the first direction X.

[0116] Here, Fig.121 shows a plurality of pixel circuits 100 included in a plurality of sub-pixels SP constituting one row in the display area DA (that is, a plurality of pixel circuits 100 connected to one power line supplying the initialization voltage Vini in the comparative example of the present embodiment). Fig.12 In the above, it is assumed that a short circuit occurs between the anode and cathode of the light emitting element 20 driven by one pixel circuit 100 a among the plurality of pixel circuits 100 (EL short circuit between the anode electrode and the cathode electrode).

[0117] As described above, when a short circuit occurs between the anode and cathode of the light emitting element 20, the light emitting element 20 cannot emit light. Fig.13 As shown, the sub-pixel SP including the light emitting element 20 is visually recognized as a dark spot 201 in the display area DA (the picture displayed in the display area DA).

[0118] In addition, in the above Fig.10 As described in , in order to make the light emitting element 20 emit light in the pixel circuit 100, a voltage of Vdata+Vth-Vini needs to be applied to the storage capacitor Cst, and the transistor Tr6 in the pixel circuit 100 is turned on.

[0119] In this case, the control signal line that supplies the control signal EM for setting the transistor Tr6 to the on state extends in the first direction X, and the pixel circuits 100 included in the plurality of sub-pixels SP constituting one row (that is, arranged in the first direction X) turn on the transistor Tr6 at the same timing.

[0120] In the comparative example of the present embodiment, the power supply line for supplying the initialization voltage Vini extends in the first direction X, and the initialization voltage Vini is commonly supplied to the plurality of pixel circuits 100 included in the plurality of sub-pixels SP constituting one row. Fig. 9 As described in , the initialization voltage Vini is supplied to the node n4 via the transistor Tr6 , but the initialization voltage Vini is set to a value that does not flow current to the light emitting element 20 . Therefore, current does not flow to the light emitting element 20 , and the pixel circuit 100 can operate properly.

[0121] However, in the above Fig.12 In the case shown in FIG. 1 , in which a short circuit occurs between the anode and cathode of the light-emitting element 20 driven by the pixel circuit 100a, when the transistor Tr6 in the pixel circuit 100a is turned on, current flows from the power line supplying the initialization voltage Vini to the power line supplying the power voltage VSSEL via the short circuit, resulting in a potential change in the initialization voltage Vini supplied via the power line connected to the pixel circuit 100a.

[0122] Since the power supply line for supplying the initialization voltage Vini is connected to each of the pixel circuits 100 included in the plurality of sub-pixels SP constituting one row, the initialization voltage Vini with potential fluctuation as described above is also supplied to the pixel circuits 100b other than the pixel circuit 100a.

[0123] As described above, in the pixel circuit 100, the output current Idrt given by the transistor Tr2 is 1 / 2 Cox*μ*W / L*(Vdata-Vini) 2 Therefore, the potential change generated by the initialization voltage Vini affects the output current Idrt. That is, in other sub-pixels SP (that is, sub-pixels SP including the pixel circuit 100b) arranged in the same row as the sub-pixel SP including the pixel circuit 100a, the brightness of the light-emitting element 20 changes according to the potential change generated by the initialization voltage Vini as described above.

[0124] It should be noted that the brightness change of the light-emitting element 20 can be said to be generated in the sub-pixel SP during the period when the potential change of the initialization voltage Vini is generated (that is, the period when the transistor Tr6 of the pixel circuit 100 that drives the short-circuited light-emitting element 20 is in the on state) and the above-mentioned sampling period (the period when the data signal Data is written) coincides.

[0125] It can be seen from this that in the comparative example of the present embodiment, Fig.13 As shown, stripes 202 extending in the first direction X starting from the dark spot 201 are visually recognized in the display area DA (that is, light horizontal stripes are generated in one entire line), and the display quality of the display device DSP is degraded.

[0126] Therefore, in this embodiment, if Fig.14 As shown in FIG. 1 , the power supply line for supplying the initialization voltage Vini is arranged so as to extend in the second direction Y instead of the first direction X. According to this configuration, for example, even if a short circuit occurs between the anode and the cathode of the light-emitting element 20 included in one sub-pixel SP, the initialization voltage Vini with a potential change is not supplied to the plurality of pixel circuits 100 included in the plurality of sub-pixels SP constituting the same row as the sub-pixel SP, thereby avoiding the above-mentioned Fig.13 The illustrated example shows a situation where such light-colored horizontal stripes are generated on the display area DA.

[0127] Fig.15 An example of the layout of the pixel circuit 100 in this embodiment is shown. Fig.15For example, the components of the pixel circuit 100 (transistors Tr1 to Tr7 , storage capacitor Cst, gate signal lines, control signal lines, data signal lines, and various power supply lines) formed in the circuit layer 12 composed of the first to third layers are shown.

[0128] It should be noted that the first layer is a layer formed under the second layer, and the second layer is a layer formed under the third layer. In other words, the first to third layers are stacked in order, with the first layer being the lowermost layer and the third layer being the uppermost layer.

[0129] The first layer is a layer for forming a semiconductor layer, and the second and third layers are layers for forming electrodes constituting a transistor and wirings connected to the transistor.

[0130] Specifically, the transistors Tr1 to Tr7 are formed on the first layer and the second layer. Also, similarly to the transistors Tr1 to Tr7, the storage capacitor Cst is formed on the first layer and the second layer.

[0131] In addition, gate signal lines and control signal lines are formed in the second layer, and data signal lines and various power supply lines are formed in the third layer.

[0132] Regarding the connection between the various elements of the pixel circuit 100, as shown in Fig. 9 Therefore, a detailed description thereof will be omitted here, but Fig.15 As shown, elements formed in different layers are connected together via contact holes CH.

[0133] It should be noted that Fig.15 The layout of the pixel circuit 100 shown is an example, and a portion of the layout of the pixel circuit 1000 may be different from that of the pixel circuit 1000. Fig.15 The examples shown are different.

[0134] Here, Fig.16 1 shows a plurality of pixel circuits 100 included in a plurality of sub-pixels SP constituting one column in the display area DA (that is, a plurality of pixel circuits 100 connected to one power line supplying the initialization voltage Vini in the present embodiment). Fig.16 In the example, it is assumed that a short circuit occurs between the anode and the cathode of the light emitting element 20 driven by one pixel circuit 100 a among the plurality of pixel circuits 100 .

[0135] In this case, in the present embodiment, the power supply line for supplying the initialization voltage Vini extends in the second direction Y (connected to the plurality of pixel circuits 100 arranged in the second direction Y). Fig.16When the transistor Tr6 of the pixel circuit 100a shown is turned on, a short circuit occurs between the anode and cathode of the light emitting element 20 driven by the pixel circuit 100a, causing a potential change in the initialization voltage Vini supplied via the power line connected to the pixel circuit 100a.

[0136] Since the power supply line for supplying the initialization voltage Vini is connected to each of the pixel circuits 100 included in the plurality of sub-pixels SP constituting one column, the initialization voltage Vini with a potential change as described above is also supplied to the pixel circuits 100c other than the pixel circuit 100a.

[0137] As described above, in the pixel circuit 100, the output current Idrt given by the transistor Tr2 is expressed by 1 / 2Cox*μ*W / L*(Vdata-Vini) 2 Therefore, the potential change generated by the initialization voltage Vini affects the output current Idrt. That is, in the plurality of sub-pixels SP arranged in the same column as the sub-pixel SP including the pixel circuit 100a (that is, the sub-pixel SP including the pixel circuit 100c), the luminance of the light-emitting element 20 changes due to the potential change generated by the initialization voltage Vini as described above.

[0138] As can be seen from the above, in this embodiment, stripes (light vertical stripes) extending in the second direction Y starting from dark spots visually confirmed by short circuits between the anode and cathode of the light emitting element 20 are considered to occur in the display area DA.

[0139] Here, Fig.17 An output example of gate signals Scan1 to Scan3 and a control signal EM for each row composed of a plurality of sub-pixels SP arranged in the display area DA is shown.

[0140] It should be noted that in Fig.17 In the figure, for example, due to a short circuit between the anode and cathode of the light-emitting element 20 included in a sub-pixel SP among the multiple sub-pixels SP constituting n rows, the initialization voltage Vini produces a potential change during the period T when the transistor Tr6 of the pixel circuit 100 included in the sub-pixel SP is in the on state (hereinafter marked as the change period).

[0141] In addition, as described above, the brightness variation of the light emitting element 20 due to the influence of the potential variation of the initialization voltage Vini is a case where the sampling period and the variation period T overlap. Fig.17As shown, the timing of outputting gate signals Scan1 to Scan3 and control signal EM is different in each row in display area DA. In other words, the timing of starting and ending the sampling period is different for different rows in display area DA, so in this embodiment, the brightness of the light emitting element 20 does not change in all sub-pixels SP that are arranged in the same column as the sub-pixel SP including the light emitting element 20 with a short circuit between the anode and the cathode (that is, connected to the power supply line that supplies the same initialization voltage Vini as the sub-pixel SP).

[0142] Specifically, when the gate signals Scan1 to Scan3 and the control signal EM are output (supplied) according to a predetermined horizontal period (1H), Fig.17 In the example shown, the period (that is, the variation period) T during which the potential of the initialization voltage Vini varies by supplying a control signal EM that sets the transistor Tr6 of the pixel circuit 100 included in the plurality of sub-pixels SP constituting n rows to an on state is four horizontal periods (4H), and the variation period T overlaps with the sampling period only for the n-2 row, the n-1 row, the n row, and the n+1 row.

[0143] That is, according to Fig.17 In the example shown, even if a short circuit occurs between the anode and cathode of the light-emitting element 20 included in a sub-pixel SP among a plurality of sub-pixels SP constituting n rows, only the brightness of the light-emitting element 20 included in the sub-pixels SP of the n-2 row, n-1 row, n row and n+1 row of the sub-pixels SP arranged in the same column as the sub-pixel SP changes, and the brightness of the sub-pixels SP constituting other rows does not change.

[0144] In this case, if Fig.18 As shown, in the display area DA, short vertical stripes 203 are generated starting from the dark spot 201, spanning two sub-pixels SP located in the opposite direction to the second direction Y (that is, the upward direction) and one sub-pixel SP located in the second direction Y (that is, the downward direction).

[0145] As described above, the display device DSP of the present embodiment includes: a substrate 10; a plurality of sub-pixels SP arranged in a matrix along the first direction X and the second direction Y intersecting each other on the display area DA on the substrate 10; a control signal line for supplying a control signal EM to each of the plurality of sub-pixels SP; and a power supply line for supplying an initialization voltage Vini to each of the plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a pixel circuit 100 composed of a plurality of transistors and a light-emitting element 20 driven by the pixel circuit 100. The plurality of transistors constituting the pixel circuit 100 include a transistor Tr6 (first transistor) arranged between the power supply line for supplying the initialization voltage Vini and the light-emitting element 20 and turned on based on the control signal EM. In addition, the control signal line for supplying the control signal EM extends in a manner connected to the plurality of sub-pixels SP arranged in the first direction X and arranged in a row in the second direction Y. The power supply line for supplying the initialization voltage Vini extends in a manner connected to the plurality of sub-pixels SP arranged in the second direction Y and arranged in a row in the first direction X.

[0146] It should be noted that, in addition to multiple transistors, the pixel circuit 100 is also composed of a holding capacitor Cst. The multiple transistors include a transistor Tr2 (a second transistor) that supplies current to the light-emitting element 20. The holding capacitor Cst is configured such that the transistor Tr2 maintains a voltage that controls the current supplied to the light-emitting element 20, and the transistor Tr6 is connected to the holding capacitor Cst.

[0147] In addition, the plurality of transistors constituting the pixel circuit 100 include a transistor Tr1 (third transistor) connected to a data signal line for supplying a data signal Data and turned on based on a gate signal Scan2. The data signal line for supplying the data signal Data extends in a manner connected to a plurality of sub-pixels SP arranged in the second direction Y and arranged in a row in the first direction X. The gate signal line for supplying the gate signal Scan2 extends in a manner connected to a plurality of sub-pixels SP arranged in the first direction X and arranged in a row in the second direction Y.

[0148] In the present embodiment, according to the above-mentioned configuration, in order to write the data signal Data to each of the plurality of sub-pixels SP (a row composed of the plurality of sub-pixels SP) arranged in the first direction X, even when the transistors Tr6 of the plurality of pixel circuits 100 included in the plurality of sub-pixels SP are turned on, it is possible to avoid, for example, Fig.13 In the case where horizontal stripes are generated in one entire row in the display area DA, as shown in FIG. Fig.18The short vertical stripes 203 shown are generated only in the display area DA, and are at a level that cannot be visually confirmed. That is, according to this embodiment, as in the comparative example of this embodiment described above, it is possible to suppress the degradation of the display quality of the display device DSP compared to the configuration in which the power line for supplying the initialization voltage Vini is extended in the first direction X.

[0149] It should be noted that, in the present embodiment, the control signal line for supplying the control signal EM extends in the first direction X, and the power line for supplying the initialization voltage Vini extends in the second direction Y. However, as long as the control signal line and the power line are arranged in intersecting directions, for example, the control signal line can be extended in the second direction Y, and the power line can be extended in the first direction X.

[0150] In addition, as described above, in order to efficiently drive the light-emitting elements 20 included in the plurality of sub-pixels SP arranged in a matrix, the control signal line for supplying the control signal EM and the gate signal line for supplying the gate signals Scan1 to Scan3 are arranged to extend in the same direction, and the power line for supplying the initialization voltage Vini and the data signal line for supplying the data signal Data are preferably arranged to extend in the same direction.

[0151] Any display device implemented by a person skilled in the art after appropriately changing the design based on the display device described above as the embodiment of the present invention belongs to the scope of the present invention as long as it includes the gist of the present invention.

[0152] In the scope of the concept of the present invention, those skilled in the art can think of various variations, and it should be understood that these variations also belong to the scope of the present invention. For example, variations obtained by those skilled in the art appropriately adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes relative to the above-mentioned embodiments are also included in the scope of the present invention as long as they have the gist of the present invention.

[0153] In addition, other effects brought about by the forms described in the above embodiments that are clearly derived from the description of this specification or that can be appropriately thought of by a person skilled in the art should of course be understood to be brought about by the present invention.

Claims

1. A display device, characterized in that: have: Base material; A plurality of pixels are arranged in a matrix in a display area on the substrate along a first direction and a second direction intersecting each other; a control signal line that supplies a control signal to each of the plurality of pixels; as well as a power supply line for supplying an initialization voltage to each of the plurality of pixels, Each of the plurality of pixels includes a pixel circuit formed of a plurality of transistors and a light emitting element driven by the pixel circuit. The plurality of transistors constituting the pixel circuit include a first transistor, the first transistor being arranged between the power line and the light emitting element and being turned on based on the control signal, The control signal line extends in a manner connected to a plurality of pixels arranged in the first direction and is arranged in parallel in the second direction. The power supply lines extend so as to be connected to a plurality of pixels arranged in the second direction, and are arranged side by side in the first direction.

2. The display device according to claim 1, characterized in that The pixel circuit includes a holding capacitor in addition to the plurality of transistors. The plurality of transistors constituting the pixel circuit include a second transistor for supplying current to the light emitting element. The holding capacitor constituting the pixel circuit is configured to hold a voltage for controlling a current supplied from the second transistor to the light emitting element. The first transistor is connected to the holding capacitor.

3. The display device according to claim 2, characterized in that: Also available: a data signal line that supplies a data signal to each of the plurality of pixels; as well as a gate signal line for supplying a gate signal to each of the plurality of pixels, The plurality of transistors constituting the pixel circuit include a third transistor, the third transistor being connected to the data signal line and being turned on based on the gate signal. The data signal lines extend in a manner connected to a plurality of pixels arranged in the second direction and are arranged in parallel in the first direction. The gate signal lines extend so as to be connected to a plurality of pixels arranged in the first direction, and are arranged side by side in the second direction.

4. The display device according to claim 3, characterized in that: For each of the plurality of pixels, the data signal is written into each of the plurality of pixels arranged in the first direction, The first transistor is turned on to write the data signal to the plurality of pixels arranged in the first direction.

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