Display device

Abstract

The invention relates to a display device. The display device includes a base layer including a display area including a first area and a second area and a non-display area including a chip area and a pad area positioned farther from the display area than the chip area. The display device includes: a first pixel in a first area; a first optical sensor in the second region; a first data line extending from the chip area to the first area in the second direction, and electrically connecting the first pixel to the driving chip; a first readout line extending from the pad region to the second region in the second direction, and electrically connected to the first optical sensor; and a power line extending from the pad area in the second direction to overlap the first readout line in the non-display area.

Description

Technical Field

[0001] The present disclosure relates to a display device, and, for example, to a display device including an optical sensing element. Background Art

[0002] Electronic devices that provide images to users (such as smart phones, digital cameras, laptops, navigation systems, and smart TVs) include a display device for displaying images. The display device includes a display panel that generates images, an input unit such as an input sensor, a camera that captures external images, and one or more suitable sensors.

[0003] The input sensor is arranged on the display panel to detect the user's touch. The sensor may include a fingerprint sensor, a proximity sensor, and an optical sensor. Among the sensors, the fingerprint sensor detects the user's fingerprint provided to the display panel. Summary of the invention

[0004] The present disclosure provides a display device having an increased light sensing area.

[0005] One or more embodiments of the present disclosure provide a display device, the display device comprising: a base layer, comprising a display area and a non-display area, the display area comprising a first area and a second area adjacent to the first area in a first direction, the non-display area comprising a chip area and a pad area, the pad area being positioned farther away from the display area than the chip area in a second direction intersecting the first direction; a driver chip, in the chip area; a first pixel, in the first area and comprising a first light-emitting element; a first optical sensor, in the second area; a first data line, extending from the chip area to the first area in a second direction, and configured to electrically connect the first pixel to the driver chip; a first readout line, extending from the pad area to the second area in a second direction, and electrically connected to the first optical sensor; and a power line, extending from the pad area in the second direction, and overlapping with the first readout line in the non-display area. In one or more embodiments, the first data line and the first readout line do not overlap with each other in the non-display area, and the first readout line and the power line may be at different layers in an area where the first readout line and the power line overlap with each other in the non-display area.

[0006] In one or more embodiments of the present disclosure, a display device includes: a base layer, including a display area and a non-display area defined by a first direction and a second direction intersecting each other, the non-display area including a sealing area, a pad area farther from the display area than the sealing area in the second direction, and a chip area between the sealing area and the pad area; a first inorganic layer, a second inorganic layer, a third inorganic layer, a fourth inorganic layer, a fifth inorganic layer, and a sixth inorganic layer, on the base layer, overlapping with the display area and the non-display area, and sequentially stacked; a first organic layer, a second organic layer, and a third organic layer, on the sixth inorganic layer, exposing the sixth inorganic layer in the sealing area. The invention relates to a contact area of ​​a layer and is stacked in sequence; a driving chip in the chip area; a pixel in the display area and including a dummy electrode, a first transistor, a second transistor and a light-emitting element; an optical sensor in the display area; a data line extending from the chip area to the display area in the second direction and electrically connecting the pixel to the driving chip; a readout line extending from the pad area to the display area in the second direction and electrically connected to the optical sensor; a power line extending from the pad area in the second direction and overlapping with the readout line in the non-display area; and an inorganic encapsulation layer on the third organic layer to cover the light-emitting element and contact with the contact area of ​​the sixth inorganic layer in the sealed area. In one or more embodiments, the data line and the readout line do not overlap with each other in the non-display area, the readout line and the power line may overlap with each other in the sealed area, the readout line may be located below the first inorganic layer or between the fifth inorganic layer and the sixth inorganic layer in the sealed area, and the power line may be located between the first inorganic layer and the fourth inorganic layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of the present disclosure. The accompanying drawings illustrate embodiments of the present disclosure and together with the description are used to explain the principles of the embodiments of the present disclosure. In the accompanying drawings:

[0008] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0009] Figure 2 It is shown Figure 1 A cross-sectional view of an example of a display device shown in ;

[0010] Figure 3 It is shown Figure 2 A cross-sectional view of an example of a display panel shown in ;

[0011] Figure 4 is a block diagram of a display device according to one or more embodiments of the present disclosure;

[0012] Figure 5 Shows Figure 4 An equivalent circuit of one of the pixels shown in and an optical sensor adjacent to the pixel;

[0013] Figure 6 It is shown Figure 5 A cross-sectional view of an example of a light emitting element, a first transistor, a fourth transistor, and a sixth transistor of a pixel shown in FIG.

[0014] Figure 7 It is shown Figure 5 A cross-sectional view of an example of an optical sensing element, a first sensing transistor, and a second sensing transistor of an optical sensor shown in FIG.

[0015] Figure 8 It is shown that the arrangement Figure 4 A view of a planar arrangement of light emitting elements and optical sensing elements in a partial area of ​​a display area shown in FIG.

[0016] Fig. 9 is a plan view of a display device according to one or more embodiments of the present disclosure;

[0017] Fig.10 is a plan view showing a partial area of ​​a display device according to one or more embodiments of the present disclosure;

[0018] Fig.11 is a plan view showing a partial area of ​​a display device according to one or more embodiments of the present disclosure;

[0019] Fig.12 is a plan view showing a first data line, a first readout line, and a power line according to one or more embodiments of the present disclosure;

[0020] Fig.13 It is along Fig.12 A cross-sectional view taken along line II' of FIG.

[0021] Figures 14 to 16 is a cross-sectional view illustrating a sealing area of ​​a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] In the present disclosure, it will also be understood that if (for example, when) a component (or region, layer, portion) is referred to as being "disposed on" "connected to" or "coupled to" another component, it may be directly disposed on / directly connected / directly coupled to a component, or an intervening third component may also be present.

[0023] The same reference numerals represent the same elements throughout the text, and repeated descriptions thereof may not be provided. In addition, in the accompanying drawings, the thickness, proportion and size of the components are exaggerated for clarity of illustration. The term "and / or" includes any and all combinations of one or more of the related elements.

[0024] It will be understood that although terms such as "first" and "second" are used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, without departing from the spirit or scope of the present disclosure, an element referred to as a first element in one or more embodiments may be referred to as a second element in one or more embodiments. Unless otherwise mentioned, a term in the singular may include a plural form.

[0025] In addition, “under,” “below,” “on,” “above,” etc. are used to explain the relative relationship of elements shown in the drawings. Terms may be relative concepts and described based on the directions expressed in the drawings.

[0026] The meaning of “include” specifies properties, fixed quantities, processes, operations, elements, components and / or their (e.g., any suitable) combinations thereof, but does not exclude other properties, fixed quantities, processes, operations, elements, components and / or one or more (e.g., any suitable) combinations thereof.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and unless explicitly defined herein, they should not be interpreted as overly ideal or overly formal meanings.

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0029] Figure 1 is a perspective view of a display device DD according to one or more embodiments of the present disclosure.

[0030] refer to Figure 1, the display device DD according to one or more embodiments of the present disclosure may have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not necessarily limited to this. For example, the display device DD may have one or more suitable shapes, such as a circular shape or other polygonal shapes. Hereinafter, a direction intersecting substantially orthogonally (e.g., vertically) with a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the present disclosure, the meaning of if (e.g., when) observed on a "plane" is defined as a state observed in the third direction DR3.

[0031] A top surface of the display device DD may be defined as a display surface DS and have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated in the display device DD may be provided to a user through the display surface DS.

[0032] The display surface DS may include a display area DA and a non-display area NDA around the display area DA along an edge or periphery of the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display the image IM. The non-display area NDA may be around the display area DA (e.g., surrounding the display area DA), but the present disclosure is not necessarily limited thereto, and the non-display area NDA may be arranged at one side of the display area DA.

[0033] Figure 2 It is shown Figure 1 2 is a cross-sectional view of an example of a display device DD shown in FIG.

[0034] refer to Figure 2 The display device DD includes a display panel DP, an input sensor IS, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2. In one or more embodiments of the present disclosure, the input sensor IS may not be provided.

[0035] The display panel DP according to one or more embodiments of the present disclosure may be an emission type or kind of display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0036] The input sensor IS may be arranged on the display panel DP. The input sensor IS may include a plurality of sensors that sense external input in a capacitive manner. If (for example, when) the display device DD is manufactured, the input sensor IS may be directly arranged on the display panel DP. However, the present disclosure is not necessarily limited thereto, and the input sensor IS may be provided as a panel separated from the display panel DP and then may be attached to the display panel DP through an adhesive layer.

[0037] The anti-reflection layer RPL may be disposed on the input sensor IS. If (eg, when) the display device DD is manufactured, the anti-reflection layer RPL may be directly disposed on the input sensor IS. The anti-reflection layer RPL may include a color filter and may further include a black mattress.

[0038] However, the present disclosure is not necessarily limited thereto, and the anti-reflection layer RPL may be provided as a separate panel and then attached to the input sensor IS through an adhesive layer. The anti-reflection layer RPL may include an optical film such as a polarizing film. The anti-reflection layer RPL may reduce the reflectivity of external light incident from the upper side of the display device DD toward the display panel DP. Due to the anti-reflection layer RPL, the external light may not be visible to the user.

[0039] The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensor IS, and the anti-reflection layer RPL from external scratches and impacts. The window WIN may be attached to the anti-reflection layer RPL through a second adhesive layer AL2.

[0040] The panel protection film PPF may be arranged below the display panel DP. The panel protection film PPF may protect the lower portion of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET). The panel protection film PPF may be attached to the display panel DP by a first adhesive layer AL1.

[0041] Figure 3 It is shown Figure 2 0 is a cross-sectional view of an example of a display panel DP shown in FIG.

[0042] refer to Figure 3 The display panel DP may include a base layer SUB, a circuit element layer DP-CL arranged on the base layer SUB, a display element layer DP-OLED arranged on the circuit element layer DP-CL, and a thin film encapsulation layer TFE arranged on the display element layer DP-OLED.

[0043] as Figure 1In the display device DD, the base layer SUB may include a display area DA and a non-display area NDA around the display area DA. The base layer SUB may include a flexible plastic material and / or glass, such as polyimide.

[0044] The circuit element layer DP-CL may include a driving circuit for a light emitting element and a driving circuit for an optical sensing element. The display element layer DP-OLED may include a light emitting element and an optical sensing element. The thin film encapsulation layer TFE may be arranged on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen and / or foreign matter.

[0045] Figure 4 is a block diagram of a display device DD according to one or more embodiments of the present disclosure.

[0046] refer to Figure 4 , the display device DD includes a display panel DP, a driving controller 100, and a driving circuit of the display device DD. For example, the driving circuit of the display device DD may include a data driver 200, a scan driver 300, an emission driver 350, a voltage generator 400, and a readout circuit 500. In one or more embodiments, the voltage generator 400 and the readout circuit 500 may be implemented as a single driving chip with the driving controller 100.

[0047] The display panel DP may include a plurality of pixels PX arranged in the display area DA and a plurality of optical sensors SN arranged in the display area DA. For example, each of the optical sensors SN may be arranged between two adjacent pixels PX. However, the arrangement relationship between the optical sensors SN and the pixels PX is not necessarily limited thereto.

[0048] The display panel DP may include initialization scan lines GI1 to GIn, compensation scan lines GC1 to GCn, bias scan lines GB1 to GBn, write scan lines GW1 to GWn, emission control lines EML1 to EMLn, reset scan lines GR1 to GRn, data lines DL1 to DLm, and readout lines RL1 to RLh. The initialization scan lines GI1 to GIn, compensation scan lines GC1 to GCn, bias scan lines GB1 to GBn, write scan lines GW1 to GWn, emission control lines EML1 to EMLn, and reset scan lines GR1 to GRn may extend in the second direction DR2. The data lines DL1 to DLm and the readout lines RL1 to RLh may extend in the first direction DR1.

[0049] The pixels PX may be electrically connected to initialization scan lines GI1 to GIn, compensation scan lines GC1 to GCn, write scan lines GW1 to GWn, bias scan lines GB1 to GBn, emission control lines EML1 to EMLn, and data lines DL1 to DLm. However, the number of signal lines connected to each pixel PX is not necessarily limited thereto and may vary.

[0050] The optical sensors SN may be electrically connected to write scan lines GW1 to GWn, reset scan lines GR1 to GRn, and readout lines RL1 to RLh. The number of signal lines connected to each of the optical sensors SN is not necessarily limited thereto and may vary.

[0051] The driving controller 100 may receive the image signal RGB and the control signal CTRL. The driving controller 100 may generate the image data signal DATA obtained by converting the data format of the image signal RGB to meet the interface specification with the data driver 200. The driving controller 100 may output the first control signal DCS, the second control signal SCS, the third control signal ECS, and the fourth control signal RCS.

[0052] The data driver 200 may receive a first control signal DCS and an image data signal DATA from the driving controller 100. The data driver 200 may convert the image data signal DATA into a data signal and output the data signal to a plurality of data lines DL1 to DLm, which will be described in more detail later. The data signal is an analog voltage corresponding to a gray level (e.g., gray level value or gray value) of the image data signal DATA.

[0053] The scan driver 300 may receive a second control signal SCS from the drive controller 100. The scan driver 300 may output an initialization scan signal to the initialization scan lines GI1 to GIn in response to the second control signal SCS, and output a compensation scan signal to the compensation scan lines GC1 to GCn. In addition, the scan driver 300 may output a write scan signal to the write scan lines GW1 to GWn in response to the second control signal SCS, and output a black scan signal to the bias scan lines GB1 to GBn. In addition, the scan driver 300 may output a reset scan signal to the reset scan lines GR1 to GRn in response to the second control signal SCS.

[0054] The emission driver 350 may receive a third control signal ECS from the driving controller 100. The emission driver 350 may output an emission control signal to the emission control lines EML1 to EMLn in response to the third control signal ECS. In addition, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the emission driver 350 may not be provided, and the scan driver 300 may output an emission control signal to the emission control lines EML1 to EMLn.

[0055] The readout circuit 500 may receive a fourth control signal RCS from the driving controller 100. The readout circuit 500 may receive a sensing signal from the sensing lines RL1 to RLh in response to the fourth control signal RCS. The readout circuit 500 may process the sensing signal received from the sensing lines RL1 to RLh to provide a processed sensing signal S_FS to the driving controller 100. The driving controller 100 may identify biometric information based on the processed sensing signal S_FS.

[0056] The voltage generator 400 may generate voltages required for the operation of the display panel DP. In this embodiment, the voltage generator 400 may generate a first driving voltage ELVDD, a second driving voltage ELVSS having a level lower than that of the first driving voltage ELVDD, a first initialization voltage VINT, a second initialization voltage AINT, a reset voltage VRST, and a bias voltage VBIAS.

[0057] Figure 5 Shows Figure 4 0 is an equivalent circuit of one pixel PXij among the pixels PX and an optical sensor SNij adjacent to the one pixel PXij shown in .

[0058] For example, Figure 5 1 shows a pixel PXij connected to the i-th scan line SLi, the i-th emission line ELi and the j-th data line DLj. Figure 5 An optical sensor SNij connected to the i-th reset scan line GRi and the j-th readout line RXj is shown. Here, i and j are positive integers. The i-th scan line SLi may include the i-th initialization scan line GIi, the i-th compensation scan line GCi, the i-th bias scan line GBi, and the i-th write scan line GWi.

[0059] refer to Figure 5 , the pixel PXij may include a pixel driving circuit PC (or a first driving circuit) and a light emitting element OLED electrically connected to the pixel driving circuit PC. The light emitting element OLED may be turned on or off by the control of the pixel driving circuit PC.

[0060] The pixel driving circuit PC may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing through the light emitting element OLED. The light emitting element OLED may generate light with a specific brightness according to the amount of current provided.

[0061] The i-th write scan line GWi may receive the i-th write scan signal GWSi, and the i-th compensation scan line GCi may receive the i-th compensation scan signal GCSi. The i-th initialization scan line GIi may receive the i-th initialization scan signal GISi, and the i-th bias scan line GBi may receive the i-th bias scan signal GBSi. The i-th reset scan line GRi may receive the i-th reset scan signal GRSi. The i-th emission line ELi may receive the i-th emission signal ESi.

[0062] The first initialization line VIL1 may receive a first initialization voltage VINT, and the second initialization line VIL2 may receive a second initialization voltage AINT. The bias line VBL may receive a bias voltage VBIAS. The first power line PL1 may receive a first driving voltage ELVDD, and the second power line PL2 may receive a second driving voltage ELVSS. The light emitting element OLED may be connected to the second power line PL2. The reset line VRL may receive a reset voltage VRST.

[0063] Each of the transistors T1 to T8 may include a source (or source terminal), a drain (or drain terminal), and a gate (or gate terminal). Figure 5 In the present invention, for convenience, one of the source and the drain is defined as a first electrode, and the other is defined as a second electrode. In addition, the gate is defined as a gate electrode or a control electrode.

[0064] The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first transistor T1, the second transistor T2, and the fifth to eighth transistors T5 to T8 may be PMOS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0065] The first transistor T1 may be defined as a driving transistor, and the second transistor T2 may be defined as a switching transistor. The third transistor T3 may be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 may be defined as emission control transistors. The eighth transistor T8 may be defined as a bias transistor.

[0066] The light emitting element OLED may include an organic light emitting diode. The light emitting element OLED may include a first electrode, a second electrode, and an emission layer arranged between the first electrode and the second electrode. In this embodiment, for ease of explanation, the first electrode is described as an anode AE, and the second electrode is described as a cathode CE. The anode AE ​​may be electrically connected to the first power line PL1 through the sixth transistor T6, the first transistor T1, and the fifth transistor T5. The cathode CE may be electrically connected to the second power line PL2.

[0067] The first transistor T1 may be disposed between and connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be connected to the first power line PL1 through the fifth transistor T5, and to the anode AE ​​through the sixth transistor T6.

[0068] The first transistor T1 may include a first electrode connected to the first power line PL1 through a fifth transistor T5 , a second electrode connected to the anode AE ​​through a sixth transistor T6 , and a gate electrode connected to the first node N1 .

[0069] The first electrode of the first transistor T1 may be connected to the fifth transistor T5, and the second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the light emitting element OLED according to the voltage of the first node N1 applied to the gate electrode of the first transistor T1.

[0070] The second transistor T2 may be disposed between the first transistor T1 and the jth data line DLj and then connected to the first transistor T1 and the jth data line DLj. The second transistor T2 may include a first electrode connected to the jth data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the ith write scan line GWi.

[0071] The second transistor T2 may be turned on by the i-th write scan signal GWSi applied through the i-th write scan line GWi to electrically connect the j-th data line DLj to the first electrode of the first transistor T1. The second transistor T2 may perform a switching operation to provide the data voltage VD applied through the j-th data line DLj to the first electrode of the first transistor T1.

[0072] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a gate electrode connected to the i-th compensation scan line GCi.

[0073] The third transistor T3 may be turned on by the i-th compensation scan signal GCSi applied through the i-th compensation scan line GCi to electrically connect the second electrode of the first transistor T1 to the gate electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 may be connected in the form of a diode (e.g., the first transistor T1 may be diode-connected).

[0074] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a gate electrode connected to the i-th initialization scan line GIi. The fourth transistor T4 may be turned on by the i-th initialization scan signal GISi applied through the i-th initialization scan line GIi to provide the first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1.

[0075] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th emission line ELi. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a gate electrode connected to the i-th emission line ELi.

[0076] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th emission signal ESi applied via the i-th emission line ELi. The first driving voltage ELVDD can be provided to the light emitting element OLED through the turned-on fifth transistor T5, the first transistor T1 and the sixth transistor T6, so that the driving current flows to the light emitting element OLED. Therefore, the light emitting element OLED can emit light.

[0077] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a gate electrode connected to the i-th bias scan line GBi. The seventh transistor T7 may be turned on by the i-th bias scan signal GBSi applied through the i-th bias scan line GBi to provide the second initialization voltage AINT received through the second initialization line VIL2 to the anode AE ​​of the light emitting element OLED.

[0078] In one or more embodiments, the seventh transistor T7 may not be provided. In one or more embodiments, the second initialization voltage AINT may have a different level from the first initialization voltage VINT, but the present disclosure is not necessarily limited thereto and may have the same level as the first initialization voltage VINT.

[0079] The seventh transistor T7 can improve the black display capability of the pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitor of the light emitting element OLED can be discharged. Therefore, if (for example, when) black brightness is achieved, the light emitting element OLED may not emit light due to the leakage current of the first transistor T1, and therefore, the black display capability can be improved.

[0080] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined according to the voltage stored in the capacitor CST.

[0081] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the i-th bias scan line GBi. In one or more embodiments, the eighth transistor T8 may not be provided.

[0082] The eighth transistor T8 may be turned on by the i-th bias scan signal GBSi and may provide the bias voltage VBIAS to the first electrode of the first transistor T1. When the bias voltage VBIAS is applied to the first transistor T1, movement of the hysteresis curve of the first transistor T1 may be suppressed or reduced.

[0083] The optical sensor SNij may include a sensor driving circuit SNC (or a second driving circuit) and an optical sensing element LRE electrically connected to the sensor driving circuit SNC. The sensor driving circuit SNC may detect the operation of the optical sensing element LRE.

[0084] The sensor driving circuit SNC may include a first sensing transistor T1 ′, a second sensing transistor T2 ′, and a third sensing transistor T3 ′. The first sensing transistor T1 ′ and the third sensing transistor T3 ′ may be PMOS transistors, and the second sensing transistor T2 ′ may be an NMOS transistor.

[0085] The optical sensing element LRE may be defined as a photodiode. The optical sensing element LRE may convert light energy incident from the outside into electrical energy. The optical sensing element LRE may include a first electrode, a second electrode, and a photoelectric conversion layer arranged between the first electrode and the second electrode. In this embodiment, for ease of explanation, the first electrode is described as an anode AE', and the second electrode is described as a cathode CE'. The anode AE' may be connected to a second node N2, and the cathode CE' may be connected to a second power line PL2. In order to distinguish the anode AE ​​and cathode CE of the light emitting element OLED from the anode AE' and cathode CE' of the optical sensing element LRE, the anode AE ​​and the cathode CE may be defined as a first electrode and a second electrode, respectively, and the anode AE' and the cathode CE' of the optical sensing element LRE may be defined as a first-first electrode and a second-first electrode, respectively.

[0086] The first sensing transistor T1' may be connected to the optical sensing element LRE, the second sensing transistor T2', and the third sensing transistor T3'. The first sensing transistor T1' may include a first electrode receiving a second initialization voltage AINT, a gate electrode connected to the second node N2, and a second electrode connected to the third sensing transistor T3'. The first electrode of the first sensing transistor T1' may be connected to the second initialization line VIL2 to receive the second initialization voltage AINT. The second sensing transistor T2' may include a first electrode connected to the second node N2, a gate electrode connected to the i-th reset scan line GRi, and a second electrode connected to the reset line VRL. The third sensing transistor T3' may include a first electrode connected to the second electrode of the first sensing transistor T1', a gate electrode connected to the i-th write scan line GWi, and a second electrode connected to the j-th readout line RXj. The third sensing transistor T3' may be turned on by the i-th write scan signal GWSi received through the i-th write scan line GWi.

[0087] The second sensing transistor T2' may be turned on by the i-th reset scan signal GRSi received through the i-th reset scan line GRi. The turned-on second sensing transistor T2' may receive the reset voltage VRST to provide the reset voltage VRST to the second node N2. The second node N2 may be reset by the reset voltage VRST. In one or more embodiments, Figure 4 All optical sensors SN shown in can receive the same reset scanning signal. The second sensing transistors T2 ′ of all optical sensors SN can be turned on at the same timing, and can also be turned off at the same timing.

[0088] The i-th write scan signal GWSi may be applied to the gate electrode of the third sensing transistor T3' to turn on the third sensing transistor T3'. The first sensing transistor T1' may be connected to the j-th readout line RXj through the turned-on third sensing transistor T3'.

[0089] The optical sensing element LRE may receive light to convert the light into an electrical signal. Here, the voltage of the second node N2 may change. When the first sensing transistor T1' is turned on, the second initialization voltage AINT supplied to the first sensing transistor T1' may be controlled or selected according to the change in the voltage of the second node N2, and then supplied to the j-th readout line RXj through the third sensing transistor T3'. Therefore, the signal sensed by the optical sensing element LRE may be output as a sensing signal RS through the j-th readout line RXj.

[0090] Figure 6 It is shown Figure 5 0 is a cross-sectional view of an example of a light emitting element OLED, a first transistor T1, a fourth transistor T4 and a sixth transistor T6 of a pixel PXij shown in FIG.

[0091] Figure 6 Shows Figure 5 The first transistor T1, the fourth transistor T4 and the sixth transistor T6 of the pixel driving circuit PC. Figure 6 , the shielding electrode BML may be arranged on the base layer SUB. The shielding electrode BML may overlap with the first transistor T1 in the thickness direction (e.g., the third direction DR3) of the base layer SUB. The shielding electrode BML may include a metal, and a constant voltage may be applied to the shielding electrode BML. When the constant voltage is applied to the shielding electrode BML, the value of the threshold voltage of the first transistor T1 arranged on the shielding electrode BML may remain unchanged. In addition, the shielding electrode BML may block light incident on the first transistor T1 from the lower side of the shielding electrode BML. For example, the shielding electrode BML may include a reflective metal. In one or more embodiments, the shielding electrode BML may not be provided.

[0092] The buffer layer BFL may be disposed on the base layer SUB, and the buffer layer BFL may include an inorganic layer. The buffer layer BFL may cover the shielding electrode BML. The metal layer disposed on the base layer SUB together with the shielding electrode BML may be defined as a shielding layer. In one or more embodiments, the buffer layer BFL may not be provided.

[0093] The semiconductor layer SCP1 (or semiconductor pattern region, hereinafter, referred to as the first semiconductor layer) of the first transistor T1 and the semiconductor layer SCP6 (or semiconductor pattern region, hereinafter, referred to as the sixth semiconductor layer) of the sixth transistor T6 may be disposed on the buffer layer BFL. Hereinafter, each of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include polycrystalline silicon. However, the present disclosure is not necessarily limited thereto, and each of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include amorphous silicon.

[0094] The first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be formed by substantially the same process, and a partial region of each of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be doped with an N type or kind of dopant or a P type or kind of dopant. Each of the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may include a high-doped region and a low-doped region. The conductivity of the high-doped region is greater than the conductivity of the low-doped region. The high-doped region may substantially correspond to the source and drain of the first transistor T1 and the sixth transistor T6. The low-doped region may substantially correspond to the active portion (or channel) of the first transistor T1 and the sixth transistor T6.

[0095] The high doping region of the first semiconductor layer SCP1 may include a first source region S1 and a first drain region D1. The low doping region of the first semiconductor layer SCP1 may be defined as a first channel region A1 and may be arranged between the first source region S1 and the first drain region D1. Similar to the first semiconductor layer SCP1, the sixth semiconductor layer SCP6 may include a sixth source region S6, a sixth channel region A6, and a sixth drain region D6.

[0096] exist Figure 6 In the cross section of FIG. 1 , the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be separated from each other (e.g., spaced apart or separated), but on the same plane, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be integral with each other. For example, the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be different parts or different regions of one semiconductor pattern.

[0097] The first insulating layer INS1 covering the first semiconductor layer SCP1 and the sixth semiconductor layer SCP6 may be arranged on the buffer layer BFL. The gate electrodes of the first transistor T1 and the sixth transistor T6 may be arranged on the first insulating layer INS1. The gate electrodes of the first transistor T1 and the sixth transistor T6 may be formed by substantially the same process. Hereinafter, the gate electrode of the first transistor T1 may be defined as the first gate electrode G1, and the gate electrode of the sixth transistor T6 may be defined as the sixth gate electrode G6. The metal layer arranged on the first insulating layer INS1 may be defined as a first gate layer together with the first gate electrode G1 and the sixth gate electrode G6. In addition to the first gate electrode G1 and the sixth gate electrode G6, the first gate layer may also include a plurality of patterns. The first gate electrode G1 and the sixth gate electrode G6 may overlap with the first channel region A1 and the sixth channel region A6, respectively, in the third direction DR3.

[0098] The second insulating layer INS2 may be arranged on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. The dummy electrode DME may be arranged on the second insulating layer INS2. The dummy electrode DME may be arranged on the first gate electrode G1 to overlap with the first gate electrode G1 if (for example, when) viewed in a plan view (for example, the dummy electrode DME may overlap with the first gate electrode G1 in the third direction DR3). The dummy electrode DME may form the above-mentioned capacitor CST together with the first gate electrode G1. For example, the first gate electrode G1 may correspond to one electrode of the capacitor CST, and the dummy electrode DME may correspond to another electrode of the capacitor CST. The metal layer arranged on the second insulating layer INS2 may be defined as a second gate layer together with the dummy electrode DME. In addition to the dummy electrode DME, the second gate layer may also include a plurality of patterns.

[0099] The third insulating layer INS3 may be arranged on the second insulating layer INS2 to cover the dummy electrode DME. The semiconductor layer SCP4 (or semiconductor pattern region, hereinafter, referred to as the fourth semiconductor layer) of the fourth transistor T4 may be arranged on the third insulating layer INS3. The fourth semiconductor layer SCP4 may include an oxide semiconductor including a metal oxide. The oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor.

[0100] The fourth semiconductor layer SCP4 may include a plurality of regions divided according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduction region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduction region). The reduction region may substantially correspond to the source and drain of the fourth transistor T4. The non-reduction region may substantially correspond to the active portion (or channel) of the fourth transistor T4.

[0101] The reduction region of the fourth semiconductor layer SCP4 may include a fourth source region S4 and a fourth drain region D4. A fourth channel region A4 may be disposed between the fourth source region S4 and the fourth drain region D4.

[0102] The fourth insulating layer INS4 may be arranged on the third insulating layer INS3 to cover the fourth semiconductor layer SCP4. The fourth gate electrode G4 of the fourth transistor T4 may be arranged on the fourth insulating layer INS4. The metal layer formed on the fourth insulating layer INS4 together with the fourth gate electrode G4 may be defined as a third gate layer. In addition to the fourth gate electrode G4, the third gate layer may further include a plurality of patterns. The fourth gate electrode G4 may overlap with the fourth channel region A4 in the third direction DR3.

[0103] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4 . The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include an inorganic layer.

[0104] The connection electrode CNE may be disposed between the sixth transistor T6 and the light emitting element OLED. The connection electrode CNE may electrically connect the sixth transistor T6 to the light emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1, a second connection electrode CNE2 disposed on the first connection electrode CNE1, and a third connection electrode CNE3 disposed on the second connection electrode CNE2.

[0105] The first connection electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. The metal layer disposed on the fifth insulating layer INS5 together with the first connection electrode CNE1 may be defined as a first source / drain layer. In addition to the first connection electrode CNE1, the first source / drain layer may further include a plurality of patterns.

[0106] The sixth insulating layer INS6 may be arranged on the fifth insulating layer INS5 to cover the first connection electrode CNE1. The second connection electrode CNE2 may be arranged on the sixth insulating layer INS6. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6. The metal layer arranged on the sixth insulating layer INS6 may be defined as a second source / drain layer together with the second connection electrode CNE2. The second source / drain layer may further include a plurality of patterns in addition to the second connection electrode CNE2.

[0107] The seventh insulating layer INS7 may be arranged on the sixth insulating layer INS6 to cover the second connection electrode CNE2. The third connection electrode CNE3 may be arranged on the seventh insulating layer INS7. The third connection electrode CNE3 may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7. The metal layer arranged on the seventh insulating layer INS7 may be defined as a third source / drain layer together with the third connection electrode CNE3. In addition to the third connection electrode CNE3, the third source / drain layer may further include a plurality of patterns.

[0108] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 to cover the third connection electrode CNE3. The light emitting element OLED may be disposed on the eighth insulating layer INS8. Each of the sixth to eighth insulating layers INS6 to INS8 may include an inorganic layer or an organic layer. In this embodiment, each of the sixth to eighth insulating layers INS6 to INS8 may include an organic layer.

[0109] The light emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and an emission layer EML. The first electrode AE ​​may be Figure 5 The anode AE ​​shown in FIG. 1 and the second electrode CE may be Figure 5 The cathode CE shown in FIG. The second electrode CE may be arranged on the first electrode AE, the hole control layer HCL and the electron control layer ECL may be arranged between the first electrode AE ​​and the second electrode CE, and the emission layer EML may be arranged between the hole control layer HCL and the electron control layer ECL. The first electrode AE ​​may be arranged on the eighth insulating layer INS8. The first electrode AE ​​may be electrically connected to the third connection electrode CNE3 through a fourth contact hole CH4 defined in the eighth insulating layer INS8.

[0110] A pixel defining layer PDL exposing an appropriate portion (e.g., a preset or predetermined portion) of the first electrode AE ​​may be disposed on the first electrode AE ​​and the eighth insulating layer INS8. A first opening PDL-OP1 exposing an appropriate portion (e.g., a preset or predetermined portion) of the first electrode AE ​​may be defined in the pixel defining layer PDL. The first opening PDL-OP1 may correspond to the emission area LEA. The display area DA may include an emission area LEA corresponding to the first opening PDL-OP1 and a non-emission area NLEA adjacent to the emission area LEA.

[0111] The hole control layer HCL may be disposed on the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may be commonly disposed in the emission area LEA and the non-emission area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0112] The emission layer EML may be disposed on the hole control layer HCL. The emission layer EML may be disposed in a region corresponding to the first opening PDL-OP1. The emission layer EML may include an organic material and / or an inorganic material. The emission layer EML may emit one of red light, green light, and blue light.

[0113] The electron control layer ECL may be disposed on the hole control layer HCL to cover the emission layer EML. The electron control layer ECL may be commonly disposed in the emission area LEA and the non-emission area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0114] The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be commonly disposed on Figure 4 In the pixel PX shown in . For example, the second electrode CE may be commonly disposed on the emission layer EML of the pixel PX.

[0115] A layer arranged from the buffer layer BFL to the eighth insulating layer INS8 may be defined as a circuit element layer DP-CL. A layer in which a light emitting element OLED is arranged may be defined as a display element layer DP-OLED.

[0116] The thin film encapsulation layer TFE may be arranged on the light emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially. Each of the inorganic layers may include an inorganic material and protect the pixel PX from moisture / oxygen. The organic layer may include an organic material to protect the pixel PX from foreign matter such as dust particles.

[0117] Figure 7 It is shown Figure 5 1 , which is a cross-sectional view of an example of an optical sensing element LRE, a first sensing transistor T1 ′ and a second sensing transistor T2 ′ of an optical sensor SNij shown in FIG. Figure 6 Given with Figure 6 The configuration described in the detailed description is the same as the configuration described in.

[0118] The semiconductor layer SCP1' of the first sensing transistor T1' (hereinafter, referred to as the first sensing semiconductor layer) can be connected to Figure 6 The semiconductor layer SCP2' of the second sensing transistor T2' (hereinafter, referred to as the second sensing semiconductor layer) can be formed by the same process as the first semiconductor layer SCP1 of the first sensing transistor T2'. Figure 6The fourth semiconductor layer SCP4 is formed by substantially the same process. The first sensing semiconductor layer SCP1' may include a first source region S1', a first drain region D1' and a first channel region A1'. The second sensing semiconductor layer SCP2' may include a second source region S2', a second drain region D2' and a second channel region A2'.

[0119] The stacked structure of the first sensing transistor T1' can be Figure 6 The stacked structure of the first transistor T1 shown in FIG. 1 is substantially the same as that of the second sensing transistor T2′. Figure 6 The stacked structure of the fourth transistor T4 shown in FIG. 1 is substantially the same. In one or more embodiments, the stacked structure of the third sensing transistor T3 ′ may be substantially the same as the stacked structure of the first sensing transistor T1 ′.

[0120] The connection electrode CNE′ may include a first connection electrode CNE1′ (or a first sensing connection electrode), a second connection electrode CNE2′ (or a second sensing connection electrode), and a third connection electrode CNE3′ (or a third sensing connection electrode). The first connection electrode CNE1′ may be disposed at a position corresponding to the first connection electrode CNE1′. Figure 6 The first connection electrode CNE1 is disposed on the same layer as the first connection electrode CNE1 shown in FIG. 1 (e.g., can be arranged at the same layer), and can be connected to the first gate electrode G1' of the first sensing transistor T1' through the first contact hole CH1'. Hereinafter, the first gate electrode G1' is defined as a first sensing gate electrode G1' to be distinguished from the above-mentioned first gate electrode G1.

[0121] The second connection electrode CNE2′ may be arranged at Figure 6 The third connection electrode CNE3' may be disposed on the same layer as the second connection electrode CNE2 shown in FIG. 1 and may be connected to the first connection electrode CNE1' through a second contact hole CH2' defined in the sixth insulating layer INS6. Figure 6 The first electrode AE' may be connected to the third link electrode CNE3' through a third contact hole CH3'. The first electrode AE' may be connected to the third link electrode CNE3' through a fourth contact hole CH4 defined in the eighth insulating layer INS8.

[0122] refer to Figure 7 , the display area DA may include a light receiving area LRA corresponding to the optical sensor SNij and a non-emission area NLEA adjacent to the light receiving area LRA. The non-emission area NLEA may be Figure 6 The non-emitting area NLEA shown in .

[0123] The optical sensing element LRE may include a first electrode AE', a second electrode CE', a hole control layer HCL', an electron control layer ECL', and a photoelectric conversion layer OPD. The first electrode AE' may be Figure 5 The anode AE' shown in FIG. 1 and the second electrode CE' may be Figure 5 The cathode CE' shown in FIG. The second opening PDL-OP2 may be defined in the pixel defining layer PDL to expose an appropriate portion (eg, a preset or predetermined portion) of the first electrode AE'. The light receiving area LRA may correspond to the second opening PDL-OP2.

[0124] The first electrode AE' can be connected to Figure 6 The second electrode CE', the hole control layer HCL' and the electron control layer ECL' may have the same Figure 6 The second electrode CE, the hole control layer HCL and the electron control layer ECL shown in FIG. 1 are in an integrated shape. Figure 7 The second electrode CE' and Figure 6 The second electrode CE in the embodiment may be a different region of the common electrode. The common electrode may be deposited through an open mask to have an integral shape. Figure 7 The hole control layer HCL' and Figure 6 The hole control layer HCL in the embodiment may also be different regions of a common hole control layer, and Figure 7 The electronic control layer ECL' and Figure 6 The electron control layer ECL in can also be different regions of a common electron control layer.

[0125] Figure 8 It is shown that the arrangement Figure 4 0 is a view of a planar arrangement of the light emitting element OLED and the optical sensing element LRE in a partial area of ​​the display area DA shown in FIG.

[0126] Figure 8 A unit region RPU arranged in the first area of ​​the display area DA is shown. At least one pixel PX1, PX2, PX3, and PX4 and an optical sensor SN are arranged to correspond to each of the unit regions RPU. A combination of pixels PX1, PX2, PX3, and PX4 corresponding to the unit regions RPU, respectively, may be defined as a unit pixel PXU.

[0127] The unit area RPU may be arranged throughout the display area DA, but is not necessarily limited thereto. A unit area of ​​a different type (kind) from the aforementioned unit area RPU may be arranged in the second area of ​​the display area DA. For example, the optical sensor SN may not be arranged in the unit area arranged in the second area of ​​the display area DA.

[0128] In this embodiment, the unit pixel PXU includes a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. However, the number of pixels of the unit pixel PXU may vary. The first pixel PX1 may include a first light emitting element OLED-R and a first driving circuit PC1 electrically connected to the first light emitting element OLED-R, the second pixel PX2 may include a second-first light emitting element OLED-G1 and a first driving circuit PC2 electrically connected to the second-first light emitting element OLED-G1, the third pixel PX3 may include a third light emitting element OLED-B and a first driving circuit PC3 electrically connected to the third light emitting element OLED-B, and the fourth pixel PX4 may include a second-second light emitting element OLED-G2 and a first driving circuit PC4 electrically connected to the second-second light emitting element OLED-G2. For example, the four first driving circuits PC1, PC2, PC3, and PC4 may be defined as a first-first driving circuit PC1, a first-second driving circuit PC2, a first-third driving circuit PC3, and a first-fourth driving circuit PC4.

[0129] The optical sensor SN may include a first optical sensor SN1 and a second optical sensor SN2. However, the number of optical sensors SN corresponding to the unit pixel PXU may vary. The first optical sensor SN1 may include a first optical sensing element LRE1 and a second driving circuit SNC1 electrically connected to the first optical sensing element LRE1, and the second optical sensor SN2 may include a second optical sensing element LRE2 and a second driving circuit SNC2 electrically connected to the second optical sensing element LRE2.

[0130] The first light emitting element OLED-R, the second-first light emitting element OLED-G1, the third light emitting element OLED-B, and the second-second light emitting element OLED-G2 of the unit pixel PXU and the first optical sensing element LRE1 and the second optical sensing element LRE2 may be arranged to overlap each other in each of the unit regions RPU. Hereinafter, the light emitting elements OLED-R, OLED-G1, OLED-B, and OLED-G2 corresponding to the unit pixel PXU may be defined as the unit light emitting element UO. The arrangement of the unit light emitting element UO and the first optical sensing element LRE1 and the second optical sensing element LRE2 of the unit region RPU may be the same.

[0131] The first light emitting element OLED-R may generate a first color light (e.g., red light), the second-first light emitting element OLED-G1 and the second-second light emitting element OLED-G2 may generate a second color light (e.g., green light), and the third light emitting element OLED-B may generate a third color light (e.g., blue light). The emission area of ​​the third light emitting element OLED-B may be the largest, and the emission areas of the second-first light emitting element OLED-G1 and the second-second light emitting element OLED-G2 may be the smallest.

[0132] In this embodiment, the first light emitting element OLED-R and the third light emitting element OLED-B may be arranged on the same row, and the first light emitting element OLED-R and the third light emitting element OLED-B may be spaced apart from each other (e.g., spaced apart or separated) in the second direction DR2. The first optical sensing element LRE1 may be arranged between the first light emitting element OLED-R and the third light emitting element OLED-B in the second direction DR2. The third light emitting element OLED-B may be arranged between the first optical sensing element LRE1 and the second optical sensing element LRE2 in the second direction DR2. The second-first light emitting element OLED-G1 and the second-second light emitting element OLED-G2 may be arranged on the same line, but the second-first light emitting element OLED-G1 and the second-second light emitting element OLED-G2 may be arranged on a different line from the first light emitting element OLED-R and the third light emitting element OLED-B. The second-first light emitting element OLED-G1 may be arranged at one side of the first optical sensing element LRE1 in the first direction DR1, and the second-second light emitting element OLED-G2 may be arranged at one side of the second optical sensing element LRE2 in the first direction DR1. In this embodiment, the second-first light emitting element OLED-G1 may be disposed above the first optical sensing element LRE1.

[0133] In one or more embodiments, one of the first optical sensing element LRE1 and the second optical sensing element LRE2 may not be provided. In one or more embodiments, the optical sensing element may be further arranged above the first light emitting element OLED-R in the first direction DR1, or the optical sensing element may be arranged above the third light emitting element OLED-B in the first direction DR1. For example, four optical sensors SN may be arranged to correspond to the unit region RPU.

[0134] In one or more embodiments, the unit area RPU may be divided based on the arrangement of the first drive circuits PC1, PC2, PC3 and PC4 and the second drive circuits SNC1 and SNC2. Four first drive circuits PC1, PC2, PC3 and PC4 and two second drive circuits SNC1 and SNC2 may be arranged in each of the unit areas RPU. As described above, the four first drive circuits PC1, PC2, PC3 and PC4 may be defined as a first-first drive circuit PC1, a first-second drive circuit PC2, a first-third drive circuit PC3 and a first-fourth drive circuit PC4, and the two second drive circuits SNC1 and SNC2 may be defined as a second-first drive circuit SNC1 and a second-second drive circuit SNC2.

[0135] Each of the first light emitting element OLED-R, the second-first light emitting element OLED-G1, the third light emitting element OLED-B, and the second-second light emitting element OLED-G2 may overlap or not overlap with a corresponding driving circuit of the first-first driving circuit PC1, the first-second driving circuit PC2, the first-third driving circuit PC3, and the first-fourth driving circuit PC4 on a plane. For example, if (for example, when) Figure 6 When the third connection electrode CNE3 has an extended shape on a plane, like the second-first light emitting element OLED-G1, the light emitting element OLED connected to the third connection electrode CNE3 may not overlap with the corresponding first-second driving circuit PC2.

[0136] Although all of the first-first drive circuit PC1, the first-second drive circuit PC2, the first-third drive circuit PC3, the first-fourth drive circuit PC4, the first light-emitting element OLED-R, the second-first light-emitting element OLED-G1, the third light-emitting element OLED-B, and the second-second light-emitting element OLED-G2 are described as being arranged within the unit area RPU, the present disclosure is not necessarily limited to this. In one or more embodiments, one of the four first drive circuits PC1, PC2, PC3, and PC4 arranged in the first unit area of ​​the unit area RPU may be connected to one of the first light-emitting element OLED-R, the second-first light-emitting element OLED-G1, the third light-emitting element OLED-B, and the second-second light-emitting element OLED-G2 arranged in the second unit area adjacent to the first unit area. For example, if (for example, when) Figure 6 When the third connection electrode CNE3 in the embodiment further extends from the first unit region to the second unit region on a plane, the driving circuit arranged in the first unit region and the light emitting element arranged in the second unit region may constitute one pixel.

[0137] In addition, it has been described that all the second-first drive circuit SNC1 and the second-second drive circuit SNC2 and the first optical sensing element LRE1 and the second optical sensing element LRE2 are arranged in the unit region RPU, but the present disclosure is not necessarily limited thereto. For example, if (for example, when) Figure 7 If the third connection electrode CNE3 ′ further extends from the first unit region to the second unit region on a plane, the driving circuit arranged in the first unit region and the optical sensing element arranged in the second unit region may constitute an optical sensor.

[0138] Fig. 9 is a perspective view of a display device DD according to one or more embodiments of the present disclosure. Fig.10 is a plan view showing a partial area of ​​a display device DD according to one or more embodiments of the present disclosure. Fig.11 is a plan view showing a partial area of ​​a display device DD according to one or more embodiments of the present disclosure.

[0139] refer to Fig. 9 , the display panel DP may include a display area DA and a non-display area NDA around (e.g., surrounding) the display area DA. The display area DA may include a first area DA1 and a second area DA2. In this embodiment, the second area DA2 arranged at both sides (e.g., opposite sides) of the first area DA1 in the second direction DR2 is shown, but the present disclosure is not necessarily limited thereto. In one or more embodiments, the second area DA2 may be arranged only at one side of the first area DA1.

[0140] The first area DA1 may be an area in which the first data line DL-1 is arranged as will be described in more detail later, and the second area DA2 may be an area in which the first readout line RX-1 is arranged as will be described in more detail later. Fig.10 As shown in , a dummy readout line RX-D may be further arranged in the second area DA2, and a second readout line RX-2 different from the first readout line RX-1 may be further arranged in the first area DA1. Fig.11 As shown in FIG. 1 , a dummy data line DL-D may be further arranged in the first area DA1 , and a second data line DL- 2 different from the first data line DL- 1 may be further arranged in the second area DA2 .

[0141] refer to Fig. 9, the non-display area NDA may include at least a sealing area ENA, a chip area CA, and a pad area PDA. The sealing area ENA, the chip area CA, and the pad area PDA may be sequentially arranged from the display area DA in the first direction DR1. The sealing area ENA may be an area around the display area DA (e.g., surrounding the display area DA), but this is not necessarily limited thereto. The sealing area ENA will be described in more detail later.

[0142] The pad area PDA may be an area on which the printed circuit board FPC is coupled, and may be arranged farther from the display area DA than the chip area CA in the first direction DR1. The chip area CA may be an area on which the driving chip DRV is mounted.

[0143] The display panel DP may be divided into a first area NBA1, a second area NBA2, and a bending area BA in a first direction DR1. The second area NBA2 and the bending area BA may be partial areas of the non-display area NDA. The bending area BA may be disposed between the first area NBA1 and the second area NBA2. When the display panel DP is bent in the bending area BA, the base layer SUB (see FIG. 1 ) of the first area NBA1 may be formed. Figure 6 ) and the base layer SUB of the second area NBA2 (see Figure 6 ) may be arranged to face adjacently to each other. The bending area BA may be arranged between the sealing area ENA and the pad area PDA in the first direction DR1.

[0144] The first data line DL-1 may extend from the chip area CA to the first area DA1 in the first direction DR1 to electrically connect the pixel PX to the driving chip DRV. The first data line DL-1 connected to the pixel PX refers to the first data line DL-1 connected to the first area DA1. Figure 8 The first driving circuits PC1, PC2, PC3, and PC4 are shown in FIG. One end of the first data line DL-1 may be disposed in the chip area CA and may be electrically connected to a bump of the driving chip DRV.

[0145] The first readout line RX-1 may extend from the pad area PDA to the second area DA2 in the first direction DR1 to electrically connect the optical sensor SN to the printed circuit board FPC. The first readout line RX-1 connected to the pixel PX means that the first readout line RX-1 is connected to the pixel PX. Figure 8 The second driving circuits SNC1 and SNC2 shown in FIG. The printed circuit board FPC may include a pad area F-PDA coupled to the pad area PDA and a plurality of signal lines F-SL transmitting signals. One of the signal lines F-SL may be electrically connected to one first readout line RX-1.

[0146] The first readout line RX-1 may not overlap with the first data line DL-1 in the non-display area NDA. This is done to suppress coupling between the first readout line RX-1 and the first data line DL-1. In addition, this is done to prevent the data signal periodically applied to the first data line DL-1 from acting as noise for the sensing signal read from the first readout line RX-1.

[0147] The power line PL may extend from the pad area PDA along the first direction DR1 within the non-display area NDA. The power line PL may extend to an area adjacent to the display area DA. The power line PL may be connected to the power line PSL adjacent to the display area DA. A power line PSL having a closed line shape is shown as an example, but the present disclosure is not necessarily limited thereto. Figure 7 The second electrode CE' and Figure 6 The second electrode CE in the embodiment may be a different region of the common electrode and Figure 4 Common electrodes of the plurality of pixels PX and the plurality of optical sensors SN shown in FIG. 4 may be connected to the power line PSL. In one or more embodiments, an additional power line extending from the power line PSL may be further arranged in the display area DA.

[0148] The power line PL and the first readout line RX-1 may overlap each other within the non-display area NDA to increase the surface area of ​​the second area DA2. In the area where the power line PL and the first readout line RX-1 overlap each other, the power line PL and the first readout line RX-1 may be arranged on different layers. Even if the power line PL and the first readout line RX-1 overlap each other, the bias voltage applied to the power line PL may act as noise to the sensing signal read from the first readout line RX-1. If the power line PL and the first readout line RX-1 do not overlap each other, the area in which the first readout line RX-1 is arranged may necessarily be limited, and therefore, it is difficult to ensure the surface area of ​​the second area DA2. This will be described in more detail later.

[0149] In addition, if the power line PL and the first readout line RX-1 are arranged not to overlap each other, there is a limitation in reducing the surface area of ​​the non-display area NDA because the area in which the plurality of first data lines DL-1, the plurality of power lines PL, and the plurality of first readout lines RX-1 are arranged must be protected. This limitation can be solved by allowing the power line PL and the first readout line RX-1 to overlap each other.

[0150] refer to Fig. 9, in the bending area BA, the first data line DL-1, the power line PL, and the first readout line RX-1 may not overlap with each other. In some areas of the non-display area NDA arranged between the bending area BA and the display area DA, the first data line DL-1 and the first readout line RX-1 may still not overlap with each other. In some areas of the non-display area NDA arranged between the bending area BA and the display area DA, the first readout line RX-1 may overlap with the power line PL. For example, the first readout line RX-1 and the power line PL may cross each other in the sealing area ENA.

[0151] The first readout line RX-1 arranged in a narrow area in the bending area BA can be expanded after the bending area BA. This is because the interval between the first readout lines RX-1 in the second area DA2 is larger than the interval between the first readout lines RX-1 in the bending area BA. Therefore, if the first readout line RX-1 does not overlap with the power line PL in some areas of the non-display area NDA arranged between the bending area BA and the display area DA, the surface area of ​​the second area DA2 can be narrowed.

[0152] The first data line DL-1 arranged in a narrow area in the bending area BA may be expanded behind the bending area BA. The first data line DL-1 may not be interfered by other signal lines arranged in some areas between the bending area BA and the display area DA from the non-display area NDA.

[0153] Signal lines SL extending from the pad area PDA to the chip area CA to electrically connect the printed circuit board FPC to the driving chip DRV may be further disposed in the non-display area NDA of the display panel DP. The signal lines SL may connect the reference Figure 4 The described first control signal DCS and the image data signal DATA are transmitted to the driving chip DRV.

[0154] refer to Fig.10 , the surface area of ​​the light sensing region can be increased by bypass line design. Fig.10 As shown in the figure, the electrical connection Fig. 9 The optical sensor SN of the printed circuit board FPC may be arranged in the first area DA1 through a bypass line design. When the optical sensor SN arranged in the second area DA2 is defined as a first optical sensor, the optical sensor SN arranged in the first area DA1 may be defined as a second optical sensor.

[0155] A dummy readout line RX-D extending from the pad area PDA in the first direction DR1 may be arranged in the second area DA2. A second readout line RX-2 extending in the first direction DR1 may be arranged in the first area DA1. Unlike the first readout line RX-1, the second readout line RX-2 may not be a signal line extending from the pad area PDA, and the second readout line RX-2 may have a length smaller than that of the first readout line RX-1 and may not overlap with the first readout line RX-1. Fig. 9 The second sensing line RX-2 and the dummy sensing line RX-D may be connected to each other through a connection line CNL extending in the second direction DR2.

[0156] Figure 8 The unit pixel PXU shown in FIG. 1 may be arranged in each of the first area DA1 and the second area DA2. The first optical sensor SN1 and the second optical sensor SN2 of the first area DA1 (eg, see Figure 8 ) may be connected to the second readout line RX-2, and each of the first optical sensor SN1 and the second optical sensor SN2 of the second area DA2 may be connected to the first readout line RX-1.

[0157] refer to Fig.11 , the pixels PX may be arranged in the second area DA2 by a bypass line design. Fig.11 As shown in FIG. 1 , the pixels PX electrically connected to the driving chip DRV may be arranged in the second area DA2 through a bypass line design. When the pixels PX arranged in the first area DA1 are defined as first pixels, the pixels PX arranged in the second area DA2 may be defined as second pixels.

[0158] A dummy data line DL-D extending from the chip area CA in the first direction DR1 may be arranged in the first area DA1. A second data line DL-2 extending in the first direction DR1 may be arranged in the second area DA2. Unlike the first data line DL-1, the second data line DL-2 may not be a signal line extending from the chip area CA, and the second data line DL-2 may have a length smaller than that of the first data line DL-1 and may not overlap with the first data line DL-1. Fig. 9 The second data line DL-2 and the dummy data line DL-D may be connected to each other through a connection line CNL extending in the second direction DR2.

[0159] Figure 8The unit pixel PXU shown in the figure may be arranged in each of the first area DA1 and the second area DA2. Each of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 of the first area DA1 may be connected to the first data line DL-1, and each of the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 of the second area DA2 may be connected to the second data line DL-2.

[0160] Fig.12 is a plan view showing a first data line DL- 1 , a first readout line RX- 1 , and a power line PL according to one or more embodiments of the present disclosure. Fig.13 It is along Fig.12 A cross-sectional view taken along line II'.

[0161] exist Fig.12 In the Fig. 9 One of the first data lines DL-1 shows Fig. 9 The first readout line RX-1 is one of the Fig. 9 One of the power lines PL.

[0162] Each of the first data line DL-1, the first readout line RX-1, and the power line PL may include a plurality of parts arranged on different layers according to regions. The first data line DL-1 may include a first part P1 to a fourth part P4, the first readout line RX-1 may include a first part P10 to a fifth part P50, and the power line PL may include a first part P100 to a fourth part P400. When one of the plurality of parts is referred to as a first part, another part may be simply referred to as a second part, and the names of the parts are not necessarily limited to the arrangement order of the parts.

[0163] The first portion P1 of the first data line DL-1 overlapping the display area DA of the first area NBA1 may be referred to as Figure 6 and Figure 7 In this embodiment, the first portion P1 of the first data line DL-1 may be formed of the third source / drain layer. The second portion P2 of the first data line DL-1 overlapping the non-display area NDA of the first area NBA1 may be formed of the reference 1 source / drain layer, the second source / drain layer, and the third source / drain layer. Figure 6 and Figure 7The first data line DL-1 may be formed by one of the first gate layer, the second gate layer, and the third gate layer described. In this embodiment, the second portion P2 of a first data line DL-1 may be formed by the first gate layer, and the second portion P2 of another first data line DL-1 adjacent thereto may be formed by the second gate layer. The second portion P2 of the first data line DL-1 may be connected to the first portion P1 through a contact hole CH. Adjacent portions of the first portion P1 to the fourth portion P4 may be connected to each other through the contact hole CH. The insulating layer through which the contact hole CH passes may be changed according to the stacking position of the first portion P1 and the stacking position of the second portion P2. Although the contact hole CH is shown as being defined at the boundary between adjacent regions, the contact hole CH may be defined in one of the adjacent regions. The contact hole CH may not be defined in the bending area BA.

[0164] The third portion P3 of the first data line DL-1 overlapping the bending area BA may be referred to as Figure 6 and Figure 7 The third portion P3 may be arranged away from the base layer SUB (see Figure 6 ), so that tensile stress is applied to the first data line DL-1 during bending. The third portion P3 of the first data line DL-1 may be formed of the third source / drain layer. In this embodiment, the third portion P3 of one first data line DL-1 may be formed of the second source / drain layer, and the third portion P3 of another first data line DL-1 adjacent thereto may be formed of the third source / drain layer.

[0165] The fourth portion P4 of the first data line DL-1 overlapping the second area NBA2 may be represented by a reference Figure 6 and Figure 7 The fourth portion P4 of the first data line DL-1 may be formed by one of the first gate layer, the second gate layer, and the third gate layer described. In this embodiment, the fourth portion P4 of one first data line DL-1 may be formed by the first gate layer, and the fourth portion P4 of another first data line DL-1 adjacent thereto may be formed by the second gate layer. The fourth portion P4 of the first data line DL-1 may be connected to the pad electrode PD through the contact hole CH. The second portion P2 of the first data line DL-1 formed by the first gate layer may be connected to the third portion P3 of the first data line DL-1 formed by the third source / drain layer. For process reasons, the resistance may vary for each gate layer, and therefore, a resistance deviation may occur between the first data line DL-1 formed by the first gate layer and the first data line DL-1 formed by the third source / drain layer. Here, the resistance deviation between the first data lines DL-1 may be reduced by portions in which the first data lines DL-1 are respectively formed by different gate layers.

[0166] The first portion P10 of the first readout line RX-1 overlapping the display area DA of the first area NBA1 may be represented by a reference Figure 6 and Figure 7 In this embodiment, the first portion P10 of the first readout line RX- 1 may be formed of one of the first source / drain layer, the second source / drain layer, and the third source / drain layer.

[0167] The second portion P20 of the first readout line RX- 1 disposed between the display area DA and the sealing area ENA may be referred to as Figure 6 and Figure 7 The shielding layer, the first gate layer, the second gate layer, and the third gate layer described are formed. The third portion P30 of the first readout line RX-1 arranged in the sealing area ENA may be arranged on a layer different from the power line PL. In one or more embodiments, the second portion P20 of the first readout line RX-1 and the third portion P30 of the first readout line RX-1 may be arranged on the same layer and be integral with each other.

[0168] The fourth portion P40 of the first sensing line RX-1 arranged from the area after the sealing area ENA to the bending area BA (eg, the fourth portion P40 of the first sensing line RX-1 arranged in the area between the sealing area ENA and the bending area BA) may be represented by reference Figure 6 and Figure 7 One of the described first source / drain layer, the second source / drain layer, and the third source / drain layer is formed. In one or more embodiments, the area between the sealing area ENA and the bending area BA may not be provided or may be formed to be narrow so as to be ignored.

[0169] When bending is performed, the fourth portion P40 of the first readout line RX-1 may be formed of the second source / drain layer or the third source / drain layer, so that tensile stress is applied to the fourth portion P40 of the first readout line RX-1. In this embodiment, the fourth portion P40 of one first readout line RX-1 may be formed of the second source / drain layer, and the fourth portion P40 of another first readout line RX-1 adjacent thereto may be formed of the third source / drain layer.

[0170] A fifth portion P50 of the first readout line RX-1 overlapping the second area NBA2 may be represented by a reference Figure 6 and Figure 7The fifth portion P50 of the first readout line RX-1 may be formed by one of the first source / drain layer, the second source / drain layer, and the third source / drain layer described. In this embodiment, the fifth portion P50 of the first readout line RX-1 may be formed by the second source / drain layer. The fifth portion P50 of the first readout line RX-1 may be connected to the pad electrode PD through the contact hole CH. Adjacent portions of the first portion P10 to the fifth portion P50 may be connected to each other through the contact hole CH. In one or more embodiments, at least two adjacent portions of the first portion P10 to the fifth portion P50 may be arranged on the same layer and have an integral shape.

[0171] The first portion P100 of the power line PL disposed between the display area DA and the sealing area ENA may be represented by reference Figure 6 and Figure 7 One of the first source / drain layer, the second source / drain layer, and the third source / drain layer described above is formed. In one or more embodiments, the first portion P100 of the power line PL may be disposed on the same layer as the power line PSL.

[0172] The second portion P200 of the power line PL arranged in the sealing area ENA may be represented by reference Figure 6 and Figure 7 The second portion P200 of the power line PL may have a double-line structure. The second portion P200 of the power line PL may include a portion formed by the second gate layer and a portion formed by the third gate layer. In one or more embodiments, the third portion P300 of the power line PL arranged from the area after the sealing area ENA to the bending area BA (for example, the third portion P300 of the power line PL arranged in the area between the sealing area ENA and the bending area BA) may be formed by referring to Figure 6 and Figure 7 One of the described first source / drain layer, second source / drain layer, and third source / drain layer is formed.

[0173] The fourth portion P400 of the power line PL overlapping the second area NBA2 may be represented by reference Figure 6 and Figure 7 The fourth portion P400 of the power line PL may have a double-line structure. The fourth portion P400 of the power line PL may include two portions of a portion formed by the first source / drain layer, a portion formed by the second source / drain layer, and a portion formed by the third source / drain layer.

[0174] The fourth portion P400 of the power line PL may be connected to the pad electrode PD through the contact hole CH. Adjacent portions of the first to fourth portions P100 to P400 may be connected to each other through the contact hole CH. In one or more embodiments, at least two adjacent portions of the first to fourth portions P100 to P400 may be arranged on the same layer and have an integral shape.

[0175] refer to Fig.13 , the buffer layer BFL to the eighth insulating layer INS8 may be disposed on the base layer SUB. In this embodiment, the buffer layer BFL to the fifth insulating layer INS5 may be an inorganic layer, and the sixth insulating layer INS6 to the eighth insulating layer INS8 may be an organic layer.

[0176] exist Fig.13 In the figure, it is briefly shown Figure 6 The fourth transistor T4 and the sixth transistor T6 of the non-display area NDA may be provided. An opening OP1 (hereinafter, referred to as a first opening) corresponding to the bending area BA may be defined in the buffer layer BFL to the fifth insulating layer INS5. The first opening OP1 may extend in the second direction DR2. The first opening OP1 may be defined to prevent or reduce the buffer layer BFL to the fifth insulating layer INS5 from being damaged due to stress if (for example, when) the non-display area NDA is bent.

[0177] An opening OP2 (hereinafter, referred to as a second opening) corresponding to the sealing area ENA may be defined in the sixth insulating layer INS6 to the eighth insulating layer INS8. The second opening OP2 may extend in the second direction DR2 to expose the fifth insulating layer INS5 as the uppermost inorganic layer. A partial area CNA (hereinafter, referred to as a contact area) of the fifth insulating layer INS5 may be exposed from the sixth insulating layer INS6 to the eighth insulating layer INS8 through the second opening OP2. The thin film encapsulation layer TFE may be arranged inside the second opening OP2 and may contact the contact area CNA of the fifth insulating layer INS5. The thin film encapsulation layer TFE that seals the display element layer DP-OLED may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 that are sequentially stacked. However, the layers constituting the thin film encapsulation layer TFE are not necessarily limited thereto. The first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may contact the fifth insulating layer INS5 to protect the display element layer DP-OLED from external moisture.

[0178] The input sensor IS disposed on the display panel DP may include at least one conductive layer and at least one insulating layer. In this embodiment, the input sensor IS may include a first insulating layer 210 , a first conductive layer 220 , a second insulating layer 230 , a second conductive layer 240 , and a third insulating layer 250 .

[0179] The first insulating layer 210 may be directly disposed on the display panel DP. The first insulating layer 210 may include an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer 220 and the second conductive layer 240 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3. The first conductive layer 220 and the second conductive layer 240 may include conductive wires defining mesh-shaped electrodes.

[0180] The second insulating layer 230 may cover the first conductive layer 220. The second insulating layer 230 may include an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. The third insulating layer 250 may cover the second conductive layer 240. The third insulating layer 250 may include an organic layer. The first insulating layer 210, the second insulating layer 230, and the third insulating layer 250 may be sequentially stacked. An opening corresponding to the bending area BA may be defined in the first insulating layer 210 and the second insulating layer 230.

[0181] Figures 14 to 16 is a cross-sectional view illustrating a sealing area ENA of a display device DD according to one or more embodiments of the present disclosure.

[0182] exist Figures 14 to 16 , the first read line RX-1 and the power line PL arranged in the sealing area ENA are shown in one cross section for comparison with each other. The first read line RX-1 and the power line PL may not overlap with each other except for the area where the first read line RX-1 and the power line PL cross each other, but the first read line RX-1 and the power line PL may be shown in one cross section for comparison with each other. Figures 14 to 16 The first readout line RX-1 and the multiple parts of each of the power line PL shown in FIG. 1 can be described as Fig.12 Some of the multiple parts shown in .

[0183] refer to Fig.14 , the third portion P30 of the first readout line RX- 1 may be disposed under the buffer layer BFL. Figure 6 The shielding electrode BML and the third portion P30 of the first readout line RX-1 described above may be formed by substantially the same process. Fig.14 As shown in FIG. 1 , the second portion P20 and the fourth portion P40 of the first readout line RX-1 may be disposed on the sixth insulating layer INS6. Each of the second portion P20 and the fourth portion P40 of the first readout line RX-1 may be connected to the third portion P30 of the first readout line RX-1 through a contact hole CH20. The contact hole CH20 may be connected to the third portion P30 of the first readout line RX-1 through a contact hole CH20. Figure 6The second contact hole CH2 in the first sensing line RX-1 may be formed by substantially the same process or may be formed by an additional etching process. In one or more embodiments, the second portion P20 and the fourth portion P40 of the first sensing line RX-1 may be disposed on the seventh insulating layer INS7 in an area that does not interfere with the power line PL.

[0184] The second portion P200 of the power line PL may be arranged between the first insulating layer INS1 and the third insulating layer INS3. In this embodiment, the second portion P200 of the power line PL may include a second-first portion P200-1 and a second-second portion P200-2 arranged on different layers. The second-first portion P200-1 and the second-second portion P200-2 may be connected to each other through a contact hole CH-1. The double-line structure may reduce the resistance of the power line PL. In one or more embodiments, one of the second-first portion P200-1 and the second-second portion P200-2 may not be provided.

[0185] like Fig.14 As shown in FIG. 1 , the first portion P100 and the third portion P300 of the power line PL may be disposed on the seventh insulating layer INS7. Each of the first portion P100 and the third portion P300 of the power line PL may be connected to the second portion P200 of the power line PL through a connection electrode CNE20 disposed on the sixth insulating layer INS6. The connection electrode CNE20 may be connected to the second portion P200 of the power line PL through a contact hole CH20. The contact hole CH20 may be connected to the second portion P200 of the power line PL through a contact hole CH20. Figure 6 The second contact hole CH2 in the power line PL is formed by substantially the same process. Each of the first portion P100 and the third portion P300 of the power line PL can be connected to the connection electrode CNE20 through the contact hole CH30. The contact hole CH30 can be connected to the connection electrode CNE20 through the contact hole CH30. Figure 6 The third contact hole CH3 in is formed by substantially the same process.

[0186] In one or more embodiments, the connection electrode CNE20 may not be provided, and each of the first portion P100 and the third portion P300 of the power line PL may be directly connected to the second portion P200 of the power line PL. In one or more embodiments, each of the first portion P100 and the third portion P300 of the power line PL may be connected to the second portion P200 of the power line PL through a connection electrode disposed on the fifth insulating layer INS5.

[0187] According to this embodiment, the third portion P30 of the first readout line RX-1 and the second portion P200 of the power line PL can be arranged under the fifth insulating layer INS5, and thus can be prevented from being affected by the wet etching process of forming the second opening PDL-OP2. For example, if the third portion P30 of the first readout line RX-1 or the second portion P200 of the power line PL is formed by the first source / drain layer arranged on the fifth insulating layer INS5, the limitation of corrosion of the corresponding line may occur.

[0188] The third portion P30 of the first readout line RX-1 may be disposed under the first insulating layer INS1 to reduce noise. Fig.12 The second portion P2 of the first data line DL-1 in the embodiment may be disposed on the same layer as the second-first portion P200-1 and the second-second portion P200-2, and Fig.12 The first portion P1 and the third portion P3 of the first data line DL-1 in the embodiment may be arranged on the same layer as the first portion P100 of the power line PL. Therefore, the third portion P30 of the first readout line RX-1 arranged under the first insulating layer INS1 may be relatively far away from the first data line DL-1.

[0189] In the following, reference will be made to Fig.15 and Fig.16 describe Fig.14 The first readout line RX-1 is different from the power line PL.

[0190] refer to Fig.15 , each of the second portion P20 and the fourth portion P40 of the first readout line RX-1 may be connected to the third portion P30 of the first readout line RX-1 through a connection electrode CNE10 disposed on the fifth insulating layer INS5. Each of the second portion P20 and the fourth portion P40 of the first readout line RX-1 may be connected to the connection electrode CNE10 through a contact hole CH20. The contact hole CH20 may be connected to the connection electrode CNE10 through the contact hole CH20. Figure 6 The connection electrode CNE10 may be connected to the third portion P30 of the first readout line RX-1 through the contact hole CH10. The contact hole CH10 may be connected to the third portion P30 of the first readout line RX-1 through the contact hole CH10. Figure 6 The first contact hole CH1 is formed by substantially the same process.

[0191] In one or more embodiments, the second portion P20 and the fourth portion P40 of the first readout line RX-1 may be disposed on the seventh insulating layer INS7. Here, the second portion P20 and the fourth portion P40 of the first readout line RX-1 may be connected to the third portion P30 of the first readout line RX-1 through a connection electrode disposed on the sixth insulating layer INS6 and a connection electrode disposed on the fifth insulating layer INS5. For example, the connection relationship between the second portion P20 of the first readout line RX-1 and the third portion P30 of the first readout line RX-1 may be similar to Figure 6 The connection relationship between the sixth semiconductor layer SCP6 and the third connection electrode CNE3.

[0192] refer to Fig.16 , the third portion P30 of the first readout line RX-1 may be disposed on the fourth insulating layer INS4. Each of the second portion P20 and the fourth portion P40 of the first readout line RX-1 may be connected to the third portion P30 of the first readout line RX-1 through a contact hole CH20. Fig.16 , the contact hole CH20 connecting the connection electrode CNE20 to the second portion P200 of the power line PL may be arranged in a region that does not interfere with the third portion P30 of the first readout line RX- 1. In this sense, the contact hole CH20 may be shown as a dotted line.

[0193] In one or more embodiments, each of the second portion P20 and the fourth portion P40 of the first readout line RX- 1 may be connected to the third portion P30 of the first readout line RX- 1 through a connection electrode disposed on the fifth insulating layer INS5 .

[0194] According to one or more embodiments of the present disclosure, the readout line and the power line can be arranged to overlap each other in the non-display area, thereby simplifying the line design to increase the surface area of ​​the light sensing area. The first readout line can be used to ensure the light sensing area corresponding to the second area. In order to further increase the light sensing area in the first area, it may be further desired or necessary to dummy the readout line, the second readout line, and the connecting line, and therefore, the line design may be more complicated.

[0195] The readout lines and the power lines may be arranged to overlap each other in the non-display area, thereby reducing the surface area of ​​the non-display area.

[0196] It will be apparent to those skilled in the art that one or more suitable modifications and variations may be made in the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the embodiments provided within the scope of the appended claims and their equivalents. Therefore, to the maximum extent permitted by law, the scope of the present disclosure will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be limited or restricted by the foregoing detailed description.

Claims

1. Display equipment, including: A base layer including a display area and a non-display area, wherein the display area includes a first area and a second area adjacent to the first area in a first direction, the non-display area includes a chip area and a pad area, and the pad area is positioned farther from the display area than the chip area in a second direction intersecting the first direction; A driver chip, in the chip region; a first pixel in the first region and comprising a first light emitting element; a first optical sensor in the second region; a first data line extending from the chip region to the first region and electrically connecting the first pixel to the driving chip; a first readout line extending from the pad region to the second region and electrically connected to the first optical sensor; as well as a power line extending from the pad region and overlapping the first readout line in the non-display region; wherein the first data line and the first readout line do not overlap each other in the non-display area, and wherein the first readout line and the power line are at different layers in a region of the non-display area where the first readout line and the power line overlap each other.

2. The display device according to claim 1, further comprising: a plurality of inorganic layers on the base layer to overlap the display area and the non-display area; a plurality of organic layers on the plurality of inorganic layers and exposing a contact region of an uppermost inorganic layer among the plurality of inorganic layers in the non-display region; as well as A thin film encapsulation layer is on the plurality of organic layers to cover the first light emitting element and to contact the contact region of the uppermost inorganic layer.

3. The display device according to claim 2, wherein: The non-display area further includes a sealing area corresponding to the contact area of ​​the uppermost inorganic layer, and Wherein, the first sensing line and the power line overlap each other in the sealing area.

4. The display device according to claim 3, wherein: The first sensing line and the power line are located below the uppermost inorganic layer in the sealing area.

5. The display device according to claim 3, wherein: The first data line and the power line are on the same layer in the sealing area.

6. The display device according to claim 3, wherein: The sealing area is located between the display area and the chip area in the second direction.

7. The display device according to claim 3, wherein: The first pixel further includes a shielding electrode, a dummy electrode, a first transistor and a second transistor. The first transistor includes a silicon semiconductor layer and a first gate electrode on the silicon semiconductor layer. the second transistor includes an oxide semiconductor layer on the first gate electrode and a second gate electrode on the oxide semiconductor layer, The dummy electrode is located between the first gate electrode and the second gate electrode, and The shielding electrode is located below the silicon semiconductor layer.

8. The display device according to claim 7, wherein: the first readout line comprises a first portion within the sealing area on the same layer as the shielding electrode, and The electric force line includes a first portion on the same layer as the first gate electrode or the dummy electrode within the sealing region.

9. The display device according to claim 8, wherein: The non-display area further includes a bending area between the sealing area and the pad area, The first sense line further includes a second portion within the bend region on a different layer than the first portion of the first sense line, and The power line also includes a second portion within the bend region on a different layer than the first portion of the power line.

10. The display device according to claim 7, wherein: the first readout line comprises a first portion within the sealing area on the same layer as the shielding electrode, and The electric force line includes a first portion on the same layer as the first gate electrode and a second portion on the same layer as the dummy electrode in the sealing region, and The first portion and the second portion of the power line are electrically connected to each other through a contact hole, which passes through one of the plurality of inorganic layers and is located between the first portion and the second portion of the power line.

11. The display device according to claim 7, wherein: the first readout line comprises a first portion within the sealing area on the same layer as the shielding electrode, and The electric force line includes a first portion on the same layer as the second gate electrode in the sealing region.

12. The display device according to claim 3, wherein: The non-display area further includes a bending area which is bent so that a portion of the base layer corresponding to the display area and a portion of the base layer corresponding to the pad area become close to each other, and Wherein, the first data line, the first readout line, and the power line are on the same layer in the bending region.

13. The display device according to claim 12, wherein: The first readout line and the power line are on different layers in a region between the bending region and the pad region of the non-display region in the second direction.

14. The display device according to claim 12, wherein: A width of a portion of the non-display region corresponding to the bending region in the first direction is smaller than a width of a portion of the non-display region corresponding to the pad region in the first direction.

15. The display device according to claim 1, further comprising: a second pixel in the second region and comprising a second light emitting element; a dummy data line extending from the chip area to the first area; a second data line in the second region and electrically connected to the second light emitting element; as well as A connecting line electrically connects the second data line to the dummy data line.

16. The display device according to claim 1, further comprising: a second optical sensor in the first region; a dummy readout line extending from the pad region to the second region; a second readout line in the first region and electrically connected to the second optical sensor; as well as A connection line electrically connects the second readout line to the dummy readout line.

17. Display equipment, including: A base layer, comprising a display area and a non-display area defined by a first direction and a second direction intersecting each other, wherein the non-display area comprises a sealing area, a pad area which is farther from the display area than the sealing area in the second direction, and a chip area between the sealing area and the pad area; A first inorganic layer, a second inorganic layer, a third inorganic layer, a fourth inorganic layer, a fifth inorganic layer and a sixth inorganic layer are on the base layer, overlapped with the display area and the non-display area, and are sequentially stacked; A first organic layer, a second organic layer and a third organic layer are sequentially stacked on the sixth inorganic layer, exposing a contact region of the sixth inorganic layer in the sealing region; A driver chip, in the chip region; a pixel in the display area and comprising a dummy electrode, a first transistor, a second transistor and a light emitting element; an optical sensor in the display area; a data line extending from the chip area to the display area and electrically connecting the pixel to the driving chip; a readout line extending from the pad region to the display region and electrically connected to the optical sensor; a power line extending from the pad region and overlapping the readout line in the non-display region; as well as an inorganic encapsulation layer on the third organic layer to cover the light emitting element and in contact with the contact region of the sixth inorganic layer within the sealing region, wherein the data line and the readout line do not overlap each other in the non-display area, wherein the readout line and the power line overlap each other within the sealing area, wherein the readout line is located below the first inorganic layer or between the fifth inorganic layer and the sixth inorganic layer in the sealing area, and Wherein, the electric force lines are located between the first inorganic layer and the fourth inorganic layer.

18. The display device according to claim 17, wherein: The first transistor includes a silicon semiconductor layer located below the first inorganic layer and a first gate electrode located between the first inorganic layer and the second inorganic layer. wherein the second transistor includes an oxide semiconductor layer located between the third inorganic layer and the fourth inorganic layer and a second gate electrode located between the fourth inorganic layer and the fifth inorganic layer, and Wherein, the dummy electrode is located between the second inorganic layer and the third inorganic layer.

19. The display device according to claim 18, wherein: The readout line includes a first portion located below the first inorganic layer in the sealing region, and wherein the electric force line includes, in the sealing region, a first portion on the same layer as the first gate electrode and a second portion on the same layer as the dummy electrode, and The first portion and the second portion of the power line are connected to each other through a contact hole passing through the second inorganic layer.

20. The display device according to claim 18, wherein: The readout line includes a first portion on the same layer as the second gate electrode in the sealing region, and The electric force line includes a first portion on the same layer as the first gate electrode and a second portion on the same layer as the dummy electrode in the sealing region, The first portion and the second portion of the power line are connected to each other through a contact hole passing through the second inorganic layer.

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