Display module and electronic device

Abstract

The invention relates to a display module and an electronic device. The display module includes a display panel having a display area in which a plurality of pixels are disposed and a non-display area having a first pad area in which a plurality of first signal pads electrically connected to the plurality of pixels through a plurality of first signal lines, respectively, are disposed; and an input sensor disposed on the display panel and including a sensing insulating layer including an organic material, and a sensing conductive layer. Each of the plurality of first signal pads includes a plurality of first conductive patterns stacked in a thickness direction of the display panel. At least one of the plurality of first conductive patterns includes a same material as a material of the sensing conductive layer. A first opening overlapping the first pad region is defined in the sensing insulating layer. A first residual conductive pattern including the same material as that of the sensing conductive layer is disposed on a boundary of the first opening.

Description

Technical Field

[0001] The present disclosure relates to a display module, and more particularly, to a display module including a signal pad and a signal line, and an electronic device including the signal pad and the signal line. Background Art

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles may include display modules that display images. These display modules are capable of detecting external inputs such as touch. The display modules may be electrically coupled to a data driver that provides the electrical signals necessary to display the image. Summary of the invention

[0003] A display module includes a display panel, the display panel has a display area and a non-display area, a plurality of pixels are arranged in the display area, the non-display area has a first pad area, a plurality of first signal pads are arranged in the first pad area and are electrically connected to the plurality of pixels through a plurality of first signal lines respectively; an input sensor is arranged on the display panel and includes a sensing insulating layer containing an organic material, and a sensing conductive layer. Each of the plurality of first signal pads includes a plurality of first conductive patterns stacked along the thickness direction of the display panel, and at least one of the plurality of first conductive patterns includes the same material as the sensing conductive layer. A first opening overlapping the first pad area is defined in the sensing insulating layer. A first residual conductive pattern including the same material as the sensing conductive layer is arranged on a boundary of the first opening.

[0004] The first residual conductive pattern may be spaced apart from the plurality of first signal pads by a predetermined distance.

[0005] A minimum distance between the first residual conductive pattern and the plurality of first signal pads may be about 20 μm or more.

[0006] The sensing insulation layer may not overlap the plurality of first signal pads.

[0007] The plurality of first signal lines may cross the first residual conductive pattern and the display module may further include an insulating layer disposed between the plurality of first signal lines and the first residual conductive pattern.

[0008] Each of the plurality of pixels may include a transistor and a light emitting element connected to the transistor, and the insulating layer may contain the same material as that of at least one of the plurality of insulating layers provided between the transistor and the light emitting element.

[0009] Each of the plurality of pixels may include a transistor and a light emitting element connected to the transistor. The transistor may include a semiconductor pattern and a gate electrode disposed on the semiconductor pattern. The display panel may further include a first connection electrode and a second connection electrode connecting the transistor to the light emitting element.

[0010] The plurality of first conductive patterns may include: a 1-1 conductive pattern including the same material as that of the gate electrode; a 1-2 conductive pattern including the same material as that of the first connection electrode; a 1-3 conductive pattern including the same material as that of the second connection electrode; and a 1-4 conductive pattern including the same material as that of the sensing conductive layer. The 1-1 conductive pattern to the 1-4 conductive pattern may be electrically connected to each other.

[0011] Each of the plurality of first signal lines may include a same material as a material of at least one of the gate electrode and the second connection electrode.

[0012] Each of the plurality of first signal lines may include the same material as that of the second connection electrode. An insulating layer may be disposed between the plurality of first signal lines and the first residual conductive pattern. The first residual conductive pattern may be spaced apart from an end of the insulating layer by at least about 20 μm.

[0013] The non-display area may further include a second pad area, in which a plurality of second signal pads are arranged. The plurality of second signal pads may be spaced farther from the display area than the plurality of first signal pads, and the plurality of second signal pads may be electrically connected to the plurality of pixels through a plurality of second signal lines, respectively. Each of the plurality of second signal pads may include a plurality of second conductive patterns stacked along the thickness direction of the display panel and at least one of the plurality of second conductive patterns may contain the same material as the material of the sensing conductive layer. A second opening overlapping the second pad area may be defined in the sensing insulating layer. A second residual conductive pattern including the same material as the material of the sensing conductive layer may be arranged on the boundary of the second opening.

[0014] The second residual conductive pattern may be spaced apart from the plurality of second signal pads by a predetermined distance.

[0015] The second signal line may include: a 2-1 signal line; and a 2-2 signal line, the 2-2 signal line is electrically connected between the 2-1 signal line and a plurality of second signal pads, the 2-2 signal line may cross the second residual conductive pattern, and the display module may further include an insulating layer disposed between the 2-2 signal line and the second residual conductive pattern.

[0016] Each of the plurality of pixels may include a transistor and a light emitting element connected to the transistor. The transistor may include a semiconductor pattern and a gate electrode disposed on the semiconductor pattern. The display panel may further include a first connection electrode and a second connection electrode connecting the transistor to the light emitting element. The 2-1 signal line may contain the same material as that of the sensing conductive layer, and the 2-2 signal line may contain the same material as that of the second connection electrode.

[0017] A minimum distance between the plurality of second signal pads may be about 10 μm or more.

[0018] The non-display area may further include a third pad area, in which a plurality of test pads are arranged. The plurality of test pads may be spaced farther from the display area than the plurality of second signal pads. The plurality of test pads may be electrically connected to the plurality of pixels through a plurality of third signal lines, respectively. Each of the plurality of test pads may include a plurality of third conductive patterns stacked along the thickness direction of the display panel, and at least one of the plurality of third conductive patterns may contain the same material as the material of the sensing conductive layer. A third opening overlapping the third pad area may be defined in the sensing insulating layer. A third residual conductive pattern including the same material as the material of the sensing conductive layer may be arranged on the boundary of the third opening.

[0019] The plurality of test pads may be bonded to the test circuit board via the conductive adhesive layer.

[0020] An electronic device includes: a display panel, the display panel having a display area and a non-display area, pixels are arranged in the display area, the non-display area has a first pad area and a second pad area, and a plurality of first signal pads and a plurality of second signal pads are arranged in the first pad area and the second pad area, respectively electrically connected to the pixels through a plurality of signal lines; an input sensor is arranged on the display panel and includes a sensing insulating layer containing an organic material and a sensing conductive layer; a data driver is arranged on the non-display area and electrically connected to the plurality of first signal pads through a first conductive adhesive layer; a flexible circuit board is arranged on the non-display area and electrically connected to the plurality of second signal pads through a second conductive adhesive layer. Each of the plurality of first signal pads includes a plurality of first conductive patterns stacked along the thickness direction of the display panel, and at least one of the plurality of first conductive patterns includes the same material as the material of the sensing conductive layer. A first opening overlapping the first pad area is defined in the sensing insulating layer. A first residual conductive pattern including the same material as the material of the sensing conductive layer is arranged on the boundary of the first opening.

[0021] The first residual conductive pattern may be spaced apart from the plurality of first signal pads by a predetermined distance.

[0022] In the non-display area, each of the plurality of second signal pads may include a plurality of second conductive patterns stacked along the thickness direction of the display panel, and at least one of the plurality of second conductive patterns may contain the same material as that of the sensing conductive layer, and a second opening overlapping the second pad area may be defined in the sensing insulating layer. A second residual conductive pattern including the same material as that of the sensing conductive layer may be provided on a boundary of the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the inventive concept and together with the description are used to explain the principles of the inventive concept. In the accompanying drawings:

[0024] Figure 1 is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0025] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the inventive concept;

[0026] Figure 3 is a cross-sectional view of a display module according to an embodiment of the inventive concept;

[0027] Figure 4 is a plan view of a display panel according to an embodiment of the inventive concept;

[0028] Figure 5 is a plan view of an input sensor according to an embodiment of the inventive concept;

[0029] Figure 6 is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0030] Figure 7 is a cross-sectional view of a display module according to an embodiment of the inventive concept;

[0031] Figure 8 is an enlarged plan view of a display module according to an embodiment of the inventive concept;

[0032] Fig.9A According to the embodiment of the present invention, Figure 8 A cross-sectional view taken along line II';

[0033] Fig. 9B According to the embodiment of the present invention, Figure 8 A cross-sectional view taken along line II-II';

[0034] Fig.10 is an enlarged plan view of a display module according to an embodiment of the inventive concept;

[0035] Fig.11A According to the embodiment of the present invention, Fig.10 A cross-sectional view taken along line III-III';

[0036] Fig. 11B According to the embodiment of the present invention, Fig.10 A cross-sectional view taken along line IV-IV';

[0037] Fig.12 is an enlarged plan view of a display module according to an embodiment of the inventive concept;

[0038] Fig.13A According to the embodiment of the present invention, Fig.12 A cross-sectional view taken along line V-V';

[0039] Fig. 13B According to the embodiment of the present invention, Fig.12 A cross-sectional view taken along line VI-VI';

[0040] Fig.14 is a perspective view of an electronic device according to an embodiment of the inventive concept;

[0041] Fig.15 is an enlarged plan view of a display module according to an embodiment of the inventive concept;

[0042] Fig.16 According to the embodiment of the present invention, Fig.15 A cross-sectional view taken along line VII-VII';

[0043] Fig.17A is a cross-sectional view of a test pad according to an embodiment of the inventive concept; and

[0044] Fig. 17B is a cross-sectional view of a test pad according to a comparative example. DETAILED DESCRIPTION

[0045] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element can be directly set on, connected to or coupled to the other element, or an intervening element may be set between the element and the other element.

[0046] Throughout the drawings and description, the same reference numerals or symbols may refer to the same elements. Although each of the drawings may represent one or more specific embodiments of the present disclosure, drawn to scale so that relative lengths, thicknesses, and angles can be inferred therefrom, it should be understood that the present invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be changed within the spirit and scope of the present disclosure, for example, to allow for manufacturing limitations, etc.

[0047] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] It will be understood that, although the terms first, second, etc. can be used to describe various elements, components, regions, layers and / or sections in this article, these elements, components, regions, layers and / or sections should not necessarily be limited by these terms. These terms are used to distinguish an element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the scope of the present invention, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section. Similarly, the second element, component, region, layer or section can be referred to as the first element, component, region, layer or section. Unless the context clearly indicates otherwise, as used herein, the singular form "one", "one (kind / person)" and "described (the)" are also intended to include plural forms.

[0049] In addition, terms such as "below", "on the lower side", "above", or "on the upper side" may be used to describe the relationship of elements shown in the drawings. These terms have a relative concept and are described based on the directions indicated in the drawings.

[0050] It will also be understood that when used in this specification, the terms “including” and / or “having” specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] Hereinafter, embodiments of the inventive concept are described with reference to the accompanying drawings.

[0052] Figure 1 is a perspective view of an electronic device EA according to an embodiment of the inventive concept. Figure 2 is an exploded perspective view of an electronic device EA according to an embodiment of the inventive concept.

[0053] refer to Figure 1 and Figure 2 , the electronic device EA can be activated in response to the electrical signal, display the image IM and detect the external input TC. For example, the electronic device EA may include devices such as a computer monitor, a mobile phone, a tablet computer, a navigation system and a game console. However, unless it departs from the concept of the present invention, the above-mentioned embodiments of the electronic device EA are examples, and the electronic device EA is not necessarily limited to any one embodiment. In this embodiment, the electronic device EA is exemplarily shown as a mobile phone.

[0054] In a plan view, the electronic device EA may have a rectangular shape having a pair of short sides extending in a first direction DR1 and a pair of long sides extending in a second direction DR2 crossing the first direction DR1. However, embodiments of the inventive concept are not necessarily limited thereto, and the electronic device EA may have various shapes in a plan view, such as a circular shape and other polygonal shapes.

[0055] In the present embodiment, the third direction DR3 may be defined as a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. The front surface (or upper surface) and the rear surface (or lower surface) of each of the many elements constituting the electronic device EA may face away from each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The distance between the front surface and the rear surface defined along the third direction DR3 may correspond to the thickness of a given element.

[0056] In the present specification, "in a plan view" may be defined as a state when viewed from the third direction DR3. In the present specification, "in a cross-sectional view" may be defined as a state when viewed from the first direction DR1 or the second direction DR2. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and thus may be changed to other directions.

[0057] The electronic device EA may be rigid or flexible. "Flexible" may mean having a bendable property, and may include structures ranging from a fully folded structure to a bendable structure at a level of a few nanometers. For example, the flexible electronic device EA may include a bendable electronic device, a rollable electronic device, or a foldable electronic device.

[0058] The electronic device EA may display an image IM through a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The image IM may include a still image and a dynamic (eg, moving) image. Figure 1 A clock and an icon are shown as examples of the image IM.

[0059] The display surface FS of the electronic device EA may include only a flat surface, or may also include a curved surface bent from at least one side of the flat surface. The display surface FS may correspond to the front surface of the electronic device EA and simultaneously correspond to the front surface of the window WM. Hereinafter, the display surface FS of the electronic device EA and the front surface FS of the window WM are represented by the same reference numerals.

[0060] According to an embodiment, the electronic device EA can detect an external input TC. The external input TC may include various types of inputs, such as power, pressure, temperature, or light. In the present embodiment, the external input TC is shown as a user's hand applied to the front surface of the electronic device EA. However, this is shown exemplarily, and the external input TC may include an input by a pen / stylus or an input applied close to the electronic device EA (such as hovering).

[0061] The electronic device EA can detect the user's input through the display surface FS defined at the front surface, and respond to the detected input signal. However, the area of ​​the electronic device EA for detecting the external input TC is not necessarily limited to the front surface of the electronic device EA, but can be changed according to the design of the electronic device EA. For example, the electronic device EA can also detect the user's input applied to the side surface or rear surface of the electronic device EA.

[0062] The electronic device EA may include a window WM, a display module DM, an electronic module ELM, a power module PSM, and a housing HAU. The window WM may be coupled to the housing HAU to form an appearance of the electronic device EA.

[0063] The window WM may be disposed on the display module DM. The window WM may cover the front surface IS of the display module DM and may protect the display module DM from external impacts and scratches. The window WM may be bonded to the display module DM by an adhesive layer.

[0064] The window WM may include an optically transparent insulating material. For example, the window WM may include glass or a synthetic resin as a base film. The window WM may have a single-layer structure or a multi-layer structure. For example, the multi-layer window WM may include a synthetic resin film bonded by an adhesive, or include a glass film and a synthetic resin film bonded by an adhesive. The window WM may also include a functional layer disposed on the transparent base film, such as an anti-fingerprint layer, a phase control layer and / or a hard coating layer.

[0065] The front surface FS of the window WM may correspond to the front surface of the electronic device EA. The front surface FS of the window WM may include a transmissive area TA and a bezel area BZA.

[0066] The transmission area TA may be an optically transparent area. The transmission area TA may transmit the image IM provided by the display module DM. In the present embodiment, the transmission area TA is shown as a quadrilateral shape in the plan view, but the shape of the transmission area TA in the plan view is not necessarily limited thereto, and the transmission area TA may have various shapes in the plan view.

[0067] The bezel area BZA may be an area having a light transmittance lower than that of the transmissive area TA. The bezel area BZA may correspond to an area printed with a material having a predetermined color. The bezel area BZA may prevent light transmission and thus prevent components of the display module DM that are overlapped with the bezel area BZA from being observed from the outside.

[0068] The border area BZA may be adjacent to the transmission area TA. The shape of the transmission area TA in a plan view may be substantially defined by the border area BZA. For example, the border area BZA may be disposed outside the transmission area TA and may thus surround the transmission area TA. However, this is shown exemplarily, and the border area BZA may be adjacent to only one side of the transmission area TA, or may be disposed on a side surface (not a front surface) of the electronic device EA. In addition, the border area BZA may also be omitted.

[0069] The display module DM may be disposed between the window WM and the housing HAU. The display module DM may display an image IM and detect an external input TC. The image IM may be displayed in the front surface IS of the display module DM. The front surface IS of the display module DM may include an active area AA and a peripheral area NAA.

[0070] The active area AA may be activated in response to an electrical signal. For example, the active area AA may be an area in which the image IM is displayed and at the same time an area in which the external input TC is detected. The active area AA may overlap at least a portion of the transmissive area TA. Therefore, the user may observe the image IM or provide the external input TC through the transmissive area TA. However, this is an example, and in the active area AA, the area in which the image IM is displayed and the area in which the external input TC is detected may also be separated, and the active area AA is not necessarily limited to any one embodiment of the inventive concept.

[0071] The peripheral area NAA may be adjacent to the active area AA. For example, the peripheral area NAA may at least partially surround the active area AA, which may mean that the peripheral area NAA is close to the active area AA on one or more sides thereof and may be close to the active area AA on the opposite side or may fully surround the active area AA. The phrase "at least partially surrounds" may be similarly interpreted when used elsewhere within this specification. In the peripheral area NAA, a driving circuit or driving wiring, etc. may be provided for driving the active area AA. The peripheral area NAA may overlap with at least a portion of the border area BZA, and the border area BZA may prevent components provided in the peripheral area NAA from being observed from the outside.

[0072] The display module DM may include a display panel and an input sensor. The display panel may display an image IM, and the input sensor may detect an external input TC. This will be described in detail later.

[0073] A portion of the display module DM may be bent relative to a bending axis extending in the first direction DR1. For example, the portion of the display module DM may be bent toward a rear surface corresponding to the active area AA of the display module DM. The bent portion of the display module DM may be connected to the flexible circuit board FCB, and thus, in a plan view, the flexible circuit board FCB may overlap with the display module DM.

[0074] The flexible circuit board FCB may be electrically connected to the display module DM through one side of the display module DM. The flexible circuit board FCB may generate an electrical signal to provide to the display module DM, or receive a signal generated from the display module DM to calculate a result value including information about a position where the external input TC is detected or about the intensity of the detected external input TC.

[0075] The electronic module ELM and the power module PSM may be disposed below the display module DM and may be electrically connected via a separate circuit board.

[0076] The power module PSM may supply power necessary for the operation of the electronic device EA. For example, the power module PSM may include a general battery module.

[0077] The electronic module ELM may include various functional modules for operating the electronic device EA. For example, the electronic module ELM may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an optical module, and an external interface module, etc. The electronic module ELM may include a main circuit board, and the modules of the electronic module ELM may be mounted on the main circuit board, or electrically connected to the main circuit board through a separate circuit board.

[0078] The control module of the electronic module ELM can control the overall operation of the electronic device EA. For example, the control module can activate or deactivate the display module DM in response to the user's input. The control module may include at least one microprocessor. The optical module of the electronic module ELM may include a camera module, a proximity sensor, a biosensor or a light output lamp that detects a part of the user's body (e.g., a fingerprint, an iris, or a face), etc.

[0079] The housing HAU may be coupled to the window WM to provide an internal space for accommodating the display module DM, the electronic module ELM, the power module PSM, and the flexible circuit board FCB. The housing HAU may include a material having a relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates, and the plurality of frames and / or plates may include glass, plastic, or metal, or may be composed of a combination thereof. The housing HAU may absorb impacts applied from the outside, or prevent foreign matter / moisture, etc. from penetrating therein, and may therefore protect the components of the electronic device EA housed in the housing HAU.

[0080] Figure 3 is a cross-sectional view of a display module DM according to an embodiment of the inventive concept.

[0081] refer to Figure 3 , the display module DM may include a display panel DP and an input sensor ISP. The input sensor ISP may be disposed on the display panel DP. For example, the input sensor ISP may be directly disposed on the display panel DP. In the present embodiment, “the input sensor ISP is directly disposed on the display panel DP” means that the input sensor ISP is formed on the display panel DP through a continuous process and is thus coupled to the display panel DP without using a separate adhesive layer. For example, components of the input sensor ISP may be formed on a substrate surface provided from the display panel DP.

[0082] The display panel DP may display an image in response to an electrical signal. According to an embodiment, the display panel DP may be an emission type display panel, but is not necessarily limited thereto. For example, the display panel DP may be an organic light emitting diode (OLED) display panel, an inorganic light emitting display panel, or a quantum dot light emitting display panel. The light emitting layer of the organic light emitting diode display panel may include an organic light emitting material, and the light emitting layer of the inorganic light emitting display panel may include an inorganic light emitting material. The light emitting layer of the quantum dot light emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel DP is described as an organic light emitting diode display panel.

[0083] The display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL, and an encapsulation layer ECL, which are sequentially stacked along the third direction DR3.

[0084] The base substrate BS may be a rigid substrate, or a flexible substrate that can be bent, folded, or curled to a significant degree without breaking or otherwise being damaged. For example, the base substrate BS may be a glass substrate, a metal substrate, or a polymer substrate, etc. The base substrate BS may provide a base surface on which the circuit layer DP-CL is disposed.

[0085] The base substrate BS may include an inorganic layer, an organic layer or a composite material layer. The base substrate BS may have a single-layer structure or a multi-layer structure. For example, the multi-layer base substrate BS may include a synthetic resin layer and a multi-layer inorganic layer or a single inorganic layer disposed between the synthetic resin layers. The synthetic resin layer may include an acrylate resin, a methacrylate resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin or a perylene resin, etc., but the material of the synthetic resin layer is not necessarily limited thereto.

[0086] The circuit layer DP-CL may be disposed on the base substrate BS. The circuit layer DP-CL may include at least one insulating layer, a semiconductor pattern, and a conductive pattern. The insulating layer, the semiconductor pattern, and the conductive pattern included in the circuit layer DP-CL may form driving elements such as transistors, signal lines, and pads.

[0087] The display element layer DP-OL may be disposed on the circuit layer DP-CL. The display element layer DP-OL may include light emitting elements, each of which emits light. For example, the light emitting elements may include organic light emitting elements, inorganic light emitting elements, micro LEDs, nano LEDs, etc. The light emitting elements of the display element layer DP-OL may be electrically connected to the driving elements of the circuit layer DP-CL to emit light in response to electrical signals provided by the driving elements.

[0088] The encapsulation layer ECL may be disposed on the display element layer DP-OL to seal the light emitting element. The encapsulation layer ECL may increase the optical efficiency of the display element layer DP-OL, or include at least one thin film for protecting the display element layer DP-OL. For example, the encapsulation layer ECL may include an inorganic film and / or an organic film. The inorganic film of the encapsulation layer ECL may protect the light emitting element from moisture / oxygen. The organic film of the encapsulation layer ECL may protect the light emitting element from foreign matter (such as dust particles).

[0089] Input sensor ISP can detect external input TC (see Figure 1 ) and provides an input signal including information about the external input TC so that the display panel DP can display an image corresponding to the external input TC. The input sensor ISP may operate in various types such as a capacitive type, a resistive type, an infrared type, a sound wave type, or a pressure type, and the operation type of the input sensor ISP is not necessarily limited to any one as long as the external input TC can be detected. In the present embodiment, the input sensor ISP is described as an input sensing panel operating in a capacitive type.

[0090] The input sensor ISP may include a base layer IL1, a first sensing conductive layer CL1, a first sensing insulating layer IL2, a second sensing conductive layer CL2, and a second sensing insulating layer IL3 sequentially stacked along a third direction DR3. The base layer IL1 of the input sensor ISP may be in contact with the encapsulation layer ECL. However, embodiments of the inventive concept are not necessarily limited thereto, and at least one of the base layer IL1 and the second sensing insulating layer IL3 may be omitted.

[0091] The first sensing conductive layer CL1 and the second sensing conductive layer CL2 may each have a single-layer structure or a multi-layer structure. The conductive layer having a multi-layer structure may include at least two layers as a transparent conductive layer and / or a metal layer. The conductive layer having a multi-layer structure may include a metal layer containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), polyethylene dioxythiophene (PEDOT), metal nanowires and / or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum and / or their alloys. For example, the first sensing conductive layer CL1 and the second sensing conductive layer CL2 may each have a double-layer structure such as ITO / copper, or the embodiments of the present inventive concept are not necessarily limited thereto. The first sensing conductive layer CL1 and the second sensing conductive layer CL2 may each have a three-layer structure of titanium / aluminum / titanium.

[0092] The first and second sensing conductive layers CL1 and CL2 may include sensing conductive patterns, and the sensing conductive patterns of the first and second sensing conductive layers CL1 and CL2 may form sensing electrodes constituting the input sensor ISP and sensing lines connected to the sensing electrodes.

[0093] The base layer IL1, the first sensing insulating layer IL2, and the second sensing insulating layer IL3 may each include an inorganic film and / or an organic film. For example, the inorganic film may include aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and / or hafnium oxide, and the organic film may include an acrylate resin, a methacrylate resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and / or a perylene resin. However, the material of the inorganic film and the material of the organic film are not necessarily limited to the above examples. In an embodiment, the base layer IL1 may include an inorganic film, and the first sensing insulating layer IL2 and the second sensing insulating layer IL3 may each include an organic film including an organic material.

[0094] Figure 4 is a plan view of a display panel DP according to an embodiment of the inventive concept.

[0095] refer to Figure 4The display panel DP may include a base substrate BS, pixels PX, signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2 and PL electrically connected to the pixels PX, a scan driver SDV, an emission driver EDV, a data driver DDV and display pads D-PD.

[0096] The base substrate BS may provide a base surface on which electrical elements, wires, etc. of the display panel DP are disposed. The base substrate BS may include a first base area AA1, a bending area BA, and a second base area AA2 separated in the second direction DR2. That is, it can be understood that the electronic device EA (see Figure 2 ) may include a first base area AA1, a bending area BA, and a second base area AA2 separated in the second direction DR2. The bending area BA may extend from the first base area AA1 in the second direction DR2. The second base area AA2 may extend from the bending area BA in the second direction DR2. Therefore, the first base area AA1 and the second base area AA2 may be spaced apart from each other, and the bending area BA is between the first base area AA1 and the second base area AA2.

[0097] The first base area AA1 may include a display area DA. The display area DA may be a region in which a light emitting element of a pixel PX is disposed. Therefore, the pixel PX may display an image through the display area DA. The display area DA may correspond to a display module DM (see Figure 2 ) of the active area AA (see Figure 2 ) and with the transmissive area TA (see Figure 2 )overlapping.

[0098] The first base area AA1, the bending area BA, and the second base area AA2 other than the display area DA may be defined as a non-display area NDA. The non-display area NDA may be an area adjacent to the display area DA and in which no image is displayed. The non-display area NDA may at least partially surround the display area DA. In the non-display area NDA, a scan driver SDV, an emission driver EDV, and a data driver DDV for driving the pixel PX, and a display pad D-PD electrically connected to the signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL may be provided. The signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL electrically connected to the pixel PX may extend to be provided in the non-display area NDA.

[0099] The bending area BA may be an area that is bendable relative to a bending axis extending in the first direction DR1. For example, the bending area BA may be bent toward the rear surface of the display panel DP corresponding to the first base area AA1. According to the bending operation of the bending area BA, the second base area AA2 extending from one side of the bending area BA may overlap with the first base area AA1 in a plan view. For example, the second base area AA2 may be disposed on the rear surface of the display panel DP corresponding to the first base area AA1.

[0100] In the first direction DR1, the width of each of the bending area BA and the second base area AA2 may be smaller than the width of the first base area AA1. Since the bending area BA has a width smaller than the width of the first base area AA1 in a direction parallel to the bending axis, the bending area BA may be easily bendable. However, this is shown exemplarily, and in the first direction DR1, at least one of the width of the bending area BA or the width of the second base area AA2 may be the same as the width of the first base area AA1, and the width is not necessarily limited to any one embodiment of the inventive concept.

[0101] Due to the bending of the bending area BA, the second base area AA2 may be an area positioned below the first base area AA1 and provided as a flat surface. The second base area AA2 may be an area in which the data driver DDV and signal lines extending toward the display pad D-PD through the bending area BA among the signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL are disposed.

[0102] The area in which the display pad D-PD is set and the area in which the sensing pad I-PD is set (see Figure 5 ) area (to be described later) can be respectively distinguished into a display pad area PD-A and a sensing pad area IPD-A. Figure 4 The display pad region PD-A is exemplarily shown to be separated from the sensing pad region IPD-A in the first direction DR1. For example, the sensing pad region IPD-A may be provided to be adjacent to both sides of the second base region AA2 in the first direction DR1, and the display pad region PD-A may be provided to the center portion. However, the embodiments of the inventive concept are not necessarily limited thereto, and the arrangement positions of the display pads D-PD and the sensing pads I-PD (see Figure 5 )'s arrangement position can be changed variously.

[0103] Flexible circuit board FCB (see Figure 2 ) can be set in which the display pad D-PD and the sensing pad I-PD are set (see Figure 5) in the second base region AA2 and is thus electrically connected to the display pad D-PD and the sensing pad I-PD (see Figure 5 According to the bending operation of the bending area BA, the flexible circuit board FCB (see Figure 2 ) can be positioned on the rear surface of the display panel DP. Figure 2 ) is located in the electronic equipment EA (see Figure 2 ) below the first base area AA1 at the front surface, so that the electronic device EA (see Figure 2 )’s border area.

[0104] The pixels PX may each include a pixel driving circuit composed of a transistor (e.g., a switching transistor, a driving transistor, etc.) and at least one capacitor, and a light emitting element electrically connected to the pixel driving circuit. The pixel PX may generate light in response to an electrical signal applied to each of the plurality of pixels PX, and display an image through the display area DA. According to an embodiment, some of the plurality of pixels PX may include a transistor disposed in the non-display area NDA, and the pixel PX is not necessarily limited to any embodiment of the inventive concept.

[0105] The scan driver SDV and the emission driver EDV may be disposed in the non-display area NDA corresponding to the first base area AA1. The data driver DDV may be disposed in the non-display area NDA corresponding to the second base area AA2. In an embodiment, the data driver DDV may be provided as an integrated circuit chip mounted in the non-display area NDA of the display panel DP. However, embodiments of the inventive concept are not necessarily limited thereto, and the data driver DDV may also be mounted on a flexible circuit board FCB (see Figure 2 )superior.

[0106] The signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2 and PL may include scan lines SL1 to SLm, data lines DL1 to DLn, emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, and a power line PL. Here, m and n are positive integers.

[0107] The data lines DL1 to DLn may cross the scan lines SL1 to SLm and the emission lines EL1 to ELm while being insulated from the scan lines SL1 to SLm and the emission lines EL1 to ELm. For example, the scan lines SL1 to SLm may extend in a first direction DR1 to be electrically connected to a scan driver SDV. The data lines DL1 to DLn may extend in a second direction DR2 to be electrically connected to a data driver DDV. The emission lines EL1 to ELm may extend in a first direction DR1 to be electrically connected to an emission driver EDV.

[0108] The power line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion of the power line PL extending in the first direction DR1 and the portion extending in the second direction DR2 may be disposed on different layers, or integrally disposed on the same layer. The portion of the power line PL extending in the first direction DR1 may be electrically connected to the pixel PX and the portion of the power line PL extending in the second direction DR2. The portion of the power line PL extending in the second direction DR2 may be disposed in the non-display area NDA, and thus electrically connected to the display pad D-PD from the first base area AA1 via the bending area BA and the second base area AA2. The power line PL may provide a first voltage to the pixel PX.

[0109] The first control line CSL1 may be electrically connected to the scan driver SDV and extend toward the lower end of the second base area AA2 via the bending area BA. The second control line CSL2 may be electrically connected to the emission driver EDV and extend toward the lower end of the second base area AA2 via the bending area BA.

[0110] The display pad D-PD may be disposed adjacent to the lower end of the second base area AA2. In the second base area AA2, the display pad D-PD may be disposed closer to the lower end of the base substrate BS than the data driver DDV. A plurality of display pads D-PD may be spaced apart from each other in the first direction DR1. The power line PL, the first control line CSL1, and the second control line CSL2 may each be electrically connected to a corresponding display pad D-PD among the plurality of display pads D-PD. The data lines DL1 to DLn may each be electrically connected to a corresponding display pad D-PD among the plurality of display pads D-PD through the data driver DDV.

[0111] The display pad D-PD can be electrically connected to the flexible circuit board FCB through the anisotropic conductive adhesive layer (see Figure 2 ) and from the flexible printed circuit board FCB (see Figure 2 ) can be transmitted to the display panel DP through the display pad D-PD. However, the connection between the display pad D-PD and the flexible circuit board FCB (see Figure 2) is not necessarily limited to this.

[0112] The scan driver SDV may generate a scan signal in response to a scan control signal. The scan signal may be applied to the pixel PX through the scan lines SL1 to SLm. The data driver DDV may generate a data voltage corresponding to the image signal in response to the data control signal. The data voltage may be applied to the pixel PX through the data lines DL1 to DLn. The emission driver EDV may generate an emission signal in response to an emission control signal. The emission signal may be applied to the pixel PX through the emission lines EL1 to ELm.

[0113] The pixel PX may receive a data voltage in response to a scan signal. In response to an emission signal, the pixel PX may emit light of brightness corresponding to the data voltage, thereby generating an image. The emission time of the pixel PX may be controlled by the emission signal.

[0114] Figure 5 ISP is a plan view of an input sensor ISP according to an embodiment of the present invention. For ease of description, Figure 5 The components of the input sensor ISP arranged on the previously described base substrate BS are schematically shown.

[0115] In an embodiment, the input sensor ISP may operate in a mutual capacitance type. Figure 5 , the input sensor ISP may include a first sensing electrode TEX (first sensing electrodes TEX1 to TEX6), a second sensing electrode TEY (second sensing electrodes TEY1 to TEY4), a first sensing line TLX1 to TLX6, a second sensing line TLY1 to TLY4, and a sensing pad I-PD. However, embodiments of the inventive concept are not necessarily limited thereto, and the input sensor ISP may operate in a self-capacitance type.

[0116] The plurality of first sensing electrodes TEX may each extend along the first direction DR1 , and the first sensing electrodes TEX may be arranged along the second direction DR2 . Figure 5 Six first sensing electrodes TEX1 to TEX6 are exemplarily shown. However, the number of first sensing electrodes TEX included in the input sensor ISP is not necessarily limited thereto. One first sensing electrode TEX may include first sensing patterns SP1 arranged along the first direction DR1 and first connection patterns BP1 connecting the first sensing patterns SP1.

[0117] The plurality of second sensing electrodes TEY may each extend along the second direction DR2 , and the second sensing electrodes TEY may be arranged along the first direction DR1 . Figure 5Four second sensing electrodes TEY1 to TEY4 are exemplarily shown. However, the number of second sensing electrodes TEY included in the input sensor ISP is not necessarily limited thereto. One second sensing electrode TEY may include second sensing patterns SP2 arranged along the second direction DR2 and second connection patterns BP2 connecting the second sensing patterns SP2.

[0118] The first sensing electrode TEX and the second sensing electrode TEY may be electrically insulated from each other. The input sensor ISP may detect an external input TC (see Figure 1 ). The first sensing electrode TEX and the second sensing electrode TEY may be disposed in a region corresponding to the display region DA of the base substrate BS. Figure 1 ) can display an image through the display area DA and at the same time can detect an external input TC applied to the display area DA.

[0119] The first sensing lines TLX1 to TLX6 may be disposed in the non-display area NDA to be electrically connected to the first sensing electrodes TEX1 to TEX6, respectively. Some of the first sensing lines TLX1 to TLX6 may be disposed on the left side of the non-display area NDA, and other of the first sensing lines TLX1 to TLX6 may be disposed on the right side of the non-display area NDA. For example, the first sensing lines TLX1, TLX3, and TLX5 respectively connected to the first sensing electrodes TEX1, TEX3, and TEX5 disposed in odd rows may be respectively connected to the left side of the first sensing electrodes TEX1, TEX3, and TEX5, and the first sensing lines TLX2, TLX4, and TLX6 respectively connected to the first sensing electrodes TEX2, TEX4, and TEX6 disposed in even rows may be respectively connected to the right side of the first sensing electrodes TEX2, TEX4, and TEX6. However, the arrangement of the first sensing lines TLX1 to TLX6 is not necessarily limited thereto, and each of the first sensing lines TLX1 to TLX6 may be disposed on the left side of the non-display area NDA, or all of the first sensing lines TLX1 to TLX6 may be disposed on the right side of the non-display area NDA.

[0120] The first sensing lines TLX1 to TLX6 may each extend from the first base area AA1 toward the second base area AA2 via the bending area BA. The first sensing lines TLX1 to TLX6 may be electrically connected to sensing pads I-PD disposed in the second base area AA2, respectively.

[0121] The second sensing lines TLY1 to TLY4 may be disposed in the non-display area NDA to be electrically connected to the second sensing electrodes TEY1 to TEY4, respectively. Some of the second sensing lines TLY1 to TLY4 may be disposed adjacent to the left side of the non-display area NDA, and the other of the second sensing lines TLY1 to TLY4 may be disposed adjacent to the right side of the non-display area NDA. For example, the second sensing lines TLY1 and TLY2 electrically connected to the second sensing electrodes TEY1 and TEY2 disposed on the left side in the first direction DR1 among the second sensing electrodes TEY1 to TEY4, respectively, may be disposed adjacent to the left side of the first base area AA1, and the second sensing lines TLY3 and TLY4 electrically connected to the second sensing electrodes TEY3 and TEY4 disposed on the right side in the first direction DR1 among the second sensing electrodes TEY1 to TEY4, respectively, may be disposed adjacent to the right side of the first base area AA1. However, the arrangement of the second sensing lines TLY1 to TLY4 is not necessarily limited thereto.

[0122] The second sensing lines TLY1 to TLY4 may each extend from an area adjacent to a lower end of the first base area AA1 toward the second base area AA2 via the bending area BA. The second sensing lines TLY1 to TLY4 may be electrically connected to a plurality of sensing pads I-PD disposed in the second base area AA2, respectively.

[0123] Some of the plurality of sensing pads I-PD may be disposed in an area adjacent to the left side of the second base area AA2 in the first direction DR1, and other of the plurality of sensing pads I-PD may be disposed in an area adjacent to the right side of the second base area AA2. For example, the sensing pads I-PD may be divided into two groups spaced apart from each other, and the display pad area PD-A is interposed between the two groups. However, the arrangement of the sensing pads I-PD is not necessarily limited thereto.

[0124] The sensing pad I-PD may be arranged on top of the display pad D-PD (see Figure 4 ). The sensing pad I-PD may be disposed on a layer different from the layer on which the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 are disposed, and connected to the layer through a contact hole. However, embodiments of the inventive concept are not necessarily limited thereto, and the sensing pad I-PD may be disposed on the layer on which the display pad D-PD (see Figure 4 For example, the plurality of sensing pads I-PD may be integrally formed on the same layer as the layer on which the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 are disposed.

[0125] The first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 may be disposed on the display panel DP (see Figure 4 ) above the components in the area corresponding to the non-display area NDA of the base substrate BS. Therefore, the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 may be connected to the display panel DP (see Figure 4 )'s components in the bending area BA and the second base area AA2 overlap.

[0126] Figure 6 is a perspective view of an electronic device EA according to an embodiment of the inventive concept. Figure 6 The arrangement of some components of the electronic device EA corresponding to the second base area AA2 is schematically shown.

[0127] The second base area AA2 corresponds to the non-display area NDA (see Figure 4 ) part of the area. Figure 6 As shown in FIG, the non-display area NDA (see Figure 4 ) or an area of ​​the second base area AA2 bonded to the data driver DDV may be defined as a first pad area PA1, and a non-display area NDA (see Figure 4 ) or the area of ​​the second base area AA2 bonded with the flexible circuit board FCB may be defined as a second pad area PA2. The first signal pads PD1 and PD2 may be disposed in the first pad area PA1. The display pad D-PD may be disposed in the second pad area PA2.

[0128] The data driver DDV may be bonded to the first pad area PA1 through the first conductive adhesive layer CF1, and the flexible circuit board FCB may be bonded to the second pad area PA2 through the second conductive adhesive layer CF2. The first conductive adhesive layer CF1 and the second conductive adhesive layer CF2 may each be provided as an anisotropic conductive adhesive. For example, the first conductive adhesive layer CF1 and the second conductive adhesive layer CF2 may each include an adhesive resin and conductive particles dispersed in the adhesive resin.

[0129] However, embodiments of the inventive concept are not necessarily limited thereto, and in embodiments, the first conductive adhesive layer CF1 and / or the second conductive adhesive layer CF2 may be omitted. For example, the data driver DDV and the flexible circuit board FCB may be bonded to the first pad area PA1 and the second pad area PA2, respectively, by ultrasonic bonding.

[0130] The display panel DP may include a plurality of pads PD. The plurality of pads PD may include first signal pads PD1 and PD2 and a display pad D-PD (or a second signal pad). The first signal pads PD1 and PD2 and the display pad D-PD (or a second signal pad) may be pads each disposed on a transmission path of a signal.

[0131] The first signal pads PD1 and PD2 may include a 1-1st signal pad PD1 and a 1-2nd signal pad PD2. The 1-1st signal pad PD1 may be an input pad provided corresponding to an output bump of the data driver DDV, and receive a signal from the data driver DDV. The 1-2nd signal pad PD2 may be an output pad provided corresponding to an input bump of the data driver DDV, and output a signal to the data driver DDV. The display pad D-PD may be a panel input pad that receives a signal from the flexible circuit board FCB.

[0132] The plurality of 1-1 signal pads PD1 may be electrically connected to the pixels PX of the display panel DP through a plurality of signal lines, respectively (see Figure 4 ), and to the pixel PX (see Figure 4 ) sends signals to / from pixel PX (see Figure 4 ) receives a signal. The plurality of 1st-2nd signal pads PD2 may each be electrically connected to a corresponding display pad D-PD among the plurality of display pads D-PD through a signal line, and the display pad D-PD and the 1st-2nd signal pad PD2 electrically connected to each other may transmit and receive a signal therebetween.

[0133] The first pad area PA1 may include a first sub-pad area PA1-1 and a second sub-pad area PA1-2. The first sub-pad area PA1-1 may be defined as an area in which the 1-1th signal pad PD1 is disposed. The second sub-pad area PA1-2 may be defined as an area in which the 1-2nd signal pad PD2 is disposed.

[0134] 1-1th signal pads PD1 may be arranged in the first and second directions DR1 and DR2 in the first sub pad area PA1-1. Among the plurality of 1-1th signal pads PD1, 1-1th signal pads PD1 arranged in the first direction DR1 may be defined as a pad row. Figure 6 Five pad rows arranged along the second direction DR2 are exemplarily shown. The arrangement of the 1-1th signal pad PD1 is not necessarily limited to any one embodiment of the inventive concept as long as at least two pad rows are arranged along the second direction DR2.

[0135] The first residual conductive pattern YMR1 may include a 1-1th residual conductive pattern YMR1-1 and a 1-2th residual conductive pattern YMR1-2. The first residual conductive pattern YMR1 may at least partially surround the first sub-pad area PA1-1 and the second sub-pad area PA1-2. In a plan view, the first residual conductive pattern YMR1 may be spaced apart from the 1-1th signal pad PD1. In a plan view, the first residual conductive pattern YMR1 may be spaced apart from the 1-2th signal pad PD2.

[0136] The 1-1st residual conductive pattern YMR1-1 may at least partially surround the first sub-pad area PA1-1. The 1-1st residual conductive pattern YMR1-1 may include a first portion extending along the first direction DR1 and a second portion extending along the second direction DR2. The 1-1st residual conductive pattern YMR1-1 may be defined as a quadrilateral shape having the first portion and the second portion. The 1-1st signal pad PD1 may be disposed inside the 1-1st residual conductive pattern YMR1-1. Figure 6 The 1-1th residual conductive pattern YMR1-1 is shown as a quadrilateral shape, but this is an example and the shape of the 1-1th residual conductive pattern YMR1-1 may be changed as needed. For example, the 1-1th residual conductive pattern YMR1-1 may have a closed curve shape surrounding the first sub-pad area PA1-1 or other polygonal shapes.

[0137] The 1-2nd residual conductive pattern YMR1-2 may at least partially surround the second sub-pad area PA1-2. The 1-2nd residual conductive pattern YMR1-2 may include a first portion extending along the first direction DR1 and a second portion extending along the second direction DR2. The 1-2nd residual conductive pattern YMR1-2 may be defined as a quadrilateral shape having a first portion and a second portion. The 1-2nd signal pad PD2 may be disposed inside the 1-2nd residual conductive pattern YMR1-2. Figure 6 The 1-2nd residual conductive pattern YMR1-2 is shown as a quadrilateral shape, but this is an example and the shape of the 1-2nd residual conductive pattern YMR1-2 may be changed as needed. For example, the 1-2nd residual conductive pattern YMR1-2 may have a closed curve shape surrounding the second sub-pad area PA1-2 or other polygonal shapes.

[0138] The second residual conductive pattern YMR2 may at least partially surround the second pad area PA2. The second residual conductive pattern YMR2 may include a first portion extending along the first direction DR1 and a second portion extending along the second direction DR2. The second residual conductive pattern YMR2 may be defined as a quadrilateral shape having a first portion and a second portion. The display pad D-PD may be disposed inside the second residual conductive pattern YMR2. Figure 6The second residual conductive pattern YMR2 is shown as a quadrilateral shape, but this is an example and the shape of the second residual conductive pattern YMR2 may be changed as needed. For example, the second residual conductive pattern YMR2 may have a closed curve shape surrounding the second pad area PA2 or other polygonal shapes.

[0139] The 1-2 th signal pads PD2 may be arranged in the second sub-pad area PA1-2 along the first direction DR1. The 1-2 th signal pads PD2 may be provided as one pad row. However, the arrangement of the 1-2 th signal pads PD2 is not necessarily limited thereto.

[0140] Figure 7 is a cross-sectional view of a display module DM according to an embodiment of the present invention. More particularly, according to an embodiment of the present invention, Figure 7 The pixel PX disposed in the first matrix area AA1 is exemplarily shown (see Figure 4 ) and a cross section of the first signal pads PD1 and PD2 disposed in the second base area AA2.

[0141] refer to Figure 7 , the display module DM may include a display panel DP and an input sensor ISP disposed on the display panel DP. The foregoing description may be equally applicable to each of the plurality of components.

[0142] refer to Figure 7 , the display panel DP may include a base substrate BS, a circuit layer DP-CL, a display element layer DP-OL and an encapsulation layer ECL.

[0143] The base substrate BS may be insulating and may provide a base surface on which components of the display module DM are disposed. The base substrate BS may be flexible so as to be bendable. As previously described, the base substrate BS may include a first base area AA1, a bending area BA (see Figure 4 ) and the second base area AA2, and the bending area BA of the base substrate BS (see Figure 4 ) can be bent with a predetermined curvature.

[0144] The circuit layer DP-CL may include insulating layers 10 to 60 disposed on the base substrate BS, pixels PX (see Figure 4 ) of the transistor TR, the upper electrode UE, and the connecting electrodes CN1 and CN2. The insulating layers 10 to 60 may include first to sixth insulating layers 10 to 60 sequentially stacked on the base substrate BS along the thickness direction. However, embodiments of the insulating layers 10 to 60 included in the circuit layer DP-CL are not necessarily limited thereto and may be changed according to the configuration or manufacturing process of the circuit layer DP-CL.

[0145] The first insulating layer 10 may be disposed on the base substrate BS. The first insulating layer 10 may be provided as a barrier layer and / or a buffer layer to prevent foreign matter from being introduced from the outside. The first insulating layer 10 may increase the coupling force between the base substrate BS and the semiconductor pattern SM and / or the conductive pattern of the circuit layer DP-CL. The first insulating layer 10 may include a silicon oxide layer and / or a silicon nitride layer. In an embodiment, the first insulating layer 10 may include an alternately stacked silicon oxide layer and a silicon nitride layer.

[0146] Pixel PX (see Figure 4 ) may be disposed on a base substrate BS. Figure 4 ) can be arranged corresponding to the display area DA of the first base area AA1. Figure 4 ) may include a transistor TR and a light emitting element OL.

[0147] The transistor TR may include a semiconductor pattern SM and a gate electrode GE. The semiconductor pattern SM may be disposed on the first insulating layer 10. The semiconductor pattern SM may include a channel S1, a source S2, and a drain S3. The semiconductor pattern SM may include a silicon semiconductor including a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, or an amorphous silicon semiconductor. The embodiments of the present inventive concept are not necessarily limited thereto, and the semiconductor pattern SM may also include an oxide semiconductor. According to the embodiments of the present inventive concept, the semiconductor pattern SM may be formed of various materials as long as it has semiconductor characteristics, and is not necessarily limited to any one embodiment of the present inventive concept.

[0148] The semiconductor pattern SM may include a plurality of regions having different electrical characteristics depending on whether it is doped or reduced. For example, the semiconductor pattern SM may include a region that is doped or in which a metal oxide is reduced, and thus the region has high conductivity, and the region having high conductivity may be used as an electrode or signal line of the transistor TR. This may correspond to the source S2 and drain S3 of the transistor TR. The semiconductor pattern SM may include an undoped region, and thus has relatively low conductivity, and this may correspond to the channel S1 (or active portion) of the transistor TR.

[0149] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the semiconductor pattern SM. The gate electrode GE may be disposed on the second insulating layer 20. The second insulating layer 20 may be disposed between the semiconductor pattern SM of the transistor TR and the gate electrode GE. In a plan view, the gate electrode GE may overlap the channel S1 of the semiconductor pattern SM. The gate electrode GE may be used as a mask in a doping process of the semiconductor pattern SM. The gate electrode GE may include molybdenum (Mo) having heat resistance, an alloy including molybdenum, titanium (Ti), an alloy including titanium, etc., but embodiments of the inventive concept are not necessarily limited thereto.

[0150] Figure 7 The structure of the transistor TR shown in is an example, and the source S2 or drain S3 of the transistor TR may also be an electrode formed independently of the semiconductor pattern SM. In this case, the source S2 and the drain S3 may be in contact with the semiconductor pattern SM, or pass through the insulating layer to be connected to the semiconductor pattern SM. In addition, the gate electrode GE may be disposed under the semiconductor pattern SM. According to an embodiment of the inventive concept, the transistor TR may be formed in various structures and is not necessarily limited to any one embodiment of the inventive concept.

[0151] The second insulating layer 20 and the third insulating layer 30 to the sixth insulating layer 60 to be described later may include at least one of an inorganic layer and an organic layer. For example, the inorganic layer may include aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide and / or hafnium oxide. The organic layer may include an acrylate resin, a methacrylate resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin and / or a perylene resin.

[0152] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the gate electrode GE. The upper electrode UE may be disposed on the third insulating layer 30. The upper electrode UE may overlap the gate electrode GE in a plan view, and the gate electrode GE and the upper electrode UE overlapping each other may form a capacitor.

[0153] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and may cover the upper electrode UE. The connection electrodes CN1 and CN2 may include a first connection electrode CN1 and a second connection electrode CN2. The first connection electrode CN1 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the first connection electrode CN1. The second connection electrode CN2 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second connection electrode CN2. In an embodiment, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 may include an organic layer and may cover a step between components disposed thereunder to provide a flat upper surface.

[0154] The first connection electrode CN1 may be electrically connected to the semiconductor pattern SM through a contact hole passing through the second to fourth insulating layers 20 to 40. The second connection electrode CN2 may be electrically connected to the first connection electrode CN1 through a contact hole passing through the fifth insulating layer 50.

[0155] The first connection electrode CN1 and the second connection electrode CN2 may each include a conductive material. The first connection electrode CN1 and the second connection electrode CN2 may each include gold, silver, copper, aluminum, platinum, molybdenum, titanium and / or an alloy thereof. At least one of the first connection electrode CN1 and the second connection electrode CN2 may include a conductive layer in a multilayer structure. For example, at least one of the first connection electrode CN1 and the second connection electrode CN2 may have a three-layer structure of titanium / aluminum / titanium. However, embodiments of the inventive concept are not necessarily limited thereto.

[0156] According to an embodiment of the circuit layer DP-CL, at least one of the first connection electrode CN1 and the second connection electrode CN2 may be omitted. Alternatively, according to an embodiment of the circuit layer DP-CL, an additional connection electrode that connects the transistor TR to the light emitting element OL may also be provided. Depending on the number of insulating layers provided between the light emitting element OL and the transistor TR, the type of electrical connection between the light emitting element OL and the transistor TR may be variously changed, and is not necessarily limited to any one embodiment of the inventive concept.

[0157] The display element layer DP-OL may include a light emitting element OL and a pixel defining layer PDL. The light emitting element OL and the pixel defining layer PDL may be disposed on the sixth insulating layer 60. The light emitting element OL may include a first electrode AE, a light emitting layer EM, and a second electrode CE.

[0158] The first electrode AE ​​may be electrically connected to the second connection electrode CN2 through a contact hole passing through the sixth insulating layer 60. The first electrode AE ​​may be electrically connected to the transistor TR through the first connection electrode CN1 and the second connection electrode CN2.

[0159] A pixel opening PX-OP exposing at least a portion of the first electrode AE ​​may be defined in the pixel defining film PDL. An area of ​​the first electrode AE ​​exposed from the pixel defining film PDL may correspond to a light emitting area. The pixel defining film PDL may include an inorganic layer, an organic layer, or a composite material layer. According to an embodiment, the pixel defining film PDL may further include a black pigment or a black dye.

[0160] The light-emitting layer EM may be disposed on the first electrode AE. The light-emitting layer EM may provide light of a predetermined color. The light-emitting layer EM may be disposed corresponding to the pixel opening PX-OP defined in the pixel definition film PDL. The light-emitting element OL and the pixel opening PX-OP may be provided in plurality, and the plurality of light-emitting layers EM of the plurality of light-emitting elements OL may be disposed respectively corresponding to the plurality of pixel openings PX-OP, and provided in the form of a plurality of patterns spaced apart from each other. However, the embodiments of the present inventive concept are not necessarily limited thereto, and the plurality of light-emitting layers EM of the plurality of light-emitting elements OL may also be integrally formed as a common layer.

[0161] The second electrode CE may be disposed on the light emitting layer EM and the pixel defining film PDL. The second electrode CE may be provided to commonly cross the pixels PX (see Figure 4 ) is a common electrode set.

[0162] The light emitting element OL may further include a hole control region disposed between the first electrode AE ​​and the light emitting layer EM and / or an electron control region disposed between the light emitting layer EM and the second electrode CE. The hole control region may include a hole generation layer, a hole transport layer and / or an electron blocking layer, and the electron control region may include an electron generation layer, an electron transport layer and / or a hole blocking layer.

[0163] The encapsulation layer ECL may be disposed on the display element layer DP-OL. The encapsulation layer ECL may be disposed on the light emitting element OL and the pixel defining film PDL, and thus may seal the light emitting element OL. The encapsulation layer ECL may include an inorganic film and / or an organic film. In the present embodiment, the encapsulation layer ECL may include a first inorganic film EN1, a second inorganic film EN3, and an organic film EN2 disposed between the first inorganic film EN1 and the second inorganic film EN3. However, the composition of the encapsulation layer ECL is not necessarily limited thereto, as long as the encapsulation layer ECL can seal the light emitting element OL.

[0164] The first inorganic film EN1 may be disposed on the second electrode CE, and the organic film EN2 and the second inorganic film EN3 may be sequentially disposed on the first inorganic film EN1 in the thickness direction of the display panel DP. The first inorganic film EN1 and the second inorganic film EN3 may protect the light emitting element OL from moisture or oxygen introduced from the outside. For example, the first inorganic film EN1 and the second inorganic film EN3 may each include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide and / or aluminum oxide. However, the materials of the first inorganic film EN1 and the second inorganic film EN3 are not necessarily limited to these examples. The organic film EN2 may prevent foreign matter from being introduced into the light emitting element OL, and cover the steps of the components disposed below the organic film EN2. For example, the organic film EN2 may include an acrylic organic material. However, the material of the organic film EN2 is not necessarily limited to the examples.

[0165] The input sensor ISP may be disposed on the display panel DP. The input sensor ISP may include a base layer IL1, a first sensing insulating layer IL2, a first sensing conductive layer CL1, and a second sensing conductive layer CL2. The input sensor ISP may further include a second sensing insulating layer IL3 (see Figure 3 ). The preceding description may be equally applicable to each of the multiple components.

[0166] The base layer IL1 may be in contact with the uppermost layer of the encapsulation layer ECL. For example, the base layer IL1 may be in contact with the second inorganic film EN3 of the encapsulation layer ECL. The base layer IL1 of the input sensor ISP may be formed directly on a base surface provided by the encapsulation layer ECL. However, embodiments of the inventive concept are not necessarily limited thereto. According to an embodiment, the base layer IL1 may be omitted, and in this case, the first sensing conductive layer CL1 of the input sensor ISP may be in contact with the encapsulation layer ECL.

[0167] The first sensing conductive layer CL1 may be disposed on the base layer IL1, and the second sensing conductive layer CL2 may be disposed on the first sensing insulating layer IL2. The first sensing conductive layer CL1 and the second sensing conductive layer CL2 may form a sensing electrode TE. The sensing electrode TE may correspond to the first sensing electrode TEX described previously (see Figure 5 ) and the second sensing electrode TEY (see Figure 5 ). For example, the first sensing conductive layer CL1 may include the connection pattern BP of the sensing electrode TE, and the second sensing conductive layer CL2 may include the sensing pattern SP of the sensing electrode TE. However, embodiments of the inventive concept are not necessarily limited thereto, and the first sensing conductive layer CL1 may include the sensing pattern SP, and the second sensing conductive layer CL2 may include the connection pattern BP.

[0168] The connection pattern BP may correspond to the first connection pattern BP1 described previously (see Figure 5 ) or the second connection pattern BP2 (see Figure 5 ), and the sensing pattern SP may correspond to the first sensing pattern SP1 described previously (see Figure 5 ) or the second sensing pattern SP2 (see Figure 5 ). The connection pattern BP may be disposed on a layer different from the layer on which the sensing pattern SP is disposed, and thus may be connected to the sensing pattern SP through a contact hole passing through the first sensing insulating layer IL2. However, embodiments of the inventive concept are not necessarily limited thereto, and the connection pattern BP and the sensing pattern SP may be disposed on the same layer to be integrally formed.

[0169] The sensing electrode TE may have a pattern in the form of a grid and may be disposed corresponding to an area in which the pixel definition film PDL is disposed. However, embodiments of the present inventive concept are not necessarily limited thereto, and the sensing electrode TE may be provided as a single pattern overlapping the light emitting element OL, and in this case, the sensing electrode TE may include a transparent conductive material.

[0170] The first insulating layer 10 and the second insulating layer 20 may extend from the first base area AA1 on the base substrate BS to be disposed in the second base area AA2. The 1-1st signal pad PD1 and the 1-2nd signal pad PD2 may be disposed on the second insulating layer 20. The 1-1st signal pad PD1 may be disposed in the first sub-pad area PA1-1, and the 1-2nd signal pad PD2 may be disposed in the second sub-pad area PA1-2. The 1-1st signal pad PD1 may be disposed closer to the display area DA in the first base area AA1 than the 1-2nd signal pad PD2.

[0171] The first signal pads PD1 and PD2 may each include a plurality of conductive patterns CP1, CP2, CP3, and CP4 disposed along the thickness direction. The first conductive pattern CP1 (or the 1-1 conductive pattern) of the 1-1st signal pad PD1 and the first conductive pattern CP1 (or the 1-1 conductive pattern) of the 1-2nd signal pad PD2 may be disposed on the second insulating layer 20.

[0172] The first conductive pattern CP1 of the 1-1 signal pad PD1 and the first conductive pattern CP1 of the 1-2 signal pad PD2 may be formed by the same process as the process by which the gate electrode GE of the transistor TR is formed, and may include the same material as the gate electrode GE. For example, after a conductive layer is formed on the second insulating layer 20 by a deposition process such as sputtering or chemical vapor deposition, the conductive layer may be patterned to form the gate electrode GE and the first conductive pattern CP1 of the first signal pads PD1 and PD2. The first conductive pattern CP1 of the first signal pads PD1 and PD2 may be disposed on the same layer on which the gate electrode GE of the transistor TR is disposed, and thus may include the same material as the gate electrode GE.

[0173] The third insulating layer 30 and the fourth insulating layer 40 may extend from the first base area AA1 to be disposed in the second base area AA2. A through hole exposing the upper surface of each of the first conductive pattern CP1 of the 1-1st signal pad PD1 and the first conductive pattern CP1 of the 1-2nd signal pad PD2 may be defined in the third insulating layer 30 and the fourth insulating layer 40. The third insulating layer 30 and the fourth insulating layer 40 may be formed by sequentially depositing into the first base area AA1 and the second base area AA2 and then being etched so that a portion of each of the upper surfaces of the first conductive patterns CP1 of the first signal pads PD1 and PD2 is exposed.

[0174] like Figure 7As shown in the figure, at least some of the plurality of insulating layers disposed in the first base area AA1 may be disposed in the second base area AA2, and the stacking structure of the insulating layers disposed in the second base area AA2 is not particularly limited to that shown in the drawing.

[0175] The second conductive pattern CP2 (or the 1-2 conductive pattern) of the 1-1 signal pad PD1 and the second conductive pattern CP2 (or the 1-2 conductive pattern) of the 1-2 signal pad PD2 may be respectively disposed on the exposed upper surface of the first conductive pattern CP1. The plurality of second conductive patterns CP2 may be in contact with the plurality of first conductive patterns CP1, respectively. A portion of each of the plurality of second conductive patterns CP2 may be disposed on the fourth insulating layer 40. For example, the portion of each of the plurality of second conductive patterns CP2 may be disposed on the fourth insulating layer 40 while covering the inner side surfaces of the third insulating layer 30 and the fourth insulating layer 40 exposed by the through hole.

[0176] The second conductive pattern CP2 of the 1-1 signal pad PD1 and the second conductive pattern CP2 of the 1-2 signal pad PD2 may be formed by the same process as the process by which at least one of the plurality of conductive electrodes in the circuit layer DP-CL is formed. For example, the second conductive pattern CP2 of the 1-1 signal pad PD1 and the second conductive pattern CP2 of the 1-2 signal pad PD2 may be formed by the same process as the process by which the first connection electrode CN1 is formed, and may include the same material as the material of the first connection electrode CN1. After a conductive layer is formed on the fourth insulating layer 40 by a deposition process such as sputtering or chemical vapor deposition, the conductive layer may be patterned to form the first connection electrode CN1 and the second conductive pattern CP2 of the first signal pads PD1 and PD2. The second conductive pattern CP2 of the first signal pads PD1 and PD2 may be disposed on the same layer on which the first connection electrode CN1 is disposed, and may include the same material as the material of the first connection electrode CN1.

[0177] The third conductive pattern CP3 (or the 1-3 conductive pattern) of the 1-1 signal pad PD1 and the third conductive pattern CP3 (or the 1-3 conductive pattern) of the 1-2 signal pad PD2 can be respectively arranged on the plurality of second conductive patterns CP2. The plurality of third conductive patterns CP3 can be in contact with the plurality of second conductive patterns CP2, respectively. The third conductive pattern CP3 of the 1-1 signal pad PD1 and the third conductive pattern CP3 of the 1-2 signal pad PD2 can be formed by the same process as the process by which at least one of the plurality of conductive electrodes in the circuit layer DP-CL is formed. For example, the third conductive pattern CP3 of the 1-1 signal pad PD1 and the third conductive pattern CP3 of the 1-2 signal pad PD2 can be formed by the same process as the process by which the second connection electrode CN2 is formed, and can include the same material as the material of the second connection electrode CN2. The fifth insulating layer 50 disposed below the second connection electrode CN2 can be opened corresponding to the area where the first signal pads PD1 and PD2 are disposed. For example, the fifth insulating layer 50 may not be disposed on the second conductive pattern CP2 of the first signal pads PD1 and PD2, and a portion of the conductive layer deposited on the fifth insulating layer 50 may be in contact with the second conductive pattern CP2. After forming a conductive layer on the fifth insulating layer 50 by a deposition process such as sputtering or chemical vapor deposition, the conductive layer may be patterned to form the second connection electrode CN2 and the third conductive pattern CP3 of the first signal pads PD1 and PD2. The third conductive pattern CP3 may be disposed on the same layer on which the second connection electrode CN2 is disposed, and may include the same material as that of the second connection electrode CN2.

[0178] The fourth conductive pattern CP4 (or 1-4 conductive pattern) of the 1-1st signal pad PD1 and the fourth conductive pattern CP4 (or 1-4 conductive pattern) of the 1-2nd signal pad PD2 may be disposed on upper surfaces of the third conductive pattern CP3, respectively. The fourth conductive patterns CP4 may contact the third conductive patterns CP3, respectively.

[0179] The fourth conductive pattern CP4 of the 1-1 signal pad PD1 and the fourth conductive pattern CP4 of the 1-2 signal pad PD2 may be formed by the same process as the process by which at least one of the multiple conductive layers of the input sensor ISP is formed. For example, the fourth conductive pattern CP4 of the 1-1 signal pad PD1 and the fourth conductive pattern CP4 of the 1-2 signal pad PD2 may be formed by the same process as the process by which the second sensing conductive layer CL2 is formed, and may include the same material as the material of the second sensing conductive layer CL2. The fourth conductive pattern CP4 may include the same material as the first sensing conductive layer CL1 or the second sensing conductive layer CL2. The first conductive pattern CP1 to the fourth conductive pattern CP4 may be electrically connected.

[0180] Figure 8 is an enlarged plan view of a display module DM according to an embodiment of the inventive concept. More particularly, Figure 8 is an enlarged plan view of a first sub pad area PA1 - 1 according to an embodiment of the inventive concept.

[0181] refer to Figure 8 , a plurality of 1-1st signal pads PD1 may be provided in the first sub-pad region PA1-1. The first sub-pad region PA1-1 may include a 1-1st signal pad region PDA1 corresponding to the 1-1st signal pad PD1. The first sub-pad region PA1-1 may include a plurality of 1-1st signal pads PD1 corresponding to the 1-1st signal pads PD1 formed on the first sensing insulating layer IL2 (see Fig.9A ) in the opening OP-IL2 (see Fig.9A ). The 1-1 opening area OPA1-1 may overlap with the 1-1 signal pad area PDA1. Fig.9A The 1-1th opening area OPA1-1 is described.

[0182] The 1-1st signal pad PD1 may be provided in plurality inside the 1-1st residual conductive pattern YMR1-1. The 1-1st signal pad PD1 may include a plurality of pad rows, and the plurality of pad rows may be arranged along the second direction DR2. Here, the 1-1st signal pad PD1 is schematically illustrated as having a rectangular shape extending in the second direction DR2, but the shape of the 1-1st signal pad PD1 is not necessarily limited thereto.

[0183] The 1-1th signal pad PD1 may be electrically connected to the pixel PX through the 1-1th signal line SCL1-1 (see Figure 4 ). In a plan view, the 1-1th signal line SCL1-1 may cross the 1-1th residual conductive pattern YMR1-1 while being electrically insulated from the 1-1th residual conductive pattern YMR1-1.

[0184] The 1-1th residual conductive pattern YMR1-1 may be disposed on a boundary of the 1-1th opening area OPA1-1. In a plan view, the 1-1th residual conductive pattern YMR1-1 may be spaced apart from the 1-1th signal pad PD1 by a predetermined distance. In a plan view, the 1-1th residual conductive pattern YMR1-1 may not overlap with the 1-1th signal pad PD1.

[0185] The minimum distance between the 1-1st residual conductive pattern YMR1-1 and the 1-1st signal pad PD1 may be about 20 μm or more. When the minimum distance between the 1-1st residual conductive pattern YMR1-1 and the 1-1st signal pad PD1 is less than about 20 μm, a short circuit may occur between the 1-1st residual conductive pattern YMR1-1 and the 1-1st signal pad PD1.

[0186] A minimum distance TD1 between the 1-1th residual conductive pattern YMR1-1 and the 1-1th signal pad PD1 in the first direction DR1 may be about 20 μm or more. A minimum distance TD2 between the 1-1th residual conductive pattern YMR1-1 and the 1-1th signal pad PD1 in the second direction DR2 may be about 20 μm or more.

[0187] Fig.9A According to the embodiment of the present invention, Figure 8 A cross-sectional view taken along line II'.

[0188] refer to Fig.9A , a plurality of 1-1st signal pads PD1 may be arranged along the first direction DR1. Adjacent 1-1st signal pads PD1 may be spaced apart from each other by a predetermined distance, thereby preventing a short circuit between the plurality of 1-1st signal pads PD1. The 1-1st signal pad PD1 and the 1-1st residual conductive pattern YMR1-1 may be spaced apart from each other by a minimum distance TD1 along the first direction DR1. Therefore, a short circuit between the 1-1st residual conductive pattern YMR1-1 and the 1-1st signal pad PD1 may be prevented.

[0189] A first sub pad area PA1-1 (see FIG. 1 ) which is adjacent to the first sensing insulating layer IL2 in a plan view may be defined in the first sensing insulating layer IL2. Figure 8 ) is overlapped with the insulating opening OP-IL2 (or the first opening). The insulating opening OP-IL2 may completely overlap with the plurality of 1-1st signal pad areas PDA1 in a plan view. The inner side surface of the first sensing insulating layer IL2 defining the insulating opening OP-IL2 may be spaced apart from the 1-1st signal pad area PDA1 by a predetermined distance. The first sensing insulating layer IL2 may not contact the 1-1st signal pad PD1. The first sensing insulating layer IL2 may not overlap with the 1-1st signal pad PD1 in a plan view.

[0190] Since the first sensing insulating layer IL2 does not overlap the 1-1th signal pad PD1 in a plan view, a problem that may occur in the 1-1th signal pad PD1 due to the first sensing insulating layer IL2 may be solved.

[0191] For example, in the case where the first sensing insulating layer IL2 overlaps the 1-1 signal pad PD1 in a plan view, a portion of the first sensing insulating layer IL2 may overlap the 1-1 signal pad area PDA1 in a plan view, and the fourth conductive pattern CP4 may be disposed on the portion of the first sensing insulating layer IL2. At this time, in the case where the first sensing insulating layer IL2 is an organic film including an organic material, when pressure is applied to the first sensing insulating layer IL2, the first sensing insulating layer IL2 may be deformed. In the case where the data driver DDV (see Figure 6 ) and the 1-1 signal pad PD1, the first sensing insulating layer IL2 may be deformed by the pressure. Therefore, the fourth conductive pattern CP4 disposed on the first sensing insulating layer IL2 may be deformed, thereby causing cracks in the fourth conductive pattern CP4.

[0192] In addition, since the first sensing insulating layer IL2 includes an organic material with relatively high moisture permeability, moisture may be supplied to the conductive layer provided on the first sensing insulating layer IL2 for forming the fourth conductive pattern CP4. Therefore, a portion of the conductive layer may be oxidized. For the oxidized conductive layer, etching may not be performed smoothly in the etching process for forming the fourth conductive pattern CP4. Therefore, the fourth conductive pattern CP4 may not be formed correctly, and a short circuit may occur between adjacent 1-1 signal pads PD1 due to the unetched conductive layer. Since the first sensing insulating layer IL2 does not overlap with the 1-1 signal pad PD1 in a plan view, the above-mentioned problem can be solved.

[0193] An opening corresponding to the insulating opening OP-IL2 may also be defined in the base layer IL1. An end portion of the base layer IL1 and an end portion of the first sensing insulating layer IL2 may be formed at the same position in the first direction DR1.

[0194] including a second sensing conductive layer CL2 (see Figure 7 ) may be defined on the boundary of the insulating opening OP-IL2. The 1-1 residual conductive pattern YMR1-1 may include the same material as the material of the fourth conductive pattern CP4. The 1-1 residual conductive pattern YMR1-1 may be formed of the same conductive layer as the conductive layer forming the fourth conductive pattern CP4. For example, the 1-1 residual conductive pattern YMR1-1 may be a portion that remains unetched in the etching process of forming the fourth conductive pattern CP4 after forming the conductive layer.

[0195] Since the 1-1th residual conductive pattern YMR1-1 is spaced apart from the 1-1th signal pad PD1 by the minimum distance TD1, a short circuit caused by contact between the 1-1th residual conductive pattern YMR1-1 and the fourth conductive pattern CP4 of the 1-1th signal pad PD1 may be prevented.

[0196] Fig. 9B According to the embodiment of the present invention, Figure 8 A cross-sectional view taken along line II-II'.

[0197] refer to Fig. 9B , the 1-1 signal line SCL1-1 may be disposed on the same layer as the layer on which the first conductive pattern CP1 of the 1-1 signal pad PD1 is disposed, and include the same material as the material of the first conductive pattern CP1 of the 1-1 signal pad PD1. The 1-1 signal line SCL1-1 may be disposed on the same layer as the layer on which the gate electrode GE (see Figure 7 ) and includes the same material as that of the gate electrode GE. The 1-1 signal line SCL1-1 may overlap the 1-1 residual conductive pattern YMR1-1 in a plan view. The insulating layers 30 and 40 may be disposed between the 1-1 signal line SCL1-1 and the 1-1 residual conductive pattern YMR1-1. The insulating layers 30 and 40 disposed between the 1-1 signal line SCL1-1 and the 1-1 residual conductive pattern YMR1-1 may include the same material as that disposed in the transistor TR (see Figure 7 ) and the light emitting element OL (see Figure 7 ) are made of the same material as the third insulating layer 30 and the fourth insulating layer 40 therebetween. Therefore, the 1-1 signal line SCL1-1 and the 1-1 residual conductive pattern YMR1-1 crossing each other in a plan view can be prevented from being electrically connected.

[0198] The 1-1th residual conductive pattern YMR1-1 may be spaced apart from the 1-1th signal pad PD1 by a minimum distance TD2. Therefore, the 1-1th residual conductive pattern YMR1-1 and the 1-1th signal pad PD1 may be electrically insulated from each other.

[0199] Fig.10 is an enlarged plan view of a display module according to an embodiment of the inventive concept. More particularly, Fig.10 is an enlarged plan view of the second sub pad area PA1 - 2 according to an embodiment of the inventive concept.

[0200] refer to Fig.10, a plurality of 1st-2nd signal pads PD2 may be provided in the second sub-pad area PA1-2. The second sub-pad area PA1-2 may include a 1st-2nd signal pad area PDA2 corresponding to the 1st-2nd signal pads PD2. The second sub-pad area PA1-2 may include a plurality of 1st-2nd signal pads PD2 corresponding to the 1st-2nd signal pads PD2. Fig.11A ) in the opening OP-IL2 (see Fig.11A ) of the 1st-2 opening area OPA1-2. The 1st-2 opening area OPA1-2 may overlap with the 1st-2 signal pad area PDA2. Fig.11A Describe the 1st-2nd opening area OPA1-2.

[0201] A plurality of 1-2nd signal pads PD2 may be disposed inside the 1-2nd residual conductive pattern YMR1-2. The 1-2nd signal pads PD2 may be arranged in the first direction DR1. Here, the 1-2nd signal pads PD2 are schematically illustrated as having a rectangular shape extending in the second direction DR2, but the shape of the 1-2nd signal pads PD2 is not necessarily limited thereto.

[0202] The 1-2 signal pad PD2 may be electrically connected to the pixel PX through the 1-2 signal line SCL1-2 (see Figure 4 ) and the corresponding display pad D-PD (see Figure 6 ). In a plan view, the 1-2 th signal line SCL1-2 may cross the 1-2 th residual conductive pattern YMR1-2 while being electrically insulated from the 1-2 th residual conductive pattern YMR1-2.

[0203] The 1-2nd residual conductive pattern YMR1-2 may be disposed on a boundary of the 1-2nd opening area OPA1-2. In a plan view, the 1-2nd residual conductive pattern YMR1-2 may be spaced apart from the 1-2nd signal pad PD2 by a predetermined distance. In a plan view, the 1-2nd residual conductive pattern YMR1-2 may not overlap with the 1-2nd signal pad PD2.

[0204] The minimum distance between the 1-2nd residual conductive pattern YMR1-2 and the 1-2nd signal pad PD2 may be about 20 μm or more. When the minimum distance between the 1-2nd residual conductive pattern YMR1-2 and the 1-2nd signal pad PD2 is less than about 20 μm, a short circuit may occur between the 1-2nd residual conductive pattern YMR1-2 and the 1-2nd signal pad PD2.

[0205] A minimum distance TD3 between the 1-2 th residual conductive pattern YMR1 - 2 and the 1-2 th signal pad PD2 in the first direction DR1 may be about 20 μm or more.

[0206] Fig.11AAccording to the embodiment of the present invention, Fig.10 A cross-sectional view taken along line III-III'.

[0207] refer to Fig.11A , the plurality of 1-2 signal pads PD2 may be arranged along the first direction DR1. The plurality of 1-2 signal pads PD2 may be spaced apart from each other by a predetermined distance, thereby preventing a short circuit between the plurality of 1-2 signal pads PD2. The 1-2 signal pads PD2 and the 1-2 residual conductive patterns YMR1-2 may be spaced apart from each other by a minimum distance TD3 along the first direction DR1.

[0208] A second sub pad area PA1-2 (see FIG. 1-4 ) which is adjacent to the second sub pad area PA1-2 in a plan view may be defined in the first sensing insulating layer IL2. Fig.10 ) overlapping insulating opening OP-IL2 (or second opening). The insulating opening OP-IL2 may completely overlap with a plurality of 1-2 signal pad areas PDA2 in a plan view. The inner side surface of the first sensing insulating layer IL2 defining the insulating opening OP-IL2 may be spaced apart from the 1-2 signal pad area PDA2 by a predetermined distance. The first sensing insulating layer IL2 may not contact the 1-2 signal pad PD2. The first sensing insulating layer IL2 may not overlap with the 1-2 signal pad PD2 in a plan view.

[0209] An opening corresponding to the insulating opening OP-IL2 may also be defined in the base layer IL1. An end portion of the base layer IL1 and an end portion of the first sensing insulating layer IL2 may be formed at the same position in the first direction DR1.

[0210] including a second sensing conductive layer CL2 (see Figure 7 ) may be defined on the boundary of the insulating opening OP-IL2. The 1-2nd residual conductive pattern YMR1-2 may include the same material as the fourth conductive pattern CP4. The 1-2nd residual conductive pattern YMR1-2 may be formed of the same conductive layer as the conductive layer forming the fourth conductive pattern CP4. The 1-2nd residual conductive pattern YMR1-2 may be a portion that remains unetched in the etching process of forming the fourth conductive pattern CP4 after forming the conductive layer.

[0211] Since the 1-2nd residual conductive pattern YMR1-2 is spaced apart from the 1-2nd signal pad PD2 by the minimum distance TD3, a short circuit caused by contact between the 1-2nd residual conductive pattern YMR1-2 and the fourth conductive pattern CP4 of the 1-2nd signal pad PD2 may be prevented.

[0212] Fig. 11B According to the embodiment of the present invention, Fig.10A cross-sectional view taken along line IV-IV'.

[0213] refer to Fig. 11B , the 1-2 signal line SCL1-2 may be disposed on the same layer as the layer on which the third conductive pattern CP3 of the 1-2 signal pad PD2 is disposed, and include the same material as the material of the third conductive pattern CP3 of the 1-2 signal pad PD2. The 1-2 signal line SCL1-2 may be disposed on the same layer as the layer on which the second connection electrode CN2 (see Figure 7 ) and includes the same material as that of the second connection electrode CN2. The 1-2 signal line SCL1-2 may overlap the 1-2 residual conductive pattern YMR1-2 in a plan view. The sixth insulating layer 60 may be disposed between the 1-2 signal line SCL1-2 and the 1-2 residual conductive pattern YMR1-2. Therefore, the 1-2 signal line SCL1-2 and the 1-2 residual conductive pattern YMR1-2, which cross each other in a plan view, may be prevented from being electrically connected.

[0214] The 1-2nd residual conductive pattern YMR1-2 may be disposed on the sixth insulating layer 60. In a plan view, the 1-2nd residual conductive pattern YMR1-2 may be spaced apart from an end of the sixth insulating layer 60 by a predetermined distance TD4. In a plan view, the predetermined distance TD4 between the 1-2nd residual conductive pattern YMR1-2 and the sixth insulating layer 60 may be about 20 μm or more. When the predetermined distance TD4 between the 1-2nd residual conductive pattern YMR1-2 and the sixth insulating layer 60 in a plan view is less than about 20 μm, the 1-2nd residual conductive pattern YMR1-2 may become close to the 1-2nd signal line SCL1-2 disposed under the sixth insulating layer 60. Therefore, it is increasingly likely that the 1-2nd residual conductive pattern YMR1-2 and the 1-2nd signal line SCL1-2 are electrically connected to each other, so that a short circuit occurs between the 1-2nd residual conductive pattern YMR1-2 and the 1-2nd signal line SCL1-2. Therefore, it may be desirable that the predetermined distance TD4 between the 1-2 th residual conductive pattern YMR1-2 and the sixth insulating layer 60 is about 20 μm or more in a plan view.

[0215] Fig.12 is an enlarged plan view of a display module according to an embodiment of the inventive concept. More particularly, Fig.12 is an enlarged plan view of the second pad area PA2 according to an embodiment of the inventive concept.

[0216] refer to Fig.12, a plurality of display pads D-PD may be provided in the second pad area PA2. The second pad area PA2 may include a display pad area DPDA corresponding to the display pads D-PD. The second pad area PA2 may include a display pad area DPDA corresponding to the display pads D-PD formed on the first sensing insulating layer IL2 (see Fig.13A ) in the opening OP-IL2 (see Fig.13A ). The second opening area OPA2 may overlap with the second pad area PA2 in a plan view.

[0217] The display pad D-PD may be set to be larger than the first signal pads PD1 and PD2 (see Figure 6 ) away from the display area DA (see Figure 4 The display pad D-PD may be provided in plurality inside the second residual conductive pattern YMR2. The display pad D-PD may be electrically connected to the pixel PX through the second signal lines SCL2-1, SCL2-2, and SCL2-3 (see Figure 4 ). The second signal line SCL2 may include a 2-1st signal line SCL2-1, a 2-2nd signal line SCL2-2, and a 2-3rd signal line SCL2-3. The 2-1st signal line SCL2-1 may be disposed on a layer different from a layer on which the 2-2nd signal line SCL2-2 is disposed. The 2-1st signal line SCL2-1 may be connected to the 2-2nd signal line SCL2-2 through a first contact hole CNT1. The 2-2nd signal line SCL2-2 may be disposed on a layer different from a layer on which the 2-3rd signal line SCL2-3 is disposed. The 2-2nd signal line SCL2-2 may be connected to the 2-3rd signal line SCL2-3 through a second contact hole CNT2. The 2-3rd signal line SCL2-3 may be electrically connected between the display pad D-PD and the 2-2nd signal line SCL2-2. In a plan view, the 2-3rd signal line SCL2-3 may cross the second residual conductive pattern YMR2 while being electrically insulated from the second residual conductive pattern YMR2.

[0218] The second residual conductive pattern YMR2 may be disposed on a boundary of the second opening area OPA2. In a plan view, the second residual conductive pattern YMR2 may be spaced apart from the display pad D-PD by a predetermined distance. In a plan view, the second residual conductive pattern YMR2 may not overlap with the display pad D-PD.

[0219] The minimum distance between the second residual conductive pattern YMR2 and the display pad D-PD may be about 20 μm or more. When the minimum distance between the second residual conductive pattern YMR2 and the display pad D-PD is less than about 20 μm, a short circuit may occur between the second residual conductive pattern YMR2 and the display pad D-PD.

[0220] Fig.13AAccording to the embodiment of the present invention, Fig.12 A cross-sectional view taken along line V-V'.

[0221] refer to Fig.13A , a plurality of display pads D-PD may be arranged along the first direction DR1. The plurality of display pads D-PD may be spaced apart from each other by a predetermined distance, thereby preventing a short circuit between the plurality of display pads D-PD. The display pads D-PD and the second residual conductive pattern YMR2 may be spaced apart from each other by a predetermined distance along the first direction DR1.

[0222] The display pad D-PD may include a portion of the display pad along the display panel DP (see Figure 7 ) in the thickness direction of the plurality of conductive patterns CP1, CP2, CP3 and CP4 stacked. The first conductive pattern CP1 of the display pad D-PD may be disposed on the second insulating layer 20. The first conductive pattern CP1 of the display pad D-PD may be formed by connecting to the transistor TR (see Figure 7 ) of the gate electrode GE (see Figure 7 ) is formed by the same process as that by which the gate electrode GE is formed, and includes the same material as that of the gate electrode GE. The second conductive pattern CP2 of the display pad D-PD may be formed by the same process as that by which the first connection electrode CN1 (see Figure 7 ) is formed by the same process as the process of forming the second connection electrode CN2 (see Figure 7 ) is formed by the same process as the process of forming the second sensing conductive layer CL2 (see Figure 7 ) is formed by the same process as that of the second sensing conductive layer CL2 and includes the same material as that of the second sensing conductive layer CL2.

[0223] The sixth insulating layer 60 may be disposed on the fourth insulating layer 40. The sixth insulating layer 60 may contact a portion of the upper surface of the third conductive pattern CP3 and may contact a portion of the lower surface of the fourth conductive pattern CP4. The sixth insulating layer 60 may provide a flat upper surface except for a portion of the sixth insulating layer 60 overlapping the display pad area DPDA. The base layer IL1, the first sensing insulating layer IL2, and the second residual conductive pattern YMR2 may be disposed on the sixth insulating layer 60.

[0224] The sixth insulating layer 60 may include an organic material. Since the sixth insulating layer 60 includes an organic material with relatively high moisture permeability, moisture may be supplied to the conductive layer provided on the sixth insulating layer 60 for forming the fourth conductive pattern CP4. Therefore, a portion of the conductive layer may be oxidized. For the oxidized conductive layer, etching may not be performed smoothly in the etching process for forming the fourth conductive pattern CP4. Therefore, due to the unetched conductive layer, adjacent display pads D-PD may be connected, resulting in a short circuit between adjacent display pads D-PD. In order to prevent this, the minimum distance between the display pads D-PD may be about 10 μm or more.

[0225] A second pad area PA2 (see FIG. 1 ) which is adjacent to the second pad area PA2 in a plan view may be defined in the first sensing insulating layer IL2. Fig.12 ) overlapping insulating opening OP-IL2 (or second opening). The insulating opening OP-IL2 may completely overlap with the plurality of display pad areas DPDA in a plan view. The inner side surface of the first sensing insulating layer IL2 defining the insulating opening OP-IL2 may be spaced apart from the display pad area DPDA by a predetermined distance. The first sensing insulating layer IL2 may not contact the display pad D-PD. The first sensing insulating layer IL2 may not overlap with the display pad D-PD in a plan view.

[0226] An opening corresponding to the insulating opening OP-IL2 may also be defined in the base layer IL1. An end portion of the base layer IL1 and an end portion of the first sensing insulating layer IL2 may be formed at the same position in the first direction DR1.

[0227] including a second sensing conductive layer CL2 (see Figure 7 ) may be defined on the boundary of the insulating opening OP-IL2. The second residual conductive pattern YMR2 may include the same material as that of the fourth conductive pattern CP4.

[0228] Since the second residual conductive pattern YMR2 may be spaced apart from the display pad D-PD by a predetermined distance, a short circuit caused by contact between the second residual conductive pattern YMR2 and the fourth conductive pattern CP4 of the display pad D-PD may be prevented.

[0229] Fig. 13B According to the embodiment of the present invention, Fig.12 A cross-sectional view taken along line VI-VI'.

[0230] refer to Fig. 13B , the conductive layer CNL may be disposed on the fifth insulating layer 50. The conductive layer CNL may be a voltage line for transmitting a low driving voltage. The 2-1st signal line SCL2-1 may include a first sensing conductive layer CL1 (see Figure 7 ) of the same material. The 2-2nd signal line SCL2-2 may include the same material as the second sensing conductive layer CL2 (see Figure 7 ) of the same material. The 2-3rd signal line SCL2-3 may include the same material as the second connection electrode CN2 (see Figure 7 ) of the same material.

[0231] The 2-2 signal line SCL2-2 may be electrically connected to the 2-1 signal line SCL2-1 through a first contact hole CNT1 passing through the first sensing insulating layer IL2. The 2-3 signal line SCL2-3 may be electrically connected to the 2-2 signal line SCL2-2 through a second contact hole CNT2 passing through the first sensing insulating layer IL2, the base layer IL1, and the sixth insulating layer 60. The 2-3 signal line SCL2-3 may be electrically connected to the third conductive pattern CP3 of each of the plurality of display pads D-PD.

[0232] The 2-3rd signal line SCL2-3 may overlap the second residual conductive pattern YMR2 in a plan view. The sixth insulating layer 60 may be disposed between the 2-3rd signal line SCL2-3 and the second residual conductive pattern YMR2. Therefore, the 2-3rd signal line SCL2-3 and the second residual conductive pattern YMR2, which cross each other in a plan view, may be prevented from being electrically connected.

[0233] The second residual conductive pattern YMR2 may be spaced apart from the display pad D-PD by a predetermined distance and thus be electrically insulated from the display pad D-PD.

[0234] Fig.14 is a perspective view of an electronic device according to an embodiment of the inventive concept.

[0235] refer to Fig.14 Before completion, the display panel may further include a display pad disposed farther from the display area DA than the display pad D-PD (see Figure 4 ) and is electrically connected to the pixel PX (see Figure 4 The test pad C-PD may be disposed at a position farther from the display area DA than the second pad area PA2 (see Figure 4 ) in the test pad area CPA (or the third pad area).

[0236] The test circuit board CFCB may be bonded to the test pad area CPA through the third conductive adhesive layer CF3. The third conductive adhesive layer CF3 may be provided as an anisotropic conductive adhesive. The test circuit board CFCB and the test pad C-PD connected to the test circuit board CFCB may be used to test defects of the pixel PX. The test pad C-PD may be removed later by a cutting process. By removing the test pad area CPA positioned at the lower end of the cutting line CL, the non-display area NDA may be reduced (see Figure 4 ) area.

[0237] The third residual conductive pattern YMR3 may at least partially surround the test pad area CPA. In a plan view, the third residual conductive pattern YMR3 may be spaced apart from the test pad C-PD. The third residual conductive pattern YMR3 may include a first portion extending in a first direction DR1 and a second portion extending in a second direction DR2. The third residual conductive pattern YMR3 may be defined as a quadrilateral shape having a first portion and a second portion. The test pad C-PD may be disposed inside the third residual conductive pattern YMR3. Fig.14 The third residual conductive pattern YMR3 is shown as a quadrangular plane shape, but this is an example, and the plane shape of the third residual conductive pattern YMR3 may be changed as needed.

[0238] Fig.15 is an enlarged plan view of a display module according to an embodiment of the inventive concept. More particularly, Fig.15 is an enlarged plan view of a test pad area CPA according to an embodiment of the inventive concept.

[0239] refer to Fig.15 , a plurality of test pads C-PD may be disposed in the test pad area CPA. The test pad area CPA may include a sub-test pad area CPDA corresponding to the test pads C-PD. The test pad area CPA may include a sub-test pad area CPDA corresponding to the test pads C-PD formed on the first sensing insulating layer IL2 (see Fig.16 ) in the opening OP-IL2 (see Fig.16 ). The third opening area OPA3 may overlap the test pad area CPA.

[0240] The test pad C-PD can be electrically connected to the pixel PX through the third signal line SCL3 (see Figure 4 ). In a plan view, the third signal line SCL3 may cross the third residual conductive pattern YMR3 while being electrically insulated from the third residual conductive pattern YMR3.

[0241] The third residual conductive pattern YMR3 may be disposed on a boundary of the third opening area OPA3. In a plan view, the third residual conductive pattern YMR3 may be spaced apart from the test pad C-PD by a predetermined distance. In a plan view, the third residual conductive pattern YMR3 may not overlap the test pad C-PD.

[0242] Fig.16 According to the embodiment of the present invention, Fig.15 A cross-sectional view taken along line VII-VII'.

[0243] refer to Fig.16 , a plurality of test pads C-PD may be arranged along the first direction DR1. The plurality of test pads C-PD may be spaced apart from each other by a predetermined distance, thereby preventing a short circuit between the plurality of test pads C-PD. The test pad C-PD and the third residual conductive pattern YMR3 may be spaced apart from each other by a predetermined distance. Therefore, a short circuit between the third residual conductive pattern YMR3 and the test pad C-PD may be prevented.

[0244] The plurality of test pads C-PD may each include a plurality of test pads C-PD along the display panel DP (see Figure 4 ) is stacked in the thickness direction of the plurality of conductive patterns CP1, CP2, CP3 and CP4. The first conductive pattern CP1 of the test pad C-PD can be formed by connecting to the transistor TR (see Figure 7 ) of the gate electrode GE (see Figure 7 ) is formed by the same process as that by which the gate electrode GE is formed, and includes the same material as that of the gate electrode GE. The second conductive pattern CP2 of the test pad C-PD may be formed by the same process as that by which the first connection electrode CN1 (see Figure 7 ) is formed by the same process as that by which the second connection electrode CN2 (see Figure 7 ) is formed by the same process as that by which the second connection electrode CN2 is formed, and includes the same material as that of the second connection electrode CN2. Figure 7 ) is formed by the same process as that of the second sensing conductive layer CL2 and includes the same material as that of the second sensing conductive layer CL2.

[0245] A test pad area CPA (see FIG. 1 ) which is adjacent to the test pad area CPA in a plan view may be defined in the first sensing insulating layer IL2. Fig.15) overlapping insulating opening OP-IL2 (or third opening). The insulating opening OP-IL2 may completely overlap with a plurality of sub-test pad areas CPDA in a plan view. The inner side surface of the first sensing insulating layer IL2 defining the insulating opening OP-IL2 may be spaced apart from the sub-test pad area CPDA by a predetermined distance. The first sensing insulating layer IL2 may not contact the test pad C-PD. The first sensing insulating layer IL2 may not overlap with the test pad C-PD in a plan view.

[0246] including a second sensing conductive layer CL2 (see Figure 7 ) may be defined on the boundary of the insulating opening OP-IL2. The third residual conductive pattern YMR3 may include the same material as that of the fourth conductive pattern CP4.

[0247] Fig.17A is a cross-sectional view of a test pad according to an embodiment of the inventive concept. Fig. 17B is a cross-sectional view of a test pad according to a comparative example.

[0248] refer to Fig.17A , the test pad C-PD according to an embodiment of the inventive concept may not be aligned with the base layer IL1 (see Fig. 17B ) and the first sensing insulating layer IL2 (see Fig. 17B ) overlap. Fig. 17B , the test pad C-PD according to the comparative example may overlap the base layer IL1 and the first sensing insulating layer IL2 in a plan view. Fig. 17B The fourth conductive pattern CP4 of the test pad C-PD may be disposed on the first sensing insulating layer IL2 along an upper surface of the first sensing insulating layer IL2. The fourth conductive pattern CP4 disposed on the first sensing insulating layer IL2 may be bent at a second angle BB at a boundary of the first sensing insulating layer IL2. Fig. 17B The second angle BB of the fourth conductive pattern CP4 of the test pad C-PD may be greater than Fig.17A The fourth conductive pattern CP4 of the test pad C-PD in the circuit board CFCB is bent at a first angle CC. When the angle at which the fourth conductive pattern CP4 is bent becomes larger, the pressure applied during the pressing of the test pad C-PD and the test circuit board CFCB may be concentrated to cause damage to the fourth conductive pattern CP4. This may cause a defect in the test pad C-PD.

[0249] The following table 1 shows ( Fig.17A The defect rate of the example in which the test pad C-PD does not overlap with the first sensing insulating layer IL2 in a plan view, and (as shown in FIG. Fig. 17B) is a defect rate of a comparative example in which the test pad C-PD overlaps the first sensing insulating layer IL2 in a plan view.

[0250] [Table 1]

[0251]

[0252] refer to Fig.17A , Fig. 17B As shown in Table 1, in the example, regardless of the thickness of the first sensing insulating layer IL2, the defect rate is 0%. However, in the comparative example, when the thickness of the first sensing insulating layer IL2 is 3.5 μm, 3.8 μm, and 4 μm, the defect rates are 6.7%, 7.5%, and 3.3%, respectively. Therefore, in the case where the first sensing insulating layer IL2 is removed from the test pad C-PD, as in the embodiment of the inventive concept, it can be seen that the defect rate of the test pad C-PD is reduced.

[0253] In the display module according to an embodiment of the inventive concept, since an opening overlapping a pad area is defined in a sensing insulating layer including an organic material, cracks on a conductive pattern or a short between signal pads caused by the sensing insulating layer may be prevented.

[0254] In addition, since the insulating layer is provided between the residual conductive pattern formed on the boundary of the opening and the signal line, a short circuit between the residual conductive pattern and the signal line can be prevented.

[0255] Although the embodiments of the present invention have been described, it is understood that the present invention should not be limited to these embodiments, but a person skilled in the art can make various changes and modifications within the spirit and scope of the present invention. Therefore, the technical scope of the present invention is not necessarily limited to the contents described in the specific embodiments of this specification.

Claims

1. A display module, wherein: The display module comprises: The display panel comprises a display area and a non-display area, wherein a plurality of pixels are arranged in the display area, the non-display area has a first pad area, a plurality of first signal pads are arranged in the first pad area, and the plurality of first signal pads are electrically connected to the plurality of pixels through a plurality of first signal lines respectively; and An input sensor, disposed on the display panel and comprising a sensing insulating layer including an organic material, and a sensing conductive layer; wherein each of the plurality of first signal pads comprises a plurality of first conductive patterns stacked along a thickness direction of the display panel, and at least one of the plurality of first conductive patterns comprises the same material as that of the sensing conductive layer, A first opening overlapping the first pad region is defined in the sensing insulating layer, and Wherein, a first residual conductive pattern including a material same as that of the sensing conductive layer is disposed on a boundary of the first opening.

2. The display module according to claim 1, wherein: The first residual conductive pattern is spaced apart from the plurality of first signal pads by a predetermined distance.

3. The display module according to claim 2, wherein: A minimum distance between the first residual conductive pattern and the plurality of first signal pads is 20 μm or more.

4. The display module according to claim 1, wherein: The sensing insulation layer does not overlap the plurality of first signal pads.

5. The display module according to claim 1, wherein: The plurality of first signal lines cross the first residual conductive pattern, and Wherein, the display module further includes an insulating layer arranged between the plurality of first signal lines and the first residual conductive pattern.

6. The display module according to claim 5, wherein: Each of the plurality of pixels includes a transistor and a light emitting element connected to the transistor, and The insulating layer includes a material that is the same as a material of at least one of a plurality of insulating layers disposed between the transistor and the light emitting element.

7. The display module according to claim 1, wherein: Each of the plurality of pixels includes a transistor and a light emitting element connected to the transistor, The transistor includes a semiconductor pattern and a gate electrode disposed on the semiconductor pattern, and The display panel further includes a first connection electrode and a second connection electrode for connecting the transistor to the light emitting element.

8. The display module according to claim 7, wherein: The plurality of first conductive patterns include: A 1-1 conductive pattern including the same material as that of the gate electrode; A 1-2 conductive pattern including the same material as that of the first connection electrode; A 1-3rd conductive pattern including the same material as that of the second connection electrode; and The first to fourth conductive patterns include the same material as the material of the sensing conductive layer, and Wherein, the 1-1th conductive pattern to the 1-4th conductive pattern are electrically connected to each other.

9. The display module according to claim 7, wherein: Each of the plurality of first signal lines includes a same material as a material of at least one of the gate electrode and the second connection electrode.

10. The display module according to claim 7, wherein: The plurality of first signal lines include the same material as that of the second connection electrodes, and An insulating layer is disposed between the plurality of first signal lines and the first residual conductive pattern, and the first residual conductive pattern is spaced apart from an end of the insulating layer by at least 20 μm.

11. The display module according to claim 1, wherein: The non-display area further includes a second pad area, in which a plurality of second signal pads are arranged, the plurality of second signal pads are spaced farther from the display area than the plurality of first signal pads and the plurality of second signal pads are electrically connected to the plurality of pixels through a plurality of second signal lines, respectively. wherein each of the plurality of second signal pads comprises a plurality of second conductive patterns stacked along the thickness direction of the display panel, and at least one of the plurality of second conductive patterns comprises the same material as the material of the sensing conductive layer, A second opening overlapping the second pad region is defined in the sensing insulating layer, and Wherein, a second residual conductive pattern including a material same as that of the sensing conductive layer is disposed on a boundary of the second opening.

12. The display module according to claim 11, wherein: The second residual conductive pattern is spaced apart from the plurality of second signal pads by a predetermined distance.

13. The display module according to claim 11, wherein: The second signal line includes: Signal line 2-1; and a 2-2 signal line, the 2-2 signal line being electrically connected between the 2-1 signal line and the plurality of second signal pads, wherein the 2-2 signal line intersects the second residual conductive pattern, and Wherein, the display module further includes an insulating layer arranged between the 2-2 signal line and the second residual conductive pattern.

14. The display module according to claim 13, wherein: Each of the plurality of pixels includes a transistor and a light emitting element connected to the transistor, The transistor includes a semiconductor pattern and a gate electrode disposed on the semiconductor pattern. The display panel further comprises a first connection electrode and a second connection electrode for connecting the transistor to the light emitting element. wherein the 2-1st signal line comprises the same material as the material of the sensing conductive layer, and The 2-2 signal line includes the same material as that of the second connection electrode.

15. The display module according to claim 11, wherein: A minimum distance between the plurality of second signal pads is 10 μm or more.

16. The display module according to claim 11, wherein: The non-display area further includes a third pad area, in which a plurality of test pads are arranged, the plurality of test pads are spaced farther from the display area than the plurality of second signal pads and the plurality of test pads are electrically connected to the plurality of pixels through a plurality of third signal lines, respectively. wherein each of the plurality of test pads comprises a plurality of third conductive patterns stacked along the thickness direction of the display panel, and at least one of the plurality of third conductive patterns comprises the same material as the material of the sensing conductive layer, A third opening overlapping the third pad region is defined in the sensing insulating layer, and Wherein, a third residual conductive pattern including the same material as the material of the sensing conductive layer is disposed on a boundary of the third opening.

17. The display module according to claim 16, wherein: The plurality of test pads are bonded to a test circuit board through a conductive adhesive layer.

18. An electronic device, wherein: The electronic device comprises: The display panel comprises a display area and a non-display area, wherein pixels are arranged in the display area, the non-display area has a first pad area and a second pad area, and a plurality of first signal pads and a plurality of second signal pads are arranged in the first pad area and the second pad area, respectively electrically connected to the pixels through a plurality of signal lines; an input sensor disposed on the display panel and comprising a sensing insulating layer including an organic material and a sensing conductive layer; a data driver disposed on the non-display area and electrically connected to the plurality of first signal pads through a first conductive adhesive layer; and a flexible circuit board disposed on the non-display area and electrically connected to the plurality of second signal pads through a second conductive adhesive layer, wherein each of the plurality of first signal pads comprises a plurality of first conductive patterns stacked along a thickness direction of the display panel, and at least one of the plurality of first conductive patterns comprises the same material as that of the sensing conductive layer, A first opening overlapping the first pad region is defined in the sensing insulating layer, and Wherein, a first residual conductive pattern including a material same as that of the sensing conductive layer is disposed on a boundary of the first opening.

19. The electronic device according to claim 18, wherein: The first residual conductive pattern is spaced apart from the plurality of first signal pads by a predetermined distance.

20. The electronic device according to claim 18, wherein: The plurality of second signal pads are spaced farther from the display area than the plurality of first signal pads and the plurality of second signal pads are electrically connected to the pixels through a plurality of second signal lines, respectively. wherein each of the plurality of second signal pads comprises a plurality of second conductive patterns stacked along the thickness direction of the display panel, and at least one of the plurality of second conductive patterns comprises the same material as the material of the sensing conductive layer, A second opening overlapping the second pad region is defined in the sensing insulating layer, and Wherein, a second residual conductive pattern including a material same as that of the sensing conductive layer is disposed on a boundary of the second opening.

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