Display panel and display device

Abstract

This invention discloses a display panel and a display device. By setting the first and second plates of a first capacitor to be located on the first and second conductive layers respectively, and the active layer located on the side of the second conductive layer away from the substrate, the first capacitor is positioned below the first or second driving transistor. This allows the first or second plate of the first capacitor to provide bottom-shielding for the first or second driving transistor, which helps to reduce the impact of light on the electrical performance of the driving transistor and improve the display effect. The second plate of the first capacitor is connected to the driving gate of the first driving transistor and the driving gate of the second driving transistor in the pixel circuit. The first and second driving transistors are connected in parallel, and the driving gates of the first and second driving transistors are located on different sides of the active layer. This results in good uniformity of low grayscale display on the display panel and a high maximum brightness of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for screen display effects.

[0003] The existing display panels have poor display quality, which affects the user experience. Summary of the Invention

[0004] This invention provides a display panel and a display device to improve the display effect of the display panel and enhance the user experience.

[0005] According to one aspect of the present invention, a display panel is provided, comprising:

[0006] Substrate;

[0007] An active layer and multiple conductive layers are stacked on one side of the substrate, and a plurality of pixel circuits are formed in the active layer and the conductive layers; the pixel circuit includes a first driving transistor, a second driving transistor and a first capacitor; the first driving transistor and the second driving transistor are connected in parallel;

[0008] The multilayer conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate; the first electrode of the first capacitor is located on the first conductive layer, the second electrode of the first capacitor is located on the second conductive layer, and the second electrode of the first capacitor is connected to the driving gate of the first driving transistor and the driving gate of the second driving transistor; along the thickness direction of the display panel, the driving gate of the first driving transistor and the driving gate of the second driving transistor are located on different sides of the active layer.

[0009] The active layer is located on the side of the second conductive layer away from the substrate.

[0010] According to another aspect of the present invention, a display device is provided, including a display panel according to any embodiment of the present invention.

[0011] The display panel and display device of this invention, through a multilayer conductive layer including a first conductive layer and a second conductive layer, are configured with stacked conductive layers. A first electrode and a second electrode of a first capacitor are located on the first and second conductive layers, respectively. An active layer is located on the side of the second conductive layer away from the substrate. This allows the first capacitor to be positioned below a first or second driving transistor, enabling the first or second electrode of the first capacitor to provide bottom-level light shielding for the first or second driving transistor. This helps to mitigate the impact of light on the electrical performance of the driving transistor and improves the display effect. The second electrode of the first capacitor is connected to the driving gate of the first driving transistor and the driving gate of the second driving transistor in the pixel circuit. The first and second driving transistors are connected in parallel. Along the thickness direction of the display panel, the driving gates of the first and second driving transistors are located on different sides of the active layer, resulting in good uniformity of low grayscale display and high maximum brightness of the display panel. Thus, the parallel structure of the first and second driving transistors further enhances the display effect of the display panel.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a top view of a display panel provided in an embodiment of the present invention;

[0015] Figure 2 This is a cross-sectional view of a display panel provided in an embodiment of the present invention;

[0016] Figure 3 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0017] Figure 4 This is a top view of another display panel provided in an embodiment of the present invention;

[0018] Figure 5 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0019] Figure 6 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0020] Figure 7 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0021] Figure 8 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0022] Figure 9 This is a top view of another display panel provided in an embodiment of the present invention;

[0023] Figure 10 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0024] Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0025] Figure 12 yes Figure 11 A schematic diagram of the structure of the first conductive layer in the middle;

[0026] Figure 13 yes Figure 11 A schematic diagram of the structure of the first and second conductive layers in the middle;

[0027] Figure 14 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, and the third conductive layer;

[0028] Figure 15 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, and the first type of via;

[0029] Figure 16 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, the first type of via, and the second type of via;

[0030] Figure 17 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, the first type of via, the second type of via, and the fourth conductive layer;

[0031] Figure 18 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, and the fifth conductive layer;

[0032] Figure 19 yes Figure 11 A schematic diagram of the structure of the second conductive layer, the active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer;

[0033] Figure 20 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0034] Figure 21 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0035] Figure 22 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0036] Figure 23 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0037] Figure 24 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0038] Figure 25 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0039] Figure 26 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0040] Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] Figure 1This is a top view of a display panel provided in an embodiment of the present invention. Figure 2 This is a cross-sectional view of a display panel provided in an embodiment of the present invention. Figure 3 This is a cross-sectional view of another display panel provided in an embodiment of the present invention, wherein... Figure 2 Can correspond Figure 1 Obtained by cutting along AA'. Figure 3 Can correspond Figure 1 Obtained by cutting along BB', see reference. Figures 1-3 The display panel includes a substrate 10; an active layer and multiple conductive layers stacked on one side of the substrate 10, wherein multiple pixel circuits are formed in the active layer and conductive layers; the pixel circuits include a first driving transistor DT1, a second driving transistor DT2, and a first capacitor C1; the first driving transistor DT1 and the second driving transistor DT2 are connected in parallel; the multiple conductive layers include a first conductive layer 31 and a second conductive layer 32, the second conductive layer 32 being located on the side of the first conductive layer 31 away from the substrate 10; the first electrode 01 of the first capacitor C1 is located on the first conductive layer 31, the second electrode 02 of the first capacitor C1 is located on the second conductive layer 32, and the second electrode 02 of the first capacitor C1 is connected to the driving gate of the first driving transistor DT1 (denoted as the first driving gate G1) and the driving gate of the second driving transistor DT2 (denoted as the second driving gate G2); along the thickness direction z of the display panel, the driving gates of the first driving transistor DT1 and the second driving transistor DT2 are located on different sides of the active layer; the active layer is located on the side of the second conductive layer 32 away from the substrate 10.

[0044] Specifically, the substrate 10 serves to provide protection and support for the display panel. The substrate 10 can be a flexible substrate made of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate made of materials such as glass. An active layer and multiple conductive layers are disposed on one side of the substrate 10. An insulating layer is disposed between the active layer and adjacent conductive layers, and the multiple conductive layers are isolated from each other by the insulating layers. Multiple pixel circuits are formed in the active layer and the multiple conductive layers. The pixel circuits are used to drive the light-emitting elements in the display panel to emit light.

[0045] The pixel circuit includes a first driving transistor DT1 and a second driving transistor DT2 connected in parallel. The parallel connection of the first driving transistor DT1 and the second driving transistor DT2 means that the first terminal of the first driving transistor DT1 is connected to the first terminal of the second driving transistor DT2, and the second terminal of the first driving transistor DT1 is connected to the second driving transistor DT2. The first terminal is the source, and the second terminal is the drain, or vice versa. The first driving transistor DT1 and the second driving transistor DT2 each include a driving gate, which is the gate through which the data voltage is written. The first driving transistor DT1 and the second driving transistor DT2 can generate driving currents according to the data voltage on their driving gates. The sum of the driving currents generated by the first driving transistor DT1 and the second driving transistor DT2 is the total driving current for driving the light-emitting device to emit light.

[0046] In this embodiment, along the thickness direction z of the display panel, the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 are located on different sides of the active layer. In one optional embodiment, the first driving transistor DT1 is bottom-gate driven (that is, the first driving transistor DT1 includes a bottom gate located on the side of the active layer close to the substrate 10, and the bottom gate of the first driving transistor DT1 serves as the driving gate of the first driving transistor DT1), and the second driving transistor DT2 is top-gate driven (that is, the second driving transistor DT2 includes a top gate located on the side of the active layer away from the substrate 10, and the top gate of the second driving transistor DT2 serves as the driving gate of the second driving transistor DT2); or the first driving transistor DT1 is top-gate driven (that is, the first driving transistor DT1 includes a top gate located on the side of the active layer away from the substrate 10, and the top gate of the first driving transistor DT1 serves as the driving gate of the first driving transistor DT1), and the second driving transistor DT2 is bottom-gate driven (that is, the second driving transistor DT2 includes a bottom gate located on the side of the active layer close to the substrate 10, and the bottom gate of the second driving transistor DT2 serves as the driving gate of the second driving transistor DT2). The large subthreshold swing of bottom-gate driven transistors is beneficial for improving the display uniformity of low grayscale images; the small subthreshold swing of top-gate driven transistors is beneficial for increasing the driving current and improving the maximum brightness of the display. Thus, the parallel connection of the first driving transistor DT1 and the second driving transistor DT2 improves the display effect of the display panel. In some embodiments, the first driving transistor DT1 and the second driving transistor DT2 can be single-gate devices; in other embodiments, the first driving transistor DT1 and the second driving transistor DT2 are dual-gate devices; in other optional embodiments of the present invention, one of the first driving transistor DT1 and the second driving transistor DT2 is a single-gate device, and the other is a dual-gate device.

[0047] In this embodiment, the pixel circuit further includes a first capacitor C1. The first plate 01 and the second plate 02 of the first capacitor C1 are located on the first conductive layer 31 and the second conductive layer 32, respectively. The second plate 02 of the first capacitor C1 is connected to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2. The first capacitor C1 can store the voltage of the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2. In some optional embodiments, the second plate 02 of the first capacitor C1 can serve as either the driving gate of the first driving transistor DT1 or the driving gate of the second driving transistor DT2. In other optional embodiments, the second plate 02 of the first capacitor C1 can be discretely disposed from the driving gate of the first driving transistor DT1, and the second plate 02 of the first capacitor C1 can be connected to the driving gate of the first driving transistor DT1 via vias and / or jumpers. Similarly, the second plate 02 of the first capacitor C1 can be discretely disposed from the driving gate of the second driving transistor DT2, and the second plate 02 of the first capacitor C1 can be connected to the driving gate of the second driving transistor DT2 via vias and / or jumpers.

[0048] The pixel circuit includes transistor elements such as the first driving transistor DT1 and the second driving transistor DT2. Since the channel region of the transistor element located in the active layer is sensitive to light, light illuminating the channel region of the transistor element will affect its electrical performance. In this embodiment, the active layer is located on the side of the second conductive layer 32 away from the substrate 10, such that the first plate 01 or the second plate of the first capacitor C1 is located below the first driving transistor DT1 or the second driving transistor DT2. This allows the first plate 01 or the second plate 02 of the first capacitor C1 to provide bottom-level light shielding for the first driving transistor DT1 or the second driving transistor DT2, which helps to mitigate the impact of light on the electrical performance of the driving transistors and further improves the display effect.

[0049] Alternatively, the active layer may be made of metal oxide, which helps to reduce leakage current in the pixel circuitry.

[0050] The display panel of this embodiment comprises a first conductive layer and a second conductive layer, stacked in multiple conductive layers. The first and second plates of a first capacitor are located on the first and second conductive layers, respectively. The active layer is located on the side of the second conductive layer away from the substrate. This positions the first capacitor below the first or second driving transistor, allowing the first or second plate of the first capacitor to provide bottom-level light shielding for the driving transistor. This helps mitigate the impact of light on the electrical performance of the driving transistor, improving the display effect. The second plate of the first capacitor connects to the driving gates of the first and second driving transistors in the pixel circuit. The first and second driving transistors are connected in parallel. Along the thickness direction of the display panel, the driving gates of the first and second driving transistors are located on different sides of the active layer, resulting in good uniformity of low grayscale display and high maximum brightness. Thus, the parallel structure of the first and second driving transistors further enhances the display effect of the display panel.

[0051] Figure 4 This is a top view of another display panel provided in an embodiment of the present invention. Figure 5 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 6 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 7 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 8 This is a cross-sectional view of another display panel provided in an embodiment of the present invention, wherein, Figure 5 Can correspond Figure 4 Obtained by cutting along CC'. Figure 6 Can correspond Figure 4 Obtained by cutting along DD'. Figure 7 Can correspond Figure 4 Obtained by cutting along EE'. Figure 8 Can correspond Figure 4 Obtained by cutting along FF', see reference. Figures 1-8 Optionally, the active layer includes a first active layer 21, and the channel regions of the first driving transistor DT1 and the second driving transistor DT2 are located in the first active layer 21.

[0052] In this configuration, the orthographic projection of the driving gate (first driving gate G1) of the first driving transistor DT1 onto the substrate 10 at least partially overlaps with the orthographic projection of the channel region of the first driving transistor DT1 onto the substrate 10. Similarly, the orthographic projection of the driving gate (second driving gate G2) of the second driving transistor DT2 onto the substrate 10 at least partially overlaps with the orthographic projection of the channel region of the second driving transistor DT2 onto the substrate 10. The channel region of the first driving transistor DT1 is located in the first active layer 21, and the source and drain regions of the first driving transistor DT1 are located on opposite sides of the channel region of the first driving transistor DT1, meaning that the first electrode and the second electrode of the first driving transistor DT1 are located on opposite sides of the channel region of the first driving transistor DT1. The channel region of the second driving transistor DT2 is located in the first active layer 21, and the source and drain regions of the second driving transistor DT2 are located on opposite sides of the channel region of the second driving transistor DT2, meaning that the first electrode and the second electrode of the second driving transistor DT2 are located on opposite sides of the channel region of the second driving transistor DT2. The channel regions of the first driving transistor DT1 and the second driving transistor DT2 are located on the same layer, so that the source of the first driving transistor DT1 and the source of the second driving transistor DT2 can be connected in the first active layer 21, and the drain of the first driving transistor DT1 and the drain of the second driving transistor DT2 can also be connected in the first active layer 21. This allows the parallel connection of the first driving transistor DT1 and the second driving transistor DT2 to be achieved in the first active layer 21, without the need for vias and / or jumpers. This simplifies the manufacturing process of the display panel, simplifies the layout structure of the display panel, and is beneficial for improving pixel density.

[0053] Continue to refer to Figures 4-8 Optionally, the first driving transistor DT1 includes a first gate and a second gate G3. The first gate is located on the side of the active layer closer to the substrate 10, and the second gate G3 is located on the side of the active layer away from the substrate 10. The orthogonal projections of the first gate and the second gate G3 on the substrate 10 at least partially cover the orthogonal projection of the channel region of the first driving transistor DT1 on the substrate 10. The first gate serves as the driving gate of the first driving transistor DT1, that is, the first gate serves as the first driving gate G1. Optionally, the display panel also includes a third conductive layer 33, which is located on the side of the active layer away from the substrate 10, and the second gate G3 is located in the third conductive layer 33.

[0054] In this design, the first gate serves as the bottom gate of the first driving transistor DT1, and the second gate G3 serves as the top gate of the first driving transistor DT1. The bottom gate serves as the driving gate of the first driving transistor DT1. The orthographic projections of the first gate and the second gate G3 onto the substrate 10 at least partially cover the orthographic projection of the channel region of the first driving transistor DT1 onto the substrate 10. This allows the first gate and the second gate G3 to shield the bottom and top of the channel region of the first driving transistor DT1 from light, respectively, thus improving the impact of illumination on the electrical performance of the first driving transistor DT1. By setting the first driving transistor DT1 as a dual-gate structure, the gate's control over the channel region can be enhanced, and the bottom-gate driving method is beneficial for improving the subthreshold swing of the first driving transistor DT1, which is beneficial for grayscale expansion and improving the uniformity of display brightness. Specifically, on the first active layer 21, the area covered by the second gate G3 of the first driving transistor DT1 serves as the channel region of the first driving transistor DT1.

[0055] Optionally, the second gate G3 of the first driving transistor DT1 is connected to the first terminal of the first driving transistor DT1. In this way, it can be ensured that the threshold voltage of the first driving transistor DT1 is not affected by the voltage of the second gate G3.

[0056] Continue to refer to Figures 4-8 The second driving transistor DT2 includes a third gate G4 and a fourth gate. The third gate G4 is located on the side of the active layer closer to the substrate 10, and the fourth gate is located on the side of the active layer away from the substrate 10. The orthogonal projections of the third gate G4 and the fourth gate on the substrate 10 at least partially cover the orthogonal projection of the channel region of the second driving transistor DT2 on the substrate 10. The fourth gate serves as the driving gate of the second driving transistor DT2, that is, the fourth gate serves as the second driving gate G2.

[0057] In this design, the third gate G4 serves as the bottom gate of the second driving transistor DT2, and the fourth gate serves as the top gate of the second driving transistor DT2. The top gate acts as the driving gate of the second driving transistor DT2. The orthogonal projection of the third gate G4 onto the substrate 10 at least partially covers the orthogonal projection of the channel region of the second driving transistor DT2 onto the substrate 10, allowing the third gate G4 and the fourth gate to shield the bottom and top of the channel region of the second driving transistor DT2, respectively. This mitigates the impact of illumination on the electrical performance of the second driving transistor DT2 and enhances the display effect. By setting the second driving transistor DT2 as a dual-gate structure, the gate's control over the channel region is enhanced, and the top-gate driving method results in a smaller subthreshold swing of the second driving transistor DT2, which is beneficial for increasing the driving current and thus improving the maximum brightness of the light-emitting device. Specifically, on the first active layer 21, the area covered by the fourth gate of the second driving transistor DT2 serves as the channel region of the second driving transistor DT2.

[0058] Optionally, the length of the channel region of the second driving transistor DT2 is less than the length of the channel region of the first driving transistor DT1; in this way, the threshold voltage of the second driving transistor DT2 can be close to the threshold voltage of the first driving transistor DT1, so that when the pixel circuit includes a threshold voltage compensation module, the threshold voltage compensation effect of the first driving transistor DT1 and the second driving transistor DT2 is good, thereby improving the display effect of the display panel.

[0059] Optionally, the third gate G4 of the second driving transistor DT2 is connected to the first terminal of the second driving transistor DT2; in this way, it can be ensured that the threshold voltage of the second driving transistor DT2 is not affected by the voltage of the third gate G4.

[0060] In some embodiments, the third gate G4 is located in the second conductive layer 32. In some embodiments, the fourth gate is located in the third conductive layer 33.

[0061] Continue to refer to Figures 1-8 Optionally, the first active layer 21 includes a first active portion 211, which extends along a first direction x, and the channel region of the first driving transistor DT1 is located in the first active portion 211.

[0062] On the first active portion 211, the area covered by the second gate G3 of the first driving transistor DT1 serves as the channel region of the first driving transistor DT1, the first end of the first active portion 211 serves as the source of the first driving transistor DT1, and the second end of the first active portion 211 serves as the drain of the first driving transistor DT1. Along the first direction x, the first end and the second end of the first active portion 211 are located on both sides of the channel region of the first driving transistor DT1.

[0063] Optionally, the first active layer 21 includes a second active portion 212, which extends along a first direction x; the channel region of the second driving transistor DT2 is located in the second active portion 212.

[0064] On the second active portion 212, the area covered by the fourth gate of the second driving transistor DT2 serves as the channel region of the second driving transistor DT2, the first end of the second active portion 212 serves as the source of the second driving transistor DT2, and the second end of the second active portion 212 serves as the drain of the second driving transistor DT2. Along the first direction x, the first end and the second end of the second active portion 212 are located on both sides of the channel region of the second driving transistor DT2.

[0065] The first active layer 21 further includes a third active portion 213 and a fourth active portion 214, which extend along a second direction y, intersecting with a first direction x. The third active portion 213 is connected to the first end of the first active portion 211 and the first end of the second active portion 212, respectively; the fourth active portion 214 is connected to the second end of the first active portion 211 and the second end of the second active portion 212, respectively. Thus, in the first active layer 21, the source terminals of the first driving transistor DT1 and the second driving transistor DT2 are connected through the third active portion 213, and the drain terminals of the first driving transistor DT1 and the second driving transistor DT2 are connected through the fourth active portion 214, thereby achieving a parallel connection of the first driving transistor DT1 and the second driving transistor DT2 in the first active layer 21.

[0066] Continue to refer to Figures 1-8 Optionally, the second plate 02 of the first capacitor C1 serves as the driving gate of the first driving transistor DT1. This eliminates the need for vias or jumpers to connect the second plate 02 of the first capacitor C1 to the driving gate of the first driving transistor DT1, simplifying the display panel structure and improving pixel density. Optionally, the orthographic projection of the first plate 01 of the first capacitor C1 onto the substrate 10 at least partially overlaps with the orthographic projection of the second plate 02 of the first capacitor C1 onto the substrate 10, and the overlapping area constitutes the effective capacitance of the first capacitor C1. In some embodiments, the orthographic projection of the first plate 01 of the first capacitor C1 onto the substrate 10 covers the orthographic projection of the second plate 02 of the first capacitor C1 onto the substrate 10.

[0067] Optionally, the second plate 02 of the first capacitor C1 is projected onto the substrate 10 in a way that at least partially covers the projection of the channel region of the first driving transistor DT1 onto the substrate 10. That is, the driving gate of the first driving transistor DT1 and the channel region of the first driving transistor DT1 are overlapped, so that the second plate 02 of the first capacitor C1 can serve as both the upper plate of the first capacitor C1 and the bottom of the first driving transistor DT1, thereby improving the effect of light on the electrical performance of the first driving transistor DT1.

[0068] Optionally, the first electrode plate 01 of the first capacitor C1 is projected onto the substrate 10 in a way that at least partially covers the projection of the channel region of the first driving transistor DT1 onto the substrate 10. This allows the first electrode plate located in the first conductive layer 31 to serve as both the lower electrode plate of the first capacitor C1 and the light-shielding layer of the driving transistor, thereby saving layout space, improving layout space utilization, and preventing changes in the electrical performance of the driving transistor caused by light. This is beneficial for improving the reliability of the pixel circuit and thus improving the reliability of the screen.

[0069] Continue to refer to Figures 1-8Optionally, the display panel also includes a first connection line L1, the first end of which is electrically connected to the driving gate of the first driving transistor DT1 through a first type via K1, and the second end of which is electrically connected to the driving gate of the second driving transistor DT2 through a second type via K2.

[0070] In this configuration, the orthographic projection of the first connection line L1 on the substrate 10 at least partially overlaps with the orthographic projection of the driving gate of the first driving transistor DT1 on the substrate 10, and the orthographic projection of the first connection line L1 on the substrate 10 at least partially overlaps with the orthographic projection of the driving gate of the second driving transistor DT2 on the substrate 10. This allows the first connection line L1 to be connected to the driving gates of the first driving transistor DT1 and the second driving transistor DT2 respectively through vias, thus achieving electrical connection between them. By connecting the gates of the first driving transistor DT1 and the second driving transistor DT2 through the first connection line L1, the layout space occupied by the first driving transistor DT1 and the second driving transistor DT2 can be reduced, thereby increasing pixel density.

[0071] Optionally, the display panel further includes a fourth conductive layer 34, which is located on the side of the third conductive layer 33 away from the substrate 10. The first connecting line L1 is located in the fourth conductive layer 34. An interlayer insulating layer 140 is disposed between the third conductive layer 33 and the fourth conductive layer 34. A second gate insulating layer 130 is disposed between the third conductive layer 33 and the active layer. A first gate insulating layer 120 is disposed between the active layer and the second conductive layer 32. A first-type via K1 connecting the first end of the first connecting line L1 to the driving gate of the first driving transistor DT1 penetrates the interlayer insulating layer 140, the second gate insulating layer 130, and the first gate insulating layer 120. A second-type via K2 connecting the second end of the first connecting line L1 to the driving gate of the second driving transistor DT2 penetrates the interlayer insulating layer 140. Optionally, the resistivity of the fourth conductive layer 40 is less than the resistivity of the third conductive layer 33.

[0072] Figure 9 This is a top view of another display panel provided in an embodiment of the present invention, see reference. Figure 9Optionally, the display panel also includes a power line VDD, wherein the orthographic projection of the power line VDD on the substrate 10 does not overlap with or only partially overlaps with the orthographic projection of the first connecting line L1 on the substrate 10. Specifically, when the orthographic projection of the power line VDD on the substrate 10 overlaps with the orthographic projection of the first connecting line L1 on the substrate 10, the power line VDD and the first connecting line L1 have a directly opposite area, and a parasitic capacitance will be formed between them. Since the first connecting line L1 is connected to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 respectively, the larger the parasitic capacitance formed between the first connecting line L1 and the power line VDD, the greater the impact of this parasitic capacitance on the voltage of the driving gates of the first driving transistor DT1 and the second driving transistor DT2, which is detrimental to the improvement of the display effect. In some embodiments, the power line VDD is set to not overlap with the orthographic projection of the first connecting line L1 on the substrate 10, that is, the directly opposite area of ​​the power line VDD and the first connecting line L1 is 0, so that there is no parasitic capacitance between them, thereby improving the display effect. In other embodiments, the orthographic projection of the power line VDD on the substrate 10 is partially overlapped with the orthographic projection of the first connecting line L1 on the substrate 10, rather than completely overlapping. This also reduces the parasitic capacitance between the two, which is beneficial for improving the display effect.

[0073] Optionally, the power line VDD includes a first sub-power line VDD1 extending along the second direction y. The orthographic projection of the first sub-power line VDD1 on the substrate 10 does not overlap with or partially overlaps with the first connection line L1. The extension of the first sub-power line VDD1 along the first direction x includes one or a combination of at least two of the following: a straight line, a broken line, or a curve.

[0074] Continue to refer to Figures 4-9 Optionally, the display panel further includes a second connecting line L2. The first end of the second connecting line L2 is electrically connected to the second gate G3 of the first driving transistor DT1 via a second-type via K2. The second end of the second connecting line L2 is electrically connected to the third gate G4 of the second driving transistor DT2 via a first-type via K1. The third end of the second connecting line L2 is connected to the first electrode of both the first driving transistor DT1 and the second driving transistor DT2 via a second-type via K2. The second electrode of the first driving transistor DT1 is connected to the second electrode of the second driving transistor DT2 via a fourth active portion 214. Optionally, the second connecting line L2 is located in the fourth conductive layer 34.

[0075] Specifically, a second-type via K2 connecting the first end of the second connection line L2 and the second gate G3 of the first driving transistor DT1 penetrates the interlayer insulating layer 140; a first-type via K1 connecting the second end of the second connection line L2 and the third gate G4 of the second driving transistor DT2 penetrates the interlayer insulating layer 140, the second gate insulating layer 130, and the first gate insulating layer 120; a second-type via K2 connecting the third end of the second connection line L2 and the first terminal of the first driving transistor DT1 and the first terminal of the second driving transistor DT2 penetrates the interlayer insulating layer 140 and the second gate insulating layer 130. Optionally, the third end of the second connection line L2 can be connected to the first end of the first active part 211, the first end of the second active part 212, or the third active part 213 through the second-type via K2. In this embodiment, the second gate G3 of the first driving transistor DT1 is connected to the first electrode, and the third gate G4 of the second driving transistor DT2 is connected to the first electrode, and the second gate G3 of the first driving transistor DT1 is connected to the third gate G4 of the second driving transistor DT2, by means of a jumper wire via the second connection line L2. This can reduce the layout space occupied by the first driving transistor DT1 and the second driving transistor DT2, thereby improving the pixel density.

[0076] Figure 10 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 12 yes Figure 11 A schematic diagram of the structure of the first conductive layer. Figure 13 yes Figure 11 Schematic diagram of the structure of the first and second conductive layers. Figure 14 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, and the third conductive layer. Figure 15 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, and the first type of via. Figure 16 yes Figure 11 A schematic diagram of the structure consisting of a first conductive layer, a second conductive layer, an active layer, a third conductive layer, a first type of via, and a second type of via. Figure 17 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, the first type of via, the second type of via, and the fourth conductive layer. Figure 18 yes Figure 11 A schematic diagram of the structure of the first conductive layer, the second conductive layer, the active layer, the third conductive layer, and the fifth conductive layer. Figure 19 yes Figure 11A schematic diagram of the structure of the second conductive layer, active layer, third conductive layer, fourth conductive layer, and fifth conductive layer is provided for reference. Figures 10-19 Optionally, the pixel circuit also includes a first transistor T1, the gate of which is located in the third conductive layer 33; the display panel also includes a second active layer 22, which is on the same layer as the first active layer 21 but not connected, and the channel region of the first transistor T1 is in the second active layer 22.

[0077] The channel region of the first transistor T1 is located at the orthogonal projection position of the gate of the first transistor T1 on the second active layer 22. The gate of the first transistor T1 is located on the third conductive layer 33. For example, the first metal line J1 located on the third conductive layer 33 includes the gate of the first transistor T1. On the second active layer 22, the position where the second active layer 22 and the first metal line J1 intersect is the channel region of the first transistor T1.

[0078] Optionally, the display panel also includes a first initialization signal line Vref1, the first electrode of the first transistor T1 is connected to the first initialization signal line Vref1 through a second type via K2, and the second electrode of the first transistor T1 is connected to the first plate O1 of the first capacitor C1 through a third connection line L3.

[0079] Optionally, the first initialization signal line Vref1 includes a first sub-initialization signal line Vref11 extending along a first direction x, and the first electrode of the first transistor T1 is connected to the first sub-initialization signal line Vref11 through a second-type via K2. In some embodiments, the first sub-initialization signal line Vref11 is located in the fourth conductive layer 34. The second-type via K2 connecting the first electrode of the first transistor T1 and the first sub-initialization signal line Vref11 penetrates the interlayer insulating layer 140 and the second gate insulating layer 130.

[0080] Figure 20 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 20 Can correspond Figure 11 Obtained by sectioning along MM', see reference. Figure 11 and Figure 20 Optionally, the third connection line L3 is located in the fourth conductive layer 34. The first end of the third connection line L3 is connected to the second electrode of the first transistor T1 via a second-type via K2, and the second end of the third connection line L3 is connected to the first plate O1 of the first capacitor C1 via a first-type via K1.

[0081] The second end of the third connection line L3 can be connected to the second active layer 22 through a second type via K2, thereby achieving connection with the second electrode of the first transistor T1. Accordingly, the second type via K2 needs to penetrate the interlayer insulating layer 140 and the second gate insulating layer 130. The first type via K1 connecting the second end of the third connection line L3 and the first electrode plate 01 of the first capacitor C1 needs to penetrate the interlayer insulating layer 140, the second gate insulating layer 130, the first gate insulating layer 120, and the capacitor insulating layer 110. The capacitor insulating layer 110 is disposed between the first conductive layer 31 and the second conductive layer 32.

[0082] When the first transistor T1 is turned on, the first initialization voltage on the first sub-initialization signal line Vref11 can be transmitted through the first transistor T1 to the first plate 01 of the first capacitor C1. The second plate 02 of the first capacitor C1 is connected to the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2. Through the coupling effect of the first capacitor C1, the initialization of the driving gate of the first driving transistor DT1 and the driving gate of the second driving transistor DT2 can be realized.

[0083] Optionally, the display panel further includes a first scan signal line Sn1. The orthographic projection of the first scan signal line Sn1 on the substrate 10 overlaps with the orthographic projection of the gate of the first transistor T1 on the substrate 10. At the overlap location, the gate of the first transistor T1 is connected to the first scan signal line Sn1 through a second type via K2. In some embodiments, the first scan signal line Sn1 extends along a first direction x. In some embodiments, the first scan signal line Sn1 is located in the fourth conductive layer 34. The first sub-initialization signal line Vref11 is located on the side of the first scan signal line Sn1 away from the second active portion 212.

[0084] As described above, the first metal line J1 located in the third conductive layer 33 includes the gate of the first transistor T1. The orthographic projection of the first scan signal line Sn1 on the substrate 10 overlaps with the orthographic projection of the first metal line J1 on the substrate 10. At the overlapping position, the first scan signal line Sn1 and the first metal line J1 are connected through a second type via K2 to provide a first scan signal to the gate of the first transistor T1.

[0085] Optionally, the display panel further includes a second transistor T2, the gate of which is located in the third conductive layer 33, the channel region of which is located in the first active layer 21, and the channel region of which is located at the orthographic projection position of the gate of which is located in the first active layer 21. Optionally, the second transistor T2 is used to compensate for the threshold voltage of the driving transistor.

[0086] On the first active layer 21, the intersection of the first active layer 21 and the first metal line J1 forms the channel region of the second transistor T2. The first metal line J1, located on the third conductive layer 33, also includes the gate of the second transistor T2. The gate of the second transistor T2 and the gate of the first transistor T1 are integrally formed. The gate of the second transistor T2 is connected to the first scan signal line Sn1 via a second-type via K2. Optionally, the first scan signal line Sn1 can be connected to the first metal line J1 through a second-type via K2 to achieve connection with the gates of the first transistor T1 and the second transistor T2 in the same pixel circuit, thereby reducing the number of vias and improving signal transmission quality. In other embodiments, the first scan signal line Sn1 can also be connected to the gate of the first transistor T1 and the gate of the second transistor T2 respectively through different second-type vias K2. For example, at the intersection of the first metal line J1 and the second active layer 22, the first scan signal line Sn1 is connected to the first metal line J1 through a second-type via K2. At the intersection of the first metal line J1 and the first active layer 21, the first scan signal line Sn1 is connected to the first metal line J1 through another second-type via K2.

[0087] Optionally, the first terminal of the second transistor T2 is connected to the second terminal of the first driving transistor DT1 and the second terminal of the second driving transistor DT2 through the fourth active part 214, and the second terminal of the second transistor T2 is connected to the driving gate of the second driving transistor DT2 through the fourth connection line L4.

[0088] Optionally, the first active layer 21 further includes a fifth active portion 215, in which the channel region of the second transistor T2 is located. The fifth active portion 215 is connected to the first active portion 211 and the second active portion 212 via the fourth active portion 214, thereby realizing the connection between the first electrode of the second driving transistor DT2 and the second electrode of the first driving transistor DT1 and the second electrode of the second driving transistor DT2.

[0089] Optionally, the first terminal of the second transistor T2 is connected to the first end of the fourth connection line L4 via the second type via K2, and the driving gate of the second driving transistor DT2 is connected to the second end of the fourth connection line L4 via the second type via K2.

[0090] In some embodiments, along the second direction y, the second active portion 212 is located between the first active portion 211 and the first scan signal line Sn1. Correspondingly, along the second direction y, the second driving transistor DT2 is located between the first driving transistor DT1 and the first scan signal line Sn1. This allows the driving gate of the second driving transistor DT2 to be closer to the first scan signal line Sn1, and consequently, the distance between the second transistor T2 and the driving gate of the second driving transistor DT2 is also closer. This results in a shorter length of the fourth connecting line L4, preventing the fourth connecting line L4 from forming a large parasitic capacitance with other signal lines in the display panel, thereby improving the display effect of the display panel.

[0091] Optionally, the second transistor T2 and the first transistor T1 are arranged along the first direction x, that is, the two transistors connected to the first scan signal line Sn1 are arranged along the first direction x. Optimizing the layout structure is beneficial to improving pixel density.

[0092] Optionally, the display panel also includes a third transistor T3, the gate of which is located in the third conductive layer 33, and the channel region of which is located in the first active layer 21. The channel region of the third transistor T3 is located at the orthographic projection of the gate of the third transistor T3 onto the first active layer 21. For example, the second metal line J2 located in the third conductive layer 33 includes the gate of the third transistor T3. The location where the first active layer 21 intersects with the second metal line J2 on the first active layer 21 is the channel region of the third transistor T3.

[0093] Optionally, the first active layer 21 further includes a sixth active portion 216. Along the second direction y, the sixth active portion 216 is located on the side of the first active portion 211 away from the fifth active portion 215. The sixth active portion 216 is connected to the first active portion 211 through the third active portion 213. The channel region of the third transistor T3 is in the sixth active portion 216.

[0094] Optionally, the display panel further includes a second initialization signal line Vref2. The first terminal of the third transistor T3 is electrically connected to the second initialization signal line Vref2 through a second-type via K2, and the second terminal of the third transistor T3 is connected to the first terminals of the first driving transistor DT1 and the second driving transistor DT2 through a third active portion 213. In some embodiments, the second initialization signal line Vref2 extends along a first direction x. Optionally, the second initialization signal line Vref2 is located in the fourth conductive layer 34.

[0095] In this configuration, the orthographic projection of the second initialization signal line Vref2 onto the substrate 10 overlaps with the orthographic projection of the sixth active portion 216 onto the substrate 10. For example, the second initialization signal line Vref2 and the sixth active portion 216 are intersected. At the intersection, the second initialization signal line Vref2 is connected to the sixth active portion 216 through a second-type via K2, thereby connecting the second initialization signal line Vref2 to the first terminal of the third transistor T3. The sixth active portion 216 is connected to the first terminal of the first active portion 211 and the first terminal of the second active portion 212 through the third active portion 213, thereby connecting the second terminal of the third transistor T3 to the first terminal of the first driving transistor DT1 and the first terminal of the second driving transistor DT2. When the third transistor T3 is turned on, the first terminal and second gate G3 of the first driving transistor DT1, and the first terminal and third gate G4 of the second driving transistor DT2 are initialized to the second initialization voltage on the second initialization signal line Vref2. When the third transistor T3 and the second transistor T2 are turned on simultaneously, the driving gate of the first driving transistor DT1 discharges to the second initialization signal line Vref2 through the second transistor T2, the first driving transistor DT1 and the third transistor T3, and the driving gate of the second driving transistor DT2 discharges to the second initialization signal line Vref2 through the second transistor T2, the second driving transistor DT2 and the third transistor T3, thereby compensating for the threshold voltages of the first driving transistor DT1 and the second driving transistor DT2.

[0096] Optionally, the display panel further includes a second scan signal line Sn2. The orthographic projection of the second scan signal line Sn2 on the substrate 10 overlaps with the orthographic projection of the gate of the third transistor T3 on the substrate 10. At the overlap location, the second scan signal line Sn2 is connected to the gate of the third transistor T3 through a second type via K2. In some embodiments, the second scan signal line Sn2 extends along a first direction x; in some embodiments, the second scan signal line Sn2 is located in the fourth conductive layer 34.

[0097] The orthographic projection of the second scan signal line Sn2 on the substrate 10 overlaps with the orthographic projection of the second metal line J2 on the substrate 10. At the overlapping position, the second scan signal line Sn2 is connected to the second metal line J2 through the second type via K2. That is, the second scan signal line Sn2 is connected to the gate of the third transistor T3 through the second type via K2 to provide the second scan signal to the gate of the third transistor T3.

[0098] Optionally, the second scan signal line Sn2 is located between the second initialization signal line Vref2 and the first scan signal line Sn1.

[0099] Optionally, the display panel also includes a fourth transistor T4, a fifth transistor T5, and a second capacitor C2; the display panel also includes a third initialization signal line Vref3 and a data line Data, the second terminal of the fourth transistor T4 is connected to the third initialization signal line Vref3, the second terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5, and connected to the first plate 03 of the second capacitor C2, the second plate 04 of the second capacitor C2 is connected to the second terminals of the first driving transistor DT1 and the second driving transistor DT2, and the first terminal of the fifth transistor T5 is connected to the data line Data. In this configuration, the fourth transistor T4 transmits a fixed voltage to the first plate 03 of the second capacitor C2, and the fifth transistor T5 transmits a data voltage to the first plate 03 of the second capacitor C2. The second capacitor C2 couples the voltage change of its first plate to its second plate, meaning it can couple the voltage change of its first plate to the second terminals of the first driving transistor DT1 and the second driving transistor DT2, and then transmit it via the second transistor T2 to the driving gates of the first driving transistor DT1 and the second driving transistor DT2. This ensures that the voltage at the driving gate of the first driving transistor DT1 is correlated with the data voltage, and the voltage at the driving gate of the second driving transistor DT2 is correlated with the data voltage. Optionally, the first plate 03 of the second capacitor C2 is located in the first conductive layer 31, and the second plate 04 of the second capacitor C2 is located in the second conductive layer 32.

[0100] Optionally, the active layer further includes a third active layer 23, which is on the same layer as the first active layer 21 but not connected; the channel regions of the fourth transistor T4 and the fifth transistor T5 are located in the third active layer 23, the channel region of the fourth transistor T4 is located at the position where the gate of the fourth transistor T4 is projected onto the third active layer 23, the channel region of the fifth transistor T5 is located at the position where the gate of the fifth transistor T5 is projected onto the third active layer 23, and the gates of the fourth transistor T4 and the fifth transistor T5 are located in the third conductive layer 33.

[0101] Optionally, the second metal line J2 includes the gate of the fourth transistor T4. The location where the third active layer 23 intersects with the second metal line J2 on the third active layer 23 forms the channel region of the fourth transistor T4. Optionally, the orthographic projection of the second scan signal line Sn2 onto the substrate 10 at least partially overlaps with the orthographic projection of the gate of the fourth transistor T4 onto the substrate 10. At the overlap location, the second scan signal line Sn2 is connected to the gate of the fourth transistor T4 through a second-type via K2. The gate of the fourth transistor T4 and the gate of the third transistor T3 are integrally formed. Optionally, the second scan signal line Sn2 can be connected to the second metal line J2 through a second-type via K2 to achieve connection with the gates of the third transistor T3 and the fourth transistor T4 in the same pixel circuit, thereby reducing the number of vias and improving signal transmission quality. In other embodiments, the second scan signal line Sn2 can also be connected to the gate of the third transistor T3 and the gate of the fourth transistor T4 respectively through different second-type vias K2. For example, at the intersection of the second metal line J2 and the first active layer 21, the second scan signal line Sn2 is connected to the second metal line J2 through a second-type via K2. At the intersection of the second metal line J2 and the third active layer 23, the second scan signal line Sn2 is connected to the second metal line J2 through another second-type via K2.

[0102] Optionally, the third active layer 23 is located on the side of the first active portion 211 away from the second active portion 212. In some embodiments, the third active layer 23 extends along the second direction y.

[0103] Specifically, the second terminal of the fourth transistor T4 is connected to the third initialization signal line Vref3 through the second type via K2, the first terminal of the fourth transistor T4 is connected to the first plate 03 of the second capacitor C2 through the fifth connection line L5, and the second plate 04 of the second capacitor C2 is connected to the second terminal of the first driving transistor DT1 and the second terminal of the first driving transistor DT1 through the sixth connection line L6. Figure 21 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 21 Can correspond Figure 11 Obtained by cutting along NN', reference Figure 11 and Figure 21 Specifically, the first end of the fifth connection line L5 is connected to the second electrode of the fourth transistor T4 through the second type via K2, and the second end of the fifth connection line L5 is connected to the first plate O3 of the second capacitor C2 through the first type via K1. Figure 22 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 22 Can correspond Figure 11 Obtained by cutting along PP', see reference. Figure 11 and Figure 22The first end of the sixth connection line L6 is connected to the second plate 04 of the second capacitor C2 through the first type of via K1, and the second end of the sixth connection line L6 is connected to the second electrode of the first driving transistor DT1 and the second electrode of the second driving transistor DT2 through the second type of via K2.

[0104] The orthographic projection of the third active layer 23 on the substrate 10 overlaps with the orthographic projection of the third initialization signal line Vref3 on the substrate 10. At the overlapping position, the third active layer 23 is connected to the third initialization signal line Vref3 through a second type via K2.

[0105] Optionally, the third initialization signal line Vref3 extends along the first direction x. In some embodiments, the third initialization signal line Vref3 is located in the fourth conductive layer 34.

[0106] Optionally, the third initialization signal line Vref3 is located between the first scan signal line Sn1 and the second scan signal line Sn2. This arrangement aims to optimize the position of each transistor in the layout, reducing the layout space occupied and thus improving layout space utilization and pixel density.

[0107] In some embodiments, the first terminal of the fifth transistor T5 is connected to the first plate 03 of the second capacitor C2 via the fifth connection line L5, and the second terminal of the fifth transistor T5 is connected to the data line Data via the seventh connection line L7. Figure 23 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 23 Can correspond Figure 11 Obtained by cutting along QQ', see reference. Figure 11 and Figure 23 Specifically, the first end of the seventh connection line L7 is connected to the second terminal of the fifth transistor T5 through the second type via K2, and the second end of the seventh connection line L7 is connected to the data line Data through the third type via K3.

[0108] Optionally, the fifth connecting line L5 is located in the fourth conductive layer 34; the sixth connecting line L6 is located in the fourth conductive layer 34; and the seventh connecting line L7 is located in the fourth conductive layer 34.

[0109] Optionally, the display panel also includes a fifth conductive layer 35, which is located on the side of the fourth conductive layer 34 away from the substrate 10, and the data line Data is located on the fifth conductive layer 35; the data line Data extends along the second direction y.

[0110] A first planarization layer 150 is provided between the fifth conductive layer 35 and the fourth conductive layer 34, and the aforementioned third type via K3 is a via that penetrates the first planarization layer.

[0111] Optionally, the third transistor T3 and the fourth transistor T4 are arranged along the first direction x; that is, the two transistors connected to the second scan signal line Sn2 are arranged along the first direction x, which optimizes the layout structure and helps to improve pixel density.

[0112] Optionally, the display panel also includes a third scan signal line Sn3. In some embodiments, the third scan signal line Sn3 is located in the third conductive layer 33. The third scan signal line Sn3 includes the gate of the fifth transistor T5. In this way, there is no need to set additional metal lines in other conductive layers as the gate of the fifth transistor T5, which can reduce the wiring in the display panel and thus improve the pixel density.

[0113] In other embodiments, the third scan signal line Sn3 is located in the fourth conductive layer 34, and its orthogonal projection on the substrate 10 at least partially covers the gate of the fifth transistor T5. The third scan signal line Sn3 is connected to the gate of the fifth transistor T5 through a second type via K2. This arrangement can reduce the resistance of the third scan signal line Sn3, reduce the signal transmission voltage drop of the third scan signal line Sn3, and improve the display effect.

[0114] Optionally, along the second direction y, the third scan signal line Sn3 is located on the side of the second scan signal line Sn2 away from the first scan signal line Sn1.

[0115] Optionally, the pixel circuit also includes a sixth transistor T6. The channel region of the sixth transistor T6 is located in the first active layer 21, and the gate of the sixth transistor T6 is located in the third conductive layer 33. The channel region of the sixth transistor T6 is located at the orthogonal projection position of the gate of the sixth transistor T6 in the first active layer 21. The first terminal of the sixth transistor T6 is connected to the first plate 01 of the first capacitor C1 through the eighth connection line L8, and the second terminal of the sixth transistor T6 is connected to the second sub-initialization signal line Vref12 through the ninth connection line L9. When the sixth transistor T6 is turned on, the first initialization voltage on the second sub-initialization signal line Vref12 can be transmitted to the first plate 01 of the first capacitor C1 to initialize the first plate 01 of the first capacitor C1.

[0116] Specifically, the first end of the eighth connection line L8 is connected to the first electrode of the sixth transistor T6 through the second type via K2, and the second end of the eighth connection line L8 is connected to the first plate 01 of the first capacitor C1 through the first type via K1; the first end of the ninth connection line L9 is connected to the second electrode of the sixth transistor T6 through the second type via K2, and the first end of the ninth connection line L9 is connected to the second sub-initialization signal line Vref12.

[0117] Optionally, the first initialization signal line Vref1 includes a second sub-initialization signal line Vref12, which extends along the second direction y. The second sub-initialization signal line Vref12 is connected to the first sub-initialization signal line Vref11 through a third type via K3. In this way, the first sub-initialization signal line Vref11 and the second sub-initialization signal line Vref12 form a mesh structure, which reduces the resistance of the first initialization signal line Vref1, reduces the transmission voltage drop of the first initialization signal line Vref1, and improves the display uniformity.

[0118] Figure 24 This is a cross-sectional view of another display panel provided in an embodiment of the present invention. Figure 24 Can correspond Figure 11 Optionally, the fifth conductive layer 35, obtained by slicing along WW', further includes a tenth connecting line L10. The orthographic projection of the tenth connecting line L10 on the substrate 10 overlaps with the orthographic projection of the eighth connecting line L8 on the substrate 10. The tenth connecting line L10 is connected to the eighth connecting line L8 through a third type via K3. Optionally, the display panel also includes a light-emitting device D1. The light-emitting device D1 includes a first electrode Y1, a light-emitting layer, and a second electrode (the second electrode is connected to a fixed voltage line VSS) stacked on the side of the conductive layer away from the substrate 10. The orthographic projection of the first electrode Y1 on the substrate 10 at least partially covers the orthographic projection of the tenth connecting line L10 on the substrate 10. The first electrode Y1 is connected to the tenth connecting line L10 through a fourth type via. Thus, through a fourth type of via between the first electrode Y1 of the light-emitting device D1 and the tenth connecting line L10, a third type of via K3 between the tenth connecting line L10 and the eighth connecting line L8, and a second type of via K2 between the eighth connecting line L8 and the first electrode of the sixth transistor T6, a total of three vias are used in the thickness direction z of the display panel to connect the first electrode Y1 of the light-emitting device D1 to the first electrode of the sixth transistor T6. This is in contrast to using a deep via connection between the first electrode Y1 of the light-emitting device D1 and the first electrode of the sixth transistor T6, making the connection between the first electrode Y1 of the light-emitting device D1 and the sixth transistor T6 easier to achieve. When the sixth transistor T6 is turned on, the first initialization voltage on the second sub-initialization signal line Vref12 can be transmitted to the first electrode Y1 of the light-emitting device D1 to initialize the first electrode Y1 of the light-emitting device D1.

[0119] Optionally, the orthographic projection of the tenth connection line L10 on the substrate 10 covers the orthographic projection of the channel region of the sixth transistor T6 on the substrate 10; thus, the tenth connection line L10 can provide top light shielding for the channel region of the sixth transistor T6, improving the impact of light on the electrical performance of the sixth transistor T6 and enhancing the display effect.

[0120] In some embodiments, the third scan signal line Sn3 is located in the third conductive layer 33, and the third scan signal line Sn3 includes the gate of the sixth transistor T6. In this way, there is no need to set additional metal lines in other conductive layers as the gate of the sixth transistor T6, which can reduce the wiring in the display panel and thus improve the pixel density.

[0121] In other embodiments, the third scan signal line Sn3 is located in the fourth conductive layer 34, and its orthogonal projection on the substrate 10 at least partially covers the gate of the sixth transistor T6. The third scan signal line Sn3 is connected to the gate of the sixth transistor T6 through a second type via K2. This arrangement can reduce the resistance of the third scan signal line Sn3, reduce the signal transmission voltage drop of the third scan signal line Sn3, and improve the display effect.

[0122] Optionally, the sixth transistor T6 and the fifth transistor T5 are arranged along the first direction x; that is, the two transistors connected to the third scan signal line Sn3 are arranged along the first direction x, which optimizes the layout structure and helps to improve pixel density.

[0123] Optionally, the display panel further includes a first light-emitting control signal line EM1 and a second light-emitting control signal line EM2, which extend along a first direction x. The pixel circuit also includes a seventh transistor T7 and an eighth transistor T8. The gates of the seventh transistor T7 and the eighth transistor T8 are located in the third conductive layer 33, and the channel regions of the seventh transistor T7 and the eighth transistor T8 are located in the first active layer 21. The channel region of the seventh transistor T7 is located at the orthographic projection position of the gate of the seventh transistor T7 in the first active layer 21, and the channel region of the eighth transistor T8 is located at the orthographic projection position of the gate of the eighth transistor T8 in the first active layer 21.

[0124] Optionally, the channel region of the seventh transistor T7 is located in the fifth active region 215.

[0125] Optionally, the channel region of the eighth transistor T8 is located in the third active region 213.

[0126] Specifically, the first terminal of the seventh transistor T7 is connected to the power line VDD through a second-type via K2, and the second terminal of the seventh transistor T7 is connected to the second terminals of the first driving transistor DT1 and the second driving transistor DT2 through the fourth active part 214. The first terminal of the eighth transistor T8 is connected to the first terminals of the first driving transistor DT1 and the second driving transistor DT2 in the third active part 213, and the second terminal of the eighth transistor T8 is connected to the first plate O1 of the first capacitor C1 through the eighth connecting line L8. When the seventh transistor T7 and the eighth transistor T8 are turned on, the driving current generated by the first driving transistor DT1 and the second driving transistor DT2 is transmitted to the light-emitting device D1, thereby driving the light-emitting device D1 to emit light for display.

[0127] Optionally, the power line VDD includes a second sub-power line VDD2 extending along the first direction x and a first sub-power line VDD1 extending along the first direction x. The second sub-power line VDD2 and the first sub-power line VDD1 are disposed on different layers and connected through a third type via K3. The first electrode of the seventh transistor T7 is connected to the first sub-power line VDD1 through a second type via K2. In this way, the first sub-power line VDD1 and the second sub-power line VDD2 form a mesh structure of power line VDD, which reduces the resistance of the first power line VDD, thereby reducing the signal transmission voltage drop of the power line VDD and improving the display uniformity.

[0128] Optionally, the second sub-power line VDD2 is located in the fourth conductive layer 34, and the first sub-power line VDD1 is located in the fifth conductive layer 35. In some embodiments, the orthographic projection of the first sub-power line VDD1 on the substrate 10 covers the orthographic projections of the channel regions of the first driving transistor DT1, the second driving transistor DT2, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 on the substrate 10, respectively. This allows the first power line VDD on the fifth conductive layer 35 to provide top-level light shielding for the channel regions of multiple transistors in the pixel circuit, further mitigating the impact of illumination on transistor electrical performance and improving display quality.

[0129] Figure 25 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 25Optionally, the orthographic projection of the first electrode Y1 of the light-emitting device onto the substrate at least partially covers the orthographic projection of the channel region of the eighth transistor T8 onto the substrate. Thus, the channel region of the eighth transistor T8, which is not covered by the fifth conductive layer, is covered from the top by the first electrode. This can mitigate the impact of electrical performance on the electrical performance of the eighth transistor T8, and further enhance the display effect by covering the channel regions of each transistor in the pixel circuit through the fifth conductive layer and the first electrode of the light-emitting device D1.

[0130] Optionally, the first light-emitting control signal line EM1 includes the gate of the seventh transistor T7. In this case, the location where the first active layer 21 intersects with the first light-emitting control signal line EM1 is the channel region of the seventh transistor T7; or the first light-emitting control signal line EM1 is located in the fourth conductive layer 34, and the orthographic projection of the first light-emitting control signal line EM1 on the substrate 10 at least partially covers the orthographic projection of the gate of the seventh transistor T7 on the substrate 10. The first light-emitting control signal line EM1 and the gate of the seventh transistor T7 are connected through a second type via K2. Figure 11 The example illustrates a case where the first light-emitting control signal line EM1 includes the gate of the seventh transistor T7.

[0131] Optionally, the second light-emitting control signal line EM2 includes the gate of the eighth transistor T8. In this case, the location where the first active layer 21 intersects with the second light-emitting control signal line EM2 is the channel region of the eighth transistor T8; or the second light-emitting control signal line EM2 is located in the fourth conductive layer 34, and the orthographic projection of the second light-emitting control signal line EM2 on the substrate 10 at least partially covers the orthographic projection of the gate of the eighth transistor T8 on the substrate 10. The second light-emitting control signal line EM2 and the gate of the eighth transistor T8 are connected through a second type via K2. Figure 11 The example illustrates the case where the second light-emitting control signal line EM2 is located in the fourth conductive layer 34. In this case, the display panel also includes a third metal line J3 located in the third conductive layer 33. The third metal line J3 serves as the gate of the eighth transistor T8. On the first active layer 21, the position where the first active layer 21 and the third metal line J3 intersect is the channel region of the eighth transistor T8.

[0132] Optionally, the first light emission control signal line EM1 is located on the side of the first sub-initialization signal line Vref11 of the first initialization signal line Vref1 that is away from the first scan signal line Sn1; the second light emission control signal line EM2 is located on the side of the second initialization signal line Vref2 that is away from the first scan signal line Sn1. The purpose of this arrangement is to optimize the position of each transistor in the layout, so as to reduce the layout space occupied, thereby improving the layout space utilization and increasing the pixel density.

[0133] In some embodiments, the second sub-power line VDD2 is located on the side of the first light emission control signal line EM1 away from the first scan signal line Sn1.

[0134] Continue to refer to Figure 11 and Figure 12 Optionally, the first conductive layer 31 further includes a first light-shielding layer 311 and a second light-shielding layer 312. Along the first direction x, the first light-shielding layer 311 is located between the first electrode 01 of the first capacitor C1 and the first electrode 03 of the second capacitor C2. Along the second direction y, the second light-shielding layer 312 and the first light-shielding layer 311 are arranged along the second direction y. The first light-shielding layer 311 and the second light-shielding layer 312 can be used to provide bottom light shielding for the channel region of the transistor in the pixel circuit, thereby further improving the effect of light on the electrical performance of the transistor.

[0135] Combination Figures 11-14 In some embodiments, the orthogonal projection of the first light-shielding layer 311 on the substrate 10 covers at least a portion of the orthogonal projection of the channel region of the third transistor T3 on the substrate 10, at least a portion of the orthogonal projection of the channel region of the fourth transistor T4 on the substrate 10, and at least a portion of the orthogonal projection of the channel region of the fifth transistor T5 on the substrate 10, thereby providing bottom light shielding for the channel regions of the third transistor T3, the fourth transistor T4, and the fifth transistor T5, respectively, through the first light-shielding layer 311.

[0136] In some embodiments, the orthogonal projection of the second light-shielding layer 312 on the substrate 10 covers at least a portion of the orthogonal projection of the channel region of the first transistor T1 on the substrate 10, at least a portion of the orthogonal projection of the channel region of the second transistor T2 on the substrate 10, and at least a portion of the orthogonal projection of the channel region of the seventh transistor T7 on the substrate 10, thereby providing bottom light shielding for the channel regions of the first transistor T1, the second transistor T2, and the seventh transistor T7, respectively, through the second light-shielding layer 312.

[0137] In some embodiments, the orthographic projection of the first plate 01 of the first capacitor C1 onto the substrate 10 covers at least a portion of the orthographic projection of the channel region of the sixth transistor T6 onto the substrate 10 and at least a portion of the orthographic projection of the channel region of the eighth transistor T8 onto the substrate 10. Thus, the first plate 01 of the first capacitor C1 serves both as the lower plate of the first capacitor C1 and as a bottom light-shielding layer for the channel regions of the sixth transistor T6 and the eighth transistor T8. This saves layout space and reduces the impact of light on the electrical performance of the sixth transistor T6 and the eighth transistor T8, thereby improving display quality and screen reliability.

[0138] Optionally, the first electrode 01 of the first capacitor C1 includes a main body 101 and a branch 102. Along the first direction x, the branch 102 is located on one side of the main body 101 and extends along the second direction y. The orthographic projection of the branch 102 on the substrate 10 covers at least a portion of the orthographic projection of the channel region of the sixth transistor T6 on the substrate 10 and at least a portion of the orthographic projection of the channel region of the eighth transistor T8 on the substrate 10. The orthographic projection of the main body 101 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode 02 of the first capacitor C1 on the substrate 10. In this way, on the one hand, an effective capacitor is formed by the overlap of the main body 101 and the second electrode 02 of the first capacitor C1. On the other hand, the branch 102 facilitates the connection between the first electrode 01 of the first capacitor C1 and the transistors in the pixel circuit.

[0139] Optionally, the first light-shielding layer 311 is connected to the third initialization signal line Vref3 through a first type via K1; in this way, the potential of the first light-shielding layer 311 is kept fixed, so that the first light-shielding layer 311 can also play a shielding role, further improving the display effect of the display panel.

[0140] Optionally, the second light-shielding layer 312 is connected to at least one of the power supply line VDD, the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3; in this way, the potential of the second light-shielding layer 312 is fixed, so that the second light-shielding layer 312 can also play a shielding role, further improving the display effect of the display panel.

[0141] Based on the above embodiments, optionally, the display panel further includes: a capacitor insulating layer 110, located between the first conductive layer 31 and the second conductive layer 32, the orthogonal projection of the capacitor insulating layer 110 on the substrate 10 covering the orthogonal projection of the first conductive layer 31 on the substrate 10; a first gate insulating layer 120, located between the second conductive layer 32 and the active layer, the orthogonal projection of the first gate insulating layer 120 on the substrate 10 covering the orthogonal projection of the second conductive layer 32 on the substrate 10; and a second gate insulating layer 130, located between the active layer and the third conductive layer 33, the orthogonal projection of the second gate insulating layer 130 on the substrate 10 covering the orthogonal projection of the active layer 32 on the substrate 10. Orthographic projection on substrate 10; interlayer insulating layer 140, located between third conductive layer 33 and fourth conductive layer 34, the orthographic projection of interlayer insulating layer 140 on substrate 10 covers the orthographic projection of third conductive layer 33 on substrate 10; first planarization layer 150, located between fourth conductive layer 34 and fifth conductive layer 35, the orthographic projection of first planarization layer 150 on substrate 10 covers the orthographic projection of fourth conductive layer 34 on substrate 10; second planarization layer 160, located on the side of fifth conductive layer 35 away from substrate 10, the orthographic projection of second planarization layer 160 on substrate 10 covers the orthographic projection of fifth conductive layer 35 on substrate 10.

[0142] Optionally, a first type of via K1 penetrates the interlayer insulating layer 140, the second gate insulating layer 130, and the first gate insulating layer 120, or a first type of via K1 penetrates the interlayer insulating layer 140, the second gate insulating layer 130, the first gate insulating layer 120, and the capacitor insulating layer; a second type of via K2 penetrates the interlayer insulating layer 140, or a second type of via K2 penetrates the interlayer insulating layer 140 and the second gate insulating layer 130; a third type of via K3 penetrates the first planarization layer 150; and a fourth type of via penetrates the second planarization layer 160.

[0143] Figure 26 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention. This timing diagram is applicable to... Figure 11 The pixel circuit shown is for reference. Figure 11 and Figure 26 The operation of the pixel circuit includes: an initialization phase t1, a threshold voltage compensation phase t2, a data writing phase t3, and a light emission phase t4. Optionally, each transistor in the pixel circuit is an N-type transistor, which can be an oxide transistor, such as an indium gallium zinc oxide transistor.

[0144] During the initialization phase t1, the signals on the second scan signal line Sn2 and the first scan signal line Sn1 sequentially transition to high level, and the signal on the first light-emitting control signal line EM1 is also high. The first transistor T1 is turned on, and the signal on the first initialization signal line Vref1 is transmitted through the first transistor T1 to the first electrode of the light-emitting device D1 and the first plate of the first capacitor C1. The seventh transistor T7 is turned on, and the power supply voltage on the power supply line VDD is transmitted through the seventh transistor T7 to the second electrodes of the first driving transistor DT1 and the second driving transistor DT2. The second transistor T2 and the third transistor T3 are also turned on.

[0145] During the threshold voltage compensation phase t2, the signals on the second scan signal line Sn2 and the first scan signal line Sn1 remain at a high level, while the signal on the first light emission control signal line EM1 is at a low level. The second transistor T2 and the third transistor T3 remain on. The driving gate G1 of the first driving transistor DT1 discharges to the second initialization signal line Vref2 through the second transistor T2, the first driving transistor DT1, and the third transistor T3, thereby performing threshold voltage compensation on the first driving transistor DT1. The driving gate G2 of the second driving transistor DT2 discharges to the second initialization signal line Vref2 through the second transistor T2, the second driving transistor DT2, and the third transistor T3, thereby performing threshold voltage compensation on the second driving transistor DT2. The fourth transistor T4 is on, transmitting the third initialization voltage on the third initialization signal line Vref3 to the first plate of the second capacitor C2.

[0146] During the data writing phase t3, the signal on the third scan signal line Sn3 is at a high level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The data voltage on the data line Data is transmitted to the first plate of the second capacitor C2 through the fifth transistor T5. The second capacitor C2 couples the change in data voltage relative to the third initialization voltage to the driving gate G1 of the first driving transistor DT1 and the driving gate G2 of the second driving transistor DT2 through the second transistor T2. The sixth transistor T6 is turned on, and the first initialization voltage of the first initialization signal line Vref1 is transmitted to the first electrode of the light-emitting device D1.

[0147] During the light-emitting stage t4, the signals on the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are at a high level, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first driving transistor DT1 and the second driving transistor DT2 drive the light-emitting device D1 to emit light.

[0148] In this embodiment, voltage changes on the fixed voltage line VSS connected to the light-emitting device D1 cause voltage changes at the driving gates of the first driving transistor DT1 and the second driving transistor DT2. Furthermore, the presence of parasitic capacitances at the driving gates of both transistors results in voltage changes at a different magnitude than those on the fixed voltage line VSS connected to the light-emitting device D1. In this embodiment, the orthographic projection of the power line VDD onto the substrate 10 does not overlap with or only partially overlaps with the orthographic projection of the first connecting line L1 onto the substrate 10. This reduces the parasitic capacitances at the driving gates of the first driving transistor DT1 and the second driving transistor DT2, thereby reducing the impact of voltage changes on the fixed voltage line VSS on the display effect and improving display uniformity.

[0149] The present invention also provides a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Figure 27 This is a schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device can be a mobile phone or any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch interactive terminals. The present invention does not impose any special limitations on these.

[0150] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0151] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Substrate; An active layer and multiple conductive layers are stacked on one side of the substrate, and multiple pixel circuits are formed in the active layer and the conductive layers; The pixel circuit includes a first driving transistor, a second driving transistor, and a first capacitor; the first driving transistor and the second driving transistor are connected in parallel. The multilayer conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate; the first electrode of the first capacitor is located on the first conductive layer, the second electrode of the first capacitor is located on the second conductive layer, and the second electrode of the first capacitor is connected to the driving gate of the first driving transistor and the driving gate of the second driving transistor; along the thickness direction of the display panel, the driving gate of the first driving transistor and the driving gate of the second driving transistor are located on different sides of the active layer. The active layer is located on the side of the second conductive layer away from the substrate.

2. The display panel according to claim 1, characterized in that, The active layer includes a first active layer, wherein the channel regions of the first driving transistor and the second driving transistor are located in the first active layer.

3. The display panel according to claim 2, characterized in that, The first driving transistor includes a first gate and a second gate, the first gate being located on the side of the active layer closer to the substrate, and the second gate being located on the side of the active layer away from the substrate; the orthographic projections of the first gate and the second gate on the substrate at least partially cover the orthographic projection of the channel region of the first driving transistor on the substrate; The first gate serves as the driving gate of the first driving transistor.

4. The display panel according to claim 3, characterized in that, The second gate of the first driving transistor is connected to the first electrode of the first driving transistor.

5. The display panel according to claim 3, characterized in that, The display panel further includes a third conductive layer located on the side of the active layer away from the substrate, and the second gate is located on the third conductive layer.

6. The display panel according to claim 5, characterized in that, The second driving transistor includes a third gate and a fourth gate, the third gate being located on the side of the active layer closer to the substrate, and the fourth gate being located on the side of the active layer away from the substrate; the orthographic projections of the third gate and the fourth gate on the substrate at least partially cover the orthographic projection of the channel region of the second driving transistor on the substrate; The fourth gate serves as the driving gate of the second driving transistor.

7. The display panel according to claim 2, characterized in that, The length of the channel region of the second driving transistor is less than the length of the channel region of the first driving transistor.

8. The display panel according to claim 6, characterized in that, The third gate of the second driving transistor is connected to the first terminal of the second driving transistor.

9. The display panel according to claim 6, characterized in that, The third gate is located in the second conductive layer.

10. The display panel according to claim 6, characterized in that, The fourth gate is located in the third conductive layer.

11. The display panel according to claim 2, characterized in that, The first active layer includes a first active portion extending along a first direction, and the channel region of the first driving transistor is located in the first active portion.

12. The display panel according to claim 11, characterized in that, The first active layer includes a second active portion that extends along the first direction; the channel region of the second driving transistor is located in the second active portion.

13. The display panel according to claim 12, characterized in that, The first active layer further includes a third active portion and a fourth active portion, the third active portion and the fourth active portion extending along a second direction, the second direction intersecting with the first direction; the third active portion is connected to a first end of the first active portion and a first end of the second active portion; the fourth active portion is connected to a second end of the first active portion and a second end of the second active portion.

14. The display panel according to any one of claims 1-13, characterized in that, The second plate of the first capacitor serves as the driving gate of the first driving transistor.

15. The display panel according to claim 14, characterized in that, The active layer includes a first active layer, the channel region of the first driving transistor is located in the first active layer, and the second plate of the first capacitor is projected onto the substrate in an orthogonal projection that at least partially covers the orthogonal projection of the channel region of the first driving transistor onto the substrate.

16. The display panel according to claim 14, characterized in that, The first plate of the first capacitor projects onto the substrate in an orthographic projection that at least partially covers the orthographic projection of the channel region of the first driving transistor onto the substrate.

17. The display panel according to claim 14, characterized in that, The first plate of the first capacitor, when projected onto the substrate, at least partially overlaps with the second plate of the first capacitor when projected onto the substrate.

18. The display panel according to claim 14, characterized in that, The first plate of the first capacitor is projected onto the substrate and covers the second plate of the first capacitor.

19. The display panel according to claim 14, characterized in that, The display panel further includes a first connecting line, the first end of which is electrically connected to the driving gate of the first driving transistor through a first type of via, and the second end of which is electrically connected to the driving gate of the second driving transistor through a second type of via.

20. The display panel according to claim 19, characterized in that, The display panel also includes a power line, the orthographic projection of which on the substrate does not overlap with or only partially overlaps with the first connecting line.

21. The display panel according to claim 20, characterized in that, The power line includes a first sub-power line extending along a second direction, wherein the orthographic projection of the first sub-power line on the substrate does not overlap or partially overlaps with the orthographic projection of the first connecting line on the substrate.

22. The display panel according to claim 19, characterized in that, The display panel further includes a third conductive layer located on the side of the active layer away from the substrate, and a fourth conductive layer located on the side of the third conductive layer away from the substrate, with the first connecting line located on the fourth conductive layer.

23. The display panel according to claim 22, characterized in that, The display panel further includes a second connecting line. The first end of the second connecting line is electrically connected to the second gate of the first driving transistor through a second type of via. The second end of the second connecting line is electrically connected to the third gate of the second driving transistor through a first type of via. The third end of the second connecting line is connected to the first electrode of the first driving transistor and the first electrode of the second driving transistor through a second type of via. The second electrode of the first driving transistor is connected to the second electrode of the second driving transistor through a fourth active part.

24. The display panel according to claim 23, characterized in that, The second connecting line is located in the fourth conductive layer.

25. The display panel according to claim 5, characterized in that, The pixel circuit further includes a first transistor, the gate of which is located in the third conductive layer; the display panel further includes a second active layer, which is on the same layer as the first active layer but not connected, and the channel region of the first transistor is located in the second active layer.

26. The display panel according to claim 25, characterized in that, The channel region of the first transistor is located at the position of the gate of the first transistor projected onto the second active layer; the display panel further includes a first initialization signal line, the first electrode of the first transistor is connected to the first initialization signal line through a second type of via, and the second electrode of the first transistor is connected to the first plate of the first capacitor through a third connection line.

27. The display panel according to claim 26, characterized in that, The first end of the third connection line is connected to the second electrode of the first transistor through the second type of via, and the second end of the third connection line is connected to the first plate of the first capacitor through the first type of via.

28. The display panel according to claim 26, characterized in that, The display panel further includes a first scan signal line, the orthographic projection of the first scan signal line on the substrate overlaps with the orthographic projection of the gate of the first transistor on the substrate, and at the overlap position, the gate of the first transistor is connected to the first scan signal line through a second type of via.

29. The display panel according to claim 28, characterized in that, The first scan signal lines extend along the first direction.

30. The display panel according to claim 28, characterized in that, The first initialization signal line includes a first sub-initialization signal line extending along a first direction, and the first electrode of the first transistor is connected to the first sub-initialization signal line through a second type of via.

31. The display panel according to claim 30, characterized in that, The display panel further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate, and the first scan signal line is located on the fourth conductive layer.

32. The display panel according to claim 31, characterized in that, The first sub-initialization signal line is located in the fourth conductive layer; and / or, the third connection line is located in the fourth conductive layer.

33. The display panel according to claim 28, characterized in that, The first scan signal line extends along a first direction, and the orthographic projection of the first scan signal line on the substrate overlaps with the orthographic projection of the gate of the first transistor on the substrate. At the overlapping position, the first scan signal line is connected to the gate of the first transistor through a second type of via.

34. The display panel according to claim 30, characterized in that, The first active layer includes a second active portion extending along the first direction; the channel region of the second driving transistor is located in the second active portion; the first sub-initialization signal line is located on the side of the first scan signal line away from the second active portion.

35. The display panel according to claim 28, characterized in that, The display panel also includes a second transistor, the gate of which is located in the third conductive layer, the channel region of which is located in the first active layer, and the channel region of which is located at the position where the gate of which is projected onto the first active layer.

36. The display panel according to claim 35, characterized in that, The first active layer includes a first active portion extending along a first direction, and the channel region of the first driving transistor is located in the first active portion; the first active layer includes a second active portion extending along the first direction; the channel region of the second driving transistor is located in the second active portion; the first active layer further includes a third active portion and a fourth active portion extending along a second direction, which intersects with the first direction; the third active portion is connected to a first end of the first active portion and a first end of the second active portion; the fourth active portion is connected to a second end of the first active portion and a second end of the second active portion; the first electrode of the second transistor is connected to the second electrode of the first driving transistor and the second electrode of the second driving transistor through the fourth active portion; the second electrode of the second transistor is connected to the driving gate of the second driving transistor through a fourth connecting line; the gate of the second transistor is connected to the first scan signal line through a second type of via.

37. The display panel according to claim 36, characterized in that, The first terminal of the second transistor is connected to the first end of the fourth connection line via a second type of via, and the driving gate of the second driving transistor is connected to the second end of the fourth connection line via a second type of via.

38. The display panel according to claim 35, characterized in that, The second transistor is used to compensate for the threshold voltage of the driving transistor.

39. The display panel according to claim 36, characterized in that, The first active layer further includes a fifth active portion, wherein the channel region of the second transistor is located in the fifth active portion; the fifth active portion is connected to the first active portion and the second active portion through the fourth active portion.

40. The display panel according to claim 36, characterized in that, Along the second direction, the second active portion is located between the first active portion and the first scan signal line.

41. The display panel according to claim 36, characterized in that, Along the second direction, the second driving transistor is located between the first driving transistor and the first scan signal line.

42. The display panel according to claim 36, characterized in that, The second transistor and the first transistor are arranged along the first direction.

43. The display panel according to claim 39, characterized in that, It also includes a third transistor, the gate of which is located in the third conductive layer, the channel region of which is located in the first active layer, and the channel region of which is located at the position of the gate of the second transistor projected onto the first active layer.

44. The display panel according to claim 43, characterized in that, The first active layer further includes a sixth active portion along the second direction. The sixth active portion is located on the side of the first active portion away from the fifth active portion. The sixth active portion is connected to the first active portion through the third active portion. The channel region of the third transistor is located in the sixth active portion.

45. The display panel according to claim 43, characterized in that, The display panel further includes a second initialization signal line. The first electrode of the third transistor is electrically connected to the second initialization signal line through a second type of via. The second electrode of the third transistor is connected to the first electrode of the first driving transistor and the first electrode of the second driving transistor through a third active part.

46. ​​The display panel according to claim 45, characterized in that, The second initialization signal line extends along the first direction.

47. The display panel according to claim 45, characterized in that, The display panel further includes a second scan signal line, the orthographic projection of the second scan signal line on the substrate overlaps with the orthographic projection of the gate of the third transistor on the substrate, and at the overlap position, the second scan signal line is connected to the gate of the third transistor through a second type of via.

48. The display panel according to claim 47, characterized in that, The second scan signal line is located between the second initialization signal line and the first scan signal line.

49. The display panel according to claim 47, characterized in that, The second scan signal line extends along the first direction.

50. The display panel according to claim 47, characterized in that, The display panel further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate; the second scan signal line is located on the fourth conductive layer.

51. The display panel according to claim 50, characterized in that, The second initialization signal line is located in the fourth conductive layer.

52. The display panel according to claim 47, characterized in that, The display panel also includes a fourth transistor, a fifth transistor, and a second capacitor; The active layer further includes a third active layer, which is on the same layer as the first active layer but not connected; the channel regions of the fourth transistor and the fifth transistor are located in the third active layer, the channel region of the fourth transistor is located at the orthogonal projection position of the gate of the fourth transistor in the third active layer, the channel region of the fifth transistor is located at the orthogonal projection position of the gate of the fifth transistor in the third active layer, and the gates of the fourth transistor and the fifth transistor are located in the third conductive layer.

53. The display panel according to claim 52, characterized in that, The third active layer is located on the side of the first active portion away from the second active portion.

54. The display panel according to claim 52, characterized in that, The third active layer extends along the second direction.

55. The display panel according to claim 52, characterized in that, The display panel also includes a third initialization signal line. The second electrode of the fourth transistor is connected to the third initialization signal line through a second type of via. The first electrode of the fourth transistor is connected to the first plate of the second capacitor through a fifth connection line. The second plate of the second capacitor is connected to the second electrode of the first driving transistor and the second electrode of the first driving transistor through a sixth connection line.

56. The display panel according to claim 55, characterized in that, The third initialization signal line extends along the first direction.

57. The display panel according to claim 55, characterized in that, The display panel further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate; the third initialization signal line is located on the fourth conductive layer.

58. The display panel according to claim 57, characterized in that, The third initialization signal line is located between the first scan signal line and the second scan signal line.

59. The display panel according to claim 55, characterized in that, The first plate of the second capacitor is located on the first conductive layer, and the second plate of the second capacitor is located on the second conductive layer.

60. The display panel according to claim 55, characterized in that, The first end of the fifth connection line is connected to the second electrode of the fourth transistor through a second type of via, and the second end of the fifth connection line is connected to the first electrode plate of the second capacitor through a first type of via.

61. The display panel according to claim 55, characterized in that, The first end of the sixth connection line is connected to the second plate of the second capacitor through a first type of via, and the second end of the sixth connection line is connected to the second electrode of the first driving transistor and the second electrode of the second driving transistor through a second type of via.

62. The display panel according to claim 55, characterized in that, The display panel also includes a data line, the first electrode of the fifth transistor is connected to the first plate of the second capacitor through the fifth connecting line, and the second electrode of the fifth transistor is connected to the data line through the seventh connecting line.

63. The display panel according to claim 62, characterized in that, The first end of the seventh connection line is connected to the second terminal of the fifth transistor through a second type of via, and the second end of the seventh connection line is connected to the data line through a third type of via.

64. The display panel according to claim 55, characterized in that, The display panel further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate; the fifth connecting line is located on the fourth conductive layer.

65. The display panel according to claim 61, characterized in that, The display panel further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate; the sixth connecting line is located on the fourth conductive layer.

66. The display panel according to claim 63, characterized in that, The display panel further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate; the seventh connecting line is located on the fourth conductive layer.

67. The display panel according to claim 62, characterized in that, The display panel further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; the display panel further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate, and the data line is located on the fifth conductive layer; the data line extends along the second direction.

68. The display panel according to claim 52, characterized in that, The orthographic projection of the second scan signal line on the substrate at least partially overlaps with the orthographic projection of the gate of the fourth transistor on the substrate. At the overlap location, the second scan signal line is connected to the gate of the fourth transistor through a second type of via.

69. The display panel according to claim 52, characterized in that, The third transistor and the fourth transistor are arranged along the first direction.

70. The display panel according to claim 52, characterized in that, The display panel further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; the display panel also includes a third scan signal line located on the third conductive layer, the third scan signal line including the gate of the fifth transistor, or the third scan signal line located on the fourth conductive layer, the orthogonal projection on the substrate at least partially covering the gate of the fifth transistor, the third scan signal line being connected to the gate of the fifth transistor through a second type of via.

71. The display panel according to claim 70, characterized in that, The third scan signal line is located on the side of the second scan signal line that is away from the first scan signal line.

72. The display panel according to claim 70, characterized in that, The pixel circuit further includes a sixth transistor, the channel region of which is located in the first active layer, and the gate of which is located in the third conductive layer; the channel region of which is located at the orthogonal projection of the gate of which is located in the first active layer; the first electrode of which is connected to the first plate of the first capacitor via an eighth connection line; and the second electrode of which is connected to the second sub-initialization signal line via a ninth connection line.

73. The display panel according to claim 72, characterized in that, The first initialization signal line includes a first sub-initialization signal line extending along a first direction; the first initialization signal line includes a second sub-initialization signal line extending along a second direction, and the second sub-initialization signal line is connected to the first sub-initialization signal line through a third type of via.

74. The display panel according to claim 72, characterized in that, The first end of the eighth connection line is connected to the first electrode of the sixth transistor through a second type of via, and the second end of the eighth connection line is connected to the first electrode plate of the first capacitor through a first type of via.

75. The display panel according to claim 72, characterized in that, The first end of the ninth connection line is connected to the second electrode of the sixth transistor through a second type of via, and the first end of the ninth connection line is connected to the second sub-initialization signal line.

76. The display panel according to claim 72, characterized in that, The display panel further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; the display panel further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; the fifth conductive layer further includes a tenth connecting line, the orthographic projection of the tenth connecting line on the substrate overlaps with the orthographic projection of the eighth connecting line on the substrate, and the tenth connecting line is connected to the eighth connecting line through a third type of via.

77. The display panel according to claim 76, characterized in that, The display panel further includes a light-emitting device, which includes a first electrode, a light-emitting layer, and a second electrode stacked on the conductive layer away from the substrate. The orthogonal projection of the first electrode on the substrate at least partially covers the orthogonal projection of the tenth connecting line on the substrate. The first electrode is connected to the tenth connecting line through a fourth type of via.

78. The display panel according to claim 76, characterized in that, The orthographic projection of the tenth connection line on the substrate overlaps the orthographic projection of the channel region of the sixth transistor on the substrate; The third scan signal line is located in the third conductive layer and includes the gate of the sixth transistor. Alternatively, the third scan signal line is located in the fourth conductive layer, and its orthogonal projection on the substrate at least partially covers the gate of the sixth transistor. The third scan signal line is connected to the gate of the sixth transistor through a second type of via.

79. The display panel according to claim 72, characterized in that, The sixth transistor and the fifth transistor are arranged along the first direction.

80. The display panel according to claim 76, characterized in that, The display panel further includes a first light-emitting control signal line and a second light-emitting control signal line, which extend along the first direction. The pixel circuit further includes a seventh transistor and an eighth transistor, the gates of the seventh transistor and the eighth transistor being located in the third conductive layer, and the channel regions of the seventh transistor and the eighth transistor being located in the first active layer; the channel region of the seventh transistor is located at the orthogonal projection position of the gate of the seventh transistor in the first active layer, and the channel region of the eighth transistor is located at the orthogonal projection position of the gate of the eighth transistor in the first active layer.

81. The display panel according to claim 80, characterized in that, The channel region of the seventh transistor is located in the fifth active region.

82. The display panel according to claim 80, characterized in that, The channel region of the eighth transistor is located in the third active region.

83. The display panel according to claim 80, characterized in that, The first terminal of the seventh transistor is connected to the power line through a second type of via, and the second terminal of the seventh transistor is connected to the second terminal of the first driving transistor and the second driving transistor through a fourth active part.

84. The display panel according to claim 83, characterized in that, The power line includes a second sub-power line extending along the first direction and a first sub-power line extending along the first direction. The second sub-power line and the first sub-power line are disposed on different layers and connected by a third type of via. The first electrode of the seventh transistor is connected to the first sub-power line through a second type of via.

85. The display panel according to claim 84, characterized in that, The display panel further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; the second sub-power line is located on the fourth conductive layer, and the first sub-power line is located on the fifth conductive layer.

86. The display panel according to claim 84, characterized in that, The orthographic projection of the first sub-power line on the substrate covers the orthographic projections of the channel regions of the first driving transistor, the second driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor on the substrate, respectively.

87. The display panel according to claim 80, characterized in that, The display panel also includes a light-emitting device, wherein the orthogonal projection of the first electrode of the light-emitting device onto the substrate at least partially covers the orthogonal projection of the channel region of the eighth transistor onto the substrate.

88. The display panel according to claim 80, characterized in that, The first electrode of the eighth transistor is connected to the first electrode of the first driving transistor and the first electrode of the second driving transistor in the third active part, and the second electrode of the eighth transistor is connected to the first plate of the first capacitor through the eighth connecting line.

89. The display panel according to claim 80, characterized in that, The first light emission control signal line includes the gate of the seventh transistor; or the first light emission control signal line is located in the fourth conductive layer, and the orthogonal projection of the first light emission control signal line on the substrate at least partially covers the orthogonal projection of the gate of the seventh transistor on the substrate, and the first light emission control signal line is connected to the gate of the seventh transistor through a second type of via.

90. The display panel according to claim 80, characterized in that, The second light emission control signal line includes the gate of the eighth transistor; or the second light emission control signal line is located in the fourth conductive layer, and the orthogonal projection of the second light emission control signal line on the substrate at least partially covers the orthogonal projection of the gate of the eighth transistor on the substrate, and the second light emission control signal line is connected to the gate of the eighth transistor through a second type of via.

91. The display panel according to claim 80, characterized in that, The first light emission control signal line is located on the side of the first sub-initialization signal line of the first initialization signal line that is away from the first scan signal line; the second light emission control signal line is located on the side of the second initialization signal line that is away from the first scan signal line.

92. The display panel according to claim 86, characterized in that, The second sub-power line is located on the side of the first light emission control signal line that is away from the first scan signal line.

93. The display panel according to claim 83, characterized in that, The first conductive layer further includes a first light-shielding layer and a second light-shielding layer; Along the first direction, the first light-shielding layer is located between the first plate of the first capacitor and the first plate of the second capacitor; along the second direction, the second light-shielding layer and the first light-shielding layer are arranged along the second direction.

94. The display panel according to claim 93, characterized in that, The orthogonal projection of the first light-shielding layer on the substrate covers at least a portion of the orthogonal projection of the channel region of the third transistor on the substrate, at least a portion of the orthogonal projection of the channel region of the fourth transistor on the substrate, and at least a portion of the orthogonal projection of the channel region of the fifth transistor on the substrate.

95. The display panel according to claim 93, characterized in that, The display panel further includes a first light-emitting control signal line and a second light-emitting control signal line, which extend along the first direction. The pixel circuit further includes a seventh transistor and an eighth transistor, the gates of the seventh transistor and the eighth transistor being located in the third conductive layer, and the channel regions of the seventh transistor and the eighth transistor being located in the first active layer; the channel region of the seventh transistor is located at the orthographic projection of the gate of the seventh transistor onto the first active layer, and the channel region of the eighth transistor is located at the orthographic projection of the gate of the eighth transistor onto the first active layer; the orthographic projection of the second light-shielding layer onto the substrate covers at least a portion of the orthographic projection of the channel region of the first transistor onto the substrate, at least a portion of the orthographic projection of the channel region of the second transistor onto the substrate, and at least a portion of the orthographic projection of the channel region of the seventh transistor onto the substrate.

96. The display panel according to claim 95, characterized in that, The pixel circuit further includes a sixth transistor, wherein the orthographic projection of the first plate of the first capacitor onto the substrate covers at least a portion of the orthographic projection of the channel region of the sixth transistor onto the substrate and at least a portion of the orthographic projection of the channel region of the eighth transistor onto the substrate.

97. The display panel according to claim 96, characterized in that, The first plate of the first capacitor includes a main body and a branch. Along the first direction, the branch is located on one side of the main body and extends along the second direction. The orthographic projection of the branch on the substrate covers at least a portion of the orthographic projection of the channel region of the sixth transistor on the substrate and at least a portion of the orthographic projection of the channel region of the eighth transistor on the substrate. The orthographic projection of the main body on the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor on the substrate.

98. The display panel according to claim 93, characterized in that, The display panel also includes a third initialization signal line, the second electrode of the fourth transistor is connected to the third initialization signal line through a second type of via, and the first light-shielding layer is connected to the third initialization signal line through a first type of via.

99. The display panel according to claim 93, characterized in that, The display panel further includes a second initialization signal line, and the first electrode of the third transistor is electrically connected to the second initialization signal line through a second type of via; the display panel further includes a third initialization signal line, and the second electrode of the fourth transistor is connected to the third initialization signal line through a second type of via; the second light-shielding layer is connected to at least one of the power line, the first initialization signal line, the second initialization signal line and the third initialization signal line.

100. The display panel according to claim 43, characterized in that, The display panel further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; the display panel further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; the display panel further includes: A capacitor insulating layer is located between the first conductive layer and the second conductive layer, and the orthographic projection of the capacitor insulating layer on the substrate covers the orthographic projection of the first conductive layer on the substrate. A first gate insulating layer is located between the second conductive layer and the active layer, and the orthographic projection of the first gate insulating layer on the substrate covers the orthographic projection of the second conductive layer on the substrate; A second gate insulating layer is located between the active layer and the third conductive layer, and the orthographic projection of the second gate insulating layer on the substrate covers the orthographic projection of the active layer on the substrate. An interlayer insulating layer is located between the third conductive layer and the fourth conductive layer, and the orthographic projection of the interlayer insulating layer on the substrate covers the orthographic projection of the third conductive layer on the substrate; A first planarization layer is located between the fourth conductive layer and the fifth conductive layer, and the orthographic projection of the first planarization layer on the substrate covers the orthographic projection of the fourth conductive layer on the substrate. A second planarization layer is located on the side of the fifth conductive layer away from the substrate, and the orthographic projection of the second planarization layer on the substrate covers the orthographic projection of the fifth conductive layer on the substrate.

101. The display panel according to claim 100, characterized in that, A first type of via penetrates the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer; or a first type of via penetrates the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and the capacitor insulating layer. The second type of via penetrates the interlayer insulating layer, or the second type of via penetrates both the interlayer insulating layer and the second gate insulating layer; The third type of via penetrates the first planarization layer; The fourth type of via penetrates the second planarization layer.

102. The display panel according to claim 1, characterized in that, The active layer is made of metal oxides.

103. A display device, characterized in that, Includes the display panel as described in any one of claims 1-102.

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