Display device

Abstract

The present disclosure provides a display device including: a first passivation layer including a first insulating layer and a second insulating layer disposed on a portion of the first insulating layer; and a second passivation layer configured to cover the first passivation layer, and the present disclosure provides an advantage of preventing oxygen or moisture from permeating into the encapsulation layer.

Description

Technical Field

[0001] The present disclosure relates to an electronic device having a display, and more particularly, for example and without limitation, to a display device capable of preventing moisture or oxygen from penetrating into an encapsulation layer. Background Art

[0002] As the information society develops, various demands on display devices for displaying images increase. Recently, various types of display devices such as liquid crystal display (LCD) devices, organic light emitting diode (OLED) display devices, etc. have been developed and widely used.

[0003] A display panel included in a display device may include a display area and a non-display area.

[0004] The display area of ​​the display panel may include a through hole, and the optical device may be disposed under the through hole.

[0005] Descriptions provided in the discussion of the background technology section should not be assumed to be prior art simply because they are mentioned in or related to this section. The discussion of the background technology section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the invention

[0006] In the case where such a through hole is formed on a display panel in order to mount an optical device in the display device, the display device may be affected by moisture penetrating into the display panel.

[0007] In order to solve this problem, one or more aspects of the present disclosure may provide a display device capable of preventing moisture or oxygen from penetrating into an encapsulation layer.

[0008] One or more aspects of the present disclosure may provide a display device including an encapsulation layer capable of preventing moisture penetration in a process of forming a through hole.

[0009] One or more aspects of the present disclosure may provide a display device including a second encapsulation layer on a first encapsulation layer, the second encapsulation layer being an inorganic layer, having high spreadability, and capable of preventing moisture or oxygen from penetrating into the first encapsulation layer.

[0010] One or more aspects of the present disclosure may provide a display device that can prevent moisture or oxygen from penetrating into an encapsulation layer and thus be driven with low power.

[0011] According to one or more example embodiments of the present disclosure, a display device may be provided, the display device comprising: a substrate comprising a through hole and a surrounding area surrounding the through hole; a first passivation layer disposed on the substrate and comprising a first insulating layer and a second insulating layer disposed on a portion of the first insulating layer; and a second passivation layer configured to cover the first passivation layer.

[0012] In one or more aspects, the substrate may include a first substrate and a second substrate with an interlayer insulating layer interposed between the first substrate and the second substrate.

[0013] In one or more aspects, the second passivation layer may be configured to cover a side surface of the second insulating layer and a portion of a top surface of the first insulating layer.

[0014] In one or more aspects, the second passivation layer may be disposed in a stepped pattern.

[0015] In one or more aspects, the first passivation layer may be disposed in a stepped pattern.

[0016] In one or more aspects, the first passivation layer may be disposed to be spaced apart from the through-hole, and the second passivation layer may be disposed to be adjacent to the through-hole.

[0017] In one or more aspects, the second insulating layer may include a groove region provided with a plurality of grooves.

[0018] According to one or more aspects of the present disclosure, a display device capable of preventing moisture or oxygen from penetrating into an encapsulation layer may be provided.

[0019] According to one or more aspects of the present disclosure, a display device including an encapsulation layer capable of preventing moisture penetration in a process of forming a through hole may be provided.

[0020] According to one or more aspects of the present disclosure, there may be provided a display device including a second encapsulation layer on a first encapsulation layer, the second encapsulation layer being an inorganic layer, having high spreadability, and capable of preventing moisture or oxygen from penetrating into the first encapsulation layer.

[0021] According to one or more aspects of the present disclosure, a display device capable of preventing moisture or oxygen from penetrating into an encapsulation layer and thus being driven with low power may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the present disclosure, illustrate aspects of the present disclosure, and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0023] Figure 1A , Figure 1B and Figure 1C is a plan view showing an example display device according to aspects of the present disclosure;

[0024] Figure 2 An example system configuration of a display device according to aspects of the present disclosure is shown;

[0025] Figure 3 is an example cross-sectional view of a display area in a display device according to aspects of the present disclosure;

[0026] Figure 4 is an enlarged plan view showing an example optical zone structure of a display panel in a display device according to aspects of the present disclosure;

[0027] Figure 5 It is along Figure 4 A cross-sectional view taken along line II' in the optical region of FIG.

[0028] Figure 6 and Figure 7 It is along Figure 4 A cross-sectional view taken along line II' in the optical region of FIG.

[0029] Figures 8 to 11 It is shown Figure 4 A cross-sectional view of a boundary region between a contact hole and a surrounding region in FIG. 1 ; and

[0030] Fig.12 and Fig.13 It is shown Figure 4 A plan view of the boundary area between the contact hole and the surrounding area.

[0031] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The size, length, thickness, and depiction of layers, regions, and elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0032] Now, reference will be made in detail to the embodiments of the present disclosure, and examples of the embodiments of the present disclosure may be shown in the accompanying drawings. In the following description, unless otherwise specified, the structures, embodiments, implementations, methods, and operations described herein are not limited to one or more specific examples or examples set forth herein, and may be changed as known in the art. Unless otherwise specified, the same reference numerals always represent the same elements. The names of the various elements used in the following description are selected only for the convenience of writing the specification, and therefore may be different from the names used in the actual product. The advantages and features of the present disclosure and their implementation methods will be explained by the following example embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be considered to be limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that the present disclosure may be sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, in the case where a detailed description of the relevant known functions or configurations may unnecessarily obscure the various aspects of the present disclosure, the detailed description of such known functions or configurations may be omitted. The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings to describe various exemplary embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the accompanying drawings. When the terms "including", "having", "containing", "comprising", "consisting of", "comprising", "forming", etc. are used, one or more other elements may be added unless terms such as "only" are used. Unless the context clearly indicates otherwise, elements described in the singular are intended to include plural elements and vice versa.

[0033] When describing a time relationship, for example, when a time order is described as "after", "afterwards", "next", and "before", it may include discontinuous cases unless "just", "immediately", or "directly" is used.

[0034] Although the terms "first", "second", A, B, (a), (b), etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms because they are not used to define a particular order or priority. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0035] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as individual elements of the first element, the second element, and the third element.

[0036] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be understood that not only the first element may be “directly connected or coupled to” the second element or “directly contact or overlaps” the second element, but also a third element may be “interposed” between the first element and the second element, or the first element and the second element may be “connected or coupled to”, “contacts or overlaps”, etc., with each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc., with each other.

[0037] In the case of describing a positional relationship, for example, when "on", "above", "below", "above", "below", "beside", "next to", etc. are used to describe the positional relationship between two components, one or more other components may be located between the two components unless more restrictive terms such as "close to", "directly", or "adjacent" are used. For example, in the case where one element or layer is disposed "on" another element or layer, a third element or layer may be interposed between the two. In addition, the terms "left", "right", "top", "bottom", "downward", "upward", "up", "down", etc. refer to an arbitrary reference system.

[0038] In addition, when any dimension, relative dimension, etc. is mentioned, even if no relevant description is specified, the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature should be considered to include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully includes all meanings of the term "can".

[0039] Hereinafter, with reference to the accompanying drawings, various exemplary embodiments of the present disclosure will be described in detail.

[0040] Figure 1A , Figure 1B and Figure 1C is a plan view illustrating an example display device 100 according to aspects of the present disclosure.

[0041] Reference Figure 1A , Figure 1B and Figure 1C In one or more example embodiments, the display device 100 may include a display panel 110 for displaying an image, one or more optical electronic devices (11 and / or 12), etc. Here, the optical electronic device may be referred to as a light detector, a light receiver, or a light sensing device. The optical electronic device may include one or more of a camera, a camera lens, a sensor, a sensor for detecting an image, etc.

[0042] The display panel 110 may include a display area AA allowing an image to be displayed and a non-display area NA where no image is displayed.

[0043] A plurality of sub-pixels may be disposed in the display area AA, and a plurality of types of signal lines for driving the plurality of sub-pixels may be disposed in the display area AA, but are not limited thereto.

[0044] The non-display area NA may refer to an area outside the display area AA. Various types of signal lines may be provided in the non-display area NA, and various types of driving circuits may be connected to the various types of signal lines. At least a portion of the non-display area NA may be bent so as not to be visible from the front surface of the display device 100, or may be covered by a housing or a casing (not shown) of the display device 100. The non-display area NA may also be referred to as an edge area or a frame area.

[0045] Reference Figure 1A , Figure 1B and Figure 1C In one or more aspects, in the display device 100, one or more optical electronic devices (11 and / or 12) may be prepared independently of the display panel 110 and installed in the display panel 110, and located below or in the lower part of the display panel 110 (on the side opposite to the viewing surface of the display panel 110), but not limited thereto. Alternatively, one or more optical electronic devices (11 and / or 12) may be formed integrally with the display panel 110.

[0046] Light may enter the front surface (viewing surface) of the display panel 110 , pass through the display panel 110 , and reach one or more optical electronic devices ( 11 and / or 12 ) located below or in the lower portion of the display panel 110 (on the side opposite to the viewing surface).

[0047] The one or more optical electronic devices (11 and / or 12) may be devices capable of receiving or detecting light passing through the display panel 110 and performing a predefined function based on the received light. For example, the one or more optical electronic devices (11 and / or 12) may include one or more of the following: an image capture device such as a camera (image sensor); or a sensor such as a proximity sensor, an illumination sensor, etc.

[0048] Reference Figure 1A , Figure 1B and Figure 1C In one or more aspects, the display panel 110 may include one or more optical areas (OA1 and / or OA2), but is not limited thereto. Figure 1A As shown in the example of , the display area AA may include a first optical area OA1. Figure 1BAs shown in the example of , the display panel 110 may include a first optical area OA1 and a second optical area OA2.

[0049] Reference Figure 1A , Figure 1B and Figure 1C , one or more optical areas (OA1 and / or OA2) may be one or more areas overlapping with one or more optical electronic devices (11 and / or 12). For example, the optical area OA1 is an area overlapping with the first optical electronic device 11, and the optical area OA2 is an area overlapping with the second optical electronic device 12.

[0050] like Figure 1A As shown in the example of , the display area AA may be located outside the first optical area OA1. The display area AA may be configured to surround the first optical area OA1. For example, at least a portion of the first optical area OA1 may overlap with the first optical electronic device 11. Figure 1A Front and side views of an example display device according to aspects of the present disclosure are shown.

[0051] like Figure 1B As shown in the example of , the display area AA may be located outside the first optical area OA1 and the second optical area OA2. The display area AA may be configured to surround the first optical area OA1 and the second optical area OA2. Figure 1B , a portion of the display area AA may exist between the first optical area OA1 and the second optical area OA2. In this embodiment, at least a portion of the first optical area OA1 may overlap with the first optical electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optical electronic device 12. Figure 1B Front, left, and right side views of an example display device according to aspects of the present disclosure are shown.

[0052] like Figure 1C As shown in the example of , the display area AA may be located outside the first optical area OA1 and the second optical area OA2. The display area AA may be configured to surround the first optical area OA1 and the second optical area OA2. Figure 1C , the display area AA may not exist between the first optical area OA1 and the second optical area OA2. For example, the first optical area OA1 and the second optical area OA2 may contact each other (e.g., directly contact each other), but is not limited thereto. In this embodiment, at least a portion of the first optical area OA1 may overlap with the first optical electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second optical electronic device 12. Figure 1CFront, left, and right side views of an example display device according to aspects of the present disclosure are shown.

[0053] In one or more aspects, one or more optical areas (OA1 and / or OA2) need to be configured with a light-transmitting structure. For example, in order to allow light to be transmitted through one or more optical electronic devices (11 and / or 12), one or more optical areas (OA1 and / or OA2) may need to have a light-transmitting structure.

[0054] In one or more aspects, one or more optical electronic devices ( 11 and / or 12 ) that need to receive light may be exposed to the front surface (viewing surface) of the display panel 110 or the display device 100 , but is not limited thereto.

[0055] It should be noted that even if one or more optical electronic devices (11 and / or 12) are devices that need to receive light, one or more optical electronic devices (11 and / or 12) may be located on the back side of the display panel 110 (for example, on the opposite side of its viewing surface) so that light that has passed through the display panel 110 can be received.

[0056] In one example, the first optical electronic device 11 may be, for example, a camera, and the second optical electronic device 12 may be, for example, a sensor, but is not limited thereto. The sensor may be a proximity sensor, an illumination sensor, an infrared sensor, etc. For example, the camera may be a camera lens, an image sensor, or a unit including at least one of a camera lens and an image sensor, and the sensor may be an infrared sensor capable of detecting infrared light.

[0057] In another example, the first optical electronic device 11 may be, for example, a sensor, and the second optical electronic device 12 may be, for example, a camera. For example, the camera may be a camera lens, an image sensor, or a unit including at least one of a camera lens and an image sensor, and the sensor may be an infrared sensor capable of detecting infrared light.

[0058] In the following, for ease of description, the discussion is based on an example in which the first optical electronic device 11 is a camera and the second optical electronic device 12 is a sensor, but is not limited thereto. However, it should be understood that the scope of the present disclosure includes an embodiment in which the first optical electronic device 11 is a sensor and the second optical electronic device 12 is a camera. The camera may be, for example, a camera lens, an image sensor, or a unit including at least one of a camera lens and an image sensor.

[0059] In an example where the first optical electronic device 11 is a camera, the camera may be located at the back of the display panel 110 (e.g., below or in the lower portion of the display panel 110), and is a front camera capable of capturing an object or image in a front direction of the display panel 110. Therefore, a user can capture an image or a target through the first optical electronic device 11 such as a camera while viewing a viewing surface of the display panel 110.

[0060] exist Figure 1A , Figure 1B and Figure 1C In the example of , the first optical area OA1 may have various shapes such as a circle, an ellipse, a quadrangle, a hexagon, an octagon, etc., but is not limited thereto. Figure 1B and Figure 1C In the example of FIG. 1 , the second optical area OA2 may have various shapes such as circle, ellipse, quadrangle, hexagon, octagon, etc., but is not limited thereto. The first optical area OA1 and the second optical area OA2 may have the same or substantially or almost the same shape, or have different shapes.

[0061] Reference Figure 1C In an example where the first optical area OA1 and the second optical area OA2 contact each other (e.g., directly contact each other), the entire optical area including the first optical area OA1 and the second optical area OA2 may also have various shapes such as circle, ellipse, quadrilateral, hexagon, octagon, etc., but is not limited thereto.

[0062] Hereinafter, for the convenience of description related to the shapes of the optical areas (OA1 and OA2), each of the first optical area OA1 and the second optical area OA2 is considered to have a circular shape. However, it should be understood that the scope of the present disclosure includes an example in which at least one of the first optical area OA1 and the second optical area OA2 has a shape other than a circle, such as an ellipse, a quadrangle, a hexagon, an octagon, etc., but is not limited thereto.

[0063] In one or more aspects, when an implementation in which the optical areas (OA1 and OA2) are surrounded by the display area AA is applied to the display device 100, this type of display device 100 may be referred to as a display in which hole-in-active area (HiAA) technology is applied.

[0064] In an example where the HiAA technology is applied to the display device 100, a notch for camera exposure may not be formed in the display panel 110. In order to apply the technology, the display device 100 may have a camera hole formed for camera exposure.

[0065] Since there is no need to form a notch in the display panel 110 , the display device 100 may have further advantages of reducing the size of the frame area and improving the degree of freedom in design due to eliminating the limitation of such a design.

[0066] Figure 2 An example system configuration of the display device 100 according to aspects of the present disclosure is shown.

[0067] Reference Figure 2 , the display device 100 may include a display panel 110 and a display driving circuit as components for displaying one or more images.

[0068] The display driving circuit may be a circuit for driving the display panel 110 , and may include, but is not limited to, the data driving circuit 220 , the gate driving circuit 230 , the display controller 240 , and other circuit components.

[0069] The display panel 110 may include a display area AA that allows an image to be displayed and a non-display area NA that does not display an image. The non-display area NA may be an area outside the display area AA, and may also be referred to as an edge area or a frame area. All or a portion of the non-display area NA may be an area visible from the front surface of the display device 100, or an area that is curved and invisible from the front surface of the display device 100, or an area covered by a housing or casing (not shown) of the display device 100.

[0070] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB, but is not limited thereto. The display panel 110 may further include various types of signal lines to drive the plurality of sub-pixels SP. In addition, the display panel 110 may include one or more optical areas (OA1 and / or OA2).

[0071] In one or more aspects, the display device 100 may be a liquid crystal display device (LCD), a plasma display device (PDP), a field emission display device (FED), etc., or a self-luminous display device (such as an organic light emitting display (OLED) device and a micro LED (micro light emitting diode) display device) that emits light from the display panel 110 itself. In an example where the display device 100 is a self-luminous display device, each of the plurality of sub-pixels SP may include a light emitting element.

[0072] For example, the display device 100 according to various aspects of the present disclosure may be an organic light-emitting display device that uses an organic light-emitting diode (OLED) to implement a light-emitting element ED. In another example, the display device 100 according to various aspects of the present disclosure may be an inorganic light-emitting display device that uses a light-emitting diode based on an inorganic material to implement a light-emitting element. In yet another example, the display device 100 according to various aspects of the present disclosure may be a quantum dot display device implemented using quantum dots as light-emitting elements, and the quantum dots are self-luminous semiconductor crystals. However, the present disclosure is not limited thereto.

[0073] The structure of each of the plurality of sub-pixels SP may be differently configured or designed according to the type of the display device 100. In an example where the display device 100 is a self-luminous display device including self-luminous sub-pixels SP, each sub-pixel SP may include a self-luminous light-emitting element, one or more transistors, one or more capacitors, and the like.

[0074] The various types of signal lines may include, for example, a plurality of data lines DL for carrying data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for carrying gate signals (which may be referred to as scan signals), and the like.

[0075] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be configured to extend in a first direction. Each of the plurality of gate lines GL may be configured to extend in a second direction different from the first direction.

[0076] For example, the first direction may be a column direction or a vertical direction, and the second direction may be a row direction or a horizontal direction, but is not limited thereto. In another example, the first direction may be a row direction or a horizontal direction, and the second direction may be a column direction or a vertical direction.

[0077] The data driving circuit 220 may be a circuit for driving a plurality of data lines DL and may provide data signals to the plurality of data lines DL. The gate driving circuit 230 may be a circuit for driving a plurality of gate lines GL and may provide gate signals to the plurality of gate lines GL.

[0078] The display controller 240 may be a device for controlling the data driving circuit 220 and the gate driving circuit 230 , and may control a driving time of a plurality of data lines DL and a driving time of a plurality of gate lines GL.

[0079] Specifically, the display controller 240 may provide a data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220 , and provide a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230 .

[0080] The display controller 240 may receive input image data from the host system 250 and provide image data Data based on the input image data to the data driving circuit 220 .

[0081] The data driving circuit 220 may provide data signals to the plurality of data lines DL according to driving timing control of the display controller 240 .

[0082] The data driving circuit 220 may receive digital image data Data from the display controller 240 , convert the received image data Data into analog data signals, and output the obtained analog data signals to a plurality of data lines DL.

[0083] The gate driving circuit 230 may provide a gate signal to the plurality of gate lines GL according to the timing control of the display controller 240. The gate driving circuit 230 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage together with various gate driving control signals GCS, generate a gate signal, and provide the generated gate signal to the plurality of gate lines GL.

[0084] In one or more aspects, the data driving circuit 220 may be connected to the display panel 110 via a tape automated bonding (TAB) technique, or connected to a conductive pad such as a bonding pad of the display panel 110 via a chip on glass (COG) technique or a chip on panel (COP) technique, or connected to the display panel 110 via a chip on film (COF) technique, but is not limited thereto.

[0085] In one or more aspects, the gate drive circuit 230 may be connected to the display panel 110 by a tape automated bonding (TAB) technique, or connected to a conductive pad such as a bonding pad of the display panel 110 by a chip on glass (COG) technique or a chip on panel (COP) technique, or connected to the display panel 110 by a chip on film (COF) technique. In one or more aspects, the gate drive circuit 230 may be disposed in the non-display area NA of the display panel 110 by a gate in panel (GIP) technique, but is not limited thereto. Alternatively, the gate drive circuit 230 may be disposed in the display area AA of the display panel 110. The gate drive circuit 230 may be disposed on the substrate SUB, or connected to the substrate SUB. In an example where the gate drive circuit 230 is implemented by the GIP technique, the gate drive circuit 230 may be disposed in the non-display area NA of the substrate SUB. In an example where the gate drive circuit 230 is implemented by a chip on glass (COG) technique, a chip on film (COF) technique, etc., the gate drive circuit 230 may be connected to the substrate SUB.

[0086] In one or more aspects, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area AA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be configured not to overlap with the sub-pixels SP, or to overlap with one or more or all of the sub-pixels SP, or to overlap with corresponding at least one or more portions of one or more sub-pixels SP, but is not limited thereto.

[0087] The data driving circuit 220 may be located and / or electrically connected to, but not limited to, only one side or a portion (e.g., an upper edge or a lower edge) of the display panel 110. In one or more aspects, the data driving circuit 220 may be located and / or electrically connected to, but not limited to, two sides or portions (e.g., an upper edge and a lower edge) of the display panel 110 or at least two of the four sides or portions (e.g., an upper edge, a lower edge, a left edge, and a right edge) of the display panel 110, depending on a driving scheme, a panel design scheme, etc.

[0088] The gate drive circuit 230 may be located and / or electrically connected to, but not limited to, only one side or part (e.g., the left edge or the right edge) of the display panel 110, but is not limited thereto. In addition, according to a driving scheme, a panel design scheme, etc., the gate drive circuit 230 may be located and / or electrically connected to, but not limited to, at least two of the four sides or parts (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the panel 110. For example, the gate drive circuit 230 may be located and / or electrically connected to, but not limited to, two sides or parts (e.g., the left edge and the right edge) of the display panel 110.

[0089] The display controller 240 may be implemented in a separate component from the data driving circuit 220 , or incorporated in the data driving circuit 220 and thus implemented in an integrated circuit.

[0090] The display controller 240 may be a timing controller used in a typical display technology, or may be a controller or control device capable of performing other control functions in addition to the functions of a typical timing controller. In one or more exemplary embodiments, the display controller 240 may be a controller or control device different from the timing controller, or a circuit or component included in the controller or control device. The display controller 240 may be implemented with various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, etc., but is not limited thereto.

[0091] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and electrically connected to the gate driving circuit 230 and the data driving circuit 220 through the printed circuit board, the flexible printed circuit, or the like.

[0092] The display controller 240 may send signals to and receive signals from the data driving circuit 220 via one or more predefined interfaces. For example, such interfaces may include a low voltage differential signaling (LVDS) interface, an embedded clock dot-dot interface (EPI), a serial peripheral interface (SPI), etc. Similarly, the display controller 240 may send signals to and receive signals from the gate driving circuit 230 via one or more predefined interfaces.

[0093] In one or more aspects, in order to further provide touch sensing function and image display function, the display device 100 may further include at least one touch sensor and a touch sensing circuit capable of detecting the occurrence of a touch event through a touch object such as a finger or a pen, or detecting a corresponding touch position (or touch coordinates) by sensing the touch sensor.

[0094] As an example, the touch sensing circuit may include, but is not limited to, a touch driving circuit 260 capable of generating and providing touch sensing data by driving and sensing a touch sensor, a touch controller 270 capable of detecting the occurrence of a touch event or detecting a touch position (or touch coordinates) using the touch sensing data, and one or more other components.

[0095] As an example, the touch sensor may include, but is not limited to, a plurality of touch electrodes. The touch sensor may also include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit 260.

[0096] The touch sensor may be implemented in the form of a touch panel outside the display panel 110, or may be integrated inside the display panel 110. In an example where the touch sensor is implemented in the form of a touch panel outside the display panel 110, such a touch sensor may be referred to as an add-on type. In an example where an add-on type touch sensor is provided in the display device 100, the touch panel and the display panel 110 may be manufactured separately and combined during assembly. The add-on type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0097] In an example where the touch sensor is integrated inside the display panel 110 , the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during a process of manufacturing the display panel 110 .

[0098] The touch driving circuit 260 may provide a touch driving signal to at least one of the plurality of touch electrodes, and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0099] The touch sensing circuit can perform touch sensing. For example, the touch sensing circuit can perform touch sensing through self-capacitance sensing technology or mutual capacitance sensing technology, but is not limited thereto.

[0100] In an example where the touch sensing circuit performs touch sensing through self-capacitance sensing technology, the touch sensing circuit may perform touch sensing based on capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0101] According to the self-capacitance sensing technology, each of the multiple touch electrodes can act as both a driving touch electrode and a sensing touch electrode. The touch drive circuit 260 can drive all or one or more of the multiple touch electrodes and sense all or one or more of the multiple touch electrodes.

[0102] In examples where the touch sensing circuit performs touch sensing through mutual capacitance sensing technology, the touch sensing circuit may perform touch sensing based on capacitance between touch electrodes.

[0103] According to the mutual capacitance sensing technology, a plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 may drive the driving touch electrodes and sense the sensing touch electrodes.

[0104] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented as separate devices or as a single device, but are not limited thereto. In addition, the touch driving circuit 260 and the data driving circuit 220 may be implemented as separate devices or as a single device, but are not limited thereto.

[0105] The display device 100 may further include a power supply circuit for supplying various types of power to the display driving circuit and / or the touch sensing circuit.

[0106] In some aspects, the display device 100 may be a mobile terminal such as a notebook computer, a smart phone, a tablet computer, etc., or a monitor, a television (TV), etc., but is not limited thereto. Such a device may be configured in various types, sizes, and shapes. The display device 100 according to various aspects of the present disclosure is not limited thereto, and may include various types, sizes, and shapes of display devices configured to display information or images.

[0107] Figure 3 is an example cross-sectional view of a portion of a display area AA of a display panel 110 according to aspects of the present disclosure.

[0108] Reference Figure 3 , the substrate SUB may be disposed at the bottom of the display panel 110. For example, the substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. The interlayer insulating layer IPD may be interposed between the first substrate SUB1 and the second substrate SUB2. Figure 3 As shown, the interlayer insulating layer IPD may be disposed on the first substrate SUB1, and the second substrate SUB2 may be disposed on the interlayer insulating layer IPD, but is not limited thereto. Since the substrate SUB includes the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2, the substrate SUB may prevent or reduce moisture or oxygen from penetrating into the display panel 110. The first substrate SUB1 and the second substrate SUB2 may be, for example, polyimide (PI) substrates, but are not limited thereto. The first substrate SUB1 may be referred to as a first main PI substrate, and the second substrate SUB2 may be referred to as a second PI substrate.

[0109] Reference Figure 3 Various types of patterns (ACT, SD1, GATE) for forming one or more transistors such as a driving transistor DRT, various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0), and various types of metal patterns (TM, GM, ML1, ML2) may be disposed on or over a substrate SUB.

[0110] Reference Figure 3 , the multi-buffer layer MBUF may be disposed on the second substrate SUB2 , and the first active buffer layer ABUF1 may be disposed on the multi-buffer layer MBUF.

[0111] The first metal layer ML1 and the second metal layer ML2 may be disposed on the first active buffer layer ABUF1. For example, the first metal layer ML1 and the second metal layer ML2 may be light shielding layers LS for shielding light.

[0112] The second active buffer layer ABUF2 may be disposed on the first metal layer ML1 and the second metal layer ML2. Specifically, the second active buffer layer ABUF2 may be disposed on the first active buffer layer ABUF1, the first metal layer ML1 and the second metal layer ML2. The active layer ACT of the driving transistor DRT may be disposed on the second active buffer layer ABUF2.

[0113] The gate insulating layer GI may be configured to cover the active layer ACT. Specifically, the gate insulating layer GI may be configured to cover the second active buffer layer ABUF2 and the active layer ACT.

[0114] The gate electrode GATE of the driving transistor DRT may be patterned and disposed on the gate insulating layer GI. In one aspect, the gate material layer GM may be disposed on the gate insulating layer GI together with the gate electrode GATE of the driving transistor DRT at a position different from the position where the driving transistor DRT is disposed.

[0115] The first interlayer insulating layer ILD1 may be configured to cover the gate electrode GATE and the gate material layer GM. Specifically, the first interlayer insulating layer ILD1 may be configured to cover the gate insulating layer GI, the gate electrode GATE, and the gate material layer GM. The metal pattern TM may be patterned and disposed on the first interlayer insulating layer ILD1. The metal pattern TM may be located at a position different from the position where the drive transistor DRT is formed. The second interlayer insulating layer ILD2 may be configured to cover the metal pattern TM on the first interlayer insulating layer ILD1. Specifically, the second interlayer insulating layer ILD2 may be configured to cover the metal pattern TM and the first interlayer insulating layer ILD1.

[0116] Two first source-drain patterns SD1 may be patterned and disposed on the second interlayer insulating layer ILD2. One of the two first source-drain patterns SD1 may be a source node of the driving transistor DRT, and the other may be a drain node of the driving transistor DRT.

[0117] The two first source-drain patterns SD1 may be electrically connected to the first and second sides of the active layer ACT, respectively, through contact holes formed in the second interlayer insulating layer ILD2 , the first interlayer insulating layer ILD1 , and the gate insulating layer GI.

[0118] Reference Figure 3 , the second interlayer insulating layer ILD2 may include a second-first interlayer insulating layer ILD2-1 and a second-second interlayer insulating layer ILD2-2. The second-first interlayer insulating layer ILD2-1 may be configured to cover the metal pattern TM. Specifically, the second-first interlayer insulating layer ILD2-1 may be configured to cover the metal pattern TM and the first interlayer insulating layer ILD1. The second-second interlayer insulating layer ILD2-2 may be located on the second-first interlayer insulating layer ILD2-1.

[0119] A portion of the active layer ACT overlapping the gate electrode GATE may be used as a channel region. One of the two first source-drain patterns SD1 of the driving transistor DRT may be connected to a first side of the channel region of the active layer ACT, and the other of the two first source-drain patterns SD1 may be connected to a second side of the channel region of the active layer ACT.

[0120] The passivation layer PAS0 may be configured to cover the two first source-drain patterns SD1. Specifically, the passivation layer PAS0 may be configured to cover the two first source-drain patterns SD1 and the second-second interlayer insulating layer ILD2-2. The planarization layer PLN may be disposed on the passivation layer PAS0. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0121] The first planarization layer PLN1 may be disposed on the passivation layer PAS0. The second planarization layer PLN2 may be disposed on the first planarization layer PLN1.

[0122] The second source-drain pattern SD2 may be patterned and disposed on the first planarization layer PLN1. The second source-drain pattern SD2 may be connected to one of the two first source-drain patterns SD1 through a contact hole formed in the first planarization layer PLN1.

[0123] The second planarization layer PLN2 may be configured to cover the second source-drain pattern SD2. Specifically, the second planarization layer PLN2 may be disposed on the first planarization layer PLN1 and the second source-drain pattern SD2. Thereafter, a portion of the second planarization layer PLN2 may be removed by etching. The light emitting element ED of the sub-pixel SP may be disposed on the second planarization layer PLN2.

[0124] According to the example stacked structure of the light emitting element ED, the anode electrode AE ​​may be disposed on the second planarization layer PLN2. The anode electrode AE ​​may be electrically connected to the second source-drain pattern SD2 through a contact hole formed in the second planarization layer PLN2. The anode electrode AE ​​may have a multilayer structure including a transparent conductive film and an opaque conductive film having high reflection efficiency. The transparent conductive film may be made of a material having a relatively high work function value such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film may have a single layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti or an alloy thereof.

[0125] The bank BANK may be configured to cover a portion of the anode electrode AE. Specifically, the bank BANK may be configured to cover a portion of the anode electrode AE ​​and the second planarization layer PLN2. A portion of the levee BANK corresponding to the light emitting area EA of the sub-pixel SP may be opened. The bank BANK may include an insulating material. As an example, the bank BANK may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin and / or a polyimide resin. Alternatively, the bank BANK may include an inorganic insulating material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide or titanium oxide. In addition, the bank BANK may include a black dye so as to absorb light incident from the outside.

[0126] A portion of the anode electrode AE ​​may be exposed through the opening (opening portion) of the bank BANK. At least a portion of the light emitting layer EL may be located on at least one side surface of the bank BANK and within the opening (opening portion) of the bank BANK. All or at least a portion of the light emitting layer EL may be located between adjacent banks.

[0127] In the opening of the bank BANK, the light emitting layer EL may contact the anode electrode AE. The cathode electrode CE may be disposed on the light emitting layer EL. Specifically, the cathode electrode CE may be disposed on the light emitting layer EL and on a portion of the bank BANK.

[0128] The light emitting element ED may be formed by an anode electrode AE, a light emitting layer EL, and a cathode electrode CE. The light emitting layer EL may include an organic material layer. For example, the light emitting layer EL may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but the present disclosure is not limited thereto.

[0129] The encapsulation layer ENCAP may be disposed on the stack of light emitting elements ED.

[0130] The encapsulation layer ENCAP may have a single-layer stack or a multi-layer stack. Figure 3 As shown, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2. The second encapsulation layer PCL may be interposed between the first encapsulation layer PAS1 and the third encapsulation layer PAS2.

[0131] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 may be inorganic layers, and the second encapsulation layer PCL may be an organic layer, but is not limited thereto. For example, among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL may have the largest thickness, but is not limited thereto. In this example, the second encapsulation layer PCL may be used as a planarization layer. The first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2 may also be referred to as a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, respectively.

[0132] The first encapsulation layer PAS1 may be disposed on the cathode electrode CE and may be disposed as the stack closest to the light emitting element ED. The first encapsulation layer PAS1 may include an inorganic insulating material that may be deposited at a low temperature. In one or more aspects, the first encapsulation layer PAS1 may include a plurality of insulating layers. For example, the first encapsulation layer PAS1 may include, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), and the like. Since the first encapsulation layer PAS1 may be deposited in a low temperature atmosphere, during the deposition process, the first encapsulation layer PAS1 may prevent the light emitting layer EL including an organic material susceptible to a high temperature atmosphere from being damaged.

[0133] In a plan view, the second encapsulation layer PCL may have a smaller area or size than the first encapsulation layer PAS1. For example, the second encapsulation layer PCL may be configured to expose both ends or edges of the first encapsulation layer PAS1. The second encapsulation layer PCL may be used as a buffer for releasing stress between corresponding layers when the display device 100 is bent or folded, and is also used to enhance planarization performance. For example, the second encapsulation layer PCL may include an organic insulating material such as an acrylic resin, an epoxy resin, a polyimide, a polyethylene, a silicon oxycarbide (SiOC), and the like. The second encapsulation layer PCL may be formed, for example, by inkjet technology.

[0134] The third encapsulation layer PAS2 may be disposed above the substrate SUB on which the second encapsulation layer PCL is disposed, and is configured to cover the respective top and side surfaces of the second encapsulation layer PCL and the first encapsulation layer PAS1. The third encapsulation layer PAS2 may minimize or prevent external moisture or oxygen from penetrating into the first encapsulation layer PAS1 and the second encapsulation layer PCL. For example, the third encapsulation layer PAS2 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), and the like.

[0135] Reference Figure 3In an example where the touch sensor TS is embedded in the display panel 110, the touch sensor TS may be disposed on the encapsulation layer ENCAP. The structure of the touch sensor will be described in detail below.

[0136] The touch buffer layer T-BUF may be disposed on the encapsulation layer ENCAP. Specifically, the touch buffer layer T-BUF may be disposed on the third encapsulation layer PAS2. The touch sensor TS may be disposed on the touch buffer layer T-BUF.

[0137] The touch sensor TS may include a touch sensor metal TSM and at least one bridge metal BRG located in different layers. The touch sensor metal TSM may be disposed on the bridge metal BRG and a portion of the touch interlayer insulating layer T-ILD.

[0138] The touch interlayer insulating layer T-ILD may be disposed between the touch sensor metal TSM and the bridge metal BRG.

[0139] For example, the touch sensor metal TSM may include a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM disposed adjacent to each other. In an example in which the third touch sensor metal TSM is disposed between the first touch sensor metal TSM and the second touch sensor metal TSM, and the first touch sensor metal TSM and the second touch sensor metal TSM need to be electrically connected to each other, the first touch sensor metal TSM and the second touch sensor metal TSM may be electrically connected to each other through a bridge metal BRG located in different layers. The bridge metal BRG may be electrically insulated from the third touch sensor metal TSM by the touch interlayer insulating layer T-ILD.

[0140] When the touch sensor TS is provided in the display panel 110, a chemical solution (e.g., a developer or an etchant) used in a corresponding process or moisture from the outside of the display panel 110 may be generated or introduced. In this case, by providing the touch sensor TS on the touch buffer layer T-BUF, such a chemical solution or moisture can be prevented from penetrating into the light emitting layer EL including an organic material during the manufacturing process of the touch sensor TS. Therefore, the touch buffer layer T-BUF can prevent damage to the light emitting layer EL that is susceptible to the chemical solution or moisture.

[0141] In order to prevent damage to the light-emitting layer EL including an organic material that is susceptible to high temperatures, the touch buffer layer T-BUF may be formed at a low temperature less than or equal to a predetermined temperature (e.g., 100 degrees (°C)) and formed using an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer layer T-BUF may include an acrylic, epoxy, or siloxane material. When the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch sensor metal located on the touch buffer layer T-BUF may be cracked or broken. Even when the display device 100 is bent, the touch buffer layer T-BUF including an organic insulating material and having a planarization property can prevent damage to the encapsulation layer ENCAP and / or cracking or breaking of the metal (TSM, BRG) included in the touch sensor TS.

[0142] The protection layer PAC may be configured to cover the touch sensor TS. The protection layer PAC may be, for example, an organic insulating layer. Specifically, the protection layer PAC may be configured to cover the touch sensor TS and the touch interlayer insulating layer T-ILD.

[0143] Figure 4 is an enlarged plan view illustrating an example optical zone structure of the display panel 110 in the display device 100 according to aspects of the present disclosure.

[0144] Reference Figure 4 , an optical area OA may be provided in the display area AA. A plurality of pixels (not shown) may be provided adjacent to the optical area OA. The optical area OA may be Figures 1A to 1C Any one of the first optical area OA1 or the second optical area OA2.

[0145] Reference Figure 4 In one or more example embodiments, the optical area OA may include a through hole TH and a surrounding area SA surrounding the through hole TH, and the display area AA may be located outside the surrounding area SA. One or more rough patterns RP may be provided in the surrounding area SA. For example, a sub-pixel for displaying an image may not be located in the optical area OA.

[0146] In one or more aspects, the optical electronic device located below the display panel may be configured to partially overlap with the through hole TH. The optical electronic device may be the first optical electronic device 11 described above.

[0147] The through hole TH may be formed when the corresponding portion of the substrate is cut and removed along a trimming line. The shape of the through hole TH may be as follows: Figure 4 The shape shown is circular, but may also have various shapes such as oval, square, hexagonal or octagonal, but is not limited thereto.

[0148] The roughness pattern RP may include an inner roughness pattern IRP and an outer roughness pattern ORP.

[0149] Reference Figure 4 , an outer dam DMO may be located in the surrounding area SA. For example, the outer dam DMO may be located between the inner roughness pattern IRP and the outer roughness pattern ORP, so that the outer dam DMO separates the two patterns (IRP and ORP). Figure 5 The structure of the external barrier DMO is described in detail.

[0150] In one or more aspects, an inner barrier (not shown) may be further located in the display area AA. For example, the inner barrier may be located outside the inner roughness pattern IRP. The inner barrier may be configured to prevent the encapsulation layer (e.g., Figure 3 The second encapsulation layer PCL in the display area AA overflows to the outside. Figure 5 The structure of the inner barrier is described in detail in.

[0151] The shape of each barrier may correspond to the shape of the through hole TH, and may be in a closed curve shape around the through hole TH. For example, each barrier and the through hole TH may have different closed curve shapes, or may have closed curve shapes having the same shape but different sizes. For example, each barrier and the through hole TH may have the same shape such as a circle having a common center, and may be arranged to be spaced apart from each other at a predetermined interval. Each barrier structure may have a three-layer stack disposed on the substrate SUB, but is not limited thereto.

[0152] The shape of the roughness pattern RP may correspond to the shape of the through hole TH and may be in a closed curve shape around the through hole TH. For example, the roughness pattern RP and the through hole TH may have different closed curve shapes, or may have closed curve shapes having the same shape but different sizes. Figure 4 As shown, the roughness pattern RP and the through hole TH may have the same shape, such as a circle, having a common center, and are arranged to be spaced apart from each other at predetermined intervals.

[0153] A plurality of sub-pixels may be provided in the display area AA, and each sub-pixel may include a light-emitting element. In an example where the light-emitting element is an organic light-emitting element such as an organic light-emitting diode, a light-emitting layer (not shown) may be located within the display area AA, and the light-emitting layer may be an organic light-emitting layer including an organic material, but is not limited thereto.

[0154] The organic light emitting layers may be configured to extend to at least a portion of the optical area OA.

[0155] Moisture may penetrate into the organic light emitting layer, in which case defects such as dimming of sub-pixels may occur. Moisture may penetrate into the region where the through hole TH is located.

[0156] The inorganic encapsulation layer (e.g., the inorganic encapsulation layer PAS1 described above) may be located on the rough pattern RP. Moisture may penetrate the inorganic encapsulation layer, in which case the rough pattern RP may play a role in extending the path for moisture to penetrate into the inorganic encapsulation layer. According to the present embodiment, the rough pattern RP may prevent moisture, etc., flowing in through the through hole TH from reaching the light-emitting layer located in the display area AA.

[0157] Figure 5 It is along Figure 4 A cross-sectional view taken along line II' in the optical area OA.

[0158] Reference Figure 4 and Figure 5 , the optical area OA may include the through hole TH and a surrounding area SA surrounding the through hole TH, and the display area AA may be located outside the surrounding area SA.

[0159] In one or more aspects, the optical electronic device located below the display panel may be configured to partially overlap with the through hole TH. The optical electronic device may be the first optical electronic device 11 described above.

[0160] Reference Figure 5 In one or more aspects, the display device 100 may include barrier structures such as an inner barrier DMI located within the display area AA, an outer barrier DMO located within the surrounding area SA, and the like. For example, the outer barrier DMO may be located between the inner rough pattern IRP and the outer rough pattern ORP, so that the outer barrier DMO separates the two patterns (IRP and ORP). Each barrier structure may have a three-layer stack disposed on the substrate SUB, but is not limited thereto. For example, at least one of the barrier structures may include a first layer formed by a portion of a planarization layer, a second layer formed by a portion of a dam BANK, and a third layer formed by a portion of a spacer (not shown). The inner barrier DMI may be configured to prevent an encapsulation layer (e.g., Figure 3 The second encapsulation layer PCL) in the display area overflows to the outside of the display area AA.

[0161] As such a planarization layer, Figure 5 A first planarization layer (PLN1) and a second planarization layer (PLN2) are shown. In the inner barrier DMI, at least a portion of the light emitting layer EL may be located on a portion of the spacer.

[0162] In one or more aspects, one or more elements included in the light emitting element may be stacked on the outer barrier DMO. For example, the light emitting layer EL and the common electrode (not shown) may be stacked on the outer barrier DMO so that the light emitting layer EL and the common electrode extend along the outer barrier DMO or extend over the outer barrier DMO.

[0163] In one or more aspects, a rough pattern may be formed inside and outside the outer barrier DMO. The rough pattern may include an inner rough pattern IRP and an outer rough pattern ORP. For example, the rough pattern may include one or more ridges and one or more valleys formed on at least one surface of at least one insulating layer (e.g., ILD1, ILD2-1, ILD2-2, etc.).

[0164] The light emitting layer EL may be located in at least a portion of the roughness pattern. The light emitting layer EL may be an organic light emitting layer EL including an organic material, but is not limited thereto. The light emitting layer EL may extend from the display area AA to at least a portion of the surrounding area SA.

[0165] Reference Figure 5 In one or more aspects, the light emitting layer EL may be discontinuously disposed over the inner roughness pattern IRP and the outer roughness pattern ORP. According to these implementations, even if moisture flowing in through the through hole TH penetrates into the light emitting layer EL located in the surrounding area SA, moisture may be prevented from penetrating into the light emitting layer EL located in the display area AA. Since the light emitting layer EL is discontinuously disposed in the roughness pattern, the display device 100 or the display panel 110 may provide an advantage of extending a path for moisture penetration and preventing moisture flowing into the light emitting layer from reaching the display area AA.

[0166] Figure 6 and Figure 7 It is along Figure 4 A cross-sectional view taken along line II' in the optical area OA.

[0167] In the following, Figure 7 In the configuration of the display panel 110 shown in FIG. 1 , for the sake of simplicity, the Figure 3 The configuration of the display panel 110 shown is the same or substantially the same as discussed above.

[0168] A substrate SUB may be disposed at the bottom of the display panel 110. The substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. The interlayer insulating layer IPD may be interposed between the first substrate SUB1 and the second substrate SUB2.

[0169] The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may include a multi-buffer layer MBUF, a first active buffer layer ABUF1, a second active buffer layer ABUF2, and a gate insulating layer GI.

[0170] The gate electrode GATE of the driving transistor DRT may be patterned and disposed on the buffer layer BUF.

[0171] The first interlayer insulating layer ILD1 may be configured to cover the buffer layer BUF and the gate electrode GATE.

[0172] A metal pattern TM may be patterned and disposed on the first interlayer insulating layer ILD1. The metal pattern TM may be located at a position different from a position where the driving transistor DRT is formed.

[0173] The second-first interlayer insulating layer ILD2 - 1 may be configured to cover the metal pattern TM. Specifically, the second-first interlayer insulating layer ILD2 - 1 may be configured to cover the first interlayer insulating layer ILD1 and the metal pattern TM.

[0174] The second-second interlayer insulating layer ILD2-2 may be disposed on the second-first interlayer insulating layer ILD2-1. After the second-second interlayer insulating layer ILD2-2 is disposed on the second-first interlayer insulating layer ILD2-1, a portion of the second-second interlayer insulating layer ILD2-2 may be removed by etching. The second-second interlayer insulating layer ILD2-2, a portion of which has been removed by etching, may be divided into a plurality of portions, and some of the divided plurality of portions may be included in the roughness pattern and the one or more barriers.

[0175] The first source-drain pattern SD1 may be patterned and disposed on the second interlayer insulating layer ILD2. For example, the first source-drain pattern SD1 may be patterned and disposed on the second-second interlayer insulating layer ILD2-2.

[0176] A passivation layer PAS0 may be disposed on the second-second interlayer insulating layer ILD2-2. Specifically, the passivation layer PAS0 may be configured to cover the two first source-drain patterns SD1 and the second-second interlayer insulating layer ILD2-2. The passivation layer PAS0 may be disposed in the display area AA and configured to cover the first source-drain pattern SD1.

[0177] The first planarization layer PLN1 may be disposed on the passivation layer PAS0 .

[0178] The second source-drain pattern SD2 may be patterned and disposed on the first planarization layer PLN1 .

[0179] After setting the second source-drain pattern SD2, the second planarization layer PLN2 may be deposited on the first planarization layer PLN1 and the second source-drain pattern SD2. Thereafter, a portion of the second planarization layer PLN2 may be removed by etching. The second planarization layer PLN2, a portion of which has been removed by etching, may be divided into a plurality of portions, and some of the divided plurality of portions may be included in the rough pattern and one or more barriers.

[0180] A bank BANK may be provided on the second planarization layer PLN2. Thereafter, a portion of the bank BANK may be removed by etching. The bank BANK, a portion of which has been removed by etching, may be divided into a plurality of portions, and some of the divided plurality of portions may be included in a rough pattern and one or more barriers. A spacer (not shown) may be provided on the bank BANK. Thereafter, a portion of the spacer may be removed by etching. The spacer, a portion of which has been removed by etching, may be divided into a plurality of portions, and some of the divided plurality of portions may be included in a rough pattern and one or more barriers.

[0181] The light emitting layer EL may be disposed on the bank BANK. All or at least a portion of the light emitting layer EL may be located between adjacent banks. Since the light emitting layer EL is deposited on the entire surface and the bank BANK in a predetermined area, a portion of the light emitting layer EL may be disposed on the top surface of the rough pattern and the top surface of one or more barriers.

[0182] The first encapsulation layer PAS1 may be configured to cover the light emitting layer E, the roughness pattern, one or more barriers, etc. The first encapsulation layer PAS1 may include an inorganic insulating material, which may be deposited at a low temperature.

[0183] The second encapsulation layer PCL may be disposed on the first encapsulation layer PAS1. Specifically, the second encapsulation layer PCL may be disposed on a portion of the first encapsulation layer PAS1.

[0184] A third encapsulation layer PAS2 may be disposed on the second encapsulation layer PCL.

[0185] A touch buffer layer T-BUF may be disposed on the encapsulation layer ENCAP. Specifically, the touch buffer layer T-BUF may be disposed on the third encapsulation layer PAS2.

[0186] A bridge metal BRG may be patterned and disposed on the touch buffer layer T-BUF.

[0187] The touch interlayer insulating layer T-ILD may be configured to cover the touch buffer layer T-BUF and the bridge metal BRG. The touch sensor metal TSM may be disposed on the touch interlayer insulating layer T-ILD. One or more portions of the touch interlayer insulating layer T-ILD may be etched, and thus, the touch interlayer insulating layer T-ILD may include a plurality of contact holes.

[0188] The touch sensor metal TSM may be electrically connected to the bridge metal BRG through a contact hole of the touch interlayer insulating layer T-ILD.

[0189] The protection layer PAC may be configured to cover the touch interlayer insulating layer T-ILD and the touch sensor metal TSM. The protection layer PAC may be, for example, an organic insulating layer.

[0190] Reference Figure 6 , the outer roughness pattern ORP may be disposed in the surrounding area SA adjacent to the through hole TH. The outer barrier DMO may be disposed outside the outer roughness pattern ORP. The inner roughness pattern IRP may be disposed outside the outer barrier DMO. The inner barrier DMI may be disposed outside the inner roughness pattern IRP. A portion of the entire roughness pattern including the inner roughness pattern IRP and the outer roughness pattern ORP may be disposed outside the inner barrier DMI.

[0191] Reference Figure 6 , the trimming line may extend along the outer roughness pattern ORP or contact the outer roughness pattern ORP. The side surface of the outer roughness pattern ORP may correspond to the boundary or boundary area of ​​the through hole TH. That is, the boundary or boundary area of ​​the through hole TH may correspond to the side surface of the protection layer PAC, the side surface of the outer roughness pattern ORP, the side surface of the buffer layer BUF, and the side surface of the substrate SUB.

[0192] In contrast, reference Figure 7 ,and Figure 6 different, Figure 7 The boundary or boundary area of ​​the through hole TH in the substrate SUB may correspond to the side surface of the protective layer PAC and the side surface of the substrate SUB. Elements other than the protective layer PAC on the substrate SUB (i.e., stacked elements) may be arranged to be spaced apart from the trimming line. This implementation may prevent elements such as the outer roughness pattern ORP (i.e., stacked elements) from being damaged during the formation of the through hole TH. The trimming line may be referred to as a trimming area.

[0193] In one or more aspects, the first encapsulation layer PAS1 may include a plurality of insulating layers. For example, the first encapsulation layer PAS1 may be provided in a combination of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). As an example, the first encapsulation layer PAS1 may include three insulating layers, but is not limited thereto. For example, the bottom layer of the first encapsulation layer PAS1 may include silicon nitride (SiNx). The middle layer of the first encapsulation layer PAS1 may include silicon oxynitride (SiON). The top layer of the first encapsulation layer PAS1 may include silicon oxide (SiOx).

[0194] In an example where the top layer of the first encapsulation layer PAS1 includes silicon oxide (SiOx), the second encapsulation layer PCL may be disposed while making it easier to spread the second encapsulation layer PCL on the first encapsulation layer PAS1. However, when the top layer of the first encapsulation layer PAS1 includes silicon oxide (SiOx), oxygen may penetrate the top layer of the first encapsulation layer PAS1 including silicon oxide (SiOx).

[0195] To solve this problem, one or more aspects of the present disclosure may provide a display device 100 capable of preventing oxygen from penetrating into an encapsulation layer.

[0196] One or more aspects of the present disclosure may provide a display device 100 including an encapsulation layer capable of preventing moisture penetration in a process of forming a through hole.

[0197] One or more aspects of the present disclosure may provide a display device 100 including a second encapsulation layer on a first encapsulation layer, the second encapsulation layer being an inorganic layer, having high spreadability, and capable of preventing oxygen from penetrating into the first encapsulation layer.

[0198] One or more aspects of the present disclosure may provide a display device 100 that can prevent oxygen from penetrating into an encapsulation layer and thus be driven with low power.

[0199] One or more example embodiments of the present disclosure are discussed in detail below.

[0200] Figures 8 to 11 It is shown Figure 4 sectional view of a boundary region between a contact hole TH and a surrounding region in FIG.

[0201] Figure 6 and Figure 8 A first enlarged area A1 of the display panel 110 is shown.

[0202] A substrate SUB may be provided at the bottom of the display panel 110. The substrate SUB may include a through hole TH and a surrounding area SA. The substrate SUB may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyether sulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which is only an example and is not necessarily limited thereto.

[0203] The buffer layer BUF may be disposed on the substrate SUB.

[0204] The first encapsulation layer PAS1 may be disposed on the buffer layer BUF. The first encapsulation layer PAS1 may have a stepped end portion, but is not limited thereto.

[0205] The first encapsulation layer PAS1 may include a plurality of insulating layers. The plurality of insulating layers may be three or four layers, but is not limited thereto, and may also be more or less layers. For example, the first encapsulation layer PAS1 may include two layers.

[0206] Reference Figure 8 In this example, when the first encapsulation layer PAS1 is configured with a four-layer stack, the first encapsulation layer PAS1 may include a first insulating layer PAS11 including silicon nitride (SiNx), a second insulating layer PAS12 including silicon oxynitride (SiON) disposed on the first insulating layer PAS11, a third insulating layer PAS13 including silicon oxynitride (SiON) disposed on the second insulating layer PAS12, and a fourth insulating layer PAS14 including silicon oxide (SiOx) disposed on a portion of the third insulating layer PAS13, but is not limited thereto. Alternatively, in an example in which the first encapsulation layer PAS1 is configured with a two-layer stack, the first encapsulation layer PAS1 may include a third insulating layer PAS13 and a fourth insulating layer PAS14 disposed on a portion of the third insulating layer PAS13.

[0207] In this example, when the first encapsulation layer PAS1 is configured with a three-layer stack, the first encapsulation layer PAS1 may include a first insulating layer including silicon nitride (SiNx), a second insulating layer including silicon oxynitride (SiON), and a third insulating layer including silicon oxide (SiOx), but is not limited thereto.

[0208] Therefore, in Figure 8In the example, the bottom layer PAS11 of the first encapsulation layer PAS1 may include silicon nitride (SiNx), and the top layer PAS14 of the first encapsulation layer PAS1 may include silicon oxide (SiOx). Hereinafter, for ease of explanation, the discussion is based on an example in which the first encapsulation layer PAS1 is configured with four stacked layers.

[0209] Reference Figure 8 , the width of the bottom layer PAS11 (i.e., the distance between the two opposite ends) may be greater than the width of the top layer PAS14. For example, the bottom layer PAS11 may extend to the right beyond the right edge of the top layer PAS14. Similarly, the width of the second insulating layer PAS12 and the third insulating layer PAS13 (i.e., the distance between the two opposite ends) may be greater than the width of the top layer PAS14, but is not limited thereto. For example, the second insulating layer PAS12 and the third insulating layer PAS13 may extend to the right beyond the right edge of the top layer PAS14, but is not limited thereto.

[0210] Reference Figure 8 , the fourth insulating layer PAS14 may be disposed on a portion of the third insulating layer PAS13.

[0211] A portion of the first encapsulation layer PAS1 may be disposed adjacent to the through hole TH. Each of the first insulating layer PAS11 , the second insulating layer PAS12 , and the third insulating layer PAS13 may be disposed adjacent to the through hole TH.

[0212] The fourth insulating layer PAS14 may be disposed to be spaced apart from the through hole TH. In one or more aspects, the fourth insulating layer PAS14 may be disposed on the entire top surface of the third insulating layer PAS13 in a predetermined area, and the fourth insulating layer PAS14 may not be disposed on a portion of the third insulating layer PAS13 adjacent to the through hole TH. In one or more aspects, the third encapsulation layer PAS2 may be disposed on the first encapsulation layer PAS1. For example, the third encapsulation layer PAS2 may be disposed on a portion of the third insulating layer PAS13 adjacent to the through hole TH and on the fourth insulating layer PAS14.

[0213] The third encapsulation layer PAS2 may be configured to cover the first encapsulation layer PAS1.

[0214] The third encapsulation layer PAS2 may be configured to cover a side surface (eg, a right side surface) of the fourth insulating layer PAS14 and a portion of the third insulating layer PAS13 .

[0215] The third encapsulation layer PAS2 may be provided in a stepped pattern.

[0216] Reference Figure 8, a portion of the third encapsulation layer PAS2 disposed on the right side of the surrounding area SA may be disposed in parallel with the fourth insulating layer PAS14 in the horizontal direction, and may be configured to overlap with the third insulating layer PAS13 in the vertical direction. A portion of the third encapsulation layer PAS2 disposed on the left side of the surrounding area SA may be configured to overlap with the third insulating layer PAS13 in the vertical direction. A portion of the third encapsulation layer PAS2 disposed on the left side of the surrounding area SA may be disposed higher than a portion of the third encapsulation layer PAS2 disposed on the right side of the surrounding area SA, but is not limited thereto.

[0217] The third encapsulation layer PAS2 may be disposed on the first encapsulation layer PAS1 and disposed adjacent to the through hole TH.

[0218] A corresponding one side surface (eg, a corresponding right side surface) of each of the first insulating layer PAS11 , the second insulating layer PAS12 , the third insulating layer PAS13 , and the third encapsulation layer PAS2 may correspond to a trimming line or a trimming region.

[0219] Each of the first insulating layer PAS11 , the second insulating layer PAS12 , the third insulating layer PAS13 , and the third encapsulation layer PAS2 may have a cut shape at a trimming region.

[0220] Even when each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13 and the third encapsulation layer PAS2 is cut along the trimming line, since the third encapsulation layer PAS2 is configured to cover the side surface of the fourth insulating layer PAS14, the fourth insulating layer PAS14 can be protected from the penetration of moisture.

[0221] Reference Figure 7 and Fig. 9 , Figure 7 The boundary of the through hole TH in the protective layer PAC may correspond to the side surface of the protective layer PAC and the side surface of the substrate SUB. The first encapsulation layer PAS1 may be arranged to be spaced apart from the through hole TH. That is, each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13 and the fourth insulating layer PAS14 may be arranged to be spaced apart from the through hole TH. The third encapsulation layer PAS2 may be arranged adjacent to the through hole TH. The first encapsulation layer PAS1 and the third encapsulation layer PAS2 may be arranged in a stepped pattern.

[0222] Reference Figure 8 and Fig. 9 ,and Figure 8 The third encapsulation layer PAS2 is different. Fig. 9 The third encapsulation layer PAS2 may be configured to cover all side surfaces (eg, right side surface) of the first encapsulation layer PAS1.

[0223] The third encapsulation layer PAS2 may include a portion disposed along a side surface of the first encapsulation layer PAS1.

[0224] The third encapsulation layer PAS2 may be configured to cover a corresponding side surface (e.g., a corresponding right side surface) of each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13, and the fourth insulating layer PAS14, and a portion of the top surface of the substrate SUB. Therefore, a portion of the third encapsulation layer PAS2 that contacts the substrate SUB may be disposed adjacent to the through hole TH. In addition, the third encapsulation layer PAS2 may be configured to cover a portion of the top surface of the third insulating layer PAS13 and the top surface of the fourth insulating layer PAS14. In addition, the third encapsulation layer PAS2 may be configured to cover a corresponding side surface (e.g., a corresponding right side surface) of the buffer layer BUF.

[0225] The third encapsulation layer PAS2 and the substrate SUB may have a cut shape in the trimming region. Respective side surfaces of the third encapsulation layer PAS2 and the substrate SUB may correspond to the trimming region.

[0226] Even when each of the third encapsulation layer PAS2 and the substrate SUB is cut along the trimming line, since the third encapsulation layer PAS2 is configured to cover the side surface of the first encapsulation layer PAS1, the fourth insulating layer PAS14 may be protected from penetration of moisture.

[0227] Reference Figure 8 and Fig.10 ,and Figure 8 The fourth insulating layer PAS14 is different, Fig.10 The fourth insulating layer PAS14 may be configured to expose a portion of the third insulating layer PAS13 , and the fourth insulating layer PAS14 may include a portion adjacent to the through hole TH.

[0228] After the fourth insulating layer PAS14 is deposited on the entire top surface of the third insulating layer PAS13 in a predetermined region, a portion of the fourth insulating layer PAS14 spaced apart from the through hole TH may be removed by etching.

[0229] Through this process, the fourth insulating layer PAS14 may include a first portion PAS14 a adjacent to the through hole TH and a second portion PAS14 b spaced apart from the through hole TH.

[0230] The third encapsulation layer PAS2 may be configured to contact a portion of the third insulating layer PAS13 between the first portion PAS14a and the second portion PAS14b of the fourth insulating layer PAS14. Fig.10, the third encapsulation layer PAS2 may have a “T” shape. That is, the third encapsulation layer PAS2 may be configured to cover the first portion PAS14 a , the second portion PAS14 b , and the exposed portion of the third insulating layer PAS13 .

[0231] The first portion PAS14a may be spaced apart from the second portion PAS14b. In addition, the first portion PAS14a may not be completely separated from the second portion PAS14b, and a region between the first portion PAS14a and the second portion PAS14b may be a region where a through hole is formed.

[0232] The first portion PAS14 a may be disposed adjacent to the through hole TH and configured to overlap the third insulating layer PAS13 in a vertical direction.

[0233] The second portion PAS14 b may be disposed to be spaced apart from the through hole TH and configured to overlap the third insulating layer PAS13 in a vertical direction.

[0234] A portion of the third encapsulation layer PAS2 may be disposed in the region between the first portion PAS14a and the second portion PAS14b, and the third encapsulation layer PAS2 may be disposed in parallel with the first portion PAS14a and the second portion PAS14b in the horizontal direction. Specifically, a portion of the third encapsulation layer PAS2 disposed in the region between the first portion PAS14a and the second portion PAS14b may be disposed in parallel with the first portion PAS14a and the second portion PAS14b in the horizontal direction.

[0235] A corresponding side surface (eg, a corresponding right side surface) of each of the first and third encapsulation layers PAS1 and PAS2 may correspond to the trimming region. The first and third encapsulation layers PAS1 and PAS2 may have a cut shape in the trimming region.

[0236] Reference Fig.10 Since the second portion PAS14b of the fourth insulating layer PAS14 is set to be spaced apart from the through hole TH, the fourth insulating layer PAS14 can be protected from the penetration of moisture, and since the first portion PAS14a of the fourth insulating layer PAS14 is set to be adjacent to the through hole TH, the first encapsulation layer PAS1 can have a structurally strong end.

[0237] Reference Figure 7 and Fig.11 , Figure 7 The boundaries of the through holes TH in the substrate SUB may correspond to the side surfaces of the protection layer PAC and the substrate SUB. The first encapsulation layer PAS1 may be configured to be spaced apart from the through holes TH.

[0238] Reference Fig.10 and Fig.11 ,and Fig.10 The third encapsulation layer PAS2 is different. Fig.11 The third encapsulation layer PAS2 may be configured to cover all side surfaces (eg, right side surface) of the first encapsulation layer PAS1.

[0239] The third encapsulation layer PAS2 may be configured to cover a portion of the side surface of the first encapsulation layer PAS1 and the top surface of the substrate SUB. Specifically, the third encapsulation layer PAS2 may be configured to cover a corresponding side surface (e.g., a corresponding right side surface) of each of the first insulating layer PAS11, the second insulating layer PAS12, the third insulating layer PAS13, and the fourth insulating layer PAS14, and a portion of the top surface of the substrate SUB. Therefore, a portion of the third encapsulation layer PAS2 that contacts the substrate SUB may be disposed adjacent to the through hole TH.

[0240] The third encapsulation layer PAS2 may be configured to cover the side surface of the first portion PAS14a of the fourth insulating layer PAS14. The third encapsulation layer PAS2 may be configured to cover the corresponding side surfaces (e.g., the corresponding right side surfaces) of the first insulating layer PAS11, the second insulating layer PAS12, and the third insulating layer PAS13. In addition, the third encapsulation layer PAS2 may be configured to cover the corresponding side surfaces (e.g., the corresponding right side surfaces) of the buffer layer BUF.

[0241] Fig.12 and Fig.13 It is shown Figure 4 A plan view of a boundary area between a contact hole (or through hole) TH and a surrounding area SA.

[0242] Fig.12 and Fig.13 A second enlarged area A2 of the display panel 110 is shown.

[0243] Reference Fig.12 and Fig.13 , the fourth insulating layer PAS14 may include a groove region in which a plurality of grooves H are provided.

[0244] Fig.12 The distance between the fourth insulating layer PAS14 and the through hole TH shown in FIG. Figure 6 The distance between the fourth insulating layer PAS14 and the through hole TH is the same or substantially the same. Fig.12 , the side surface of the fourth insulating layer PAS14 may correspond to the trimming line. Specifically, the side surface of the groove area of ​​the fourth insulating layer PAS14 may be disposed adjacent to the trimming line. The groove area of ​​the fourth insulating layer PAS14 may be disposed adjacent to the trimming line.

[0245] Fig.13The distance between the fourth insulating layer PAS14 and the through hole TH shown in FIG. Figure 7 The distance between the fourth insulating layer PAS14 and the through hole TH is the same or substantially the same. Fig.13 , a side surface of the fourth insulating layer PAS14 may be disposed to be spaced apart from the through hole TH. A groove region of the fourth insulating layer PAS14 may be disposed to be spaced apart from the through hole TH.

[0246] Reference Fig.12 and Fig.13 , since the fourth insulating layer PAS14 includes the plurality of grooves H, a moisture permeation distance through the fourth insulating layer PAS14 may be increased.

[0247] The plurality of grooves H may be designed in various shapes to increase the moisture penetration distance. For example, the plurality of grooves H may be arranged so that moisture penetrating the fourth insulating layer PAS14 may move in a zigzag shape.

[0248] The above-described exemplary embodiments will be briefly described below.

[0249] According to example embodiments described herein, a display device may be provided, the display device comprising: a substrate comprising a through hole and a surrounding area surrounding the through hole; a first passivation layer disposed on the substrate and comprising a first insulating layer and a second insulating layer disposed on a portion of the first insulating layer; and a second passivation layer configured to cover the first passivation layer.

[0250] In one or more aspects, the substrate may include a first substrate and a second substrate with an interlayer insulating layer interposed between the first substrate and the second substrate.

[0251] In one or more aspects, the second passivation layer may be configured to cover a side surface of the second insulating layer and a portion of a top surface of the first insulating layer.

[0252] In one or more aspects, the second passivation layer may be disposed in a stepped pattern.

[0253] In one or more aspects, the first passivation layer may be disposed in a stepped pattern.

[0254] In one or more aspects, the first passivation layer may be disposed adjacent to the through hole, and the second passivation layer may be disposed on the first passivation layer and disposed adjacent to the through hole.

[0255] In one or more aspects, the first insulating layer may be disposed adjacent to the through-hole, and the second insulating layer may be disposed spaced apart from the through-hole.

[0256] In one or more aspects, the substrate may further include a trimming region as a boundary region between the through hole and the surrounding region, and a side surface of the first insulating layer of the first passivation layer and a side surface of the second passivation layer may correspond to the trimming region.

[0257] In one or more aspects, the second passivation layer may be configured to cover side surfaces of the first insulating layer.

[0258] In one or more aspects, the second passivation layer may be configured to cover a side surface of the first insulating layer and a portion of a top surface of the substrate.

[0259] In one or more aspects, the first passivation layer may be disposed to be spaced apart from the through-hole, and the second passivation layer may be disposed to be adjacent to the through-hole.

[0260] In one or more aspects, the substrate may further include a trimming region as a boundary region between the through hole and the surrounding region, and a side surface of the second passivation layer and a side surface of the substrate may correspond to the trimming region.

[0261] In one or more aspects, the second insulating layer may include a first portion adjacent to the through-hole and a second portion spaced apart from the through-hole.

[0262] In one or more aspects, the second passivation layer may be configured to contact the first insulating layer between a first portion of the second insulating layer and a second portion of the second insulating layer.

[0263] In one or more aspects, the second passivation layer may be configured to cover a side surface of the first insulating layer and a side surface of a first portion of the second insulating layer.

[0264] In one or more aspects, the second passivation layer may be configured to cover a side surface of the first insulating layer and a portion of a top surface of the substrate.

[0265] In one or more aspects, the first passivation layer may be disposed to be spaced apart from the through-hole, and the second passivation layer may be disposed to be adjacent to the through-hole.

[0266] In one or more aspects, the second insulating layer may include a groove region provided with a plurality of grooves.

[0267] In one or more aspects, the recessed region may be disposed adjacent to the through hole.

[0268] In one or more aspects, the recessed area may be disposed to be spaced apart from the through hole.

[0269] In one or more aspects, the display device may further include an optical electronic device configured to overlap the through hole.

[0270] In one or more aspects, the through hole may be a region where no image is displayed.

[0271] In one or more aspects, the substrate may further include a display area surrounding the peripheral area, and the second passivation layer may be disposed on the display area and the peripheral area.

[0272] The display device according to one or more exemplary embodiments of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, variable devices, sliding devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, netbook computers, workstations, navigation devices, car navigation devices, car display devices, car devices, theater devices, theater display devices, TVs, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, camcorders, home appliances, etc., but the embodiments of the present disclosure are not limited thereto.

[0273] The above description is proposed to enable those skilled in the art to make, use and practice the technical features of the present disclosure, and is provided as an example in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and accompanying drawings provide examples of the technical features of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present disclosure.

[0274] CROSS-REFERENCE TO RELATED APPLICATIONS

[0275] This patent application claims the benefit of priority to Korean Patent Application No. 10-2023-0146792 filed on October 30, 2023, in the Korean Intellectual Property Office, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a substrate comprising a through hole and a peripheral area surrounding the through hole; a first passivation layer disposed on the substrate and comprising a first insulating layer and a second insulating layer disposed on a portion of the first insulating layer; as well as A second passivation layer is configured to cover the first passivation layer.

2. The display device according to claim 1, wherein: The substrate includes a first substrate and a second substrate, and an interlayer insulating layer is interposed between the first substrate and the second substrate.

3. The display device according to claim 1, wherein: The second passivation layer is configured to cover side surfaces of the second insulating layer and a portion of a top surface of the first insulating layer.

4. The display device according to claim 3, wherein: The second passivation layer is disposed in a stepped pattern.

5. The display device according to claim 1, wherein: The first passivation layer is disposed in a stepped pattern.

6. The display device according to claim 1, wherein: The first passivation layer is disposed adjacent to the through hole, and the second passivation layer is disposed on the first passivation layer and disposed adjacent to the through hole.

7. The display device according to claim 1, wherein: The first insulating layer is disposed adjacent to the through hole, and the second insulating layer is disposed spaced apart from the through hole.

8. The display device according to claim 3, wherein: The substrate further includes a trimming region as a boundary region between the through hole and the surrounding region, and a side surface of the first insulating layer of the first passivation layer and a side surface of the second passivation layer correspond to the trimming region.

9. The display device according to claim 3, wherein: The second passivation layer is configured to cover side surfaces of the first insulating layer.

10. The display device according to claim 9, wherein: The second passivation layer is configured to cover side surfaces of the first insulating layer and a portion of a top surface of the substrate.

11. The display device according to claim 3, wherein: The first passivation layer is disposed to be spaced apart from the through hole, and the second passivation layer is disposed adjacent to the through hole.

12. The display device according to claim 9, wherein: The substrate further includes a trimming region as a boundary region between the through hole and the surrounding region, and Wherein, a side surface of the second passivation layer and a side surface of the substrate correspond to the trimming area.

13. The display device according to claim 1, wherein: The second insulating layer comprises: a first portion adjacent to the through hole; and A second portion is spaced apart from the through hole.

14. The display device according to claim 13, wherein: The second passivation layer is configured to contact the first insulating layer between the first portion of the second insulating layer and the second portion of the second insulating layer.

15. The display device according to claim 13, wherein: The second passivation layer is configured to cover a side surface of the first insulating layer and a side surface of the first portion of the second insulating layer.

16. The display device according to claim 13, wherein: The second passivation layer is configured to cover side surfaces of the first insulating layer and a portion of a top surface of the substrate.

17. The display device according to claim 3, wherein: The first passivation layer is disposed to be spaced apart from the through hole, and the second passivation layer is disposed adjacent to the through hole.

18. The display device according to claim 1, wherein: The second insulating layer includes a groove region provided with a plurality of grooves.

19. The display device according to claim 18, wherein: The groove area is arranged adjacent to the through hole.

20. The display device according to claim 18, wherein: The recessed area is disposed to be spaced apart from the through hole. 21 . The display device according to claim 1 , further comprising an optical electronic device configured to overlap the through hole.

22. The display device according to claim 1, wherein: The through-hole is a region where no image is displayed.

23. The display device according to claim 1, wherein: The substrate further includes a display area surrounding the peripheral area, and the second passivation layer is disposed on the display area and the peripheral area.

Images