Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises: a substrate (1); the plurality of grid lines (2) are positioned on one side of the substrate (1) and extend along a first direction (X); a plurality of data lines (3) extending in a second direction (Y); the plurality of pixel electrodes (4) comprise a first pixel electrode (41) positioned on one side of the grid line (2) and a second pixel electrode (42) positioned on the other side of the grid line (2); the first pixel electrode (41) comprises a first sub-pixel electrode (411) and a second sub-pixel electrode (412) which are distributed along a first direction (X); the second pixel electrode (42) comprises a third sub-pixel electrode (421) and a fourth sub-pixel electrode (422) which are distributed along the first direction (X); one of the first sub-pixel electrode (411) and the second sub-pixel electrode (412) is electrically connected to one of the third sub-pixel electrode (421) and the fourth sub-pixel electrode (422).

Description

Array substrate, display panel and display device

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device.

[0002] The name UV2A comes from the multiplication of ultraviolet rays (UV) and the VA method of the liquid crystal panel. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet rays, greatly improving the light transmittance.

[0003] The key to UV2A is to use a special polymer material as an alignment film to control the liquid crystal molecules to tilt along the ultraviolet direction with high precision. The unit of precision is picometer (one trillionth of a meter). The advantage of UV2A is that the liquid crystal panel is a simple structure without protrusions and slits. This "dream of liquid crystal technicians" was discussed as early as 30 years ago. Today, with the three conditions of new materials, production equipment and perfect processing, this dream has been realized. The simple structure of the liquid crystal panel can not only improve production efficiency, but also has many advantages in picture quality.

[0004] Summary of the invention

[0005] The embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate includes:

[0006] substrate;

[0007] A plurality of gate lines, located on one side of the substrate and extending along a first direction;

[0008] A plurality of data lines extending along a second direction;

[0009] A plurality of pixel electrodes, the pixel electrodes comprising: a first pixel electrode located on one side of the gate line, and a second pixel electrode located on the other side of the gate line; the first pixel electrode comprising: a first sub-pixel electrode and a second sub-pixel electrode distributed along the first direction; the second pixel electrode comprising: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the first direction;

[0010] One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode.

[0011] In a possible implementation, the array substrate further includes: a plurality of transistors; the plurality of transistors electrically connected to the same pixel electrode are electrically connected to the same data line and the same gate line;

[0012] The second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

[0013] In a possible implementation manner, the array substrate further includes: a first signal line extending along the second direction; the plurality of transistors include: a first transistor, a second transistor, and a third transistor;

[0014] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode;

[0015] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode;

[0016] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor multiplexes with the second electrode of the second transistor, and the second electrode of the third transistor multiplexes with the first signal line.

[0017] In a possible implementation, the pixel electrode further includes: a first subpixel electrode protrusion connected to the first subpixel electrode on a side facing the third subpixel electrode; and the second electrode of the first transistor is electrically connected to the first subpixel electrode through the first subpixel electrode protrusion.

[0018] In a possible implementation, the pixel electrode further includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connecting portion includes: a first connecting portion extending along the second direction, and a second connecting portion extending along a third direction; the third direction intersects the first direction and intersects the second direction;

[0019] One end of the first connection portion is electrically connected to one end of the first subpixel electrode facing the third subpixel electrode, and the other end is electrically connected to the second connection portion. The other end of the second connection portion is electrically connected to one end of the fourth subpixel electrode facing the second subpixel electrode.

[0020] In a possible implementation manner, the pixel electrode further includes: a third sub-pixel electrode protrusion connected to a side of the third sub-pixel electrode facing the first sub-pixel electrode;

[0021] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third sub-pixel electrode protrusion.

[0022] In a possible implementation, the pixel electrode further includes: a second sub-pixel electrode extension extending along the second direction, and a second sub-pixel electrode convex portion; one end of the second sub-pixel electrode extension is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end is electrically connected to the second sub-pixel electrode convex portion;

[0023] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second sub-pixel electrode protrusion.

[0024] In a possible implementation manner, an extending direction of the second sub-pixel electrode extending portion is parallel to an extending direction of the first connecting portion.

[0025] In a possible implementation, the second sub-pixel electrode convex portion has a second sub-pixel electrode convex portion outer edge away from one side of the second sub-pixel electrode and extending along the first direction; the third sub-pixel electrode convex portion has a third sub-pixel electrode convex portion outer edge away from one side of the third sub-pixel electrode and extending along the first direction;

[0026] The extension line of the outer edge of the second sub-pixel electrode protrusion coincides with the extension line of the outer edge of the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the second sub-pixel electrode protrusion at least partially overlaps with the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the third sub-pixel electrode protrusion at least partially overlaps with the second sub-pixel electrode protrusion.

[0027] In a possible implementation manner, a connecting line between the center of the convex portion of the third sub-pixel electrode and the center of the convex portion of the first sub-pixel electrode is parallel to the second direction.

[0028] In a possible implementation, the second electrode of the first transistor includes: a first transistor first portion extending along the first direction;

[0029] The orthographic projection of the first portion of the first transistor on the substrate has an overlapping area with the orthographic projection of the first sub-pixel electrode convex portion on the substrate.

[0030] In a possible implementation manner, the second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected to one end of the second transistor first portion;

[0031] The orthographic projection of the first portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the third sub-pixel electrode convex portion on the substrate; the orthographic projection of the second portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the second sub-pixel electrode convex portion on the substrate.

[0032] In a possible implementation manner, at least a portion of the second portion of the second transistor on the orthographic projection of the substrate overlaps with at least a portion of the second sub-pixel electrode extension portion on the orthographic projection of the substrate.

[0033] In a possible implementation manner, the first signal line has a recessed portion; and the second portion of the second transistor is located at least partially in a region surrounded by the orthographic projection of the recessed portion on the substrate.

[0034] In a possible implementation manner, the first signal line includes: a first signal portion, a second signal portion, and a third signal portion sequentially distributed along the second direction, a fourth signal portion extending along the first direction and connecting the second signal portion and the first signal portion, and a fifth signal portion extending along the first direction and connecting the second signal portion and the third signal portion;

[0035] An extension line of the first signal portion coincides with an extension line of the third signal portion; an extension line of the second signal portion coincides with an extension line of the first signal portion; the second signal portion, the fourth signal portion and the fifth signal portion constitute the recessed portion, and the fourth signal portion and / or the fifth signal portion at least partially overlap with the pixel electrode.

[0036] In a possible implementation, the array substrate further includes: a first common wiring located at one side of the gate line and extending along the first direction; the plurality of transistors include: a first transistor electrically connected to the data line, a second transistor, and a third transistor;

[0037] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode;

[0038] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode;

[0039] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common wiring.

[0040] In a possible implementation, the pixel electrode further includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first overlapping portion connected to the connecting portion; the connecting portion includes: a third connecting portion extending along the first direction, a fourth connecting portion, and a fifth connecting portion extending along the second direction;

[0041] One end of the third connection portion is connected to the first sub-pixel electrode, one end of the fourth connection portion is connected to the fourth sub-pixel electrode, one end of the fifth connection portion is connected to the other end of the third connection portion, and the other end of the fifth connection portion is connected to the other end of the fourth connection portion; the first lap portion is electrically connected to the third connection portion and is away from a side of the connected first sub-pixel electrode;

[0042] The second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode through the first overlapping portion.

[0043] In a possible implementation manner, the pixel electrode further includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlap portion;

[0044] One end of the first adapter portion is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, the other end of the first adapter portion is electrically connected to one end of the second adapter portion; the other end of the second adapter portion is electrically connected to the second lap portion;

[0045] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second connecting portion.

[0046] In a possible implementation manner, the second transition portion is parallel to an extending direction of the fifth connecting portion.

[0047] In a possible implementation manner, the pixel electrode further includes: a third transition portion extending along the first direction, and a third overlapping portion;

[0048] One end of the third adapter portion is electrically connected to one end of the third sub-pixel electrode facing the first sub-pixel electrode, and the other end of the third adapter portion is electrically connected to the third bridging portion;

[0049] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third bridging portion.

[0050] In a possible implementation manner, a first gap is formed between the third connecting portion and the first pixel electrode; a second gap is formed between the fourth connecting portion and the second pixel electrode;

[0051] A third gap is formed between the first transition portion and the first pixel electrode, and a fourth gap is formed between the third transition portion and the second pixel electrode.

[0052] In a possible implementation manner, the array substrate further includes: a fourth overlapping portion; and the second electrode of the third transistor is electrically connected to the first common wiring through the fourth overlapping portion.

[0053] In a possible implementation, the fourth overlapping portion has a fourth overlapping portion outer edge along the first direction, the second overlapping portion has a second overlapping portion outer edge extending along the first direction; the first overlapping portion has a first overlapping portion outer edge extending along the second direction, and the third overlapping portion has a third overlapping portion outer edge extending along the second direction;

[0054] The extension line of the outer edge of the fourth overlapping portion coincides with the extension line of the outer edge of the second overlapping portion; the extension line of the outer edge of the first overlapping portion coincides with the extension line of the outer edge of the third overlapping portion.

[0055] In a possible implementation, the second electrode of the first transistor includes: a first transistor first portion extending along the first direction;

[0056] An orthographic projection of the first portion of the first transistor on the substrate has an overlapping area with an orthographic projection of the first overlapping portion on the substrate.

[0057] In a possible implementation manner, the second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected to one end of the second transistor first portion;

[0058] The orthographic projection of the first portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the third overlapping portion on the substrate; the orthographic projection of the second portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the second overlapping portion on the substrate.

[0059] In a possible implementation, the array substrate further includes: a first common wiring located at one side of the gate line and extending along the first direction; the first common wiring is disconnected at a position where it intersects with the data line.

[0060] In a possible implementation manner, the array substrate further includes: a second common wiring group electrically connected to the first common wiring and extending toward a side away from the gate line, the second common wiring group including: two second common wirings;

[0061] The orthographic projection of the data line on the substrate and the gap between two second common lines of the same second common line group on the substrate have an overlapping area.

[0062] In a possible implementation, the array substrate further includes: a third common wiring located at the other side of the gate line and extending along the first direction, and a fourth common wiring group connected to the third common wiring and extending away from the gate line;

[0063] The third common routing line is disconnected at a position where it crosses the data line; the fourth common routing line group includes: two fourth common routing lines; the orthographic projection of the data line on the substrate and the gap between the two fourth common routing lines of the same fourth common routing line group have an overlapping area on the orthographic projection of the substrate.

[0064] In a possible implementation, the array substrate further includes: a fifth common line extending along the first direction and electrically connected to the second common line, wherein the orthographic projection of the fifth common line on the substrate passes through a central area of ​​the orthographic projection of the second pixel electrode on the substrate.

[0065] In a possible implementation, the array substrate further includes: a sixth common line extending along the first direction and electrically connected to the fourth common line, wherein the orthographic projection of the sixth common line on the substrate passes through a central area of ​​the orthographic projection of the first pixel electrode on the substrate.

[0066] In a possible implementation, the first sub-pixel electrode and the second sub-pixel electrode both include: a first sub-electrode portion and a second sub-electrode portion distributed along the second direction; the third sub-pixel electrode and the fourth sub-pixel electrode both include: a third sub-electrode portion and a fourth sub-electrode portion distributed along the second direction;

[0067] The first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion all have a plurality of slits; and an extension direction of the slits of the first sub-electrode portion is the same as an extension direction of the slits of the fourth sub-electrode portion; and an extension direction of the slits of the second sub-electrode portion is the same as an extension direction of the slits of the third sub-electrode portion.

[0068] In a possible implementation manner, the length of the slit in a direction perpendicular to the extending direction may be 2 μm to 4 μm.

[0069] In a possible implementation manner, the orthographic projection shapes of the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode, and the fourth sub-pixel electrode on the substrate are all rectangular.

[0070] In a possible implementation manner, the orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal;

[0071] In the first sub-pixel electrode and the fourth sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their top sides; in the second sub-pixel electrode and the third sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their bottom sides.

[0072] In a possible implementation manner, the orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal;

[0073] In the first sub-pixel electrode and the fourth sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their bottom sides; in the second sub-pixel electrode and the third sub-pixel electrode, the first trapezoidal sub-electrode portion and the second trapezoidal sub-electrode portion are arranged opposite to each other with their top sides.

[0074] In a possible implementation, the first sub-pixel electrode includes: a first main portion extending and connected along the second direction, a second main portion, and a first side portion extending along the first direction, a plurality of first branches extending along a fourth direction from the first main portion and the first side portion, and a plurality of second branches extending along a fifth direction from the second main portion and the first side portion; the second sub-pixel electrode includes: a third main portion extending and connected along the second direction, a fourth main portion, a fifth main portion connected to one end of the third main portion and extending along the first direction, a sixth main portion connected to one end of the fourth main portion and extending along the first direction, a plurality of third branches extending along the fourth direction from the third main portion and the fifth main portion, and a plurality of fourth branches extending along the fifth direction from the fourth main portion and the sixth main portion; the plurality of first branches are interdigitated with the plurality of third branches, and the plurality of second branches are interdigitated with the plurality of fourth branches;

[0075] The third sub-pixel electrode includes: a seventh main portion extending and connected along the second direction, an eighth main portion, a ninth main portion connected to one end of the seventh main portion and extending along the first direction, a tenth main portion connected to one end of the eighth main portion and extending along the first direction, a plurality of fifth branches extending from the seventh main portion and the ninth main portion along the fourth direction, and a plurality of sixth branches extending from the eighth main portion and the tenth main portion along the fifth direction; the fourth sub-pixel electrode includes: an eleventh main portion extending and connected along the second direction, a twelfth main portion, and a second side portion extending along the first direction, a plurality of seventh branches extending from the eleventh main portion and the second side portion along the fourth direction, and a plurality of eighth branches extending from the twelfth main portion and the second side portion along the fifth direction; the plurality of fifth branches are interdigitated with the plurality of seventh branches, and the plurality of sixth branches are interdigitated with the plurality of eighth branches.

[0076] In a possible implementation manner, the array substrate further includes: a first conductive layer located on a side of the pixel electrode facing the substrate; the first conductive layer has a first hollow, a second hollow, a third hollow, and a fourth hollow;

[0077] The first hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the first sub-pixel electrode on the substrate; the second hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the second sub-pixel electrode on the substrate; the third hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the third sub-pixel electrode on the substrate; the fourth hollowing out overlaps at least part of the orthographic projection of the substrate with at least part of the orthographic projection of the fourth sub-pixel electrode on the substrate.

[0078] The embodiment of the present disclosure further provides a display panel, which includes: the array substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0079] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0080] FIG1A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0081] FIG1B is an enlarged schematic diagram of the dashed line frame S1 in FIG1A ;

[0082] FIG1C is a schematic diagram of a single film layer of the gate line layer in FIG1A ;

[0083] FIG1D is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0084] FIG1E is a schematic diagram of a single film layer of the data line in FIG1A ;

[0085] FIG1F is a schematic diagram of a single film layer of the first insulating layer in FIG1A ;

[0086] FIG1G is a schematic diagram of a single film layer of the pixel electrode in FIG1A ;

[0087] FIG1H is a schematic diagram of light effect simulation corresponding to FIG1A ;

[0088] FIG2A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0089] FIG2B is an enlarged schematic diagram of the dashed line frame S1 in FIG2A ;

[0090] FIG2C is a schematic diagram of a single film layer of the gate line layer in FIG2A ;

[0091] FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A ;

[0092] FIG2E is a schematic diagram of a single film layer of the data line in FIG2A ;

[0093] FIG2F is a schematic diagram of a single film layer of the first insulating layer in FIG2A ;

[0094] FIG2G is a schematic diagram of a single film layer of the pixel electrode in FIG2A ;

[0095] FIG2H is a schematic diagram of light effect simulation corresponding to FIG2A ;

[0096] FIG2I is a schematic cross-sectional view of FIG2B taken along dotted line EF;

[0097] FIG3A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0098] FIG3B is an enlarged schematic diagram of the dotted line frame S1 in FIG3A ;

[0099] FIG3C is a schematic diagram of a single film layer of the gate line layer in FIG3A ;

[0100] FIG3D is a schematic diagram of a single film layer of the active layer in FIG3A ;

[0101] FIG3E is a schematic diagram of a single film layer of the data line in FIG3A ;

[0102] FIG3F is a schematic diagram of a single film layer of the first insulating layer in FIG3A ;

[0103] FIG3G is a schematic diagram of a single film layer of the pixel electrode in FIG3A ;

[0104] FIG3H is a schematic diagram of light effect simulation corresponding to FIG3A ;

[0105] FIG4A is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0106] FIG4B is an enlarged schematic diagram of the dashed line frame S1 in FIG4A ;

[0107] FIG4C is a schematic diagram of a single film layer of the gate line layer in FIG4A ;

[0108] FIG4D is a schematic diagram of a single film layer of the active layer in FIG4A ;

[0109] FIG4E is a schematic diagram of a single film layer of the data line in FIG4A ;

[0110] FIG4F is a schematic diagram of a single film layer of the first insulating layer in FIG4A ;

[0111] FIG4G is a schematic diagram of a single film layer of the pixel electrode in FIG4A ;

[0112] FIG4H is a schematic diagram of light effect simulation corresponding to FIG4A ;

[0113] FIG5A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0114] FIG5B is an enlarged schematic diagram of the dotted line frame S1 in FIG5A ;

[0115] FIG5C is a schematic diagram of a single film layer of the gate line layer in FIG5A ;

[0116] FIG5D is a schematic diagram of a single film layer of the active layer in FIG5A ;

[0117] FIG5E is a schematic diagram of a single film layer of the data line in FIG5A ;

[0118] FIG5F is a schematic diagram of a single film layer of the first insulating layer in FIG5A ;

[0119] FIG5G is a schematic diagram of a single film layer of the pixel electrode in FIG5A ;

[0120] FIG5H is a schematic diagram of light effect simulation corresponding to FIG5A ;

[0121] FIG6A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0122] FIG6B is an enlarged schematic diagram of the dashed line frame S1 in FIG6A ;

[0123] FIG6C is a schematic diagram of a single film layer of the gate line layer in FIG6A ;

[0124] FIG6D is a schematic diagram of a single film layer of the active layer in FIG6A ;

[0125] FIG6E is a schematic diagram of a single film layer of the data line in FIG6A ;

[0126] FIG6F is a schematic diagram of a single film layer of the first insulating layer in FIG6A ;

[0127] FIG6G is a schematic diagram of a single film layer of the first conductive layer in FIG6A ;

[0128] FIG6H is a schematic diagram of a single film layer of the second insulating layer in FIG6A ;

[0129] FIG6I is a schematic diagram of a single film layer of the pixel electrode in FIG6A ;

[0130] FIG6J is a schematic diagram of a black matrix corresponding to FIG6A ;

[0131] FIG6K is a schematic diagram of light effect simulation corresponding to FIG6A ;

[0132] FIG7 is a schematic diagram of dark lines in a conventional 8-domain structure;

[0133] FIG8 is a schematic diagram of dark lines of an array substrate provided in an embodiment of the present disclosure;

[0134] FIG9 is a schematic diagram of a sub-pixel equivalent circuit provided by an embodiment of the present disclosure;

[0135] FIG. 10 is a schematic cross-sectional view of a display panel provided in an embodiment of the present disclosure.

[0136] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure. The implementation method can be implemented in a variety of different forms. Ordinary technicians in the technical field can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents recorded in the following implementation methods. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0137] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0138] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%. In this specification, "substantially the same" may refer to a situation where the values ​​differ by less than 10%.

[0139] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0140] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0141] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0142] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0143] In this specification, a transistor refers to an element including at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, a channel region refers to a region where current mainly flows.

[0144] In addition, the gate of a transistor may be referred to as a control electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0145] In this specification, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle may be greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle may be greater than 85° and less than 95°.

[0146] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0147] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0148] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0149] High-resolution products, such as 8K and 16K display products, are the main direction of subsequent products. However, the current 8K products using vertical alignment liquid crystal (VA) have problems with low transmittance and poor color deviation.

[0150] In view of this, referring to FIGS. 1A-1G, 2A-2G, 3A-3G, 4A-4G, 5A-5G, and 6A-6G, an embodiment of the present disclosure provides an array substrate, which includes:

[0151] Substrate 1;

[0152] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0153] A plurality of data lines 3 extend along a second direction Y; specifically, the second direction Y may intersect the first direction X; specifically, the second direction Y may be perpendicular to the first direction X; specifically, the second direction Y may be a direction of a pixel electrode column, and the first direction X may be a direction of a pixel electrode row;

[0154] A plurality of pixel electrodes 4, the pixel electrode 4 comprising: a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2; the first pixel electrode 41 comprises: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along a first direction X; the second pixel electrode 42 comprises: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X; specifically, for example, in conjunction with FIG. 1G , the pixel electrode 4 comprises the first pixel electrode 41 located on the upper side of the gate line 2, and the second pixel electrode 42 located on the lower side of the gate line 2, wherein the first pixel electrode 41 comprises the first sub-pixel electrode 411 located on the left side, and the second sub-pixel electrode 412 located on the right side; the second pixel electrode 42 comprises the third sub-pixel electrode 421 located on the left side, and the fourth sub-pixel electrode 422 located on the right side;

[0155] One of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. The brightness of the two electrically connected together is different from the brightness of the other two. Specifically, for example, the first sub-pixel electrode 411 may be electrically connected to the third sub-pixel electrode 421, and the second sub-pixel electrode 412 may be electrically connected to the fourth sub-pixel electrode 422; or the first sub-pixel electrode 411 may be electrically connected to the fourth sub-pixel electrode 422, and the second sub-pixel electrode 412 may be electrically connected to the third sub-pixel electrode 42.

[0156] In the embodiment of the present disclosure, the pixel electrode 4 includes: a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2; the first pixel electrode 41 includes: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along the first direction X, and the second pixel electrode 42 includes: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X; and one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422, that is, one pixel electrode 4 is divided into two parts, the upper half is divided into two parts, the lower half is also divided into two parts, and the brightness of the two parts electrically connected together is different from the brightness of the other two parts, and an 8-domain distribution can be formed in one sub-pixel, and compared with the conventional 8-domain structure, the array substrate provided in the embodiment of the present disclosure has fewer dark lines, better transmittance, and can compensate for each other in viewing angles, thereby improving the color deviation of left and right viewing angles.

[0157] Specifically, as shown in Figures 7 and 8, Figure 7 shows the dark lines of a conventional 8-domain structure. It can be seen that there are more dark lines, which have a great impact on the transmittance. Figure 8 shows the dark lines of the array substrate provided in an embodiment of the present disclosure. It can be clearly seen that the number of dark lines is significantly reduced. In comparison, the 8-domain array substrate structure provided in the disclosed embodiment has obvious advantages in improving the transmittance. Moreover, the 8-domain structure shown in Figure 7 does not have a good liquid crystal angle that can compensate for the left and right viewing angles. The horizontal liquid crystals are all facing right, and there is no horizontal liquid crystal facing left. However, the array substrate provided in the embodiment of the present disclosure shown in Figure 8 can make the horizontal liquid crystals in the left and right directions compensate for each other's viewing angles, thereby improving the color deviation of the left and right viewing angles.

[0158] As shown in Figures 1A, 1G and 8, in a pixel electrode 4, the first pixel electrode 41 is a U-shaped slit, and the second pixel electrode 42 is an inverted U-shaped Slit; in conjunction with the extension direction of the slit F, the first pixel electrode 41 can be set with two liquid crystal alignment directions, which can be 225° and 135° respectively; the second pixel electrode 42 can be set with two liquid crystal alignment directions, which are 315° and 45° respectively; and combined with the left and right divided light and dark areas, an alignment mode of 8 domains in a sub-pixel can be formed when using SUVA technology.

[0159] It should be noted that in the embodiment of the present disclosure, one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. The first sub-pixel electrode 411 and the second sub-pixel electrode 412 may be electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 at the layer where the pixel electrode 4 is located, while the other two may not be connected at the layer where the pixel electrode 4 is located, and may be electrically connected through other structures, for example, both are connected to the same transistor drain. Specifically, for example, the first sub-pixel electrode 411 and the third sub-pixel electrode 421 are electrically connected at the layer where the pixel electrode 4 is located, and the two present one brightness; while the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are not electrically connected at the layer where the pixel electrode 4 is located, but both may be connected to the same transistor drain (i.e., electrically connected through the drain layer) to achieve another brightness, and the brightness of the two connected at the layer where the pixel electrode 4 is located may be different from the brightness of the other two.

[0160] It can be understood that the brightness of the two connected together by the main power is different from the brightness of the other two, which refers to the brightness comparison within a sub-pixel when the display panel is powered on and lit.

[0161] In a possible implementation, in combination with Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, 5A-5G, and 6A-6G, the array substrate further includes: a plurality of transistors T; a plurality of transistors electrically connected to the same pixel electrode 4, all electrically connected to the same data line 3 and the same gate line 2, for example, as shown in Figure 1B, there are three transistors electrically connected to the same pixel electrode 4, namely a first transistor T1, a second transistor T2, and a third transistor T3, and the three transistors are all electrically connected to the same data line 3 and the same gate line 2; the second sub-pixel electrode 412 is located on a side of the first sub-pixel electrode 411 away from the electrically connected data line 3, and the fourth sub-pixel electrode 422 is located on a side of the third sub-pixel electrode 421 away from the electrically connected data line 3; the first sub-pixel electrode 411 is electrically connected to the fourth sub-pixel electrode 422. Specifically, the first sub-pixel electrode 411 is electrically connected to the fourth sub-pixel electrode 422 at the layer where the pixel electrode 4 is located, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are both electrically connected to the second electrode TC of the second transistor T2. In the disclosed embodiment, the first sub-pixel electrode 411 is electrically connected to the fourth sub-pixel electrode 422 at the pixel electrode 4, and the second sub-pixel electrode 412 is electrically connected to the third sub-pixel electrode 421, that is, the four parts of the pixel electrode 4 are cross-electrically connected in pairs, which is conducive to forming an 8-domain distribution in the same pixel electrode 4.

[0162] It should be noted that the multiple transistors electrically connected to the same pixel electrode 4 may refer to being electrically connected to the same pixel electrode 4 in a direct or indirect manner. For example, the first transistor T1 and the second transistor T2 may be directly electrically connected to the pixel electrode 4, and the third transistor T3 may also be considered to be electrically connected to the pixel electrode 4 because it is electrically connected to the second transistor T2. Specifically, the multiple transistors electrically connected to the same pixel electrode 4 may also be transistors driving the same pixel electrode 4.

[0163] In a possible implementation, in combination with FIG. 1A to FIG. 1G , the array substrate further includes: a first signal line 5 extending along a second direction Y; the plurality of transistors T include: a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0164] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422; specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via hole K1;

[0165] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421; specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through the second via hole K2; the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through the third via hole K3;

[0166] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2 , the first electrode TB of the third transistor T3 multiplexes the second electrode TC of the second transistor T2 , and the second electrode TC of the third transistor T3 multiplexes the first signal line 5 .

[0167] 9 may be an equivalent circuit diagram corresponding to FIG. 1B , wherein S is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal to the current sub-pixel, that is, the data line electrically connected to the current sub-pixel, S is the data line on the right side of the pixel, and is also the data line of the horizontally adjacent pixels, and the pixel circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor Cpd_bright, a second capacitor Cgp_bright, a third capacitor Cst_bright, a fourth capacitor Clc_bright, a fifth capacitor Cpp_bright, a sixth capacitor Cpd_bright, a seventh capacitor Cpd_dark, an eighth capacitor Cgp_dark, a ninth capacitor Cst_dark, a tenth capacitor Clc_dark, an eleventh capacitor Cpd_bright, a twelfth capacitor CgD, and a thirteenth capacitor CcD; wherein a first capacitor Cpd_bright is formed between the first pixel electrode 41 and the data line 3, a second capacitor Cgp_bright is formed between the first pixel electrode 41 and the gate line 2, and a first capacitor Cpd_bright is formed between the first pixel electrode 41 and the third common wiring 23. A third capacitor Cst_bright can be formed in the overlapping area, a fourth capacitor Clc_bright can be formed between the first pixel electrode 41 and the common electrode on the opposite substrate side, a fifth capacitor Cpp_bright can be formed between the first pixel electrode 41 and the second pixel electrode 42, a sixth capacitor Cpd_bright can be formed between the first pixel electrode 41 and the adjacent data line 3; a seventh capacitor Cpd_bright is formed between the second pixel electrode 42 and the data line 3, an eighth capacitor Cgp_bright is formed between the second pixel electrode 42 and the gate line 2, a ninth capacitor Cst_bright can be formed in the overlapping area of ​​the second pixel electrode 42 and the first common wiring 21, a tenth capacitor Clc_bright can be formed between the second pixel electrode 42 and the common electrode on the opposite substrate side, an eleventh capacitor Cpd_bright can be formed between the second pixel electrode 42 and the adjacent data line 3, a twelfth capacitor CgD can be formed in the overlapping area of ​​the gate line 2 and the first signal line 5, and a thirteenth capacitor CcD can be formed in the overlapping area of ​​the first signal line 5 and the first common wiring 21.

[0168] Specifically, in combination with Figure 1A and Figure 9, since the third transistor T3 is connected to the second transistor T2, the voltage loaded on the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially divided to the twelfth capacitor CgD (and / or the thirteenth capacitor CcD, and / or the first signal line 5) through the third transistor T3, so that the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and thus the luminous brightness of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the luminous brightness of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, thereby forming a display effect with different brightness and darkness in the sub-pixels.

[0169] In a possible implementation manner, the voltage applied to the first signal line 5 may be consistent with the voltage applied to the common electrode layer of the opposite substrate, that is, a common voltage is applied.

[0170] In a possible implementation, as shown in FIG. 1A to FIG. 1G , the pixel electrode 4 further includes: a first sub-pixel electrode convex portion 41A connected to the side of the first sub-pixel electrode 411 facing the third sub-pixel electrode 421; and the second electrode TB of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 through the first sub-pixel electrode convex portion 41A. In the disclosed embodiment, the first sub-pixel electrode 411 is further provided with a first sub-pixel electrode convex portion 41A on the side facing the third sub-pixel electrode 421, and the wiring method when connecting with the second electrode TB of the first transistor T1 is simple and regular, which is conducive to the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure when etching patterning when the layout of multiple patterns is complex.

[0171] In a possible embodiment, in combination with Figures 1A-1G, the pixel electrode 4 also includes: a connecting portion 44 connecting the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422; the connecting portion 44 includes: a first connecting portion 441 extending along the second direction Y, and a second connecting portion 442 extending along the third direction Z; one end of the first connecting portion 441 is electrically connected to one end of the first sub-pixel electrode 411 facing the third sub-pixel electrode 421, and the other end is electrically connected to the second connecting portion 442, and the other end of the second connecting portion 422 is electrically connected to one end of the fourth sub-pixel electrode 422 facing the second sub-pixel electrode 412.

[0172] In the disclosed embodiment, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are directly electrically connected at the layer where the pixel electrode 4 is located through the connecting portion 44, and the connecting portion 44 includes: a first connecting portion 441 extending along the second direction Y, and a second connecting portion 442 extending along the third direction Z. The wiring method of the connecting portion 44 is simple and regular, which is conducive to the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is complex.

[0173] In a possible implementation, the third direction Z intersects with the first direction X and the second direction Y; the third direction Z may form an angle of 0 to 90° with the second direction Y, specifically, the third direction Z may form an angle of 30 to 60° with the second direction Y, specifically, the third direction Z may form an angle of 45° with the second direction Y.

[0174] In a possible implementation, as shown in FIG. 1A to FIG. 1G , the pixel electrode 4 further includes: a third sub-pixel electrode convex portion 43A connected to the side of the third sub-pixel electrode 421 facing the first sub-pixel electrode 411; and the second electrode TC of the second transistor T2 is electrically connected to the third sub-pixel electrode 421 through the third sub-pixel electrode convex portion 43A. In the disclosed embodiment, the third sub-pixel electrode 421 is further provided with a third sub-pixel electrode convex portion 43A on the side facing the first sub-pixel electrode 411, and the wiring method when connecting with the second electrode TC of the second transistor T2 is simple and regular, which is conducive to the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure when etching patterning when the layout of multiple patterns is complex.

[0175] In a possible embodiment, in combination with Figures 1A to 1G, the pixel electrode 4 also includes: a second sub-pixel electrode extension portion 42B extending along the second direction Y, and a second sub-pixel electrode convex portion 42A; one end of the second sub-pixel electrode extension portion 42B is electrically connected to one end of the second sub-pixel electrode 412 on the side facing the fourth sub-pixel electrode 422, and the other end is electrically connected to the second sub-pixel electrode convex portion 42A; the second pole TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second sub-pixel electrode convex portion 42A. In the disclosed embodiment, a second sub-pixel electrode extension portion 42B extending along the second direction Y and a second sub-pixel electrode convex portion 42A are further provided on the side of the second sub-pixel electrode 412 facing the fourth sub-pixel electrode 422. This facilitates the electrical connection of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 to the second pole TC of the second transistor T2, and the wiring method for connecting the second sub-pixel electrode 412 and the second pole TC of the second transistor T2 is simple and regular, which facilitates the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is more complicated.

[0176] In a possible implementation, as shown in FIG. 1A-FIG , the extension direction of the second sub-pixel electrode extension portion 42B is parallel to the extension direction of the first connection portion 441, which is beneficial to the simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is complex.

[0177] In a possible implementation, as shown in FIGS. 1A to 1G , the second sub-pixel electrode convex portion 42A has a second sub-pixel electrode convex portion outer edge f1 away from one side of the second sub-pixel electrode 412 and extending along the first direction X; the third sub-pixel electrode convex portion 43A has a third sub-pixel electrode convex portion outer edge f2 away from one side of the third sub-pixel electrode 421 and extending along the first direction X;

[0178] The extension line of the outer edge f1 of the second sub-pixel electrode protrusion coincides with the extension line of the outer edge f2 of the third sub-pixel electrode protrusion; or, the extension line of the outer edge f1 of the second sub-pixel electrode protrusion overlaps at least partially with the third sub-pixel electrode protrusion 43A; or, the extension line of the outer edge f2 of the third sub-pixel electrode protrusion overlaps at least partially with the second sub-pixel electrode protrusion 42A. In this way, the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are both electrically connected to the second electrode TC of the second transistor T2, so that the wiring between the first pixel electrode 41 and the second pixel electrode 42 is simple, and the risk of short circuit failure is avoided when the layout of multiple patterns is complex, which is easy to occur during etching patterning.

[0179] In a possible implementation, as shown in FIG. 1A to FIG. 1G , a connection line e1 between the center of the third sub-pixel electrode protrusion 43A and the center of the first sub-pixel electrode protrusion 41A is parallel to the second direction Y. This is conducive to simplifying the pattern between the first pixel electrode 41 and the second pixel electrode 42 , and avoiding the risk of short circuit failure during etching patterning when the layout of multiple patterns is complex.

[0180] In a possible embodiment, in combination with Figures 1A-1G, the array substrate includes: a first axis f7 located between the first pixel electrode 41 and the second pixel electrode 42 and extending along the first direction X, and a third sub-pixel electrode protrusion 43A, which can be symmetrical with the first sub-pixel electrode protrusion 41A about the first axis f7.

[0181] In a possible embodiment, in combination with Figures 1A to 1G, the orthographic projection shape of the first sub-pixel electrode protrusion 41A on the substrate 1 may be a trapezoid, and the orthographic projection shape of the third sub-pixel electrode protrusion 43A on the substrate 1 may be a trapezoid; in a possible embodiment, the orthographic projection shape of the first sub-pixel electrode protrusion 41A on the substrate 1 may also be a rectangle, a semicircle or a semi-ellipse; the orthographic projection shape of the third sub-pixel electrode protrusion 43A on the substrate 1 may also be a rectangle, a semicircle or a semi-ellipse.

[0182] In a possible implementation, as shown in combination with FIG. 1A to FIG. 1G , the second electrode TC of the first transistor T1 includes: a first transistor first portion T1C1 extending along the first direction X; an orthographic projection of the first transistor first portion T1C1 on the substrate 1 has an overlapping area with an orthographic projection of the first sub-pixel electrode convex portion 41A on the substrate 1. In this way, the first transistor first portion T1C1 is conveniently electrically connected to the first sub-pixel electrode convex portion 41A through the first via hole K1.

[0183] In a possible implementation, in combination with Figures 1A-1G, the second electrode TC of the first transistor T1 includes: a first transistor second part T1C2 extending along the second direction Y and electrically connected to the first transistor first part T1C1; specifically, the orthographic projection of the first transistor second part T1C2 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0184] In a possible implementation, in combination with Figures 1A to 1G, the second electrode TC of the second transistor T2 includes: a second transistor first portion T2C1 extending along the first direction X, and a second transistor second portion T2C2 extending along the second direction Y and electrically connected to one end of the second transistor first portion T2C1; the orthographic projection of the second transistor first portion T2C1 on the substrate 1 has an overlapping area with the orthographic projection of the third sub-pixel electrode convex portion 43A on the substrate 1, so that the second transistor first portion T2C1 is electrically connected to the third sub-pixel electrode convex portion 43A through the second via K2; the orthographic projection of the second transistor second portion T2C2 on the substrate 1 has an overlapping area with the orthographic projection of the second sub-pixel electrode convex portion 42A on the substrate 1, so that the second transistor second portion T2C2 is electrically connected to the second sub-pixel electrode convex portion 42A through the third via K3.

[0185] In a possible implementation, in combination with what is shown in FIG. 1A-FIG , the second electrode TC of the second transistor T2 may further include: a second transistor third portion T2C3 electrically connected to the other end of the second transistor first portion T2C1 and extending along the second direction Y. Specifically, the orthographic projection of the second transistor third portion T2C3 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0186] In a possible implementation, as shown in FIG. 1A to FIG. 1G , at least a portion of the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-pixel electrode extension portion 42B on the substrate 1. Since the second portion T2C2 of the second transistor and the gate line 2 have an overlapping area, a coupling capacitor is formed therebetween, and the second sub-pixel electrode extension portion 42B covers a portion of the second portion T2C2 of the second transistor, which can shield a portion of the coupling capacitor between the second portion T2C2 of the second transistor and the gate line 2; moreover, at least a portion of the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-pixel electrode extension portion 42B on the substrate 1, which can make it easier to wire the array substrate, reduce the wiring width, and optimize the wiring layout setting.

[0187] In a possible implementation manner, the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 may not overlap with the orthographic projection of the second sub-pixel electrode extension portion 42B on the substrate 1 .

[0188] In a possible implementation, as shown in FIG. 1A to FIG. 1G , the first signal line 5 has a recessed portion 50; at least a portion of the orthographic projection of the second portion T2C2 of the second transistor on the substrate 1 is located in the area surrounded by the orthographic projection of the recessed portion 50 on the substrate 1. In the embodiment of the present disclosure, the first signal line 5 has the recessed portion 50, so that the first signal line 5 and the second electrode TC of the second transistor T2 can be arranged in the same layer while avoiding the second portion T2C2 of the second transistor, thereby preventing the first signal line 5 and the second electrode TC of the second transistor T2 from being short-circuited.

[0189] In a possible embodiment, in combination with Figures 1A-1G, the first signal line 5 includes: a first signal portion 51, a second signal portion 52, and a third signal portion 53 distributed in sequence along the second direction Y, and a fourth signal portion 54 extending along the first direction X and connecting the second signal portion 52 and the first signal portion 51, and a fifth signal portion 55 extending along the first direction X and connecting the second signal portion 52 and the third signal portion 53; an extension line of the first signal portion 51 coincides with an extension line of the third signal portion 53; an extension line of the second signal portion 52 does not coincide with an extension line of the first signal portion 51; the second signal portion 52, the fourth signal portion 54 and the fifth signal portion 55 constitute a recessed portion 50, and the fourth signal portion 54 and / or the fifth signal portion 55 at least partially overlap with the pixel electrode 4.

[0190] Specifically, the third signal portion 53 can be used as the second electrode TC of the third transistor T3 , so as to release part of the voltage of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 to the first signal line 5 through the third transistor T3 .

[0191] In a possible implementation, as shown in FIG. 1A to FIG. 1G , the first signal line 5 is in the same layer as the data line 3. In this way, the first signal line 5 is formed while the data line 3 is formed, so as to simplify the manufacturing process of the array substrate and reduce the manufacturing cost of the array substrate while achieving different display effects of light and dark in the same sub-pixel.

[0192] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a first common wiring 21 located at one side of the gate line 2 and extending along the first direction X; the plurality of transistors T include: a first transistor T1 electrically connected to the data line 3, a second transistor T2, and a third transistor T3;

[0193] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422; specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via hole K1;

[0194] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421; specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through the second via hole K2; the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through the third via hole K3;

[0195] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2 , the first electrode TB of the third transistor T3 is multiplexed with the second electrode TC of the second transistor T2 , and the second electrode TC of the third transistor T3 is electrically connected to the first common wiring 21 .

[0196] In the disclosed embodiment, since the third transistor T3 is connected to the second transistor T2, the voltage loaded on the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially distributed to the first common wiring 21 through the third transistor T3, so that the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and thus the luminous brightness of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the luminous brightness of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, thereby forming a display effect with different brightness and darkness in the sub-pixels.

[0197] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the pixel electrode 4 further includes: a connecting portion 44 connecting the first sub-pixel electrode 412 and the fourth sub-pixel electrode 422, and a first lap portion PD1 connected to the connecting portion 44; the connecting portion 44 includes: a third connecting portion 443 extending along the first direction X, a fourth connecting portion 444, and a fifth connecting portion 445 extending along the second direction Y;

[0198] One end of the third connection portion 443 is connected to the first sub-pixel electrode 411, one end of the fourth connection portion 444 is connected to the fourth sub-pixel electrode 422, one end of the fifth connection portion 445 is connected to the other end of the third connection portion 443, and the other end of the fifth connection portion 445 is connected to the other end of the fourth connection portion 444; the first lap portion PD1 is electrically connected to the first connection portion 441 and is away from the first sub-pixel electrode 411 connected thereto;

[0199] The second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 421 through the first connecting portion PD1 .

[0200] In the disclosed embodiment, the connection portion 44 includes: a third connection portion 443 extending along the first direction X, a fourth connection portion 444, and a fifth connection portion 445 extending along the second direction Y. The wiring of the connection portion 44 is regular, which is conducive to the simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure during etching patterning when the layout of multiple patterns is more complex; moreover, the connection portion 44 is also connected to the first overlapping portion PD1, so as to facilitate the electrical connection between the first overlapping portion PD1 and the second electrode TC of the first transistor T1 through the first via K1.

[0201] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the pixel electrode further includes: a first transfer portion PZ1 extending along the first direction X, a second transfer portion PZ2 extending along the second direction Y, and a second overlap portion PD2; one end of the first transfer portion PZ1 is electrically connected to one end of the second sub-pixel electrode 412 on the side facing the fourth sub-pixel electrode 422, and the other end of the first transfer portion PZ1 is electrically connected to one end of the second transfer portion PZ2; the other end of the second transfer portion PZ2 is electrically connected to the second overlap portion PD2; and the second electrode TB of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 via the second overlap portion PD2. In the embodiment of the present disclosure, a first transfer portion PZ1, a second transfer portion PZ2 extending along the second direction Y, and a second overlap portion PD2 are further provided on one side of the second sub-pixel electrode 412, so as to realize the electrical connection between the second sub-pixel electrode 412 and the second pole TB of the second transistor T2, and the wiring method of electrically connecting the second sub-pixel electrode 412 and the second pole TB of the second transistor T2 is simple and regular, which is conducive to the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that are prone to occur during etching patterning when the layout of multiple patterns is more complicated.

[0202] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the second transfer portion PZ2 is parallel to the extension direction of the fifth connection portion 445. This is beneficial for simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is complex.

[0203] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, an extension line of the first transfer portion PZ1 coincides with an extension line of the third connection portion 443. This is beneficial for simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is complex.

[0204] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the pixel electrode 4 further includes: a third transfer portion PZ3 extending along the first direction X, and a third overlap portion PD3; one end of the third transfer portion PZ3 is electrically connected to one end of the third sub-pixel electrode 421 facing the first sub-pixel electrode 411, and the other end of the third transfer portion PZ3 is electrically connected to the third overlap portion PD3; the second pole TC of the second transistor T2 is electrically connected to the third sub-pixel electrode 421 via the third overlap portion PD3. In the disclosed embodiment, a third transfer portion PZ3 and a third overlap portion PD3 are further provided on one side of the third sub-pixel electrode 421, so as to realize the electrical connection between the third sub-pixel electrode 421 and the second electrode TB of the second transistor T2, and the wiring method of the electrical connection between the third sub-pixel electrode 421 and the second electrode TB of the second transistor T2 is simple and regular, which is conducive to the simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects during etching patterning when the layout of multiple patterns is more complicated.

[0205] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, an extension line of the third transfer portion PZ3 coincides with an extension line of the fourth connection portion 444. This is beneficial for simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is complex.

[0206] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, a first gap J1 is provided between the third connection portion 443 and the first pixel electrode 41; a second gap J2 is provided between the fourth connection portion 444 and the second pixel electrode 42; a third gap J3 is provided between the first transition portion PZ1 and the first pixel electrode 41, and a fourth gap J4 is provided between the third transition portion PZ3 and the second pixel electrode 42. Specifically, for example, as shown in FIG. 2G , the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are two parts with brighter brightness, the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are two parts with darker brightness, and the first adapter PZ1 is a structure electrically connected to the second sub-pixel electrode 412 with darker brightness, and the loaded voltage is also lower, and it has a longer relative setting area with the first sub-pixel electrode 411 with a larger loaded voltage. By providing a third gap J3 between the first adapter PZ1 and the first sub-pixel electrode 411, it is possible to avoid problems such as breakdown when the two are close to each other and have a large voltage difference. Similarly, a fourth gap J4 is provided between the third adapter PZ3 and the fourth sub-pixel electrode 422, so as to avoid problems such as breakdown when the two are close to each other and have a large voltage difference. There is a first gap J1 between the third connection portion 443 and the first pixel electrode 41; there is a second gap J2 between the fourth connection portion 444 and the second pixel electrode 42, which can form a design that is relatively symmetrical with the third gap J3 and the fourth gap J4, which is conducive to the regular and neat layout of multiple patterns.

[0207] In a possible implementation, referring to FIGS. 2A-2G , 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a fourth lap portion PD4 ; the second electrode TC of the third transistor T3 is electrically connected to the first common wiring 21 via the fourth lap portion PD4 .

[0208] In a possible implementation, referring to FIGS. 2A-2G , 3A-3G, 4A-4G, and 5A-5G, the second electrode TC of the third transistor T3 may be electrically connected to the first common wiring 21 through a fourth via K4 .

[0209] In a possible implementation, referring to FIG. 2I, FIG. 2I may be a cross-sectional schematic diagram along the dotted line EF in FIG. 2B. Specifically, the fourth via K4 may be a semi-via design, the fourth via K4 partially exposes the first common wiring 21, partially exposes the second electrode TC of the third transistor T3, the fourth lap portion PD4 partially contacts the first common wiring 21 at the fourth via K4, and partially contacts the second electrode TC of the third transistor T3, so as to realize the electrical connection between the first common wiring 21 and the second electrode TC of the third transistor T3 through the fourth lap portion PD4. Specifically, the fourth via K4 is a semi-via design, so that the fourth via K4 may form a step structure inside, play a drainage role for the alignment liquid, and avoid the technical effect of the moiré phenomenon on the screen.

[0210] In a possible embodiment, referring to Figures 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the fourth overlap portion PD4 has a fourth overlap portion outer edge f3 along the first direction X, and the second overlap portion PD2 has a second overlap portion outer edge f4 extending along the first direction X; the first overlap portion PD1 has a first overlap portion outer edge f5 extending along the second direction Y, and the third overlap portion PD3 has a third overlap portion outer edge f6 extending along the second direction Y; the extension line of the fourth overlap portion outer edge f3 coincides with the extension line of the second overlap portion outer edge f4; the extension line of the first overlap portion outer edge f5 coincides with the extension line of the third overlap portion outer edge f6.

[0211] In the disclosed embodiment, the extension line of the outer edge f3 of the fourth overlap portion coincides with the extension line of the outer edge f4 of the second overlap portion; the extension line of the outer edge f5 of the first overlap portion coincides with the extension line of the outer edge f6 of the third overlap portion. The pattern distribution between the first pixel electrode 41 and the second pixel electrode 42 is simple and regular, avoiding the risk of short circuit defects during etching patterning when the layout of multiple patterns is complex.

[0212] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the second electrode TC of the first transistor T1 includes: a first transistor first portion T1C1 extending along the first direction X; an orthographic projection of the first transistor first portion T1C1 on the substrate 1 has an overlapping area with an orthographic projection of the first lap portion PD1 on the substrate 1. In this way, the first transistor first portion T1C1 is conveniently electrically connected to the first lap portion PD1 through the first via K1.

[0213] In a possible implementation, referring to FIGS. 2A-2G , 3A-3G , 4A-4G , and 5A-5G , the second electrode TC of the first transistor T1 includes: a first transistor second portion T1C2 extending along the second direction Y and electrically connected to the first transistor first portion T1C1 ; specifically, the orthographic projection of the first transistor second portion T1C2 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1 .

[0214] In a possible implementation, referring to FIGS. 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the second electrode TC of the second transistor T2 includes: a first portion T2C1 of the second transistor extending along the first direction X, and a second portion T2C2 of the second transistor extending along the second direction Y and electrically connected to one end of the first portion T2C1 of the second transistor; an orthographic projection of the first portion T2C1 of the second transistor on the substrate 1 has an overlapping area with an orthographic projection of the third overlapping portion PD3 on the substrate 1, so that the first portion T2C1 of the second transistor is electrically connected to the third overlapping portion PD3 through the second via K2; an orthographic projection of the second portion T2C2 of the second transistor on the substrate has an overlapping area with an orthographic projection of the second overlapping portion PD2 on the substrate 1, so that the second portion T2C2 of the second transistor is electrically connected to the second overlapping portion PD2 through the third via K3.

[0215] In a possible implementation, referring to FIGS. 2A-2G , 3A-3G , 4A-4G , and 5A-5G , the second electrode TC of the second transistor T2 may further include: a second transistor third portion T2C3 electrically connected to the other end of the second transistor first portion T2C1 and extending along the second direction Y. Specifically, the orthographic projection of the second transistor third portion T2C3 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1 .

[0216] In a possible implementation, referring to FIGS. 2A-2G , 3A-3G , 4A-4G , and 5A-5G , the second electrode TC of the third transistor T3 may include: a third transistor first portion T3C1 extending along the second direction Y, and a third transistor second portion T3C2 extending along the first direction X and connected to the third transistor first portion T3C1.

[0217] In a possible implementation, referring to FIGS. 2A-2G , 3A-3G, 4A-4G, and 5A-5G, an extension direction of the first portion T3C1 of the third transistor is parallel to an extension direction of the second portion T2C2 of the second transistor.

[0218] In a possible implementation, referring to FIG. 1A to FIG. 1G , the array substrate further includes: a first common wiring 21 located at one side of the gate line 2 and extending along the first direction; the first common wiring 21 is disconnected at a position where it intersects with the data line 3, so as to avoid the first common wiring 21 and the data line 3 from overlapping, thereby increasing the load of the data line 3 and affecting the signal transmission of the data line 3.

[0219] In a possible implementation, referring to FIGS. 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a second common routing group 22 electrically connected to the first common routing 21 and extending to a side away from the gate line 2, the second common routing group 22 including: two second common routings 220; the orthographic projection of the data line 3 on the substrate 1 and the gap between the two second common routings 220 of the same second common routing group 22 have an overlapping area on the orthographic projection of the substrate 1. The orthographic projection of the second common routing 220 on the substrate 1 is located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the second pixel electrode 42.

[0220] In a possible embodiment, referring to FIGS. 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the array substrate further includes: a third common routing line 23 located on the other side of the gate line 2 and extending along the first direction X, and a fourth common routing line group 24 connected to the third common routing line 23 and extending toward a side away from the gate line 2; the third common routing line 23 is disconnected at a position where it intersects with the data line 3, so as to avoid the third common routing line 23 from overlapping with the data line 3, thereby increasing the load of the data line 3 and affecting the signal transmission of the data line 3; the fourth common routing line group 24 includes: two fourth common routing lines 240; the orthographic projection of the data line 3 on the substrate 1 and the gap between the two fourth common routing lines 240 of the same fourth common routing line group 24 have an overlapping area in the orthographic projection of the substrate 1. The orthographic projection of the fourth common wiring 240 on the substrate 1 is located on both sides of the orthographic projection of the data line 3 on the substrate 1 , which can improve the coupling capacitance between the data line 3 and the first pixel electrode 41 .

[0221] In a possible implementation, the first common wiring 21 and the third common wiring 23 may be electrically connected by drilling holes in the display area in a bridge manner, or may be electrically connected in the non-display area. In a possible implementation, the array substrate may further include a non-display area located outside the display area, and the non-display area may be provided with a ring-shaped common wiring surrounding the display area, and the first common wiring 21 and the third common wiring 23 may both be electrically connected to the ring-shaped common wiring to have the same common voltage signal.

[0222] In a possible implementation, referring to FIG. 1A-FIG , the array substrate further includes: a fifth common routing line 25 extending along the first direction X and electrically connected to the second common routing line 220 , wherein the orthographic projection of the fifth common routing line 25 on the substrate passes through the central area of ​​the orthographic projection of the second pixel electrode 42 on the substrate 1 .

[0223] In a possible implementation, referring to FIGS. 1A-1G , the array substrate further includes: a sixth common line 26 extending along the first direction X and electrically connected to the fourth common line 240 , the orthographic projection of the sixth common line 26 on the substrate 1 passing through the central area of ​​the orthographic projection of the first pixel electrode 41 on the substrate 1 .

[0224] In a possible embodiment, referring to FIGS. 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the first sub-pixel electrode 411 and the second sub-pixel electrode 412 both include: a first sub-electrode portion P1 distributed along the second direction Y, and a second sub-electrode portion P2; the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 both include: a third sub-electrode portion P3 distributed along the second direction Y, and a fourth sub-electrode portion P4; the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 all have a plurality of slits F; and an extension direction of the slits F of the first sub-electrode portion P1 is the same as an extension direction of the slits F of the fourth sub-electrode portion P4; an extension direction of the slits F of the second sub-electrode portion P2 is the same as an extension direction of the slits F of the third sub-electrode portion P3.

[0225] In a possible implementation, the length of the slit F in the direction perpendicular to the extension direction may be 2 μm to 4 μm. Specifically, the length of the slit F in the direction perpendicular to the extension direction may be 3 μm. In the embodiment of the present disclosure, in the array substrate provided based on the embodiment of the present disclosure, when the length of the slit F in the direction perpendicular to the extension direction is reduced to 3 μm, the dark lines almost disappear.

[0226] Specifically, referring to Figures 1A-1G, 2A-2G, 3A-3G, 4A-4G, and 5A-5G, the angle formed by the extension direction of the slit F of the first sub-electrode portion P1 and the first direction X may be 40°-50°, for example, 45°; the angle formed by the extension direction of the slit F of the second sub-electrode portion P2 and the first direction X may be 130°-140°, for example, 135°; the angle formed by the extension direction of the slit F of the third sub-electrode portion P3 and the first direction X may be 130°-140°, for example, 135°; the angle formed by the extension direction of the slit F of the fourth sub-electrode portion P4 and the first direction X may be 40°-50°, for example, 45°.

[0227] Specifically, the angle formed by the liquid crystal alignment direction of the area where the first sub-electrode portion P1 is located and the first direction X can be 220° to 230°, for example, 225°; the angle formed by the liquid crystal alignment direction of the area where the second sub-electrode portion P2 is located and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the liquid crystal alignment direction of the area where the third sub-electrode portion P3 is located and the first direction X can be 310° to 320°, for example, 315°; the angle formed by the liquid crystal alignment direction of the area where the fourth sub-electrode portion P4 is located and the first direction X can be 40° to 50°, for example, 45°. When a pixel electrode 4 is located, there are four alignment directions, and when the light and dark areas are divided, an alignment mode of 8 domains in a sub-pixel can be formed when using the Super UV Photo Alignment (SUVA) technology.

[0228] In a possible implementation, referring to FIGS. 1A-1G and 4A-4G , the orthographic projection shapes of the first sub-pixel electrode 411 , the second sub-pixel electrode 412 , the third sub-pixel electrode 421 , and the fourth sub-pixel electrode 422 on the substrate 1 are all rectangular.

[0229] In a possible implementation, referring to FIG. 2A to FIG. 2G , the orthographic projection shapes of the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 on the substrate 1 are all trapezoidal; in the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their top sides opposite to each other (that is, they are arranged with their short sides opposite to each other); in the second sub-pixel electrode 412 and the third sub-pixel electrode 421, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their bottom sides opposite to each other (that is, they are arranged with their long sides opposite to each other). In the disclosed embodiment, the first pixel electrode 41 and the second pixel electrode 42 can be divided in a manner parallel to the extension direction of the slit F, which can have a better transmittance effect.

[0230] In a possible implementation, referring to FIG. 3A to FIG. 3G , the orthographic projection shapes of the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 on the substrate 1 are all trapezoidal; in the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their bottom sides opposite to each other (that is, they are arranged with their long sides opposite to each other); in the second sub-pixel electrode 412 and the third sub-pixel electrode 421, the trapezoidal first sub-electrode portion P1 and the trapezoidal second sub-electrode portion P2 are arranged with their top sides opposite to each other (that is, they are arranged with their short sides opposite to each other). In the disclosed embodiment, the first pixel electrode 41 and the second pixel electrode 42 can be divided in a manner perpendicular to the extension direction of the slit F, which can have a better transmittance effect.

[0231] In a possible implementation, referring to FIGS. 5A to 5G , the first sub-pixel electrode 411 includes: a first main portion PA1 extending and connected along the second direction Y, a second main portion PA2, and a first side portion PC1 extending along the first direction X, a plurality of first branches PB1 extending along the fourth direction G1 from the first main portion PA1 and the first side portion PC1, and a plurality of second branches PB2 extending along the fifth direction G2 from the second main portion PA2 and the first side portion PC1; the second sub-pixel electrode 412 includes: a third main portion PA3 extending and connected along the second direction Y, a fourth main portion PA4 extending and connected along the second direction Y, a third main portion PA5 extending and connected along the second direction Y, a third main portion PA6 extending and connected along the second direction Y, a third main portion PA7 extending and connected along the second direction Y, a third main portion PA8 extending and connected along the second direction Y, a third main portion PA9 extending and connected along the second direction Y, a third main portion PA1 extending and connected along the second direction Y, a third main portion PA2 extending and connected along the second direction The main portion PA4, the fifth main portion PA5 connected to one end of the third main portion PA3 and extending along the first direction X, the sixth main portion PA6 connected to one end of the fourth main portion PA4 and extending along the first direction X, a plurality of third branches PB3 extending from the third main portion PA3 and the fifth main portion PA5 along the fourth direction G1, and a plurality of fourth branches PB4 extending from the fourth main portion PA4 and the sixth main portion PA6 along the fifth direction G2; the plurality of first branches PB1 and the plurality of third branches PB3 are interdigitated, and the plurality of second branches PB2 and the plurality of fourth branches PB4 are interdigitated;

[0232] The third sub-pixel electrode 421 includes: a seventh main portion PA7 extending and connected along the second direction Y, an eighth main portion PA8, a ninth main portion PA9 connected to one end of the seventh main portion PA7 and extending along the first direction X, a tenth main portion PA10 connected to one end of the eighth main portion PA8 and extending along the first direction X, a plurality of fifth branches PB5 extending from the seventh main portion PA7 and the ninth main portion PA9 along the fourth direction G1, and a plurality of sixth branches PB6 extending from the eighth main portion PA8 and the tenth main portion PA10 along the fifth direction G2; the fourth sub-pixel electrode 421 includes: a seventh main portion PA7 extending and connected along the second direction Y, an eighth main portion PA8, a ninth main portion PA9 connected to one end of the seventh main portion PA7 and extending along the first direction X, a tenth main portion PA10 connected to one end of the eighth main portion PA8 and extending along the first direction X, The pixel electrode 422 includes: an eleventh main portion PA11 extending and connected along the second direction Y, a twelfth main portion PA12, and a second side portion PC2 extending along the first direction X, a plurality of seventh branches PB7 extending along the fourth direction G1 from the eleventh main portion PA11 and the second side portion PC2, and a plurality of eighth branches PB8 extending along the fifth direction G2 from the twelfth main portion PA12 and the second side portion PC2; a plurality of fifth branches PB5 and a plurality of seventh branches PB7 are distributed in a forked manner, and a plurality of sixth branches PB6 and a plurality of eighth branches PB8 are distributed in a forked manner.

[0233] It should be noted that, for the array substrate structure corresponding to Figures 2A, 3A, and 5A provided in the embodiment of the present disclosure, a first signal line 5 can be set, and part of the voltage can be released to the first signal line 5 through the third transistor T3 to achieve a display effect with different light and dark; similarly, for the array substrate shown in Figure 1A provided in the embodiment of the present disclosure, the first signal line 5 can also be not set, and part of the voltage can be released to the first common wiring 21 through the third transistor T3 to achieve a display effect with different light and dark, and the embodiment of the present disclosure does not impose any restrictions on this.

[0234] In a possible embodiment, referring to FIGS. 6A-6J , the array substrate further includes: a first conductive layer 7 located on the side of the pixel electrode 4 facing the substrate 1; the first conductive layer 7 has a first hollow L1, a second hollow L2, a third hollow L3, and a fourth hollow L4; at least a portion of the orthographic projection of the first hollow L1 on the substrate 1 overlaps with at least a portion of the orthographic projection of the first sub-electrode portion P1 on the substrate 1; at least a portion of the orthographic projection of the second hollow L2 on the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-electrode portion P2 on the substrate 1; at least a portion of the orthographic projection of the third hollow L3 on the substrate 1 overlaps with at least a portion of the orthographic projection of the third sub-electrode portion P3 on the substrate 1; at least a portion of the orthographic projection of the fourth hollow L4 on the substrate 1 overlaps with at least a portion of the orthographic projection of the fourth sub-electrode portion P4 on the substrate 1.

[0235] In the disclosed embodiment, for a display panel in a VA display mode in which an array substrate is provided with a pixel electrode layer and an opposing substrate is provided with a common electrode layer, a first conductive layer 7 is further provided on the side of the pixel electrode 4 facing the substrate 1; the first conductive layer 7 has a first hollow L1, a second hollow L2, a third hollow L3, and a fourth hollow L4, which can make the liquid crystal twist more uniform, reduce the dark lines corresponding to the pixel electrode, reduce the width of the black matrix, and improve the transmittance of the display panel; in addition, in addition to the vertical electric field formed by the pixel electrode and the common electrode in the array substrate, the pixel electrode and the first conductive layer 7 will form a lateral electric field, which can increase the deflection direction of the liquid crystal and improve the color deviation problem of the display panel.

[0236] Specifically, the first conductive layer 7 can be located between the substrate 1 and the layer where the pixel electrode 4 is located. Specifically, the first conductive layer 7 can be loaded with the same signal as the common electrode layer of the opposite substrate. The first conductive layer 7 can be a transparent electrode layer, and the material of the first conductive layer 7 can be indium tin oxide.

[0237] In a possible implementation, as shown in FIG6G , the first conductive layer 7 may further include a first conductive connection portion 71, the orthographic projection of the first conductive connection portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1, and covers the orthographic projection of the gate line 2 on the substrate 1. In the disclosed embodiment, the orthographic projection of the first conductive connection portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1, and the coupling capacitance between the pixel electrode and the data line 3 and the coupling capacitance between the pixel electrode and the gate line 2 can be shielded by the first conductive connection portion 71, so that the second common wiring 220 (and / or the fourth common wiring 240) can be avoided, or the number or line width of the second common wiring 220 (and / or the fourth common wiring 240) can be reduced, thereby increasing the transmittance of the display panel.

[0238] In a possible implementation, as shown in FIG. 6G , the first conductive layer 7 may further include a fifth hollow L5, a sixth hollow L6, a seventh hollow L7, and an eighth hollow L8; wherein, at least a portion of the orthographic projection of the fifth hollow L5 on the substrate 1 may overlap with at least a portion of the orthographic projection of the first via K1 on the substrate 1; at least a portion of the orthographic projection of the sixth hollow L6 on the substrate 1 may overlap with at least a portion of the orthographic projection of the second via K2 on the substrate 1; at least a portion of the orthographic projection of the seventh hollow L7 on the substrate 1 may overlap with at least a portion of the orthographic projection of the third via K3 on the substrate 1; the fifth hollow L5, the sixth hollow L6, and the seventh hollow L7 are provided to facilitate conduction between the pixel electrode 4 above the first conductive layer 7 and the transistor below the first conductive layer 7.

[0239] In the embodiment of the present disclosure, the first conductive layer 7 may further include an eighth hollow L8, which can avoid overlapping capacitance between the gate line 2 and the first conductive layer 7 and affect the pixel charging rate; if the first conductive layer 7 is completely hollowed out in the area where the gate line 2 is located, light leakage will occur. In the embodiment of the present disclosure, the eighth hollow L8 is only set in the partial area where the first conductive layer 7 and the gate line 2 overlap, which can reduce light leakage, reduce the overlapping capacitance between the gate line 2 and the first conductive layer 7, and ensure the charging rate.

[0240] In a possible embodiment, the length h2 of the eighth hollow L8 in the first direction X may be one-fifth to four-fifths of the length h1 of the second hollow L2 in the first direction; in a possible embodiment, the length h2 of the eighth hollow L8 in the first direction X may be one-quarter to three-quarters of the length h1 of the second hollow L2 in the first direction; in a possible embodiment, the length h2 of the eighth hollow L8 in the first direction X may be one-half of the length h1 of the second hollow L2 in the first direction.

[0241] In a possible embodiment, the length h4 of the eighth hollow L8 in the second direction Y may be one-fifth to four-fifths of the distance h3 between the second hollow L2 and the third hollow L3; in a possible embodiment, the length h4 of the eighth hollow L8 in the second direction Y may be one-quarter to three-quarters of the distance h3 between the second hollow L2 and the third hollow L3; in a possible embodiment, the length h4 of the eighth hollow L8 in the second direction Y may be one-half of the distance h3 between the second hollow L2 and the third hollow L3.

[0242] In a possible implementation, an outer edge extension line of the eighth hollow L8 extending along the second direction Y and away from a side of the sixth hollow L6 coincides with an outer edge extension line of the second hollow L2 extending along the second direction Y.

[0243] In a possible implementation, in combination with Figures 6A-6J and Figure 10, the data line 3 can be located on the side of the gate line 2 away from the substrate 1, the first conductive layer 7 can be located on the side of the data line 3 away from the gate line 2, the pixel electrode 4 can be located on the side of the first conductive layer 7 away from the data line 3, a gate insulating layer can be provided between the layer where the gate line 2 is located and the layer where the data line 3 is located, an active layer can be provided between the gate insulating layer and the data line 3 (the active layer can include an active pattern 6, and the active layer material can be amorphous silicon, low-temperature polycrystalline silicon, metal oxide and other materials, which are not limited here), a first insulating layer 91 can be provided between the data line 3 and the first conductive layer 7, and a second insulating layer 92 can be provided between the first conductive layer 7 and the pixel electrode 4.

[0244] In combination with Figures 1H, 2H, 3H, 4H, 5H and 6K, the embodiments of the present disclosure perform optical simulations on different array substrate structures. By comparing the horizontal dark lines in the center of the sub-pixels, it can be clearly seen that for the array substrate structures corresponding to Figures 1H, 2H, 3H, 4H and 5H without the first conductive layer 7, the transmittance corresponding to the structure of Figure 2A is the highest.

[0245] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes: an array substrate as provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer.

[0246] In a possible implementation, in combination with FIGS. 6A to 6J and FIG. 10 , the display panel may further be provided with a black matrix 8, and the orthographic projection of the black matrix 8 on the substrate 1 may cover the orthographic projection of the gate line 2 on the substrate 1, and cover the orthographic projection of the data line 3 on the substrate 1. Specifically, the counter substrate may include a counter substrate 90, and the black matrix 8 may be located between the counter substrate 90 and the common electrode layer (not shown in FIG. 10 ).

[0247] In a possible implementation, as shown in FIG. 10 , the first conductive layer 7 is located on the side of the pixel electrode 4 away from the opposing substrate. In this public embodiment, the first conductive layer 7 is located on the side of the pixel electrode 4 away from the opposing substrate, which can block (or shield) the first overlap capacitance between the pixel electrode 4 and the gate line 2 and the second overlap capacitance between the pixel electrode 4 and the data line 3, greatly reducing the risk of crosstalk. At the same time, due to the presence of the first conductive layer 7, the distance between the pixel electrodes 4 can be reduced, so that the pixel electrode 4 overlaps with the gate line 2, and the pixel electrode 4 overlaps with the data line 3, reducing the risk of liquid crystal light leakage, thereby reducing the width of the black matrix, increasing the pixel aperture ratio, and improving the pixel transmittance.

[0248] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0249] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0250] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0251] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

An array substrate, wherein: include: substrate; A plurality of gate lines, located on one side of the substrate and extending along a first direction; A plurality of data lines extending along a second direction; A plurality of pixel electrodes, wherein the pixel electrodes include: a first pixel electrode located on one side of the gate line, and a second pixel electrode located on the other side of the gate line; the first pixel electrode includes: a first sub-pixel electrode and a second sub-pixel electrode distributed along the first direction; the second pixel electrode includes: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the first direction; one of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode. The array substrate according to claim 1, wherein: The array substrate also includes: a plurality of transistors; the plurality of transistors electrically connected to the same pixel electrode are all electrically connected to the same data line and the same gate line; the second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode. The array substrate according to claim 2, wherein: The array substrate also includes: a first signal line extending along the second direction; the multiple transistors include: a first transistor, a second transistor, and a third transistor; the control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode; the control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode; the control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor, and the second electrode of the third transistor reuses the first signal line. The array substrate according to claim 3, wherein: The pixel electrode further includes: a first sub-pixel electrode protrusion connected to the first sub-pixel electrode on a side facing the third sub-pixel electrode; and a second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion. The array substrate according to claim 4, wherein: The pixel electrode also includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connecting portion includes: a first connecting portion extending along the second direction, and a second connecting portion extending along a third direction; the third direction intersects with the first direction and the second direction; one end of the first connecting portion is electrically connected to one end of the first sub-pixel electrode facing the third sub-pixel electrode, and the other end is electrically connected to the second connecting portion, and the other end of the second connecting portion is electrically connected to one end of the fourth sub-pixel electrode facing the second sub-pixel electrode. The array substrate according to any one of claims 3 to 5, wherein: The pixel electrode further includes: a third sub-pixel electrode protrusion connected to the third sub-pixel electrode facing the first sub-pixel electrode; and a second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third sub-pixel electrode protrusion. The array substrate according to claim 6, wherein: The pixel electrode also includes: a second sub-pixel electrode extension portion extending along the second direction, and a second sub-pixel electrode convex portion; one end of the second sub-pixel electrode extension portion is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end is electrically connected to the second sub-pixel electrode convex portion; the second pole of the second transistor is electrically connected to the second sub-pixel electrode through the second sub-pixel electrode convex portion. The array substrate according to claim 7, wherein: An extending direction of the second sub-pixel electrode extending portion is parallel to an extending direction of the first connecting portion. The array substrate according to claim 7 or 8, wherein: The second sub-pixel electrode convex portion has an outer edge of the second sub-pixel electrode convex portion away from one side of the second sub-pixel electrode and extending along the first direction; the third sub-pixel electrode convex portion has an outer edge of the third sub-pixel electrode convex portion away from one side of the third sub-pixel electrode and extending along the first direction; the extension line of the outer edge of the second sub-pixel electrode convex portion coincides with the extension line of the outer edge of the third sub-pixel electrode convex portion; or, the extension line of the outer edge of the second sub-pixel electrode convex portion at least partially overlaps with the third sub-pixel electrode convex portion; or, the extension line of the outer edge of the third sub-pixel electrode convex portion at least partially overlaps with the second sub-pixel electrode convex portion. The array substrate according to claim 7 or 8, wherein: A connecting line between the center of the third sub-pixel electrode protrusion and the center of the first sub-pixel electrode protrusion is parallel to the second direction. The array substrate according to any one of claims 4 to 10, wherein: The second electrode of the first transistor includes: a first transistor first portion extending along the first direction; an orthographic projection of the first transistor first portion on the substrate and an orthographic projection of the first sub-pixel electrode convex portion on the substrate have an overlapping area. The array substrate according to any one of claims 8 to 11, wherein: The second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected to one end of the second transistor first portion; the orthographic projection of the second transistor first portion on the substrate has an overlapping area with the orthographic projection of the third sub-pixel electrode convex portion on the substrate; the orthographic projection of the second transistor second portion on the substrate has an overlapping area with the orthographic projection of the second sub-pixel electrode convex portion on the substrate. The array substrate according to claim 12, wherein: At least a portion of the second portion of the second transistor on the orthographic projection of the substrate overlaps with at least a portion of the second sub-pixel electrode extension portion on the orthographic projection of the substrate. The array substrate according to claim 12, wherein: The first signal line has a recessed portion; and the second portion of the second transistor is located at least partially in a region surrounded by the recessed portion in the orthographic projection of the substrate. The array substrate according to claim 14, wherein: The first signal line includes: a first signal portion, a second signal portion, and a third signal portion sequentially distributed along the second direction, a fourth signal portion extending along the first direction and connecting the second signal portion with the first signal portion, and a fifth signal portion extending along the first direction and connecting the second signal portion with the third signal portion; an extension line of the first signal portion coincides with an extension line of the third signal portion; an extension line of the second signal portion does not coincide with an extension line of the first signal portion; the second signal portion, the fourth signal portion and the fifth signal portion constitute the recessed portion, and the fourth signal portion and / or the fifth signal portion at least partially overlap with the pixel electrode. The array substrate according to claim 2, wherein: The array substrate also includes: a first common wiring located on one side of the gate line and extending along the first direction; the multiple transistors include: a first transistor electrically connected to the data line, a second transistor, and a third transistor; the control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode; the control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode; the control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common wiring. The array substrate according to claim 16, wherein: The pixel electrode also includes: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first overlapping portion connected to the connecting portion; the connecting portion includes: a third connecting portion extending along the first direction, a fourth connecting portion, and a fifth connecting portion extending along the second direction; one end of the third connecting portion is connected to the first sub-pixel electrode, one end of the fourth connecting portion is connected to the fourth sub-pixel electrode, one end of the fifth connecting portion is connected to the other end of the third connecting portion, and the other end of the fifth connecting portion is connected to the other end of the fourth connecting portion; the first overlapping portion is electrically connected to the third connecting portion and away from a side of the first sub-pixel electrode to which it is connected; the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode through the first overlapping portion. The array substrate according to claim 17, wherein: The pixel electrode also includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlap portion; one end of the first transition portion is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end of the first transition portion is electrically connected to one end of the second transition portion; the other end of the second transition portion is electrically connected to the second overlap portion; and the second pole of the second transistor is electrically connected to the second sub-pixel electrode through the second overlap portion. The array substrate according to claim 18, wherein: The second transition portion is parallel to an extending direction of the fifth connecting portion. The array substrate according to claim 18 or 19, wherein: The pixel electrode also includes: a third transition portion extending along the first direction, and a third overlap portion; one end of the third transition portion is electrically connected to one end of the third sub-pixel electrode facing the first sub-pixel electrode, and the other end of the third transition portion is electrically connected to the third overlap portion; the second pole of the second transistor is electrically connected to the third sub-pixel electrode through the third overlap portion. The array substrate according to claim 20, wherein: There is a first gap between the third connecting portion and the first pixel electrode; there is a second gap between the fourth connecting portion and the second pixel electrode; there is a third gap between the first transition portion and the first pixel electrode, and there is a fourth gap between the third transition portion and the second pixel electrode. The array substrate according to claim 20 or 21, wherein: The array substrate further includes: a fourth overlapping portion; and the second electrode of the third transistor is electrically connected to the first common wiring through the fourth overlapping portion. The array substrate according to claim 22, wherein: The fourth overlap portion has a fourth overlap portion outer edge along the first direction, and the second overlap portion has a second overlap portion outer edge extending along the first direction; the first overlap portion has a first overlap portion outer edge extending along the second direction, and the third overlap portion has a third overlap portion outer edge extending along the second direction; the extension line of the outer edge of the fourth overlap portion coincides with the extension line of the outer edge of the second overlap portion; the extension line of the outer edge of the first overlap portion coincides with the extension line of the outer edge of the third overlap portion. The array substrate according to any one of claims 20 to 23, wherein: The second electrode of the first transistor includes: a first transistor first portion extending along the first direction; an orthographic projection of the first transistor first portion on the substrate and an orthographic projection of the first overlapping portion on the substrate have an overlapping area. The array substrate according to any one of claims 20 to 24, wherein: The second electrode of the second transistor includes: a second transistor first part extending along the first direction, and a second transistor second part extending along the second direction and electrically connected to one end of the second transistor first part; the orthographic projection of the second transistor first part on the substrate has an overlapping area with the orthographic projection of the third overlapping part on the substrate; the orthographic projection of the second transistor second part on the substrate has an overlapping area with the orthographic projection of the second overlapping part on the substrate. The array substrate according to any one of claims 2 to 15, wherein: The array substrate further includes: a first common wiring located at one side of the gate line and extending along the first direction; the first common wiring is disconnected at a position where it intersects with the data line. The array substrate according to any one of claims 16 to 26, wherein: The array substrate also includes: a second common routing group electrically connected to the first common routing and extending to a side away from the gate line, the second common routing group including: two second common routings; the orthographic projection of the data line on the substrate and the gap between the two second common routings of the same second common routing group have an overlapping area on the orthographic projection of the substrate. The array substrate according to claim 27, wherein: The array substrate also includes: a third common routing line located on the other side of the gate line and extending along the first direction, and a fourth common routing line group connected to the third common routing line and extending away from the gate line; the third common routing line is disconnected at the position where it intersects with the data line; the fourth common routing line group includes: two fourth common routing lines; the orthographic projection of the data line on the substrate and the gap between the two fourth common routing lines of the same fourth common routing line group have an overlapping area in the orthographic projection of the substrate. The array substrate according to claim 27 or 28, wherein: The array substrate further includes: a fifth common line extending along the first direction and electrically connected to the second common line, wherein the orthographic projection of the fifth common line on the substrate passes through a central area of ​​the orthographic projection of the second pixel electrode on the substrate. The array substrate according to any one of claims 27 to 29, wherein: The array substrate further includes: a sixth common line extending along the first direction and electrically connected to the fourth common line, wherein the orthographic projection of the sixth common line on the substrate passes through a central area of ​​the orthographic projection of the first pixel electrode on the substrate. The array substrate according to any one of claims 1 to 30, wherein: The first sub-pixel electrode and the second sub-pixel electrode each include: a first sub-electrode portion distributed along the second direction, and a second sub-electrode portion; the third sub-pixel electrode and the fourth sub-pixel electrode each include: a third sub-electrode portion distributed along the second direction, and a fourth sub-electrode portion; the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion each have a plurality of slits; and an extension direction of the slits of the first sub-electrode portion is the same as an extension direction of the slits of the fourth sub-electrode portion; and an extension direction of the slits of the second sub-electrode portion is the same as an extension direction of the slits of the third sub-electrode portion. The array substrate according to claim 31, wherein: The length of the slit in a direction perpendicular to the extending direction may be 2 μm to 4 μm. The array substrate according to claim 31 or 32, wherein: The orthographic projection shapes of the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode, and the fourth sub-pixel electrode on the substrate are all rectangular. The array substrate according to claim 31 or 32, wherein: The orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal; in the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their top sides; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their bottom sides. The array substrate according to claim 31 or 32, wherein: The orthographic projection shapes of the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion on the substrate are all trapezoidal; in the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their bottom sides; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-electrode portion and the trapezoidal second sub-electrode portion are arranged opposite to each other with their top sides. The array substrate according to claim 31 or 32, wherein: The first sub-pixel electrode comprises: a first main portion extending and connected along the second direction, a second main portion, and a first side portion extending along the first direction, a plurality of first branches extending from the first main portion and the first side portion along a fourth direction, and a plurality of second branches extending from the second main portion and the first side portion along a fifth direction; the second sub-pixel electrode comprises: a third main portion extending and connected along the second direction, a fourth main portion, a fifth main portion connected to one end of the third main portion and extending along the first direction, a sixth main portion connected to one end of the fourth main portion and extending along the first direction, a plurality of third branches extending from the third main portion and the fifth main portion along the fourth direction, and a plurality of fourth branches extending from the fourth main portion and the sixth main portion along the fifth direction; the plurality of first branches are interdigitated with the plurality of third branches, and the plurality of second branches are interdigitated with the plurality of fourth branches; The third sub-pixel electrode includes: a seventh main portion extending and connected along the second direction, an eighth main portion, a ninth main portion connected to one end of the seventh main portion and extending along the first direction, a tenth main portion connected to one end of the eighth main portion and extending along the first direction, a plurality of fifth branches extending from the seventh main portion and the ninth main portion along the fourth direction, and a plurality of sixth branches extending from the eighth main portion and the tenth main portion along the fifth direction; the fourth sub-pixel electrode includes: an eleventh main portion extending and connected along the second direction, a twelfth main portion, and a second side portion extending along the first direction, a plurality of seventh branches extending from the eleventh main portion and the second side portion along the fourth direction, and a plurality of eighth branches extending from the twelfth main portion and the second side portion along the fifth direction; the plurality of fifth branches are interdigitated with the plurality of seventh branches, and the plurality of sixth branches are interdigitated with the plurality of eighth branches. The array substrate according to any one of claims 1 to 36, wherein: The array substrate also includes: a first conductive layer located on the side of the pixel electrode facing the substrate; the first conductive layer has a first hollow, a second hollow, a third hollow, and a fourth hollow; the first hollow overlaps with at least a portion of the orthographic projection of the first sub-pixel electrode on the substrate at least in part of the orthographic projection of the substrate; the second hollow overlaps with at least a portion of the orthographic projection of the substrate at least in part of the orthographic projection of the substrate; the third hollow overlaps with at least a portion of the orthographic projection of the substrate at least in part of the orthographic projection of the third sub-pixel electrode on the substrate; the fourth hollow overlaps with at least a portion of the orthographic projection of the substrate at least in part of the orthographic projection of the substrate at least in part of the orthographic projection of the fourth sub-pixel electrode on the substrate. A display panel, wherein include: The array substrate as described in any one of claims 1-37 further includes an opposing substrate arranged opposite to the array substrate, and the opposing substrate is provided with a common electrode layer. A display device, wherein Comprising the display panel as claimed in claim 38.

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