Array substrate, display panel and display device

Abstract

An array substrate, a display panel, and a display device are disclosed. The array substrate includes: a substrate (1); a plurality of gate lines (2) located on one side of the substrate (1) and extending along a first direction (X); a plurality of data lines (3) extending along a second direction (Y); and a plurality of pixel electrodes (4), each pixel electrode including: a first pixel electrode (41) located on one side of the gate line (2) and a second pixel electrode (42) located on the other side of the gate line (2); the first pixel electrode (41) includes: a first sub-pixel electrode (411) and a second sub-pixel electrode (412) distributed along the first direction (X); the second pixel electrode (42) includes: a third sub-pixel electrode (421) and a fourth sub-pixel electrode (422) distributed along the first direction (X); one of the first sub-pixel electrode (411) and the second sub-pixel electrode (412) is electrically connected to one of the third sub-pixel electrode (421) and the fourth sub-pixel electrode (422).

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light with the VA method of the LCD panel. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in utilizing a special polymer material as an alignment film to precisely control the tilt of liquid crystal molecules along the ultraviolet light direction. Its precision is measured in picometers (one trillionth of a meter). The advantage of UV2A is that the liquid crystal panel has a simple structure without protrusions or slits. This "dream of liquid crystal engineers" was explored as early as 30 years ago. Today, with the availability of new materials, production equipment, and a perfected processing procedure, this dream has been realized. The simple structure of the liquid crystal panel not only improves production efficiency but also offers many advantages in image quality. Summary of the Invention

[0004] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] Substrate;

[0006] Multiple gate lines are located on one side of the substrate and extend along a first direction;

[0007] Multiple data cables extend along the second direction;

[0008] A plurality of pixel electrodes, the pixel electrodes including: a first pixel electrode located on one side of the gate line, and a second pixel electrode located on the other side of the gate line; the first pixel electrode includes: a first sub-pixel electrode and a second sub-pixel electrode distributed along the first direction; the second pixel electrode includes: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the first direction;

[0009] One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode.

[0010] In one possible implementation, the array substrate further includes: a plurality of transistors; the plurality of transistors electrically connected to the same pixel electrode are all electrically connected to the same data line and the same gate line;

[0011] The second sub-pixel electrode is located on the side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on the side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode and the fourth sub-pixel electrode are electrically connected.

[0012] In one possible implementation, the array substrate further includes: a first signal line extending along the second direction; the plurality of transistors includes: a first transistor, a second transistor, and a third transistor;

[0013] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode.

[0014] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode.

[0015] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with the first signal line.

[0016] In one possible implementation, the pixel electrode further includes: a first sub-pixel electrode protrusion connected to the side of the first sub-pixel electrode facing the third sub-pixel electrode; the second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion.

[0017] In one possible implementation, the pixel electrode further includes: a connection portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connection portion includes: a first connection portion extending along the second direction, and a second connection portion extending along a third direction; the third direction intersects the first direction and the second direction.

[0018] One end of the first connecting portion is electrically connected to the end of the first sub-pixel electrode facing the third sub-pixel electrode, and the other end is electrically connected to the second connecting portion. The other end of the second connecting portion is electrically connected to the end of the fourth sub-pixel electrode facing the second sub-pixel electrode.

[0019] In one possible implementation, the pixel electrode further includes: a third sub-pixel electrode protrusion connected to the side of the third sub-pixel electrode facing the first sub-pixel electrode;

[0020] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the protrusion of the third sub-pixel electrode.

[0021] In one possible implementation, the pixel electrode further includes: a second sub-pixel electrode extension extending along the second direction, and a second sub-pixel electrode protrusion; one end of the second sub-pixel electrode extension is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end is electrically connected to the second sub-pixel electrode protrusion.

[0022] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second sub-pixel electrode protrusion.

[0023] In one possible implementation, the extension direction of the second sub-pixel electrode extension is parallel to the extension direction of the first connection portion.

[0024] In one possible implementation, the second sub-pixel electrode protrusion has an outer edge of the second sub-pixel electrode protrusion that extends away from the second sub-pixel electrode and along the first direction; the third sub-pixel electrode protrusion has an outer edge of the third sub-pixel electrode protrusion that extends away from the third sub-pixel electrode and along the first direction.

[0025] The extension line of the outer edge of the second sub-pixel electrode protrusion coincides with the extension line of the outer edge of the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the second sub-pixel electrode protrusion at least partially overlaps with the third sub-pixel electrode protrusion; or, the extension line of the outer edge of the third sub-pixel electrode protrusion at least partially overlaps with the second sub-pixel electrode protrusion.

[0026] In one possible implementation, the line connecting the center of the third sub-pixel electrode protrusion and the center of the first sub-pixel electrode protrusion is parallel to the second direction.

[0027] In one possible implementation, the second electrode of the first transistor includes: a first portion of the first transistor extending along the first direction;

[0028] The orthographic projection of the first part of the first transistor onto the substrate overlaps with the orthographic projection of the first sub-pixel electrode protrusion onto the substrate.

[0029] In one possible implementation, the second electrode of the second transistor includes: a first portion of the second transistor extending along the first direction, and a second portion of the second transistor extending along the second direction and electrically connected to one end of the first portion of the second transistor;

[0030] The orthographic projection of the first part of the second transistor onto the substrate overlaps with the orthographic projection of the third sub-pixel electrode protrusion onto the substrate; the orthographic projection of the second part of the second transistor onto the substrate overlaps with the orthographic projection of the second sub-pixel electrode protrusion onto the substrate.

[0031] In one possible implementation, at least a portion of the second portion of the second transistor projected onto the substrate overlaps with at least a portion of the second sub-pixel electrode extension projected onto the substrate.

[0032] In one possible implementation, the first signal line has a recess; at least a portion of the second portion of the second transistor's orthogonal projection onto the substrate is located in the region surrounded by the orthogonal projection of the recess onto the substrate.

[0033] In one possible implementation, the first signal line includes: a first signal portion, a second signal portion, and a third signal portion distributed sequentially along the second direction; a fourth signal portion extending along the first direction and connecting the second signal portion and the first signal portion; and a fifth signal portion extending along the first direction and connecting the second signal portion and the third signal portion.

[0034] The extension line of the first signal portion coincides with the extension line of the third signal portion; the extension line of the second signal portion does not coincide with the extension line of the first signal portion; the second signal portion, the fourth signal portion, and the fifth signal portion constitute the recessed portion, and the fourth signal portion and / or the fifth signal portion at least partially overlap with the pixel electrode.

[0035] In one possible implementation, the array substrate further includes: a first common trace located on one side of the gate line and extending along the first direction; the plurality of transistors includes: a first transistor, a second transistor, and a third transistor electrically connected to the data line;

[0036] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode.

[0037] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode.

[0038] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common trace.

[0039] In one possible implementation, the pixel electrode further includes: a connection portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first overlapping portion connected to the connection portion; the connection portion includes: a third connection portion extending along the first direction, a fourth connection portion, and a fifth connection portion extending along the second direction.

[0040] One end of the third connecting portion is connected to the first sub-pixel electrode, one end of the fourth connecting portion is connected to the fourth sub-pixel electrode, one end of the fifth connecting portion is connected to the other end of the third connecting portion, and the other end of the fifth connecting portion is connected to the other end of the fourth connecting portion; the first overlapping portion is electrically connected to the third connecting portion and is located away from the connected first sub-pixel electrode.

[0041] The second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode through the first overlapping portion.

[0042] In one possible implementation, the pixel electrode further includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlap portion;

[0043] One end of the first adapter is electrically connected to one end of the second sub-pixel electrode facing the fourth sub-pixel electrode, and the other end of the first adapter is electrically connected to one end of the second adapter; the other end of the second adapter is electrically connected to the second overlapping portion.

[0044] The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second overlap portion.

[0045] In one possible implementation, the second adapter portion is parallel to the extending direction of the fifth connector portion.

[0046] In one possible implementation, the pixel electrode further includes: a third transition portion extending along the first direction, and a third overlap portion;

[0047] One end of the third adapter is electrically connected to the end of the third sub-pixel electrode facing the first sub-pixel electrode, and the other end of the third adapter is electrically connected to the third overlap portion.

[0048] The second electrode of the second transistor is electrically connected to the third sub-pixel electrode through the third overlap portion.

[0049] In one possible implementation, the third connecting portion has a first gap with the first pixel electrode; the fourth connecting portion has a second gap with the second pixel electrode.

[0050] There is a third gap between the first adapter and the first pixel electrode, and there is a fourth gap between the third adapter and the second pixel electrode.

[0051] In one possible implementation, the array substrate further includes: a fourth overlap portion; the second electrode of the third transistor is electrically connected to the first common trace through the fourth overlap portion.

[0052] In one possible implementation, the fourth overlap has a fourth overlap outer edge along the first direction, the second overlap has a second overlap outer edge extending along the first direction; the first overlap has a first overlap outer edge extending along the second direction, and the third overlap has a third overlap outer edge extending along the second direction.

[0053] The extension line of the outer edge of the fourth overlapping portion coincides with the extension line of the outer edge of the second overlapping portion; the extension line of the outer edge of the first overlapping portion coincides with the extension line of the outer edge of the third overlapping portion.

[0054] In one possible implementation, the second electrode of the first transistor includes: a first portion of the first transistor extending along the first direction;

[0055] The first portion of the first transistor has an overlapping region with the first overlapping portion in the substrate.

[0056] In one possible implementation, the second electrode of the second transistor includes: a first portion of the second transistor extending along the first direction, and a second portion of the second transistor extending along the second direction and electrically connected to one end of the first portion of the second transistor;

[0057] The orthographic projection of the first part of the second transistor on the substrate overlaps with the orthographic projection of the third overlapping part on the substrate; the orthographic projection of the second part of the second transistor on the substrate overlaps with the orthographic projection of the second overlapping part on the substrate.

[0058] In one possible implementation, the array substrate further includes: a first common trace located on one side of the gate line and extending along the first side; the first common trace is disconnected at a position where it intersects with the data line.

[0059] In one possible implementation, the array substrate further includes: a second common trace group electrically connected to the first common trace and extending away from the gate trace, the second common trace group including: two second common traces;

[0060] The data line, when projected onto the substrate, overlaps with the gap between two second common traces in the same second common trace group when projected onto the substrate.

[0061] In one possible implementation, the array substrate further includes: a third common trace located on the other side of the gate line and extending along the first direction, and a fourth common trace group connected to the third common trace and extending away from the gate line.

[0062] The third common trace is disconnected at the location where it intersects with the data line; the fourth common trace group includes: two fourth common traces; the data line, in its orthographic projection on the substrate, has an overlapping area with the gap between the two fourth common traces in the same fourth common trace group in its orthographic projection on the substrate.

[0063] In one possible implementation, the array substrate further includes a fifth common trace extending along the first direction and electrically connected to the second common trace, wherein the orthographic projection of the fifth common trace on the substrate passes through the central region of the orthographic projection of the second pixel electrode on the substrate.

[0064] In one possible implementation, the array substrate further includes a sixth common trace extending along the first direction and electrically connected to the fourth common trace, wherein the orthographic projection of the sixth common trace on the substrate passes through the central region of the orthographic projection of the first pixel electrode on the substrate.

[0065] In one possible implementation, the first sub-pixel electrode and the second sub-pixel electrode each include: a first sub-electrode portion and a second sub-electrode portion distributed along the second direction; the third sub-pixel electrode and the fourth sub-pixel electrode each include: a third sub-electrode portion and a fourth sub-electrode portion distributed along the second direction.

[0066] The first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion each have a plurality of slits; and the extension direction of the slits in the first sub-electrode portion is the same as the extension direction of the slits in the fourth sub-electrode portion; the extension direction of the slits in the second sub-electrode portion is the same as the extension direction of the slits in the third sub-electrode portion.

[0067] In one possible implementation, the length of the slit perpendicular to the extension direction can be 2 μm to 4 μm.

[0068] In one possible implementation, the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode, and the fourth sub-pixel electrode all have rectangular orthographic projections onto the substrate.

[0069] In one possible implementation, the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion all have trapezoidal shapes in their orthogonal projection onto the substrate;

[0070] In the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their top edges facing each other; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their bottom edges facing each other.

[0071] In one possible implementation, the first sub-electrode portion, the second sub-electrode portion, the third sub-electrode portion, and the fourth sub-electrode portion all have trapezoidal shapes in their orthogonal projection onto the substrate;

[0072] In the first sub-pixel electrode and the fourth sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their bottom edges facing each other; in the second sub-pixel electrode and the third sub-pixel electrode, the trapezoidal first sub-pixel portion and the trapezoidal second sub-pixel portion are arranged with their top edges facing each other.

[0073] In one possible implementation, the first sub-pixel electrode includes: a first main portion, a second main portion, and a first side portion extending along the second direction and connected thereto; a plurality of first branches extending from the first main portion and the first side portion along a fourth direction; and a plurality of second branches extending from the second main portion and the first side portion along a fifth direction. The second sub-pixel electrode includes: a third main portion, a fourth main portion, and a fifth main portion connected to one end of the third main portion and extending along the first direction; a sixth main portion connected to one end of the fourth main portion and extending along the first direction; a plurality of third branches extending from the third main portion and the fifth main portion along the fourth direction; and a plurality of fourth branches extending from the fourth main portion and the sixth main portion along the fifth direction. The plurality of first branches and the plurality of third branches are interdigitated, and the plurality of second branches and the plurality of fourth branches are interdigitated.

[0074] The third sub-pixel electrode includes: a seventh main portion and an eighth main portion extending and connected along the second direction; a ninth main portion connected to one end of the seventh main portion and extending along the first direction; a tenth main portion connected to one end of the eighth main portion and extending along the first direction; a plurality of fifth branches extending from the seventh main portion and the ninth main portion along the fourth direction; and a plurality of sixth branches extending from the eighth main portion and the tenth main portion along the fifth direction. The fourth sub-pixel electrode includes: an eleventh main portion and a twelfth main portion extending and connected along the second direction; a second side portion extending along the first direction; a plurality of seventh branches extending from the eleventh main portion and the second side portion along the fourth direction; and a plurality of eighth branches extending from the twelfth main portion and the second side portion along the fifth direction. The plurality of fifth branches and the plurality of seventh branches are interdigitated, and the plurality of sixth branches and the plurality of eighth branches are interdigitated.

[0075] In one possible implementation, the array substrate further includes: a first conductive layer located on the side of the pixel electrode facing the substrate; the first conductive layer has a first cutout, a second cutout, a third cutout, and a fourth cutout;

[0076] At least a portion of the orthographic projection of the first cutout onto the substrate overlaps with at least a portion of the orthographic projection of the first sub-pixel electrode onto the substrate; at least a portion of the orthographic projection of the second cutout onto the substrate overlaps with at least a portion of the orthographic projection of the second sub-pixel electrode onto the substrate; at least a portion of the orthographic projection of the third cutout onto the substrate overlaps with at least a portion of the orthographic projection of the third sub-pixel electrode onto the substrate; and at least a portion of the orthographic projection of the fourth cutout onto the substrate overlaps with at least a portion of the orthographic projection of the fourth sub-pixel electrode onto the substrate.

[0077] This disclosure also provides a display panel, which includes: an array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate, the counter substrate being provided with a common electrode layer.

[0078] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description

[0079] Figure 1A This is one of the top views of the array substrate provided in the embodiments of this disclosure;

[0080] Figure 1B for Figure 1A Enlarged schematic diagram of dashed line frame S1;

[0081] Figure 1C for Figure 1ASchematic diagram of a single film layer of the middle gate line layer;

[0082] Figure 1D for Figure 1A A schematic diagram of a single-film layer with an active layer;

[0083] Figure 1E for Figure 1A A schematic diagram of a single film layer in a data cable;

[0084] Figure 1F for Figure 1A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0085] Figure 1G for Figure 1A A schematic diagram of a single film layer of the middle pixel electrode;

[0086] Figure 1H for Figure 1A Corresponding light effect simulation diagram;

[0087] Figure 2A This is a second top view of the array substrate provided in the embodiments of this disclosure;

[0088] Figure 2B for Figure 2A Enlarged schematic diagram of dashed line frame S1;

[0089] Figure 2C for Figure 2A Schematic diagram of a single film layer of the middle gate line layer;

[0090] Figure 2D for Figure 2A A schematic diagram of a single-film layer with an active layer;

[0091] Figure 2E for Figure 2A A schematic diagram of a single film layer in a data cable;

[0092] Figure 2F for Figure 2A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0093] Figure 2G for Figure 2A A schematic diagram of a single film layer of the middle pixel electrode;

[0094] Figure 2H for Figure 2A Corresponding light effect simulation diagram;

[0095] Figure 2I for Figure 2B A schematic diagram of the cross-section at the dashed line EF;

[0096] Figure 3A This is the third top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0097] Figure 3B for Figure 3A Enlarged schematic diagram of dashed line frame S1;

[0098] Figure 3C for Figure 3A Schematic diagram of a single film layer of the middle gate line layer;

[0099] Figure 3D for Figure 3A A schematic diagram of a single-film layer with an active layer;

[0100] Figure 3E for Figure 3A A schematic diagram of a single film layer in a data cable;

[0101] Figure 3F for Figure 3A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0102] Figure 3G for Figure 3A A schematic diagram of a single film layer of the middle pixel electrode;

[0103] Figure 3H for Figure 3A Corresponding light effect simulation diagram;

[0104] Figure 4A This is the fourth top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0105] Figure 4B for Figure 4A Enlarged schematic diagram of dashed line frame S1;

[0106] Figure 4C for Figure 4A Schematic diagram of a single film layer of the middle gate line layer;

[0107] Figure 4D for Figure 4A A schematic diagram of a single-film layer with an active layer;

[0108] Figure 4E for Figure 4A A schematic diagram of a single film layer in a data cable;

[0109] Figure 4F for Figure 4A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0110] Figure 4G for Figure 4A A schematic diagram of a single film layer of the middle pixel electrode;

[0111] Figure 4H for Figure 4A Corresponding light effect simulation diagram;

[0112] Figure 5AFifth top view of the array substrate provided in the embodiments of this disclosure;

[0113] Figure 5B for Figure 5A Enlarged schematic diagram of dashed line frame S1;

[0114] Figure 5C for Figure 5A Schematic diagram of a single film layer of the middle gate line layer;

[0115] Figure 5D for Figure 5A A schematic diagram of a single-film layer with an active layer;

[0116] Figure 5E for Figure 5A A schematic diagram of a single film layer in a data cable;

[0117] Figure 5F for Figure 5A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0118] Figure 5G for Figure 5A A schematic diagram of a single film layer of the middle pixel electrode;

[0119] Figure 5H for Figure 5A Corresponding light effect simulation diagram;

[0120] Figure 6A This is the sixth top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0121] Figure 6B for Figure 6A Enlarged schematic diagram of dashed line frame S1;

[0122] Figure 6C for Figure 6A Schematic diagram of a single film layer of the middle gate line layer;

[0123] Figure 6D for Figure 6A A schematic diagram of a single-film layer with an active layer;

[0124] Figure 6E for Figure 6A A schematic diagram of a single film layer in a data cable;

[0125] Figure 6F for Figure 6A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0126] Figure 6G for Figure 6A A schematic diagram of a single film layer of the first conductive layer in the middle;

[0127] Figure 6H for Figure 6AA schematic diagram of a single-film layer of the second insulating layer;

[0128] Figure 6I for Figure 6A A schematic diagram of a single film layer of the middle pixel electrode;

[0129] Figure 6J for Figure 6A The corresponding black matrix diagram;

[0130] Figure 6K for Figure 6A Corresponding light effect simulation diagram;

[0131] Figure 7 This is a schematic diagram of the dark lines in a conventional 8-domain structure.

[0132] Figure 8 A dark line diagram of an array substrate provided in an embodiment of this disclosure;

[0133] Figure 9 This is a schematic diagram of the sub-pixel equivalent circuit provided in an embodiment of the present disclosure;

[0134] Figure 10 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this disclosure. Detailed Implementation

[0135] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. Implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0136] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0137] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviation from the specific value, as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%. In this specification, “substantially the same” may mean a difference of less than 10%.

[0138] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0139] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0140] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0141] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0142] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0143] Furthermore, the gate of a transistor can be referred to as the control electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0144] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0145] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0146] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0147] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0148] High-resolution products, such as 8K and 16K displays, are the main direction for future products. However, current 8K products using vertically aligned liquid crystal (VA) have problems with low transmittance and poor color shift.

[0149] In view of this, see Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G , Figures 6A-6G As shown, this disclosure provides an array substrate, which includes:

[0150] Substrate 1;

[0151] Multiple gate lines 2 are located on one side of the substrate 1 and extend along the first direction X;

[0152] Multiple data lines 3 extend along the second direction Y; specifically, the second direction Y can intersect with the first direction X; specifically, the second direction Y can be perpendicular to the first direction X; specifically, the second direction Y can be the direction of a pixel electrode column, and the first direction X can be the direction of a pixel electrode row.

[0153] Multiple pixel electrodes 4, each pixel electrode 4 including: a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2; the first pixel electrode 41 includes: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along a first direction X; the second pixel electrode 42 includes: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X; specifically, for example, combined with Figure 1G As shown, the pixel electrode 4 includes a first pixel electrode 41 located above the gate line 2 and a second pixel electrode 42 located below the gate line 2. The first pixel electrode 41 includes a first sub-pixel electrode 411 located on the left and a second sub-pixel electrode 412 located on the right. The second pixel electrode 42 includes a third sub-pixel electrode 421 located on the left and a fourth sub-pixel electrode 422 located on the right.

[0154] One of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. The brightness of the two electrodes electrically connected together is different from the brightness of the other two. Specifically, for example, the first sub-pixel electrode 411 can be electrically connected to the third sub-pixel electrode 421, and the second sub-pixel electrode 412 can be electrically connected to the fourth sub-pixel electrode 422; or, the first sub-pixel electrode 411 can be electrically connected to the fourth sub-pixel electrode 422, and the second sub-pixel electrode 412 can be electrically connected to the third sub-pixel electrode 422.

[0155] In this embodiment, the pixel electrode 4 includes a first pixel electrode 41 located on one side of the gate line 2 and a second pixel electrode 42 located on the other side of the gate line 2. The first pixel electrode 41 includes a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along the first direction X. The second pixel electrode 42 includes a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X. One of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. That is, a pixel electrode 4 is divided into upper and lower parts, the upper part is further divided into left and right parts, and the lower part is also divided into left and right parts. The brightness of the two electrically connected parts is different from the brightness of the other two parts. It can form an 8-domain distribution in a sub-pixel. Compared with the conventional 8-domain structure, the array substrate provided in this embodiment has fewer dark lines, better transmittance, and can perform mutual compensation of viewing angles, thereby improving the effect of left and right viewing angle deviation.

[0156] Specifically, such as Figure 7 and Figure 8 As shown, Figure 7 The dark lines in the conventional 8-domain structure are numerous and have a significant impact on transmittance. Figure 8 The dark lines on the array substrate provided in the embodiments of this disclosure are clearly reduced in number. In comparison, the 8-domain array substrate structure provided in the disclosed embodiments has a significant advantage in improving transmittance. Moreover... Figure 7 The 8-domain structure shown does not have a good liquid crystal angle to compensate for the left and right viewing angles; all the horizontal liquid crystals face to the right, and there are no horizontal liquid crystals facing to the left. Figure 8 The array substrate provided in the present disclosure embodiment can enable mutual compensation of viewing angles between the horizontal liquid crystals in the left and right directions, thereby improving the effect of left and right viewing angle deviation.

[0157] Combination Figure 1A , Figure 1G and Figure 8As shown, in a pixel electrode 4, the first pixel electrode 41 is a U-shaped slit, and the second pixel electrode 42 is an inverted U-shaped slit. In conjunction with the extension direction of the slit F, the first pixel electrode 41 can be set with two liquid crystal alignment directions, which can be 225° and 135° respectively; the second pixel electrode 42 can be set with two liquid crystal alignment directions, which are 315° and 45° respectively. Combined with the left and right divided light and dark areas, an 8-domain alignment method can be formed in a sub-pixel when using SUVA technology.

[0158] It should be noted that, in this embodiment of the present disclosure, one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422. This connection can be achieved at the layer where pixel electrode 4 is located. For the other two sub-pixel electrodes, they may not be connected at the layer where pixel electrode 4 is located, but can be electrically connected through other structures, such as being connected to the same transistor drain. Specifically, for example, the first sub-pixel electrode 411 and the third sub-pixel electrode 421 are electrically connected at the layer where pixel electrode 4 is located, exhibiting one brightness; while the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are not electrically connected at the layer where pixel electrode 4 is located, but can both be connected to the same transistor drain (i.e., electrically connected through the drain layer), achieving another brightness. The brightness of the two electrodes connected at the layer where pixel electrode 4 is located can be different from the brightness of the other two.

[0159] It is understandable that the brightness of the two main electrical components connected together is different from the brightness of the other two components. This refers to the comparison of the brightness within a sub-pixel when the display panel is powered on and lit.

[0160] In one possible implementation, combined with Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G , Figures 6A-6G As shown, the array substrate also includes: multiple transistors T; multiple transistors electrically connected to the same pixel electrode 4, all electrically connected to the same data line 3 and the same gate line 2, for example, as Figure 1BIn this embodiment, three transistors are electrically connected to the same pixel electrode 4: a first transistor T1, a second transistor T2, and a third transistor T3. These three transistors are all electrically connected to the same data line 3 and the same gate line 2. The second sub-pixel electrode 412 is located on the side of the first sub-pixel electrode 411 away from the electrically connected data line 3, and the fourth sub-pixel electrode 422 is located on the side of the third sub-pixel electrode 421 away from the electrically connected data line 3. The first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected. Specifically, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected in the layer where the pixel electrode 4 is located, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are both electrically connected to the second electrode TC of the second transistor T2. In this embodiment, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected in the pixel electrode 4, and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are electrically connected. That is, the four parts of the pixel electrode 4 are electrically connected in pairs, which is beneficial for forming an 8-domain distribution within the same pixel electrode 4.

[0161] It should be noted that multiple transistors electrically connected to the same pixel electrode 4 can refer to those electrically connected to the same pixel electrode 4 directly or indirectly. For example, the first transistor T1 and the second transistor T2 can be directly electrically connected to the pixel electrode 4, while the third transistor T3, since it is electrically connected to the second transistor T2, can also be considered electrically connected to the pixel electrode 4. Specifically, multiple transistors electrically connected to the same pixel electrode 4 can also refer to individual transistors driving the same pixel electrode 4.

[0162] In one possible implementation, combined with Figures 1A-1G As shown, the array substrate also includes: a first signal line 5 extending along the second direction Y; and a plurality of transistors T including: a first transistor T1, a second transistor T2, and a third transistor T3;

[0163] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422. Specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via K1.

[0164] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through the second via K2; the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through the third via K3.

[0165] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2. The first electrode TB of the third transistor T3 is multiplexed with the second electrode TC of the second transistor T2. The second electrode TC of the third transistor T3 is multiplexed with the first signal line 5.

[0166] Figure 9 It can be Figure 1B The corresponding equivalent circuit diagram shows that S is the data line to the left of the pixel, that is, the signal line for transmitting data signals to the current sub-pixel, i.e., the data line electrically connected to the current sub-pixel. S is the data line to the right of the pixel, and also the data line of the horizontally adjacent pixels. The pixel circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor Cpd_bright, a second capacitor Cgp_bright, a third capacitor Cst_bright, a fourth capacitor Clc_bright, a fifth capacitor Cpp_bright-dark, a sixth capacitor Cpd_bright, a seventh capacitor Cpd_dark, an eighth capacitor Cgp_dark, a ninth capacitor Cst_dark, a tenth capacitor Clc_dark, an eleventh capacitor Cpd_dark, a twelfth capacitor CgD, and a thirteenth capacitor CcD; wherein, a first capacitor Cpd_bright is formed between the first pixel electrode 41 and the data line 3, a second capacitor Cgp_bright is formed between the first pixel electrode 41 and the gate line 2, and the overlapping area of ​​the first pixel electrode 41 and the third common trace 23 can be A third capacitor Cst_bright can be formed. A fourth capacitor Clc_bright can be formed between the first pixel electrode 41 and the common electrode on the opposite substrate side. A fifth capacitor Cpp_bright and dark can be formed between the first pixel electrode 41 and the second pixel electrode 42. A sixth capacitor Cpd_bright can be formed between the first pixel electrode 41 and the adjacent data line 3. A seventh capacitor Cpd_dark can be formed between the second pixel electrode 42 and the data line 3. An eighth capacitor Cgp_dark can be formed between the second pixel electrode 42 and the gate line 2. A ninth capacitor Cst_dark can be formed in the overlapping area of ​​the second pixel electrode 42 and the first common trace 21. A tenth capacitor Clc_dark can be formed between the second pixel electrode 42 and the common electrode on the opposite substrate side. An eleventh capacitor Cpd_dark can be formed between the second pixel electrode 42 and the adjacent data line 3. A twelfth capacitor CgD can be formed in the overlapping area of ​​the gate line 2 and the first signal line 5. A thirteenth capacitor CcD can be formed in the overlapping area of ​​the first signal line 5 and the first common trace 21.

[0167] Specifically, in combination Figure 1A and Figure 9 As shown, since the third transistor T3 is connected to the second transistor T2, the voltage applied to the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially distributed to the twelfth capacitor CgD (and / or, the thirteenth capacitor CcD, and / or, the first signal line 5) through the third transistor T3. This results in the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 being lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422. Consequently, the light emission brightness of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is less than the light emission brightness of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, thus forming a display effect with different brightness in the sub-pixels.

[0168] In one possible implementation, the voltage applied to the first signal line 5 can be the same as the voltage applied to the common electrode layer of the opposing substrate, that is, a common voltage is applied.

[0169] In one possible implementation, combined with Figures 1A-1G As shown, the pixel electrode 4 further includes: a first sub-pixel electrode protrusion 41A connected to the side of the first sub-pixel electrode 411 facing the third sub-pixel electrode 421; the second electrode TB of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 through the first sub-pixel electrode protrusion 41A. In this embodiment, the first sub-pixel electrode 411 is further provided with a first sub-pixel electrode protrusion 41A on the side facing the third sub-pixel electrode 421. The wiring method when connecting it to the second electrode TB of the first transistor T1 is simple and neat, which is beneficial to the concise wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure during etching patterning when multiple pattern layouts are complex.

[0170] In one possible implementation, combined with Figures 1A-1G As shown, the pixel electrode 4 further includes a connection portion 44 connecting the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422; the connection portion 44 includes a first connection portion 441 extending along the second direction Y, and a second connection portion 442 extending along the third direction Z; one end of the first connection portion 441 is electrically connected to one end of the first sub-pixel electrode 411 facing the third sub-pixel electrode 421, and the other end is electrically connected to the second connection portion 442; the other end of the second connection portion 422 is electrically connected to one end of the fourth sub-pixel electrode 422 facing the second sub-pixel electrode 412.

[0171] In this embodiment, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are directly electrically connected in the layer where the pixel electrode 4 is located through the connection portion 44. The connection portion 44 includes a first connection portion 441 extending along the second direction Y and a second connection portion 442 extending along the third direction Z. The wiring method of the connection portion 44 is simple and regular, which is conducive to the concise wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure when etching patterning when the multiple pattern layouts are more complex.

[0172] In one possible implementation, the third direction Z intersects the first direction X and the second direction Y; the angle formed between the third direction Z and the second direction Y can be 0 to 90°, specifically, the angle formed between the third direction Z and the second direction Y can be 30° to 60°, specifically, the angle formed between the third direction Z and the second direction Y can be 45°.

[0173] In one possible implementation, combined with Figures 1A-1G As shown, the pixel electrode 4 further includes a third sub-pixel electrode protrusion 43A connected to the side of the third sub-pixel electrode 421 facing the first sub-pixel electrode 411; the second electrode TC of the second transistor T2 is electrically connected to the third sub-pixel electrode 421 through the third sub-pixel electrode protrusion 43A. In this embodiment, the third sub-pixel electrode 421 is further provided with a third sub-pixel electrode protrusion 43A on the side facing the first sub-pixel electrode 411. The wiring method when connecting it to the second electrode TC of the second transistor T2 is simple and neat, which is beneficial to the concise wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure during etching patterning when multiple pattern layouts are complex.

[0174] In one possible implementation, combined with Figures 1A-1GAs shown, the pixel electrode 4 further includes: a second sub-pixel electrode extension 42B extending along the second direction Y, and a second sub-pixel electrode protrusion 42A; one end of the second sub-pixel electrode extension 42B is electrically connected to one end of the second sub-pixel electrode 412 facing the fourth sub-pixel electrode 422, and the other end is electrically connected to the second sub-pixel electrode protrusion 42A; the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second sub-pixel electrode protrusion 42A. In this embodiment, the side of the second sub-pixel electrode 412 facing the fourth sub-pixel electrode 422 is further provided with a second sub-pixel electrode extension 42B extending along the second direction Y, and a second sub-pixel electrode protrusion 42A. This facilitates the electrical connection of both the second sub-pixel electrode 412 and the third sub-pixel electrode 421 to the second electrode TC of the second transistor T2. Furthermore, the wiring method when connecting the second sub-pixel electrode 412 and the second electrode TC of the second transistor T2 is simple and regular, which is beneficial for the concise wiring between the first pixel electrode 41 and the second pixel electrode 42. This avoids the risk of short circuit failure during etching patterning when multiple pattern layouts are complex.

[0175] In one possible implementation, combined with Figures 1A-1G As shown, the extension direction of the second sub-pixel electrode extension 42B is parallel to the extension direction of the first connection 441, which is beneficial to the simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure when etching patterning when multiple pattern layouts are more complex.

[0176] In one possible implementation, combined with Figures 1A-1G As shown, the second sub-pixel electrode protrusion 42A has an outer edge f1 of the second sub-pixel electrode protrusion that extends away from the second sub-pixel electrode 412 and along the first direction X; the third sub-pixel electrode protrusion 43A has an outer edge f2 of the third sub-pixel electrode protrusion that extends away from the third sub-pixel electrode 421 and along the first direction X.

[0177] The extension line of the outer edge f1 of the second sub-pixel electrode protrusion coincides with the extension line of the outer edge f2 of the third sub-pixel electrode protrusion; or, the extension line of the outer edge f1 of the second sub-pixel electrode protrusion at least partially overlaps with the third sub-pixel electrode protrusion 43A; or, the extension line of the outer edge f2 of the third sub-pixel electrode protrusion at least partially overlaps with the second sub-pixel electrode protrusion 42A. This facilitates the electrical connection of both the second sub-pixel electrode 412 and the third sub-pixel electrode 421 to the second electrode TC of the second transistor T2, resulting in simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoiding the risk of short circuits during etching patterning when multiple pattern layouts are complex.

[0178] In one possible implementation, combined with Figures 1A-1GAs shown, the connecting line e1 between the center of the third sub-pixel electrode protrusion 43A and the center of the first sub-pixel electrode protrusion 41A is parallel to the second direction Y. This helps to simplify the pattern between the first pixel electrode 41 and the second pixel electrode 42, avoiding the risk of short circuits during etching when multiple pattern layouts are complex.

[0179] In one possible implementation, combined with Figures 1A-1G As shown, the array substrate includes: a first axis f7 located between the first pixel electrode 41 and the second pixel electrode 42 and extending along the first direction X; a third sub-pixel electrode protrusion 43A, which is symmetrical to the first sub-pixel electrode protrusion 41A about the first axis f7.

[0180] In one possible implementation, combined with Figures 1A-1G As shown, the orthographic projection shape of the first sub-pixel electrode protrusion 41A on the substrate 1 can be trapezoidal, and the orthographic projection shape of the third sub-pixel electrode protrusion 43A on the substrate 1 can be trapezoidal; in one possible embodiment, the orthographic projection shape of the first sub-pixel electrode protrusion 41A on the substrate 1 can also be rectangular, semi-circular or semi-elliptical; the orthographic projection shape of the third sub-pixel electrode protrusion 43A on the substrate 1 can also be rectangular, semi-circular or semi-elliptical.

[0181] In one possible implementation, combined with Figures 1A-1G As shown, the second electrode TC of the first transistor T1 includes: a first portion T1C1 of the first transistor extending along the first direction X; the orthographic projection of the first portion T1C1 of the first transistor on the substrate 1 overlaps with the orthographic projection of the first sub-pixel electrode protrusion 41A on the substrate 1. This facilitates electrical connection between the first portion T1C1 of the first transistor and the first sub-pixel electrode protrusion 41A through the first via K1.

[0182] In one possible implementation, combined with Figures 1A-1G As shown, the second electrode TC of the first transistor T1 includes: a second part T1C2 of the first transistor extending along the second direction Y and electrically connected to the first part T1C1 of the first transistor; specifically, the orthographic projection of the second part T1C2 of the first transistor on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0183] In one possible implementation, combined with Figures 1A-1GAs shown, the second electrode TC of the second transistor T2 includes: a first part T2C1 of the second transistor extending along the first direction X, and a second part T2C2 of the second transistor extending along the second direction Y and electrically connected to one end of the first part T2C1 of the second transistor; the orthographic projection of the first part T2C1 of the second transistor on the substrate 1 overlaps with the orthographic projection of the third sub-pixel electrode protrusion 43A on the substrate 1, so as to realize the electrical connection between the first part T2C1 of the second transistor and the third sub-pixel electrode protrusion 43A through the second via K2; the orthographic projection of the second part T2C2 of the second transistor on the substrate 1 overlaps with the orthographic projection of the second sub-pixel electrode protrusion 42A on the substrate 1, so as to realize the electrical connection between the second part T2C2 of the second transistor and the second sub-pixel electrode protrusion 42A through the third via K3.

[0184] In one possible implementation, combined with Figures 1A-1G As shown, the second electrode TC of the second transistor T2 may further include: a third part T2C3 of the second transistor that is electrically connected to the other end of the first part T2C1 of the second transistor and extends along the second direction Y. Specifically, the orthographic projection of the third part T2C3 of the second transistor on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0185] In one possible implementation, combined with Figures 1A-1G As shown, at least a portion of the second portion T2C2 of the second transistor projected onto the substrate 1 overlaps with at least a portion of the second sub-pixel electrode extension 42B projected onto the substrate 1. Since the second portion T2C2 of the second transistor and the gate line 2 have an overlapping area, forming a coupling capacitance, the second sub-pixel electrode extension 42B covering a portion of the second portion T2C2 can shield part of the coupling capacitance between the second portion T2C2 of the second transistor and the gate line 2. Furthermore, the overlap between at least a portion of the second portion T2C2 projected onto the substrate 1 and at least a portion of the second sub-pixel electrode extension 42B projected onto the substrate 1 facilitates wiring on the array substrate, reduces wiring width, and optimizes wiring layout.

[0186] In one possible implementation, the second portion T2C2 of the second transistor projected onto the substrate 1 may not overlap with the projected portion 42B of the second sub-pixel electrode onto the substrate 1.

[0187] In one possible implementation, combined with Figures 1A-1GAs shown, the first signal line 5 has a recessed portion 50; at least a portion of the orthographic projection of the second portion T2C2 of the second transistor onto the substrate 1 is located in the area surrounded by the orthographic projection of the recessed portion 50 onto the substrate 1. In this embodiment of the present disclosure, the first signal line 5 has a recessed portion 50, so that while the first signal line 5 and the second electrode TC of the second transistor T2 are disposed on the same layer, the second portion T2C2 of the second transistor is avoided, thus preventing a short circuit between the first signal line 5 and the second electrode TC of the second transistor T2.

[0188] In one possible implementation, combined with Figures 1A-1G As shown, the first signal line 5 includes: a first signal section 51, a second signal section 52, and a third signal section 53 sequentially distributed along the second direction Y; a fourth signal section 54 extending along the first direction X and connecting the second signal section 52 and the first signal section 51; and a fifth signal section 55 extending along the first direction X and connecting the second signal section 52 and the third signal section 53; the extension line of the first signal section 51 coincides with the extension line of the third signal section 53; the extension line of the second signal section 52 does not coincide with the extension line of the first signal section 51; the second signal section 52, the fourth signal section 54, and the fifth signal section 55 constitute a recessed portion 50; the fourth signal section 54 and / or the fifth signal section 55 at least partially overlap with the pixel electrode 4.

[0189] Specifically, the third signal section 53 can serve as the second electrode TC of the third transistor T3. In this way, a portion of the voltage between the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 can be released to the first signal line 5 via the third transistor T3.

[0190] In one possible implementation, combined with Figures 1A-1G As shown, the first signal line 5 is on the same layer as the data line 3. Thus, the first signal line 5 is formed simultaneously with the data line 3, which simplifies the fabrication process of the array substrate and reduces its manufacturing cost while achieving different brightness levels within the same sub-pixel.

[0191] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the array substrate also includes: a first common trace 21 located on one side of the gate line 2 and extending along the first direction X; the plurality of transistors T include: a first transistor T1, a second transistor T2, and a third transistor T3 electrically connected to the data line 3;

[0192] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422. Specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via K1.

[0193] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through the second via K2; the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through the third via K3.

[0194] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2. The first electrode TB of the third transistor T3 is multiplexed with the second electrode TC of the second transistor T2. The second electrode TC of the third transistor T3 is electrically connected to the first common trace 21.

[0195] In this embodiment, since the third transistor T3 is connected to the second transistor T2, the voltage applied to the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially distributed to the first common trace 21 through the third transistor T3. This results in the voltages obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 being lower than the voltages obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422. Consequently, the luminous brightness of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is less than the luminous brightness of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, thus creating a display effect with different brightness in the sub-pixels.

[0196] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the pixel electrode 4 further includes: a connection portion 44 connecting the first sub-pixel electrode 412 and the fourth sub-pixel electrode 422, and a first overlapping portion PD1 connected to the connection portion 44; the connection portion 44 includes: a third connection portion 443 extending along the first direction X, a fourth connection portion 444, and a fifth connection portion 445 extending along the second direction Y.

[0197] One end of the third connecting portion 443 is connected to the first sub-pixel electrode 411, one end of the fourth connecting portion 444 is connected to the fourth sub-pixel electrode 422, one end of the fifth connecting portion 445 is connected to the other end of the third connecting portion 443, and the other end of the fifth connecting portion 445 is connected to the other end of the fourth connecting portion 444; the first overlapping portion PD1 is electrically connected to the first connecting portion 441 and is located away from the connected first sub-pixel electrode 411.

[0198] The second electrode TC of the first transistor T1 is electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 421 through the first lap joint PD1.

[0199] In this embodiment, the connecting portion 44 includes a third connecting portion 443 extending along the first direction X, a fourth connecting portion 444, and a fifth connecting portion 445 extending along the second direction Y. The wiring of the connecting portion 44 is neat, which is conducive to the simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure when etching patterning when the multiple pattern layouts are more complex. Moreover, the connecting portion 44 is also connected to the first overlapping portion PD1, so as to facilitate the electrical connection between the first overlapping portion PD1 and the second electrode TC of the first transistor T1 through the first via K1.

[0200] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the pixel electrode further includes: a first adapter portion PZ1 extending along the first direction X, a second adapter portion PZ2 extending along the second direction Y, and a second overlapping portion PD2; one end of the first adapter portion PZ1 is electrically connected to one end of the second sub-pixel electrode 412 facing the fourth sub-pixel electrode 422, and the other end of the first adapter portion PZ1 is electrically connected to one end of the second adapter portion PZ2; the other end of the second adapter portion PZ2 is electrically connected to the second overlapping portion PD2; the second electrode TB of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 through the second overlapping portion PD2. In this embodiment, a first transition portion PZ1, a second transition portion PZ2 extending along the second direction Y, and a second overlapping portion PD2 are also provided on one side of the second sub-pixel electrode 412. This enables the second sub-pixel electrode 412 to be electrically connected to the second electrode TB of the second transistor T2. The wiring method for the electrical connection between the second sub-pixel electrode 412 and the second electrode TB of the second transistor T2 is simple and regular, which is beneficial for the concise wiring between the first pixel electrode 41 and the second pixel electrode 42. It avoids the risk of short circuit failure during etching patterning when multiple pattern layouts are complex.

[0201] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the extension directions of the second adapter PZ2 and the fifth connector 445 are parallel. This facilitates simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuits during etching when multiple pattern layouts are complex.

[0202] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the extension line of the first adapter PZ1 coincides with the extension line of the third connection 443. This facilitates simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit during etching patterning when multiple pattern layouts are complex.

[0203] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the pixel electrode 4 further includes: a third transition portion PZ3 extending along the first direction X, and a third overlap portion PD3; one end of the third transition portion PZ3 is electrically connected to the end of the third sub-pixel electrode 421 facing the first sub-pixel electrode 411, and the other end of the third transition portion PZ3 is electrically connected to the third overlap portion PD3; the second electrode TC of the second transistor T2 is electrically connected to the third sub-pixel electrode 421 through the third overlap portion PD3. In this embodiment, a third transition portion PZ3 and a third overlap portion PD3 are also provided on one side of the third sub-pixel electrode 421. This achieves electrical connection between the third sub-pixel electrode 421 and the second electrode TB of the second transistor T2, and the wiring method for electrical connection between the third sub-pixel electrode 421 and the second electrode TB of the second transistor T2 is simple and neat, which is beneficial for simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit failure during etching patterning when multiple pattern layouts are complex.

[0204] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the extension line of the third adapter PZ3 coincides with the extension line of the fourth connector 444. This facilitates simple wiring between the first pixel electrode 41 and the second pixel electrode 42, avoiding the risk of short circuits during etching when multiple pattern layouts are complex.

[0205] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, a first gap J1 exists between the third connecting portion 443 and the first pixel electrode 41; a second gap J2 exists between the fourth connecting portion 444 and the second pixel electrode 42; a third gap J3 exists between the first transition portion PZ1 and the first pixel electrode 41; and a fourth gap J4 exists between the third transition portion PZ3 and the second pixel electrode 42. Specifically, for example, as... Figure 2G In this structure, the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are two brighter parts, while the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are two darker parts. The first transition part PZ1 is electrically connected to the darker second sub-pixel electrode 412, and has a lower applied voltage. It also has a longer relative setting area with the first sub-pixel electrode 411, which has a higher applied voltage. By having a third gap J3 between the first transition part PZ1 and the first sub-pixel electrode 411, it is possible to avoid problems such as breakdown when the two are close together and the voltage difference is large. Similarly, the third transition part PZ3 and the fourth sub-pixel electrode 422 have a fourth gap J4, which can also prevent problems such as breakdown when the two are close together and the voltage difference is large. The third connecting part 443 has a first gap J1 between it and the first pixel electrode 41; the fourth connecting part 444 has a second gap J2 between it and the second pixel electrode 42, which can form a design that is relatively symmetrical with the third gap J3 and the fourth gap J4, which is conducive to the neat and orderly layout of multiple patterns.

[0206] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the array substrate also includes: a fourth overlap portion PD4; the second electrode TC of the third transistor T3 is electrically connected to the first common trace 21 through the fourth overlap portion PD4.

[0207] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the second terminal TC of the third transistor T3 can be electrically connected to the first common trace 21 through the fourth via K4.

[0208] In one possible implementation, see Figure 2I As shown, Figure 2I It can be Figure 2BThe cross-sectional diagram at the dashed line EF shows that the fourth via K4 can be a semi-via design. The fourth via K4 partially exposes the first common trace 21 and partially exposes the second electrode TC of the third transistor T3. The fourth overlap portion PD4 partially contacts the first common trace 21 and partially contacts the second electrode TC of the third transistor T3 at the fourth via K4, thus electrically connecting the first common trace 21 and the second electrode TC of the third transistor T3 through the fourth overlap portion PD4. Specifically, the semi-via design of the fourth via K4 allows it to form a stepped structure internally, which helps to guide the alignment fluid and avoids moiré patterns on the screen.

[0209] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the fourth overlapping portion PD4 has an outer edge f3 extending along the first direction X, and the second overlapping portion PD2 has an outer edge f4 extending along the first direction X; the first overlapping portion PD1 has an outer edge f5 extending along the second direction Y, and the third overlapping portion PD3 has an outer edge f6 extending along the second direction Y; the extension line of the outer edge f3 of the fourth overlapping portion coincides with the extension line of the outer edge f4 of the second overlapping portion; the extension line of the outer edge f5 of the first overlapping portion coincides with the extension line of the outer edge f6 of the third overlapping portion.

[0210] In this embodiment, the extension line of the outer edge f3 of the fourth overlapping portion coincides with the extension line of the outer edge f4 of the second overlapping portion; the extension line of the outer edge f5 of the first overlapping portion coincides with the extension line of the outer edge f6 of the third overlapping portion. The pattern distribution between the first pixel electrode 41 and the second pixel electrode 42 is simple and regular, avoiding the risk of short circuit failure when etching patterning when the layout of multiple patterns is more complex.

[0211] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the second electrode TC of the first transistor T1 includes: a first transistor first portion T1C1 extending along the first direction X; the orthographic projection of the first transistor first portion T1C1 onto the substrate 1 overlaps with the orthographic projection of the first overlapping portion PD1 onto the substrate 1. This facilitates electrical connection between the first transistor first portion T1C1 and the first overlapping portion PD1 through the first via K1.

[0212] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5GAs shown, the second electrode TC of the first transistor T1 includes: a second part T1C2 of the first transistor extending along the second direction Y and electrically connected to the first part T1C1 of the first transistor; specifically, the orthographic projection of the second part T1C2 of the first transistor on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0213] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the second electrode TC of the second transistor T2 includes: a first part T2C1 of the second transistor extending along the first direction X, and a second part T2C2 of the second transistor extending along the second direction Y and electrically connected to one end of the first part T2C1; the orthographic projection of the first part T2C1 of the second transistor on the substrate 1 overlaps with the orthographic projection of the third overlapping part PD3 on the substrate 1, so as to realize the electrical connection between the first part T2C1 of the second transistor and the third overlapping part PD3 through the second via K2; the orthographic projection of the second part T2C2 of the second transistor on the substrate overlaps with the orthographic projection of the second overlapping part PD2 on the substrate 1, so as to realize the electrical connection between the second part T2C2 of the second transistor and the second overlapping part PD2 through the third via K3.

[0214] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the second electrode TC of the second transistor T2 may further include: a third part T2C3 of the second transistor that is electrically connected to the other end of the first part T2C1 of the second transistor and extends along the second direction Y. Specifically, the orthographic projection of the third part T2C3 of the second transistor on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0215] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the second terminal TC of the third transistor T3 may include: a first part T3C1 of the third transistor extending along the second direction Y, and a second part T3C2 of the third transistor extending along the first direction X and connected to the first part T3C1 of the third transistor.

[0216] In one possible implementation, see Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the extension direction of the first part T3C1 of the third transistor is parallel to the extension direction of the second part T2C2 of the second transistor.

[0217] In one possible implementation, see Figures 1A-1G As shown, the array substrate further includes: a first common trace 21 located on one side of the gate line 2 and extending along the first direction; the first common trace 21 is disconnected at the position where it intersects with the data line 3. This is to avoid the first common trace 21 overlapping with the data line 3, which would increase the load on the data line 3 and affect the signal transmission of the data line 3.

[0218] In one possible implementation, see Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the array substrate further includes a second common trace group 22 electrically connected to the first common trace 21 and extending away from the gate line 2. The second common trace group 22 includes two second common traces 220. The orthographic projection of the data line 3 on the substrate 1 overlaps with the gap between the two second common traces 220 of the same second common trace group 22 on the orthographic projection of the data line 3 on the substrate 1. The orthographic projections of the second common traces 220 on the substrate 1 are located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the second pixel electrode 42.

[0219] In one possible implementation, see Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the array substrate further includes: a third common trace 23 located on the other side of the gate line 2 and extending along the first direction X, and a fourth common trace group 24 connected to the third common trace 23 and extending away from the gate line 2; the third common trace 23 is disconnected at the position where it intersects with the data line 3, so as to avoid the third common trace 23 overlapping with the data line 3, which would increase the load on the data line 3 and affect the signal transmission of the data line 3; the fourth common trace group 24 includes: two fourth common traces 240; the orthographic projection of the data line 3 on the substrate 1 and the gap between the two fourth common traces 240 of the same fourth common trace group 24 have an overlapping area in the orthographic projection of the substrate 1. The orthographic projection of the fourth common traces 240 on the substrate 1 is located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the first pixel electrode 41.

[0220] In one possible implementation, the first common trace 21 and the third common trace 23 can be electrically connected in the display area via a bridging method, or they can be electrically connected in the non-display area. In another possible implementation, the array substrate may further include a non-display area located around the outer edge of the display area. The non-display area may be provided with a ring-shaped common trace surrounding the display area. The first common trace 21 and the third common trace 23 may both be electrically connected to the ring-shaped common trace to have the same common voltage signal.

[0221] In one possible implementation, see Figures 1A-1G As shown, the array substrate further includes a fifth common trace 25 extending along the first direction X and electrically connected to the second common trace 220. The orthogonal projection of the fifth common trace 25 onto the substrate passes through the central region of the orthogonal projection of the second pixel electrode 42 onto the substrate 1.

[0222] In one possible implementation, see Figures 1A-1G As shown, the array substrate further includes a sixth common trace 26 extending along the first direction X and electrically connected to the fourth common trace 240. The orthographic projection of the sixth common trace 26 onto the substrate 1 passes through the central region of the orthographic projection of the first pixel electrode 41 onto the substrate 1.

[0223] In one possible implementation, see Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the first sub-pixel electrode 411 and the second sub-pixel electrode 412 each include a first sub-electrode portion P1 and a second sub-electrode portion P2 distributed along the second direction Y; the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 each include a third sub-electrode portion P3 and a fourth sub-electrode portion P4 distributed along the second direction Y; the first sub-electrode portion P1, the second sub-electrode portion P2, the third sub-electrode portion P3, and the fourth sub-electrode portion P4 each have a plurality of slits F; and the extension direction of the slits F of the first sub-electrode portion P1 is the same as the extension direction of the slits F of the fourth sub-electrode portion P4; the extension direction of the slits F of the second sub-electrode portion P2 is the same as the extension direction of the slits F of the third sub-electrode portion P3.

[0224] In one possible implementation, the length of the slit F perpendicular to the extension direction can be 2 μm to 4 μm. Specifically, the length of the slit F perpendicular to the extension direction can be 3 μm. In this embodiment of the present disclosure, on the array substrate provided in this embodiment of the present disclosure, when the length of the slit F perpendicular to the extension direction is reduced to 3 μm, the dark lines almost disappear.

[0225] For details, see Figures 1A-1G , Figures 2A-2G , Figures 3A-3G , Figures 4A-4G , Figures 5A-5G As shown, the angle between the extension direction of the slit F of the first sub-electrode P1 and the first direction X can be 40° to 50°, for example, 45°; the angle between the extension direction of the slit F of the second sub-electrode P2 and the first direction X can be 130° to 140°, for example, 135°; the angle between the extension direction of the slit F of the third sub-electrode P3 and the first direction X can be 130° to 140°, for example, 135°; and the angle between the extension direction of the slit F of the fourth sub-electrode P4 and the first direction X can be 40° to 50°, for example, 45°.

[0226] Specifically, the angle between the liquid crystal alignment direction in the region where the first sub-electrode P1 is located and the first direction X can be 220° to 230°, for example, 225°; the angle between the liquid crystal alignment direction in the region where the second sub-electrode P2 is located and the first direction X can be 130° to 140°, for example, 135°; the angle between the liquid crystal alignment direction in the region where the third sub-electrode P3 is located and the first direction X can be 310° to 320°, for example, 315°; and the angle between the liquid crystal alignment direction in the region where the fourth sub-electrode P4 is located and the first direction X can be 40° to 50°, for example, 45°. This achieves four alignment directions in the region where a pixel electrode 4 is located, and combined with segmented bright and dark regions, an 8-domain alignment scheme can be formed in a sub-pixel when using Super UV Photo Alignment (SUVA) technology.

[0227] In one possible implementation, see Figures 1A-1G , Figures 4A-4G As shown, the first sub-pixel electrode 411, the second sub-pixel electrode 412, the third sub-pixel electrode 421, and the fourth sub-pixel electrode 422 are all rectangular in shape when projected onto the substrate 1.

[0228] In one possible implementation, see Figures 2A-2G As shown, the first sub-electrode P1, the second sub-electrode P2, the third sub-electrode P3, and the fourth sub-electrode P4 are all trapezoidal in shape when projected onto the substrate 1. In the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, the trapezoidal first sub-electrode P1 and the trapezoidal second sub-electrode P2 are arranged with their top edges facing each other (i.e., with their short sides facing each other). In the second sub-pixel electrode 412 and the third sub-pixel electrode 421, the trapezoidal first sub-electrode P1 and the trapezoidal second sub-electrode P2 are arranged with their bottom edges facing each other (i.e., with their long sides facing each other). In this embodiment, the first pixel electrode 41 and the second pixel electrode 42 can be divided in a manner parallel to the extension direction of the slit F, which can achieve better transmittance.

[0229] In one possible implementation, see Figures 3A-3G As shown, the first sub-electrode P1, the second sub-electrode P2, the third sub-electrode P3, and the fourth sub-electrode P4 are all trapezoidal in shape when projected onto the substrate 1. In the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, the trapezoidal first sub-electrode P1 and the trapezoidal second sub-electrode P2 are arranged with their base edges facing each other (i.e., with their long sides facing each other). In the second sub-pixel electrode 412 and the third sub-pixel electrode 421, the trapezoidal first sub-electrode P1 and the trapezoidal second sub-electrode P2 are arranged with their top edges facing each other (i.e., with their short sides facing each other). In this embodiment, the first pixel electrode 41 and the second pixel electrode 42 can be divided in a manner perpendicular to the direction of the slit F, which can achieve better transmittance.

[0230] In one possible implementation, see Figures 5A-5G As shown, the first sub-pixel electrode 411 includes: a first main portion PA1 and a second main portion PA2 extending and connected along the second direction Y, and a first side portion PC1 extending along the first direction X, a plurality of first branches PB1 extending from the first main portion PA1 and the first side portion PC1 along the fourth direction G1, and a plurality of second branches PB2 extending from the second main portion PA2 and the first side portion PC1 along the fifth direction G2; the second sub-pixel electrode 412 includes: a third main portion PA3 and a fourth main portion PA4 extending and connected along the second direction Y, and a third main portion... PA3 is connected at one end to a fifth main part PA5 that extends along the first direction X, and PA6 is connected at one end to a fourth main part PA4 that extends along the first direction X. Multiple third branches PB3 extend from the third main part PA3 and the fifth main part PA5 along the fourth direction G1, and multiple fourth branches PB4 extend from the fourth main part PA4 and the sixth main part PA6 along the fifth direction G2. Multiple first branches PB1 and multiple third branches PB3 are interdigitated, and multiple second branches PB2 and multiple fourth branches PB4 are interdigitated.

[0231] The third sub-pixel electrode 421 includes: a seventh main portion PA7 extending and connected along the second direction Y, an eighth main portion PA8, a ninth main portion PA9 connected to one end of the seventh main portion PA7 and extending along the first direction X, a tenth main portion PA10 connected to one end of the eighth main portion PA8 and extending along the first direction X, a plurality of fifth branches PB5 extending from the seventh main portion PA7 and the ninth main portion PA9 along the fourth direction G1, and a plurality of sixth branches PB6 extending from the eighth main portion PA8 and the tenth main portion PA10 along the fifth direction G2; the fourth sub-pixel electrode 421 includes: a seventh main portion PA7 extending along the second direction Y and connected along the second direction Y, an eighth main portion PA7 and the ninth main portion PA9 extending along the second direction Y, a ninth main portion PA9 connected along the third direction Y and the ninth main portion PA9 extending along the first direction X, a tenth main portion PA10 connected along the second direction Y, a tenth main portion PA10 extending along the third direction G2, and a tenth main portion PA10 extending along the fifth direction G2; the fourth sub-pixel electrode 421 includes: a seventh main portion PA7 extending along the second direction Y and connected along the second direction Y, an eighth main portion PA8 extending along the second direction Y, an eighth main portion PA7 extending along the second direction Y, an eighth main portion PA8 extending along the second direction Y, a tenth main portion PA10 extending along the third direction G2, and a tenth main portion PA10 extending along the third direction Y; the fourth sub-pixel electrode 421 includes: a seventh main portion PA7 extending along the second direction Y and connected along the second direction Y, an eighth main portion PA8 extending along the second direction Y, a ninth main portion PA9 extending along the first direction X, a tenth main portion PA10 extending along the second direction Y, a tenth main portion PA10 extending along the second direction Y, a tenth main portion PA10 extending along the third direction G2, and a tenth main portion PA10 extending along the third direction Y; the fourth sub-pi The pixel electrode 422 includes: an eleventh main portion PA11 extending and connected along the second direction Y, a twelfth main portion PA12, and a second side portion PC2 extending along the first direction X; a plurality of seventh branches PB7 extending from the eleventh main portion PA11 and the second side portion PC2 along the fourth direction G1; and a plurality of eighth branches PB8 extending from the twelfth main portion PA12 and the second side portion PC2 along the fifth direction G2; the plurality of fifth branches PB5 and the plurality of seventh branches PB7 are interdigitated, and the plurality of sixth branches PB6 and the plurality of eighth branches PB8 are interdigitated.

[0232] It should be noted that, for the embodiments provided in this disclosure... Figure 2A , Figure 3A , Figure 5A The corresponding array substrate structure can also achieve different brightness display effects by setting a first signal line 5 and releasing part of the voltage to the first signal line 5 through the third transistor T3; similarly, for the embodiments provided in this disclosure... Figure 1A The array substrate shown may also omit the first signal line 5 and release part of the voltage to the first common trace 21 through the third transistor T3 to achieve different brightness display effects. This disclosure does not limit this.

[0233] In one possible implementation, see Figures 6A-6J As shown, the array substrate further includes: a first conductive layer 7 located on the side of the pixel electrode 4 facing the substrate 1; the first conductive layer 7 has a first cutout L1, a second cutout L2, a third cutout L3, and a fourth cutout L4; at least a portion of the orthographic projection of the first cutout L1 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the first sub-electrode P1 onto the substrate 1; at least a portion of the orthographic projection of the second cutout L2 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the second sub-electrode P2 onto the substrate 1; at least a portion of the orthographic projection of the third cutout L3 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the third sub-electrode P3 onto the substrate 1; at least a portion of the orthographic projection of the fourth cutout L4 onto the substrate 1 overlaps with at least a portion of the orthographic projection of the fourth sub-electrode P4 onto the substrate 1.

[0234] In this embodiment of the present disclosure, for a VA display panel with a pixel electrode layer on the array substrate and a common electrode layer on the opposing substrate, a first conductive layer 7 is also provided on the side of the pixel electrode 4 facing the substrate 1. The first conductive layer 7 has a first cutout L1, a second cutout L2, a third cutout L3, and a fourth cutout L4, which can make the liquid crystal twist more uniform, reduce the dark lines corresponding to the pixel electrode, reduce the width of the black matrix, and improve the transmittance of the display panel. In addition, in addition to the vertical electric field formed by the pixel electrode and the common electrode, the pixel electrode and the first conductive layer 7 will form a transverse electric field in the array substrate, which can increase the deflection direction of the liquid crystal and improve the color shift problem of the display panel.

[0235] Specifically, the first conductive layer 7 can be located between the substrate 1 and the layer containing the pixel electrode 4. Specifically, the first conductive layer 7 can be the same signal loaded as the common electrode layer of the opposing substrate. The first conductive layer 7 can specifically be a transparent electrode layer, and the material of the first conductive layer 7 can specifically be indium tin oxide.

[0236] In one possible implementation, see Figure 6G As shown, the first conductive layer 7 may further include a first conductive connection portion 71. The orthographic projection of the first conductive connection portion 71 onto the substrate 1 covers the orthographic projection of the data line 3 onto the substrate 1, and also covers the orthographic projection of the gate line 2 onto the substrate 1. In this embodiment, the orthographic projection of the first conductive connection portion 71 onto the substrate 1 covers the orthographic projection of the data line 3 onto the substrate 1. The first conductive connection portion 71 can shield the coupling capacitance between the pixel electrode and the data line 3, as well as the coupling capacitance between the pixel electrode and the gate line 2. This can avoid setting the second common trace 220 (and / or the fourth common trace 240), or reduce the number or line width of the second common trace 220 (and / or the fourth common trace 240), thereby increasing the transmittance of the display panel.

[0237] In one possible implementation, see Figure 6G As shown, the first conductive layer 7 may further include a fifth cutout L5, a sixth cutout L6, a seventh cutout L7, and an eighth cutout L8; wherein at least a portion of the orthographic projection of the fifth cutout L5 onto the substrate 1 may overlap with at least a portion of the orthographic projection of the first via K1 onto the substrate 1; at least a portion of the orthographic projection of the sixth cutout L6 onto the substrate 1 may overlap with at least a portion of the orthographic projection of the second via K2 onto the substrate 1; at least a portion of the orthographic projection of the seventh cutout L7 onto the substrate 1 may overlap with at least a portion of the orthographic projection of the third via K3 onto the substrate 1; the fifth cutout L5, the sixth cutout L6, and the seventh cutout L7 are configured to facilitate the conduction of the pixel electrode 4 above the first conductive layer 7 and the transistor below the first conductive layer 7.

[0238] In this embodiment, the first conductive layer 7 may further include an eighth cutout L8, which can avoid the overlapping capacitance between the gate line 2 and the first conductive layer 7, thus affecting the pixel charging rate. However, if the first conductive layer 7 is completely cutout in the area where the gate line 2 is located, it will lead to light leakage. In this embodiment, the eighth cutout L8 is only set in the part of the first conductive layer 7 that overlaps with the gate line 2, which can reduce light leakage and reduce the overlapping capacitance between the gate line 2 and the first conductive layer 7, thus ensuring the charging rate.

[0239] In one possible implementation, the length h2 of the eighth cutout L8 in the first direction X can be one-fifth to four-fifths of the length h1 of the second cutout L2 in the first direction; in one possible implementation, the length h2 of the eighth cutout L8 in the first direction X can be one-quarter to three-quarters of the length h1 of the second cutout L2 in the first direction; in one possible implementation, the length h2 of the eighth cutout L8 in the first direction X can be one-half of the length h1 of the second cutout L2 in the first direction.

[0240] In one possible implementation, the length h4 of the eighth cutout L8 in the second direction Y can be one-fifth to four-fifths of the distance h3 between the second cutout L2 and the third cutout L3; in another possible implementation, the length h4 of the eighth cutout L8 in the second direction Y can be one-quarter to three-quarters of the distance h3 between the second cutout L2 and the third cutout L3; in yet another possible implementation, the length h4 of the eighth cutout L8 in the second direction Y can be one-half of the distance h3 between the second cutout L2 and the third cutout L3.

[0241] In one possible implementation, the outer edge extension line of the eighth cutout L8 extending along the second direction Y and away from the sixth cutout L6 coincides with an outer edge extension line of the second cutout L2 extending along the second direction Y.

[0242] In one possible implementation, combined with Figures 6A-6J as well as Figure 10 As shown, the data line 3 can be located on the side of the gate line 2 away from the substrate 1, the first conductive layer 7 can be located on the side of the data line 3 away from the gate line 2, the pixel electrode 4 can be located on the side of the first conductive layer 7 away from the data line 3, a gate insulating layer can also be provided between the layer where the gate line 2 is located and the layer where the data line 3 is located, an active layer can also be provided between the gate insulating layer and the data line 3 (the active layer can include the active pattern 6, and the active layer material can be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, etc., which are not limited here), a first insulating layer 91 can also be provided between the data line 3 and the first conductive layer 7, and a second insulating layer 92 can be provided between the first conductive layer 7 and the pixel electrode 4.

[0243] Combination Figure 1H , Figure 2H , Figure 3H , Figure 4H , Figure 5H and Figure 6K As shown, this disclosure embodiment performed optical simulations on different array substrate structures. By comparing the horizontal dark lines in the center of the sub-pixels, it can be clearly seen that for those without the first conductive layer 7... Figure 1H , Figure 2H , Figure 3H , Figure 4H , Figure 5H The corresponding array substrate structure, wherein, Figure 2A The structure corresponding to this has the highest transmittance.

[0244] Based on the same inventive concept, this disclosure also provides a display panel, which includes: an array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate, the counter substrate being provided with a common electrode layer.

[0245] In one possible implementation, combined with Figures 6A-6J as well as Figure 10 As shown, the display panel can also be provided with a black matrix 8. The orthogonal projection of the black matrix 8 onto the substrate 1 can cover the orthogonal projection of the gate line 2 onto the substrate 1, and also cover the orthogonal projection of the data line 3 onto the substrate 1. Specifically, the opposing substrate can include an opposing substrate 90, and the black matrix 8 can be located between the opposing substrate 90 and the common electrode layer. Figure 10 (Not shown in the image).

[0246] In one possible implementation, combined with Figure 10 As shown, the first conductive layer 7 is located on the side of the pixel electrode 4 away from the opposing substrate. In this common embodiment, the first conductive layer 7, located on the side of the pixel electrode 4 away from the opposing substrate, can isolate (or shield) the first overlapping capacitance between the pixel electrode 4 and the gate line 2 and the second overlapping capacitance between the pixel electrode 4 and the data line 3, greatly reducing the risk of crosstalk. Simultaneously, due to the presence of the first conductive layer 7, the distance between the pixel electrodes 4 can be reduced, causing the pixel electrode 4 to overlap with the gate line 2 and with the data line 3, reducing the risk of liquid crystal leakage. This reduces the width of the black matrix, increases the pixel aperture ratio, and improves the pixel transmittance.

[0247] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0248] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0249] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0250] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The array substrate comprises: a substrate; a plurality of gate lines located on one side of the substrate and extending along a first direction; a plurality of data lines extending along a second direction; a plurality of pixel electrodes, the pixel electrodes comprising: a first pixel electrode located on one side of the gate lines, and a second pixel electrode located on the other side of the gate lines; the first pixel electrode comprising: a first sub-pixel electrode and a second sub-pixel electrode distributed along the first direction; the second pixel electrode comprising: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the first direction; one of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode.

2. The array substrate of claim 1, wherein, The array substrate further comprises: a plurality of transistors; the plurality of transistors are electrically connected to the same pixel electrode, and are electrically connected to the same data line and the same gate line; the second sub-pixel electrode is located on the side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on the side of the third sub-pixel electrode away from the electrically connected data line; the first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode.

3. The array substrate of claim 2, wherein, The array substrate further comprises: a first signal line extending along the second direction; the plurality of transistors comprise: a first transistor, a second transistor, and a third transistor; the control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first sub-pixel electrode and the fourth sub-pixel electrode; the control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode; the control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with the first signal line.

4. The array substrate of claim 3, wherein, The pixel electrode further comprises: a first sub-pixel electrode protrusion connected to the side of the first sub-pixel electrode facing the third sub-pixel electrode; the second electrode of the first transistor is electrically connected to the first sub-pixel electrode through the first sub-pixel electrode protrusion.

5. The array substrate of claim 4, wherein, The pixel electrode further comprises: a connecting portion connecting the first sub-pixel electrode and the fourth sub-pixel electrode; the connecting portion comprises: a first connecting portion extending along the second direction, and a second connecting portion extending along a third direction; the third direction intersects the first direction and the second direction; one end of the first connecting portion is electrically connected to one end of the side of the first sub-pixel electrode facing the third sub-pixel electrode, the other end is electrically connected to the second connecting portion, and the other end of the second connecting portion is electrically connected to one end of the side of the fourth sub-pixel electrode facing the second sub-pixel electrode.

6. The array substrate of claim 5, wherein, The pixel electrode further comprises: a third sub-pixel electrode protrusion connected to the side of the third sub-pixel electrode facing the first sub-pixel electrode; The second electrode of the second transistor is electrically connected with the third sub-pixel electrode through the third sub-pixel electrode protrusion.

7. The array substrate of claim 6, wherein, The pixel electrode further comprises a second sub-pixel electrode extension part extending along the second direction, and a second sub-pixel electrode protrusion; one end of the second sub-pixel electrode extension part is electrically connected with one end of the second sub-pixel electrode towards the fourth sub-pixel electrode, and the other end is electrically connected with the second sub-pixel electrode protrusion. The second electrode of the second transistor is electrically connected with the second sub-pixel electrode through the second sub-pixel electrode protrusion.

8. The array substrate of claim 7, wherein, The extending direction of the second sub-pixel electrode extension part is parallel to the extending direction of the first connecting part.

9. The array substrate of claim 7 or 8, wherein, The second sub-pixel electrode protrusion has a second sub-pixel electrode protrusion outer edge extending away from the second sub-pixel electrode and along the first direction; the third sub-pixel electrode protrusion has a third sub-pixel electrode protrusion outer edge extending away from the third sub-pixel electrode and along the first direction. The extension line of the second sub-pixel electrode protrusion outer edge coincides with the extension line of the third sub-pixel electrode protrusion outer edge; or the extension line of the second sub-pixel electrode protrusion outer edge at least partially overlaps with the third sub-pixel electrode protrusion; or the extension line of the third sub-pixel electrode protrusion outer edge at least partially overlaps with the second sub-pixel electrode protrusion.

10. The array substrate of claim 7 or 8, wherein, The center of the third sub-pixel electrode protrusion is parallel to the connection line of the center of the first sub-pixel electrode protrusion.

11. The array substrate of claim 4, wherein, The second electrode of the first transistor comprises a first transistor first part extending along the first direction. The orthographic projection of the first transistor first part on the substrate has an overlapping area with the orthographic projection of the first sub-pixel electrode protrusion on the substrate.

12. The array substrate of claim 8, wherein, The second electrode of the second transistor comprises a second transistor first part extending along the first direction, and a second transistor second part extending along the second direction and electrically connected with one end of the second transistor first part. The orthographic projection of the second transistor first part on the substrate has an overlapping area with the orthographic projection of the third sub-pixel electrode protrusion on the substrate; the orthographic projection of the second transistor second part on the substrate has an overlapping area with the orthographic projection of the second sub-pixel electrode protrusion on the substrate.

13. The array substrate of claim 12, wherein, At least part of the orthographic projection of the second transistor second part on the substrate overlaps with at least part of the orthographic projection of the second sub-pixel electrode extension part on the substrate.

14. The array substrate of claim 12, wherein, At least part of the orthographic projection of the second transistor second part on the substrate is located in the area surrounded by the orthographic projection of the recessed part on the substrate.

15. The array substrate of claim 14, wherein, The first signal line comprises a first signal part, a second signal part, and a third signal part distributed along the second direction in sequence, a fourth signal part extending along the first direction and connecting the second signal part with the first signal part, and a fifth signal part extending along the first direction and connecting the second signal part with the third signal part. The extension line of the first signal part coincides with the extension line of the third signal part; the extension line of the second signal part does not coincide with the extension line of the first signal part; the second signal part, the fourth signal part and the fifth signal part constitute the recessed part, and the fourth signal part and / or the fifth signal part at least partially overlaps with the pixel electrode.

16. The array substrate of claim 2, wherein, The array substrate further comprises: a first common wire extending along the first direction on one side of the gate line; the plurality of transistors comprises: a first transistor, a second transistor and a third transistor electrically connected with the data line; The control electrode of the first transistor is electrically connected with the gate line, the first electrode of the first transistor is electrically connected with the data line, and the second electrode of the first transistor is electrically connected with the first sub-pixel electrode and the fourth sub-pixel electrode; The control electrode of the second transistor is electrically connected with the gate line, the first electrode of the second transistor is electrically connected with the data line, and the second electrode of the second transistor is electrically connected with the second sub-pixel electrode and the third sub-pixel electrode; The control electrode of the third transistor is electrically connected with the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected with the first common wire.

17. The array substrate of claim 16, wherein, The pixel electrode further comprises: a connecting part connecting the first sub-pixel electrode and the fourth sub-pixel electrode, and a first lap joint connected to the connecting part; the connecting part comprises: a third connecting part extending along the first direction, a fourth connecting part, and a fifth connecting part extending along the second direction; One end of the third connecting part is connected with the first sub-pixel electrode, one end of the fourth connecting part is connected with the fourth sub-pixel electrode, one end of the fifth connecting part is connected with the other end of the third connecting part, and the other end of the fifth connecting part is connected with the other end of the fourth connecting part; the first lap joint is electrically connected to the third connecting part and away from the side of the first sub-pixel electrode connected; The second electrode of the first transistor is electrically connected with the first sub-pixel electrode and the fourth sub-pixel electrode through the first lap joint.

18. The array substrate of claim 17, wherein, The pixel electrode further comprises: a first adapter part extending along the first direction, and a second adapter part extending along the second direction, and a second lap joint; One end of the first adapter part is electrically connected with one end of the second sub-pixel electrode towards the fourth sub-pixel electrode, and the other end of the first adapter part is electrically connected with one end of the second adapter part; the other end of the second adapter part is electrically connected with the second lap joint; The second electrode of the second transistor is electrically connected to the second sub-pixel electrode through the second lap joint.

19. The array substrate of claim 18, wherein, The second adapter part is parallel to the extension direction of the fifth connecting part.

20. The array substrate of claim 18 or 19, wherein, The pixel electrode further comprises: a third adapter part extending along the first direction, and a third lap joint; One end of the third adapter part is electrically connected with one end of the third sub-pixel electrode towards the first sub-pixel electrode, and the other end of the third adapter part is electrically connected with the third lap joint; The second electrode of the second transistor is electrically connected with the third sub-pixel electrode through the third connecting portion.

21. The array substrate of claim 20, wherein, The third connecting portion and the first pixel electrode have a first gap therebetween; the fourth connecting portion and the second pixel electrode have a second gap therebetween. The first connecting portion and the first pixel electrode have a third gap therebetween; the third connecting portion and the second pixel electrode have a fourth gap therebetween.

22. The array substrate of claim 20, wherein, The array substrate further comprises a fourth connecting portion; the second electrode of the third transistor is electrically connected with the first common wire through the fourth connecting portion.

23. The array substrate of claim 22, wherein, The fourth connecting portion has a fourth connecting portion outer edge extending along the first direction; the second connecting portion has a second connecting portion outer edge extending along the first direction; the first connecting portion has a first connecting portion outer edge extending along the second direction; the third connecting portion has a third connecting portion outer edge extending along the second direction. An extension line of the fourth connecting portion outer edge coincides with an extension line of the second connecting portion outer edge; an extension line of the first connecting portion outer edge coincides with an extension line of the third connecting portion outer edge.

24. The array substrate of claim 20, wherein, The second electrode of the first transistor comprises a first transistor first portion extending along the first direction. A projection of the first transistor first portion on the substrate has an overlapping area with a projection of the first connecting portion on the substrate.

25. The array substrate of claim 20, wherein, The second electrode of the second transistor comprises a second transistor first portion extending along the first direction, and a second transistor second portion extending along the second direction and electrically connected with one end of the second transistor first portion. A projection of the second transistor first portion on the substrate has an overlapping area with a projection of the third connecting portion on the substrate; a projection of the second transistor second portion on the substrate has an overlapping area with a projection of the second connecting portion on the substrate.

26. The array substrate of claim 2, wherein, The array substrate further comprises a first common wire extending along the first direction on one side of the gate line; the first common wire is disconnected at a position crossing the data line.

27. The array substrate of claim 16, wherein, The array substrate further comprises a second common wire group electrically connected with the first common wire and extending away from the side of the gate line; the second common wire group comprises two second common wires. A projection of the data line on the substrate has an overlapping area with a gap between the two second common wires of the same second common wire group on the substrate.

28. The array substrate of claim 27, wherein, The array substrate further comprises a third common wire extending along the first direction on the other side of the gate line, and a fourth common wire group electrically connected with the third common wire and extending away from the side of the gate line. The third common wire is disconnected at a position crossing the data line; the fourth common wire group comprises two fourth common wires; a projection of the data line on the substrate has an overlapping area with a gap between the two fourth common wires of the same fourth common wire group on the substrate.

29. The array substrate of claim 27, wherein, The array substrate further comprises a fifth common wire extending along the first direction and electrically connected with the second common wire, and the fifth common wire passes through the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the central region of the substrate in the 30. The array substrate of claim 28, wherein, ​ 31. The array substrate of claim 1, wherein, ​ ​ 32. The array substrate of claim 31, wherein, ​ 33. The array substrate of claim 31 or 32, wherein, ​ 34. The array substrate of claim 31 or 32, wherein, ​ ​ 35. The array substrate of claim 31 or 32, wherein, ​ ​ 36. The array substrate of claim 31 or 32, wherein, The first sub-pixel electrode includes: a first main part, a second main part, and a first side part extending along the first direction, a plurality of first branch parts extending from the first main part and the first side part along a fourth direction, and a plurality of second branch parts extending from the second main part and the first side part along a fifth direction; the second sub-pixel electrode includes: a third main part, a fourth main part, a fifth main part connected to one end of the third main part and extending along the first direction, a sixth main part connected to one end of the fourth main part and extending along the first direction, a plurality of third branch parts extending from the third main part and the fifth main part along the fourth direction, and a plurality of fourth branch parts extending from the fourth main part and the sixth main part along the fifth direction; the plurality of first branch parts and the plurality of third branch parts are distributed in an interdigital manner, and the plurality of second branch parts and the plurality of fourth branch parts are distributed in an interdigital manner. The third sub-pixel electrode includes: a seventh main part, an eighth main part, a ninth main part connected to one end of the seventh main part and extending along the first direction, a tenth main part connected to one end of the eighth main part and extending along the first direction, a plurality of fifth branch parts extending from the seventh main part and the ninth main part along the fourth direction, and a plurality of sixth branch parts extending from the eighth main part and the tenth main part along the fifth direction; the fourth sub-pixel electrode includes: an eleventh main part, a twelfth main part, and a second side part extending along the first direction, a plurality of seventh branch parts extending from the eleventh main part and the second side part along the fourth direction, and a plurality of eighth branch parts extending from the twelfth main part and the second side part along the fifth direction; the plurality of fifth branch parts and the plurality of seventh branch parts are distributed in an interdigital manner, and the plurality of sixth branch parts and the plurality of eighth branch parts are distributed in an interdigital manner.

37. The array substrate of claim 1, wherein, The array substrate further includes: a first conductive layer located on a side of the pixel electrode facing the substrate; the first conductive layer has a first hollow, a second hollow, a third hollow, and a fourth hollow; The first hollow overlaps at least part of a projection of the first sub-pixel electrode on the substrate; the second hollow overlaps at least part of a projection of the second sub-pixel electrode on the substrate; the third hollow overlaps at least part of a projection of the third sub-pixel electrode on the substrate; and the fourth hollow overlaps at least part of a projection of the fourth sub-pixel electrode on the substrate.

38. A display panel, wherein, The array substrate includes: The array substrate as claimed in any one of claims 1-37, further comprising a counter substrate disposed opposite to the array substrate, the counter substrate being provided with a common electrode layer.

39. A display device comprising: The display panel as claimed in claim 38.

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