Array substrate and manufacturing method thereof, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a manufacturing method of the array substrate, a display panel and a display device. The array substrate comprises a first substrate body, a driving circuit layer, a transmission electrode layer and a reflection electrode layer which are sequentially stacked, a plurality of grid lines and a plurality of data lines in the driving circuit layer extend in the first direction and the second direction respectively, the grid lines and the data lines intersect and define a plurality of pixel areas, and each pixel area comprises a transmission area and a reflection area. In one pixel area, the transmission area comprises at least one first area and at least one second area which are connected, the first area and the second area are located between the two adjacent reflection areas in the first direction and the second direction respectively, and the length directions of the first area and the second area are the second direction and the first direction respectively. The reflection electrode layer comprises reflection electrodes which are in one-to-one correspondence with the reflection areas and cover the corresponding reflection areas. The transmission electrode layer comprises transmission electrodes which are in one-to-one correspondence with the transmission areas and at least cover the corresponding transmission areas. According to the embodiment of the invention, the aperture ratio of the display panel can be improved.

Description

Array substrate and manufacturing method thereof, display panel and display device

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.

[0002] The transflective liquid crystal display device has a reflective display mode and a transmissive display mode. In a strong light environment, the reflective display mode can maintain the contrast of the picture display and reduce power consumption; in an environment with insufficient brightness, the transmissive display mode can use a backlight source to supplement the display. The display panel of the transflective liquid crystal display device includes a first substrate and a second substrate arranged opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate.

[0003] In the related art, the first substrate includes a base substrate and a driving circuit layer, a transmission electrode layer and a reflection electrode layer sequentially stacked on the base substrate. The driving circuit layer includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines extend along a first direction, the plurality of data lines extend along a second direction, the plurality of gate lines intersect with the plurality of data lines and define a plurality of pixel areas. The transmission electrode layer includes a plurality of transmission electrodes, and the plurality of transmission electrodes are respectively located in corresponding pixel areas. The reflection electrode layer includes a plurality of reflection electrodes, and the plurality of reflection electrodes are respectively located in corresponding pixel areas.

[0004] However, in order to prevent adjacent reflective electrodes from growing and overlapping in the air to cause a short circuit, a large distance is required between two adjacent reflective electrodes, resulting in a large distance between two adjacent pixel areas and a small pixel aperture ratio.

[0005]

[0006] The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a display device, which can improve the problem that the distance between two adjacent pixel regions in a first direction is large and the pixel aperture ratio is small.

[0007] On the one hand, an array substrate is provided, the array substrate comprising a first substrate and a driving circuit layer, a transmission electrode layer and a reflection electrode layer sequentially stacked on the first substrate; the driving circuit layer comprises a plurality of gate lines and a plurality of data lines, the plurality of gate lines extend along a first direction, the plurality of data lines extend along a second direction, the plurality of gate lines intersect with the plurality of data lines and define a plurality of pixel areas; each of the pixel areas comprises a transmission area and a reflection area, in at least one of the pixel areas, the transmission area comprises at least one first area and at least one second area connected to each other, the first area is located between two adjacent reflection areas in the first direction and the length direction of the first area is consistent with the second direction, the second area is located between two adjacent reflection areas in the second direction and the length direction of the second area is consistent with the first direction; the reflection electrode layer comprises a plurality of reflection electrodes, the plurality of reflection electrodes correspond to the plurality of reflection areas one by one and cover the corresponding reflection areas respectively, the transmission electrode layer comprises a plurality of transmission electrodes, the plurality of transmission electrodes correspond to the plurality of transmission areas one by one, and each of the transmission electrodes at least covers the corresponding transmission area.

[0008] Optionally, in at least one of the pixel regions, the transmission area includes one first region and one second region.

[0009] Optionally, the multiple pixel areas include a first pixel area and a second pixel area adjacent to each other in the first direction, the reflective electrode in the first pixel area is a first reflective electrode, the reflective electrode in the second pixel area is a second reflective electrode, and the transmissive electrode in the first pixel area is a first transmissive electrode; an orthographic projection of the first transmissive electrode on the bearing surface of the first substrate overlaps with an orthographic projection of the first reflective electrode and the second reflective electrode on the bearing surface of the first substrate.

[0010] Optionally, the multiple pixel areas include a third pixel area and a fourth pixel area adjacent to each other in the second direction, the reflective electrode in the third pixel area is a third reflective electrode, the reflective electrode in the fourth pixel area is a fourth reflective electrode, and the transmissive electrode in the third pixel area is a second transmissive electrode; and the orthographic projection of the second transmissive electrode on the supporting surface of the first substrate overlaps with the orthographic projections of the third reflective electrode and the fourth reflective electrode on the supporting surface of the first substrate.

[0011] Optionally, in the first direction, a spacing between the reflection areas of two adjacent pixel areas is greater than or equal to 6 μm; in the second direction, a spacing between the reflection areas of two adjacent pixel areas is greater than or equal to 6 μm.

[0012] Optionally, the driving circuit layer further includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits correspond one-to-one to the plurality of pixel areas; the plurality of pixel driving circuits are respectively located in the reflection areas of the corresponding pixel areas.

[0013] Optionally, the array substrate further includes a passivation layer, which is located between the driving circuit layer and the transmissive electrode layer; the passivation layer has a plurality of via holes, each of the pixel driving circuits is electrically connected to the corresponding transmissive electrode through at least one of the via holes, and the via holes are located in the reflective area of ​​the corresponding pixel area.

[0014] Optionally, the array substrate further includes a planarization layer, and the planarization layer is located between the reflective electrode layer and the transmissive electrode layer.

[0015] Optionally, the planarization layer includes a plurality of isolation blocks, the plurality of isolation blocks correspond one-to-one to the plurality of pixel regions, and the isolation blocks are respectively located in the corresponding pixel regions; in the same pixel region, the reflective electrode is located on the top surface of the isolation block and at least one side wall of a plurality of side walls, and the side of the reflective electrode located on the side wall away from the top surface of the isolation block is connected to the transmissive electrode.

[0016] Optionally, an orthographic projection of the data line on the bearing surface of the first base substrate at least partially overlaps with an orthographic projection of the reflective electrode on the bearing surface of the first base substrate.

[0017] Optionally, the reflective electrode layer is made of silver or aluminum.

[0018] On the other hand, an embodiment of the present disclosure provides an array substrate, the array substrate comprising a first base substrate and a driving circuit layer, a transmission electrode layer and a reflection electrode layer sequentially stacked on the first base substrate, the driving circuit layer comprising a plurality of gate lines and a plurality of data lines, the plurality of gate lines extending along a first direction, the plurality of data lines extending along a second direction, the plurality of gate lines intersecting with the plurality of data lines and defining a plurality of pixel regions; the reflection electrode layer comprising a plurality of reflection electrodes arranged in an array, each of the reflection electrodes being located in a corresponding pixel region; the transmission electrode layer comprising a plurality of transmission electrodes arranged in an array, each of the transmission electrodes being located in a corresponding pixel region; a first reflection electrode among the plurality of reflection electrodes and a first transmission electrode among the plurality of transmission electrodes are insulated from each other, and an orthographic projection of the first reflection electrode on the first base substrate overlaps with a portion of an orthographic projection of the first transmission electrode on the first base substrate, the first reflection electrode is located in a first pixel region, the first transmission electrode is located in a second pixel region, and the first pixel region and the second pixel region are two pixel regions adjacent in the first direction or the second direction.

[0019] In another aspect, a method for manufacturing an array substrate is provided, the method comprising:

[0020] A first substrate is provided; a driving circuit layer, a transmission electrode layer and a reflection electrode layer are sequentially stacked on one side of the first substrate; wherein the driving circuit layer comprises a plurality of gate lines and a plurality of data lines, the plurality of gate lines extend along a first direction, the plurality of data lines extend along a second direction, the plurality of gate lines intersect with the plurality of data lines and define a plurality of pixel regions; each of the pixel regions comprises a transmission region and a reflection region, in at least one of the pixel regions, the transmission region comprises a first region and a second region connected, the first region is located between two adjacent reflection regions in the first direction and the length direction of the first region is consistent with the second direction, the second region is located between two adjacent reflection regions in the second direction and the length direction of the second region is consistent with the first direction; the reflection electrode layer comprises a plurality of reflection electrodes, the plurality of reflection electrodes correspond to the plurality of reflection regions one by one and cover the corresponding reflection regions respectively, the transmission electrode layer comprises a plurality of transmission electrodes, the plurality of transmission electrodes correspond to the plurality of transmission regions one by one, and each of the transmission electrodes at least covers the corresponding transmission region.

[0021] On the other hand, a display panel is provided, comprising a first substrate and a second substrate arranged opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate, wherein the first substrate is any one of the aforementioned array substrates.

[0022] Optionally, the second substrate includes a transparent substrate; or, the second substrate includes a second base substrate and a shading layer and a color filter layer stacked on the second base substrate, the color filter layer includes a plurality of color resist blocks arranged in an array along the first direction and the second direction, the plurality of color resist blocks correspond one-to-one to the plurality of pixel areas, two adjacent color resist blocks in the second direction have the same color, and two adjacent color resist blocks in the first direction have different colors, the shading layer includes a plurality of shading strips, the plurality of shading strips are located between the plurality of color resist blocks, and the plurality of shading strips are arranged in parallel and spaced apart and extend along the second direction.

[0023] On the other hand, a display device is provided, comprising any one of the aforementioned display panels and a backlight module, wherein the backlight module is used to provide a light source for the display panel.

[0024] The beneficial effects brought by the technical solution provided by the present disclosure include at least: the distance between two adjacent reflective areas needs to be greater than or equal to the limit distance to avoid the problem of overlapping short circuits between two adjacent reflective electrodes due to being too close. By providing a transmission area between two adjacent reflective areas in the first direction and the second direction, the area between two adjacent reflective electrodes in the first direction and the second direction can be fully utilized, and the aperture ratio of the display panel can be improved under the premise that the ratio of the area of ​​the transmission area to the reflective area is the same as that of the related art.

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] FIG1 is a schematic diagram of a cross-sectional structure of a display panel in the related art;

[0027] FIG. 2 is a schematic diagram of a top view of a display panel in the related art;

[0028] FIG3 is a schematic diagram of a cross-sectional structure of a display panel in the related art;

[0029] FIG4 is a schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0030] FIG5 is a schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure;

[0031] FIG6 is a schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0032] 7 is a schematic diagram of projections of a transmissive electrode and a reflective electrode in a pixel region on a supporting surface of a first base substrate provided by an embodiment of the present disclosure;

[0033] FIG8 is a schematic flow chart of a method for manufacturing an array substrate provided in an embodiment of the present disclosure;

[0034] FIG9 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present disclosure;

[0035] FIG10 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0036] FIG. 11 is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present disclosure.

[0037] Legend: x, first direction y, second direction m, transmission area n, reflection area m1, first area m2 of the transmission area, second area 1 of the transmission area, array substrate / first substrate 11, first base substrate 12, driving circuit layer 120, pixel driving circuit 121, gate line 122, data line 123, gate layer 124, gate insulating layer 125, active layer 126, source and drain layer 13, transmission electrode layer 130, transmission electrode 14, reflection electrode layer 140, reflection electrode 15, passivation layer 150, via 16, planarization layer 160, isolation block 2, second substrate 21, second base substrate 22, light shielding layer 221, light shielding strip 23, color filter layer 3, liquid crystal layer

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0039] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate quantitative restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. The directional terms mentioned in the present disclosure, such as "top", "bottom", "up", "down", "left" or "right", etc., are only referenced to the directions of the drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present disclosure, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present disclosure.

[0040] FIG1 is a schematic diagram of a cross-sectional structure of a display panel in the related art. As shown in FIG1, in the related art, the display panel includes a first substrate 1x, a second substrate 2x and a liquid crystal layer 3x located between the first substrate 1x and the second substrate 2x. The first substrate 1x includes a first base substrate 11x and a driving circuit layer 12x, a transmission electrode layer 13x and a reflection electrode layer 14x sequentially stacked on the first base substrate 11x.

[0041] FIG. 2 is a schematic diagram of a top view of the display panel in FIG. 1 , and FIG. 1 is a cross-sectional view of FIG. 2 along line AA. As shown in FIG. 2 , the driving circuit layer 12x includes a plurality of gate lines 121x and a plurality of data lines 122x, wherein the plurality of gate lines 121x extend along a first direction x, and the plurality of data lines 122x extend along a second direction y. The plurality of gate lines 121x intersect with the plurality of data lines 122x and define a plurality of pixel regions p. The plurality of pixel regions p correspond to one pixel. Each pixel region p includes a transmission region m and a reflection region n.

[0042] FIG3 is a cross-sectional view of FIG2 along the BB cross-sectional line. In combination with FIG1, FIG2 and FIG3, the reflective electrode layer 14x includes a plurality of reflective electrodes 140x, and the plurality of reflective electrodes 140x correspond to the plurality of reflective regions n one by one, and each of the reflective electrodes 140x covers the corresponding reflective region n. In combination with FIG1 and FIG2, the transmissive electrode layer 13x includes a plurality of transmissive electrodes 130x, and the plurality of transmissive electrodes 130x correspond to the plurality of transmissive regions m one by one, and each of the transmissive electrodes 130x covers the corresponding transmissive region m. In one pixel region, the transmissive region m is located on one side of the reflective region n in the second direction y.

[0043] The spacing between two adjacent reflective electrodes 140x shall not be less than the limiting distance, otherwise the reflective electrode 140x may grow in the air, resulting in a short circuit between the two adjacent reflective electrodes 140x. In the related art, in the first direction x and the second direction y, the distance between two adjacent reflective regions is greater than or equal to the limiting distance, so as to avoid the problem that two adjacent reflective electrodes 140x grow in the air due to being too close to each other until a short circuit occurs. In the related art, for a design in which the transmission region m in a pixel region p is located on one side of the reflection region n in the second direction y, the area between the two adjacent reflection regions n in the second direction y is utilized; however, in the first direction x, there is no transmission region m between the two adjacent reflection regions n, that is, the area between the two adjacent reflection regions n is not fully utilized, and the aperture ratio is therefore limited.

[0044] For a semi-transmissive and semi-reflective liquid crystal display panel, in the transmissive display mode, that is, when a backlight source is used for supplementary display, in order to prevent the backlight source from leaking through the gap between two adjacent pixel areas, a light shielding layer needs to be provided in the second substrate 2x to block light.

[0045] As shown in Figures 1 to 3, the second substrate 2x includes a second base substrate 21x and a light shielding layer 22x and a color filter layer 23x sequentially stacked on the second base substrate 21x, the color filter layer 23x includes a plurality of color blocks distributed in an array, and the light shielding layer 22x includes a black matrix structure and the black matrix structure is located between two adjacent color blocks. In the first direction x, the width of the black matrix is ​​determined by the limiting distance and the process fluctuation control capability. In the first direction x, the width of the black matrix is ​​at least equal to the sum of the limiting distance S3 and the process alignment fluctuation value S2 of the first substrate and the second substrate twice, that is, S3+2*S2. In the second direction y, the width of the black matrix is ​​at least equal to the sum of S1 and the process alignment fluctuation value S2 of the first substrate and the second substrate twice, that is, S1+2*S2, and S1 is the size of the spacing between the two pixel areas determined according to the process alignment requirements. Usually, S1 is smaller than S3.

[0046] It can be seen that in the related art, in the first direction x, the spacing between two adjacent pixel regions is limited by the limiting distance, and the pixel aperture ratio is also limited by the limiting distance. To this end, the embodiment of the present disclosure provides an array substrate that can reduce the spacing between two adjacent pixel regions and increase the pixel aperture ratio.

[0047] Fig. 4 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the present disclosure. As shown in Fig. 4 , the array substrate 1 comprises a first base substrate 11 and a driving circuit layer 12, a transmission electrode layer 13 and a reflection electrode layer 14 sequentially stacked on the first base substrate 11.

[0048] Fig. 5 is a schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, and Fig. 4 is a cross-sectional view along the CC cross-sectional line in Fig. 5. As shown in Fig. 5, the driving circuit layer 12 includes a plurality of gate lines 121 and a plurality of data lines 122, the plurality of gate lines 121 extend along a first direction x, the plurality of data lines 122 extend along a second direction y, and the plurality of gate lines 121 intersect with the plurality of data lines 122 and define a plurality of pixel areas.

[0049] Each pixel region includes a transmission region m and a reflection region n, and the transmission region m in each pixel region includes a first region m1 and a second region m2 connected to each other, and the first region m1 is located between two adjacent reflection regions n in the first direction x, and the length direction of the first region m1 is consistent with the second direction y, and the second region m2 is located between two adjacent reflection regions n in the second direction y, and the length direction of the second region m2 is consistent with the first direction x. The reflective electrode layer 14 includes a plurality of reflective electrodes 140, and the plurality of reflective electrodes 140 correspond to the plurality of reflection regions n one by one, and cover the corresponding reflection regions n respectively, and the transmittance electrode layer 13 includes a plurality of transmittance electrodes 130, and the plurality of transmittance electrodes 130 correspond to the plurality of transmission regions m one by one, and each transmittance electrode 130 at least covers the corresponding transmission region m.

[0050] In the embodiment of the present disclosure, “each reflective electrode 140 covers the corresponding reflective region n” means that the reflective electrode 140 fills up the reflective region n, or in other words, the reflective region n is consistent with the coverage of the reflective electrode 140. “each transmissive electrode 130 at least covers the corresponding transmissive region m” means that the transmissive electrode 130 at least fills up the transmissive region m and may extend beyond the transmissive region m.

[0051] In the embodiment of the present disclosure, there is a part of the transmissive electrode 130 between two adjacent reflective electrodes 140, and the part needs to occupy a certain space. When the size of the space in the arrangement direction of the two reflective electrodes 140 is greater than the limit distance, it is only necessary to consider determining the spacing between the two adjacent pixel areas according to the process alignment requirements, and the size is S1. When the process alignment accuracy is high enough, the distance between the two adjacent pixel areas can be infinitely small in theory. When the size of the space in the arrangement direction of the two reflective electrodes 140 is less than the limit distance, the spacing between the two adjacent pixel areas is limited by the difference between the limit distance and the size of the space in the arrangement direction of the two reflective electrodes 140. A transmissive area m is set between two adjacent reflective areas n in the first direction x and the second direction y, and the area between the two adjacent reflective electrodes 140 in the first direction x and the second direction y that needs to be greater than or equal to the limit distance can be fully utilized. Under the premise that the ratio of the transmissive area to the reflective area is the same as that of the related art, the display panel provided by the embodiment of the present disclosure can have a higher aperture ratio.

[0052] In other possible embodiments, each pixel region includes a transmission region m and a reflection region n, and in at least one pixel region, the transmission region m includes two connected first regions m1 and two second regions m2, and in the first direction x, the two first regions m1 are located between two adjacent reflection regions n and on both sides of the reflection region n of the pixel region, and the length direction of the first region m1 is consistent with the second direction y. In the second direction y, the two second regions m2 are located between two adjacent reflection regions n and on both sides of the reflection region n of the pixel region, and the length direction of the second region m2 is consistent with the first direction x.

[0053] In other possible embodiments, each pixel area includes a transmissive area m and a reflective area n, wherein the transmissive area m of a portion of the pixel areas includes the aforementioned connected first area m1 and second area m2, and the transmissive area m of another portion of the pixel areas includes only the first area m1 or only the second area m2.

[0054] In the embodiment of the present disclosure, there are at least two adjacent pixel areas, the reflective electrode in one pixel area and the transmissive electrode in the other pixel area are insulated from each other, and the orthographic projection of the reflective electrode in one pixel area on the first base substrate 11 partially overlaps with the orthographic projection of the transmissive electrode in the other pixel area on the first base substrate.

[0055] Optionally, the two adjacent pixel regions may be two adjacent pixel regions in the first direction x, or may be two adjacent pixel regions in the second direction y.

[0056] The following takes the reflective electrode 140 in any two adjacent pixel regions and the transmissive electrode 130 between the two reflective electrodes 140 as an example to explain the positional relationship between the reflective electrode 140 and the transmissive electrode 130. As shown in FIG4 and FIG6, whether in the first direction x or the second direction y, the transmissive electrode 130 not only covers the first region m1 or the second region m2 in the corresponding transmissive region m, but also covers part of the two adjacent reflective regions n, so that the gap between the two adjacent pixel regions is filled by the two reflective electrodes and the transmissive electrode without a gap, which can avoid the problem of backlight leakage in the transmissive display mode of the display panel.

[0057] FIG6 is a schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure, and FIG6 is an interface diagram along the DD cross-sectional line in FIG5. As shown in FIG6, the plurality of pixel regions include a first pixel region p1 and a second pixel region p2 adjacent to each other in a first direction x, the reflective electrode 140 in the first pixel region p1 is a first reflective electrode 140a, the reflective electrode 140 in the second pixel region p2 is a second reflective electrode 140b, and the transmissive electrode 130 in the first pixel region p1 is a first transmissive electrode 130a. The orthographic projection of the first transmissive electrode 130a on the bearing surface of the first base substrate 11 and the orthographic projection of the first reflective electrode 140a and the second reflective electrode 140b on the bearing surface of the first base substrate 11 both overlap.

[0058] Optionally, the sub-pixels corresponding to the first pixel region p1 and the second pixel region p2 may belong to one pixel, or may respectively belong to one pixel.

[0059] In the first direction x, the first transmissive electrode 130a not only covers the corresponding transmissive area, but also covers part of the two adjacent reflective areas. Therefore, the first pixel area p1 and the second pixel area p2 adjacent to each other are seamlessly filled with the first reflective electrode 140a, the second reflective electrode 140b and the first transmissive electrode 130a. The spacing between adjacent pixel areas is small, or even 0, which can further improve the pixel aperture ratio.

[0060] Optionally, the width of the overlapping portion of the orthographic projection of the first transmissive electrode 130a on the bearing surface of the first base substrate 11 and the orthographic projection of the first reflective electrode 140a on the bearing surface of the first base substrate 11 is D1. The width of the overlapping portion of the orthographic projection of the first transmissive electrode 130a on the bearing surface of the first base substrate 11 and the orthographic projection of the second reflective electrode 140b on the bearing surface of the first base substrate 11 is D2. The sum of D1, D2 and the alignment process fluctuation is less than the size of a pixel area in the first direction x, so that two adjacent reflective electrodes 140 in the first direction x will not contact each other.

[0061] In the embodiment of the present disclosure, referring to FIG. 4 again, the plurality of pixel regions include a third pixel region and a fourth pixel region adjacent to each other in the second direction y, the reflective electrode 140 in the third pixel region is a third reflective electrode 140c, the reflective electrode 140 in the fourth pixel region is a fourth reflective electrode 140d, and the transmissive electrode 130 in the third pixel region is a second transmissive electrode 130b. The orthographic projection of the second transmissive electrode 130b on the bearing surface of the first base substrate 11 overlaps with the orthographic projections of the third reflective electrode 140c and the fourth reflective electrode 140d on the bearing surface of the first base substrate 11.

[0062] In the second direction y, the second transmissive electrode 130b not only covers the corresponding transmissive area, but also covers part of the two adjacent reflective areas. Therefore, the third pixel area p3 and the fourth pixel area p4 adjacent to each other are seamlessly filled by the third reflective electrode 140c, the fourth reflective electrode 140d and the second transmissive electrode 130b, thereby avoiding the problem of backlight leakage in the display panel.

[0063] Optionally, the width of the overlapping portion of the orthographic projection of the second transmissive electrode 130b on the bearing surface of the first base substrate 11 and the orthographic projection of the third reflective electrode 140c on the bearing surface of the first base substrate 11 is D3. The width of the overlapping portion of the orthographic projection of the second transmissive electrode 130b on the bearing surface of the first base substrate 11 and the orthographic projection of the fourth reflective electrode 140d on the bearing surface of the first base substrate 11 is D4. The sum of D3, D4 and the alignment process fluctuation is less than the size of a pixel area in the second direction y, so that two adjacent reflective electrodes 140 in the second direction y will not contact each other.

[0064] In other possible embodiments, in the first direction x, the first transmission electrode 130a only covers the corresponding transmission area. Therefore, between the adjacent first pixel area and the second pixel area, the orthographic projection of the first transmission electrode 130a on the bearing surface of the first base substrate 11 and the orthographic projection of the first reflective electrode 140a and the second reflective electrode 140b on the bearing surface of the first base substrate 11 are seamlessly connected. In the second direction y, the second transmission electrode 130b only covers the second transmission area. The orthographic projection of the second transmission electrode 130b on the bearing surface of the first base substrate 11 and the orthographic projection of the third reflective electrode 140c and the fourth reflective electrode 140d on the bearing surface of the first base substrate 11 are seamlessly connected.

[0065] Exemplarily, the reflective electrode layer 14 is made of a metal material, such as silver or aluminum. Both silver and aluminum have high reflectivity and are suitable for making the reflective electrode layer 14. Among them, the reflectivity of silver is higher, but the reflective electrode made of silver will react with sulfur, sulfide, oxygen, etc. in the air to form silver sulfide or silver oxide particles, and the silver sulfide or silver oxide particles will gradually increase. If the distance between two adjacent reflective electrodes made of silver is too close, the silver sulfide or silver oxide particles generated by the reflective electrode made of silver will gradually increase to cover the adjacent reflective electrodes, resulting in the problem of overlapping short circuits. Therefore, the embodiments of the present disclosure are particularly suitable for reflective electrode layers made of silver.

[0066] Exemplarily, in the first direction x, the spacing between the reflection areas n of two adjacent pixel areas is greater than or equal to 6μm. In the second direction y, the spacing between the reflection areas n of two adjacent pixel areas is greater than or equal to 6μm. The spacing between two adjacent silver reflection electrodes 140 needs to be greater than or equal to 6μm, otherwise they may grow in the air to cause overlapping short circuit problems, so the spacing between two adjacent reflection areas n needs to be greater than or equal to 6μm. Optionally, the spacing between the reflection areas n of two adjacent pixel areas in the first direction x is smaller than the size of the pixel area in the first direction x; the spacing between the reflection areas n of two adjacent pixel areas in the second direction y is smaller than the size of the pixel area in the second direction y. The specific size needs to be determined according to the transmission area required by the product.

[0067] Exemplarily, as shown in FIG. 4 and FIG. 5 , the driving circuit layer 12 further includes a plurality of pixel driving circuits 120, and the plurality of pixel driving circuits 120 correspond to the plurality of pixel regions one by one. That is, a pixel driving circuit 120 is provided in each pixel region. Each pixel driving circuit 120 is located in the reflection region n of the corresponding pixel region. The plurality of pixel driving circuits 120 are respectively located in the reflection region n of the corresponding pixel region, that is, located under the corresponding reflection electrode 140, and are shielded by the reflection electrode 140, so that no other structure needs to be arranged to shield the pixel driving circuit 120, which is conducive to improving the aperture ratio.

[0068] 5 and 6, the orthographic projection of the data line 122 on the bearing surface of the first base substrate 11 at least partially overlaps with the orthographic projection of the reflective electrode 140 on the bearing surface of the first base substrate 11. Since the reflective electrode 140 can shield the data line 122 below, arranging the data line 122 below the reflective electrode 140 is conducive to improving the aperture ratio.

[0069] Exemplarily, as shown in FIG4 , the array substrate 1 further includes a passivation layer 15, and the passivation layer 15 is located between the driving circuit layer 12 and the transmissive electrode layer 13. The passivation layer 15 has a plurality of via holes 150, and each pixel driving circuit 120 is electrically connected to the corresponding transmissive electrode 130 through at least one via hole 150, and the via hole 150 is located in the reflective region of the corresponding pixel region.

[0070] In order to connect the transmissive electrode 130 with the driving circuit layer 12 , a via hole connecting the transmissive electrode 130 and the driving circuit layer 12 needs to be formed in the film layer between the transmissive electrode layer 130 and the first base substrate 11 .

[0071] In the related art, in combination with FIG. 1 , it can be seen that in the reflective region n, the reflective electrode layer 14x is electrically connected to the drive circuit layer 12x through the vias in the passivation layer 15x and other film layers. Since the film layer between the reflective electrode layer 14x and the drive circuit layer 12x is relatively thick, the vias will cause the reflective plane of the reflective region n closest to the light-emitting side to be uneven, resulting in a decrease in the effective reflectivity of the reflective region n. In the embodiment of the present disclosure, the transmissive electrode layer 13 is connected to the source-drain electrode layer 126 of the drive circuit layer 12 through the vias 150 on the passivation layer 15. Since the passivation layer 15 in the embodiment of the present disclosure is thinner than the passivation layer 15x and other film layers in the related art, the depression at the vias 150 on the passivation layer 15 is relatively shallow. Therefore, in the embodiment of the present disclosure, the vias 150 have little effect on the flatness of the reflective electrode 140, thereby improving the effective reflectivity of the reflective region n.

[0072] Optionally, the embodiment of the present disclosure does not limit the shape of the via hole 150 , which may be cylindrical, truncated cone, prism-shaped, or prism-shaped.

[0073] Exemplarily, as shown in FIG4 , the array substrate further includes a planarization layer 16, and the planarization layer 16 is located between the reflective electrode layer 14 and the transmissive electrode layer 13. By providing a thicker planarization layer 16, the mutual influence of the potential between the reflective electrode 140 in one pixel area and the transmissive electrode 130 in another pixel area in two adjacent pixel areas can be reduced. The thickness of the liquid crystal layer in the transmissive area m can also be adjusted by removing the planarization layer 16 in the transmissive area m, and the optimal cell thickness design of the transmissive area can be achieved by combining the method of adjusting the refractive index of the liquid crystal. Optionally, the liquid crystal cell thickness of the transmissive area m is about twice the liquid crystal cell thickness of the reflective area n.

[0074] Exemplarily, as shown in FIG4 , the planarization layer 16 includes a plurality of isolation blocks 160, and the plurality of isolation blocks 160 correspond to the plurality of pixel regions one by one, and the isolation blocks 160 are respectively located in the corresponding pixel regions. In the same pixel region, the reflective electrode 140 is located on the top surface of the isolation block 160 and at least one of the plurality of side walls, and the side of the reflective electrode 140 located on the side wall away from the top surface of the isolation block 160 is connected to the transmissive electrode 130. The reflective electrode 140 is connected to the transmissive electrode 130, so the reflective electrode 140 can be electrically connected to the underlying driving circuit layer 12 through the transmissive electrode 130. This arrangement can avoid making a via hole in the reflective region n for connecting the reflective layer 14 and the driving circuit layer 12, which affects the reflection effect of the reflective electrode 140. Optionally, a portion of the reflective electrode 140 extends to the side of the transmissive electrode 130 away from the first substrate 11.

[0075] Exemplarily, the connection line between the reflective electrode 140 and the transmissive electrode 130 is the boundary line between the reflective area and the transmissive area in the pixel area. As shown in FIGS. 4 and 5, the reflective electrode 140 and the transmissive electrode 130 in the cross-sectional view of FIG. 4 have an intersection, and the intersection is extended in the first direction x to be the actual connection line between the reflective electrode 140 and the part of the transmissive electrode 130 adjacent in the first direction, and the connection line is the boundary line between the second area m2 of the transmissive area and the reflective area n in FIG. 5. As shown in FIGS. 5 and 6, the reflective electrode 140 and the transmissive electrode 130 in the cross-sectional view of FIG. 6 have an intersection, and the intersection is extended in the second direction y to be the actual connection line between the reflective electrode 140 and the part of the transmissive electrode 130 adjacent in the second direction, and the connection line is the boundary line between the first area m1 of the transmissive area and the reflective area n in FIG.

[0076] Optionally, as shown in Fig. 5, in one pixel region, the transmission region m is L-shaped and the reflection region n is rectangular. In other possible embodiments, the transmission region m may also be a "mouth"-shaped ring that fully surrounds the reflection region n; or a semi-enclosed ring with a single-side opening.

[0077] FIG. 7 is a schematic diagram of projections of a transmissive electrode and a reflective electrode in a pixel region on a supporting surface of a first substrate provided by an embodiment of the present disclosure, as shown in FIG. 7 :

[0078] Optionally, as shown in FIG. 7a, in a pixel region, the reflection region n is rectangular, and the orthographic projection of the reflection electrode 140 on the bearing surface of the first substrate 11 is rectangular; the transmission region m is L-shaped, and the shape of the orthographic projection of the transmission electrode 130 on the bearing surface of the first substrate 11 is based on the L-shape and extends from one side of the L-shape towards the reflection region n. The transmission electrode 130 corresponding to the additional projection is used to connect to the driving circuit layer 12. The actual reflection electrode 140 may be a planar structure located on the top surface of the isolation block 160, and a structure that is connected to two side edges of the planar structure and extends towards the transmission electrode 130 in the transmission region n, that is, the reflection electrode 140 is located on the top surface and two side walls of the isolation block 160. Alternatively, the actual reflection electrode 140 may be a planar structure located on the top surface of the isolation block 160, and a structure that is connected to one of the two side edges of the planar structure close to the transmission region n and extends towards the transmission electrode 130 in the transmission region n, that is, the reflection electrode 140 is located on the top surface and one side wall of the isolation block 160.

[0079] Optionally, as shown in FIG. 7b, the transmission region m is in a square-ring shape with an opening, in a pixel region, the reflection region n is rectangular, and the orthographic projection of the reflection electrode 140 on the bearing surface of the first substrate 11 is rectangular; the shape of the orthographic projection of the transmission electrode 130 on the bearing surface of the first substrate 11 can be extended from any side of the square-ring shape towards the reflection region n. The transmission electrode 130 corresponding to this part of the projection is used to connect to the driving circuit layer 12. The actual reflection electrode 140 may be a planar structure located on the top surface of the isolation block 160, and a structure that is connected to at least some of the multiple side edges of the planar structure and extends towards the transmission electrode 130 in the transmission region n, that is, the reflection electrode 140 is located on the top surface and at least one side wall of the isolation block 160.

[0080] Optionally, as shown in FIG. 7c, the transmission region m is in a semi-surrounding ring shape with one side open, in a pixel region, the reflection region n is rectangular, and the orthographic projection of the reflection electrode 140 on the bearing surface of the first substrate 11 is rectangular; the shape of the orthographic projection of the transmission electrode 130 on the bearing surface of the first substrate 11 can be extended from a part of the semi-surrounding ring shape towards the reflection region n. The transmission electrode 130 corresponding to this part of the projection is used to connect to the driving circuit layer 12. The actual reflection electrode 140 may be a planar structure located on the top surface of the isolation block 160, and a structure that is connected to at least some of the multiple side edges of the planar structure and extends towards the transmission electrode 130 in the transmission region n, that is, the reflection electrode 140 is located on the top surface and at least one side wall of the isolation block 160.

[0081] In the embodiments shown in FIG. 7a , FIG. 7b and FIG. 7c , since the transmissive electrode 130 and the reflective electrode 140 in FIG. 7a have fewer intersections, the light effect in the embodiment of FIG. 7a is less affected by the step difference at the intersection between the transmissive electrode 130 and the reflective electrode 140 , and the display effect of the embodiment shown in FIG. 7a is better in comparison.

[0082] In a possible implementation, as shown in FIG4 , the driving circuit layer 12 includes a gate layer 123, a gate insulating layer 124, an active layer 125, and a source-drain electrode layer 126 stacked in sequence on the first base substrate 11. In a pixel region, a pixel driving circuit 120 includes at least one TFT (Thin Film Transistor), and each TFT includes a gate in the gate layer 123, and a source and a drain in the source-drain electrode layer 126.

[0083] In other possible implementations, the driving circuit layer includes an active layer, a gate insulating layer, a gate layer, an insulating layer, and a source-drain electrode layer stacked in sequence on the supporting surface of the first base substrate.

[0084] Exemplarily, the gate layer 123 is made of a metal material, such as one or more of molybdenum, copper, and aluminum.

[0085] Exemplarily, the gate insulating layer 124 and the insulating layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0086] Exemplarily, the active layer 125 is made of low-temperature polysilicon material or metal oxide semiconductor materials such as IGZO (Indium Gallium Zinc Oxide).

[0087] Exemplarily, the source-drain electrode layer 126 may be a single-layer metal film such as aluminum, molybdenum, copper, or titanium, or a multi-layer metal film such as a molybdenum layer, an aluminum layer, and a molybdenum layer stacked in sequence, or a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.

[0088] Exemplarily, the passivation layer 15 may be made of a silicon oxide layer, a silicon nitride layer or a silicon oxide layer.

[0089] Exemplarily, the planarization layer 16 is made of an organic insulating material, such as resin.

[0090] FIG8 is a schematic flow chart of a method for manufacturing an array substrate provided in an embodiment of the present disclosure. As shown in FIG8 , the method includes:

[0091] In step S1, a first substrate is provided.

[0092] In step S2, a driving circuit layer, a transmission electrode layer and a reflection electrode layer are sequentially stacked on a first base substrate.

[0093] The driving circuit layer includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines extend along a first direction, the plurality of data lines extend along a second direction, the plurality of gate lines intersect with the plurality of data lines and define a plurality of pixel areas; each pixel area includes a transmission area and a reflection area, in at least one pixel area, the transmission area includes a first area and a second area connected, the first area is located between two adjacent reflection areas in the first direction and the length direction of the first area is consistent with the second direction, and the second area is located between two adjacent reflection areas in the second direction and the length direction of the second area is consistent with the first direction; the reflective electrode layer includes a plurality of reflective electrodes, the plurality of reflective electrodes correspond to the plurality of reflection areas one by one and cover the corresponding reflection areas respectively, the transmittance electrode layer includes a plurality of transmittance electrodes, the plurality of transmittance electrodes correspond to the plurality of transmittance areas one by one, and each transmittance electrode at least covers the corresponding transmittance area.

[0094] Exemplarily, step S2 may include:

[0095] In the first step, an initial gate layer is formed on the first substrate by, for example, deposition, and a photoresist structure is obtained on the initial gate layer by processes such as photoresist coating, exposure, and development, and the initial gate layer is etched using the photoresist structure as a mask to form a gate layer.

[0096] The second step is to form a gate insulating layer on the gate layer by, for example, deposition. The active layer is formed on the gate insulating layer. For example, an initial active layer may be first deposited on the gate insulating layer, a photoresist structure may be obtained by processes such as photoresist coating, exposure, and development, and the initial active layer may be etched using the photoresist structure as a mask to form the active layer.

[0097] In the third step, a source-drain layer is formed on the active layer by adopting a series of processes such as deposition, photoresist coating, exposure, etching, and stripping.

[0098] Step 4: Form an initial passivation layer on the second source and drain electrode pattern layer by, for example, deposition. Through a series of processes such as photoresist coating, exposure, etching, and stripping, a plurality of vias exposing the source and drain electrode layers are formed to form a passivation layer. Form an initial transmission electrode layer on the passivation layer by, for example, deposition. A photoresist structure is obtained on the initial transmission electrode layer by processes such as photoresist coating, exposure, and development, and the initial transmission electrode layer is etched using the photoresist structure as a mask to form a transmission electrode layer, which is electrically connected to the source and drain electrode layer through the vias on the passivation layer.

[0099] Step 5: Form an initial planarization layer on the transmissive electrode layer by, for example, deposition. Form the planarization layer by a series of processes such as photoresist coating, exposure, etching, and stripping. Form an initial reflective electrode layer on the planarization layer by, for example, deposition. A photoresist structure is obtained on the initial reflective electrode layer by processes such as photoresist coating, exposure, and development, and the initial reflective electrode layer is etched using the photoresist structure as a mask to form a reflective electrode layer.

[0100] The materials of each layer refer to the above embodiments and will not be described in detail here.

[0101] FIG9 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure. As shown in FIG8 , the display panel includes a first substrate 1 and a second substrate 2 arranged opposite to each other, and a liquid crystal layer 3 located between the first substrate 1 and the second substrate 2, wherein the first substrate 1 is the aforementioned array substrate 1. The display panel has the same effect as the aforementioned array substrate 1, which will not be described in detail here.

[0102] FIG10 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure, and FIG11 is another schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure. As shown in FIG9 and FIG11, the second substrate 2 includes a second base substrate 21 and a light shielding layer 22 and a color filter layer 23 stacked on the second base substrate 21, and the color filter layer 23 includes a plurality of color blocks arranged in an array along a first direction x and a second direction y, and the plurality of color blocks correspond to a plurality of pixel areas one by one, and a color block is correspondingly arranged in each pixel area. The colors of two adjacent color blocks in the second direction y are the same. For example, as shown in FIG9, the plurality of color group blocks arranged along the second direction y can be an integrated structure. As shown in FIG11, the colors of two adjacent color blocks in the first direction x are different.

[0103] In conjunction with FIG. 10 and FIG. 11 , the light shielding layer 22 includes a plurality of light shielding strips 221, the plurality of light shielding strips 221 are located between the plurality of color-resistance blocks, and the plurality of light shielding strips 221 are arranged in parallel and spaced apart and extend along the second direction y. As described above, since the orthographic projection of the data line 122 on the first base substrate partially overlaps with the orthographic projection of the reflective electrode 140 on the first base substrate, and the data line 122 is located between the first base substrate and the reflective electrode 140, the data line 122 can be shielded by the reflective electrode 140 without the need to use the light shielding strips 221 to shield the data line 122. The light shielding strips 221 and the data line 122 are arranged in parallel in the second direction y.

[0104] For color display panels, since the colors corresponding to two adjacent pixel areas are the same in the second direction y, there is no risk of cross-color, so it is not necessary to set a shading strip extending along the first direction x, and only set a shading strip extending along the second direction y, and the width of the shading strip only needs to consider the process alignment deviation, and is not limited by the limiting distance, thereby improving the aperture ratio. Here, the process alignment deviation refers to the dimensional deviation between the first substrate 1 and the second substrate 2 in the direction parallel to the first direction x and the second direction y when they are relatively connected. Optionally, the process alignment deviation is 2μm.

[0105] Optionally, a dimension of the light shielding strip 221 in the first direction x is greater than or equal to 4 μm.

[0106] Optionally, a size of the light shielding strip 221 in the first direction x is smaller than a size of the pixel area in the first direction x.

[0107] Table 1 The improvement ratio of the aperture ratio of different PPI products in the embodiment of the present disclosure

[0108] Table 1 shows the improvement ratio of the aperture ratio of products with different PPI (Pixels Per Inch, pixel density unit) in the embodiment of the present disclosure. As can be seen from Table 1, compared with the related art, the aperture ratio of products with PPI of 150, 200, 250 and 300 in the embodiment of the present disclosure has been improved by 17.2%, 24.5%, 32.9% and 43.1% respectively. And the effect of improving the aperture ratio of high PPI products is more obvious.

[0109] Exemplarily, the display panel can adopt a normally white mode, that is, when a voltage is applied, the liquid crystal is opaque and in a dark state, and when no voltage is applied, the liquid crystal is translucent and in a bright state. Because in the normally white mode, the liquid crystal state in the dark state is controlled by the electric field, and the orientation of the liquid crystal molecules is uniformly controlled by the electric field at the step difference position where the transmission electrode and the reflection electrode overlap, a better contrast can be achieved. In contrast, in the normally black mode, that is, when a voltage is applied, the liquid crystal is translucent and in a bright state, and when no voltage is applied, the liquid crystal is opaque and in a dark state. The brightness of the dark state depends on the initial alignment of the liquid crystal molecules. The alignment is uneven at the step difference position where the transmission electrode and the reflection electrode overlap, resulting in a certain amount of black state light leakage. The normally black mode is common in vertical alignment (VA) or electronically controlled birefringence (ECB) display panels, wherein the polarizer of the former is usually a polarizing layer, a 1 / 2 wave plate and a 1 / 4 wave plate, and the polarizer of the latter is usually a polarizing layer and a 1 / 2 wave plate. The normally white mode is common in twisted nematic (TN) or electrically controlled birefringence display panels, and the polarizers of the two types are usually a polarizing layer, a 1 / 2 wave plate and a 1 / 4 wave plate.

[0110] In another possible implementation, if the display panel is a monochrome display (e.g., black and white display), the second substrate 2 may only include a transparent substrate. Since there is no risk of cross-color in the first direction x and the second direction y, there is no need to set a light shielding structure, and the aperture ratio of the monochrome display panel can be close to 100%.

[0111] An embodiment of the present disclosure provides a display device, which includes any one of the above-mentioned display panels and a backlight module, wherein the backlight module is used to provide a light source for the display panel.

[0112] For example, the display device provided in the embodiments of the present disclosure is any product or component with a display function, such as an outdoor electronic billboard, an outdoor charging pile, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Since the display device has the advantages of high reliability, good outdoor image quality, and low power consumption, it is particularly widely used in outdoor electronic billboards, outdoor charging piles, and other scenes.

[0113] The display device has the same effect as the above-mentioned display panel, which will not be described in detail here.

[0114] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

An array substrate, characterized in that: The array substrate (1) comprises a first base substrate (11) and a driving circuit layer (12), a transmission electrode layer (13) and a reflection electrode layer (14) sequentially stacked on the first base substrate (11); the driving circuit layer (12) comprises a plurality of gate lines (121) and a plurality of data lines (122); the plurality of gate lines (121) extend along a first direction; the plurality of data lines (122) extend along a second direction; the plurality of gate lines (121) intersect with the plurality of data lines (122) and define a plurality of pixel regions; each of the pixel regions comprises a transmission area and a reflection area; in at least one of the pixel regions, the transmission area comprises at least one first area and at least one second area connected to each other; In the first direction, the first region is located between two adjacent reflection regions, and the length direction of the first region is consistent with the second direction; in the second direction, the second region is located between two adjacent reflection regions, and the length direction of the second region is consistent with the first direction; the reflection electrode layer (14) comprises a plurality of reflection electrodes (140), the plurality of reflection electrodes (140) correspond one-to-one to the plurality of reflection regions, and respectively cover the corresponding reflection regions; the transmission electrode layer (13) comprises a plurality of transmission electrodes (130), the plurality of transmission electrodes (130) correspond one-to-one to the plurality of transmission regions, and each transmission electrode (130) at least covers the corresponding transmission region. The array substrate according to claim 1, characterized in that In at least one of the pixel regions, the transmission area includes a first region and a second region. The array substrate according to claim 1, characterized in that The multiple pixel areas include a first pixel area and a second pixel area adjacent to each other in the first direction; the reflective electrode (140) in the first pixel area is a first reflective electrode, the reflective electrode (140) in the second pixel area is a second reflective electrode, and the transmissive electrode (130) in the first pixel area is a first transmissive electrode; and the orthographic projection of the first transmissive electrode on the bearing surface of the first substrate (11) and the orthographic projections of the first reflective electrode and the second reflective electrode on the bearing surface of the first substrate (11) both overlap. The array substrate according to claim 1, characterized in that The plurality of pixel regions include a third pixel region and a fourth pixel region adjacent to each other in the second direction; the reflective electrode (140) in the third pixel region is a third reflective electrode; the reflective electrode (140) in the fourth pixel region is a fourth reflective electrode; and the transmissive electrode (130) in the third pixel region is a second transmissive electrode; and the orthographic projection of the second transmissive electrode on the bearing surface of the first substrate (11) overlaps with the orthographic projections of the third reflective electrode and the fourth reflective electrode on the bearing surface of the first substrate (11). The array substrate according to claim 1, characterized in that In the first direction, a distance between the reflection areas of two adjacent pixel regions is greater than or equal to 6 μm; in the second direction, a distance between the reflection areas of two adjacent pixel regions is greater than or equal to 6 μm. The array substrate according to any one of claims 1 to 5, characterized in that: The driving circuit layer (12) further comprises a plurality of pixel driving circuits (120), wherein the plurality of pixel driving circuits (120) correspond one-to-one to the plurality of pixel areas; the plurality of pixel driving circuits (120) are respectively located in the reflection areas of the corresponding pixel areas. The array substrate according to claim 6, characterized in that The array substrate (1) further comprises a passivation layer (15), wherein the passivation layer (15) is located between the drive circuit layer and the transmission electrode layer (13); the passivation layer (15) has a plurality of via holes (150), each of the pixel drive circuits (120) is electrically connected to the corresponding transmission electrode (130) via at least one of the via holes (150), and the via holes (150) are located in the reflection area of ​​the corresponding pixel area. The array substrate according to claim 7, characterized in that: The array substrate (1) further comprises a planarization layer (16), wherein the planarization layer (16) is located between the reflective electrode layer (14) and the transmissive electrode layer (13). The array substrate according to claim 8, characterized in that The planarization layer (16) comprises a plurality of isolation blocks (160), the plurality of isolation blocks (160) correspond one-to-one to the plurality of pixel regions, and the isolation blocks (160) are respectively located in the corresponding pixel regions; In the same pixel area, the reflective electrode (140) is located on the top surface of the isolation block (160) and at least one of the plurality of side walls, and the side of the reflective electrode (140) located on the side wall away from the top surface of the isolation block (160) is connected to the transmissive electrode (130). The array substrate according to any one of claims 1 to 5 and claims 7 to 9, characterized in that: The orthographic projection of the data line (122) on the bearing surface of the first base substrate (11) at least partially overlaps with the orthographic projection of the reflective electrode (140) on the bearing surface of the first base substrate (11). The array substrate according to any one of claims 1 to 5 and claims 7 to 9, characterized in that: The reflective electrode layer (14) is made of silver or aluminum. An array substrate, characterized in that: The array substrate comprises a first base substrate (11) and a driving circuit layer (12), a transmission electrode layer (13) and a reflection electrode layer (14) sequentially stacked on the first base substrate (11); the driving circuit layer comprises a plurality of gate lines (121) and a plurality of data lines (122); the plurality of gate lines (121) extend along a first direction; the plurality of data lines (122) extend along a second direction; the plurality of gate lines (121) intersect with the plurality of data lines (122) and define a plurality of pixel regions; the reflection electrode layer (14) comprises a plurality of reflection electrodes (140) arranged in an array; each reflection electrode (140) is located in a corresponding pixel region; the transmission electrode layer (14) comprises a plurality of reflection electrodes (140) arranged in an array; each reflection electrode (140) is located in a corresponding pixel region; The polar layer (13) comprises a plurality of transmission electrodes (130) arranged in an array, each of the transmission electrodes (130) being located in a corresponding pixel area; a first reflection electrode among the plurality of reflection electrodes (140) and a first transmission electrode among the plurality of transmission electrodes (130) are insulated from each other, and an orthographic projection of the first reflection electrode on the first substrate (11) partially overlaps with an orthographic projection of the first transmission electrode on the first substrate (11); the first reflection electrode is located in a first pixel area, and the first transmission electrode is located in a second pixel area; the first pixel area and the second pixel area are two adjacent pixel areas in the first direction or the second direction. A method for manufacturing an array substrate, characterized in that: The method comprises: providing a first substrate; sequentially stacking a driving circuit layer, a transmission electrode layer and a reflection electrode layer on one side of the first substrate; wherein the driving circuit layer comprises a plurality of gate lines and a plurality of data lines, the plurality of gate lines extend along a first direction, the plurality of data lines extend along a second direction, the plurality of gate lines intersect with the plurality of data lines and define a plurality of pixel regions; each of the pixel regions comprises a transmission region and a reflection region, in at least one of the pixel regions, the transmission region comprises at least one first region and at least one second region connected, the first region is located between two adjacent reflection regions in the first direction and the length direction of the first region is consistent with the second direction, the second region is located between two adjacent reflection regions in the second direction and the length direction of the second region is consistent with the first direction; the reflection electrode layer comprises a plurality of reflection electrodes, the plurality of reflection electrodes correspond to the plurality of reflection regions one by one and cover the corresponding reflection regions respectively, the transmission electrode layer comprises a plurality of transmission electrodes, the plurality of transmission electrodes correspond to the plurality of transmission regions one by one, and each of the transmission electrodes at least covers the corresponding transmission region. A display panel, characterized in that: The display panel comprises a first substrate (1) and a second substrate (2) arranged opposite to each other, and a liquid crystal layer (3) located between the first substrate (1) and the second substrate, wherein the first substrate (1) is an array substrate (1) according to any one of claims 1 to 12. The display panel according to claim 14, characterized in that The second substrate comprises a transparent substrate; or the second substrate (2) comprises a second base substrate (21) and a light shielding layer (22) and a color filter layer (23) stacked on the second base substrate (21); the color filter layer (23) comprises a plurality of color blocks arranged in an array along the first direction and the second direction; the plurality of color blocks correspond to the plurality of pixel areas one by one; two color blocks adjacent to each other in the second direction have the same color; and two color blocks adjacent to each other in the first direction have different colors; the light shielding layer (22) comprises a plurality of light shielding strips (221); the plurality of light shielding strips (221) are located between the plurality of color shielding strips, and the plurality of light shielding strips (221) are arranged in parallel and spaced apart and extend along the second direction. A display device, characterized in that The display device comprises the display panel as claimed in claim 14 or 15 and a backlight module, wherein the backlight module is used to provide a light source for the display panel.

Images