Display device with variable image resolution

Abstract

The subject matter described in this disclosure may be embodied in methods, systems, and program products for operating a display device that includes an array of pixels addressed by a set of data lines and a set of scan lines. A method includes addressing a first data line with first image data; transmitting a first scan signal to the first row of pixels using the first scan line to move the first image data to the first row of pixels; activating the first row of pixels to emit light; after the data line set has been addressed with the first image data, using a second scan line to send a second scan signal to a second row of pixels without addressing the data line set with the image data; and activating the second row of pixels to emit light after the second scan signal has been transmitted.

Description

Technical Field

[0001] This document generally relates to display devices. Background Art

[0002] The electronic device may include a display device on which the visual image is displayed. A high resolution of the visual image presented on the display may provide a more detailed presentation of the content to the user. Summary of the invention

[0003] This document describes techniques, methods, systems, and other mechanisms for providing a display device that can operate in a higher resolution mode and a reduced resolution mode. In some examples, the display device can enter a reduced resolution mode in response to the display device or a computing system including the display device entering a battery saver mode. The computing system can be, for example, a personal computer, a mobile phone, a smart phone, a smart watch, or a smart TV.

[0004] When a computing device experiences low battery power, it may enter a battery conservation mode in which display screen content (e.g., user experience (UX) images) may be simplified, screen content may include non-color images, processing speeds may be reduced, applications may be updated at a reduced frequency, and / or network transmissions may occur less frequently.

[0005] Employing a battery saving mode can reduce the power consumption of the device. However, if the display is presenting content under an always-on display (AOD) driving condition, the power consumption of the display module may remain the same and will not decrease. Therefore, the battery saving is limited. Switching the display to a reduced resolution mode can enable the computing system to remain under an always-on display driving condition while reducing the battery consumption of the display.

[0006] The disclosed technology can be implemented in a display device, such as a display device including an AMOLED display. In some examples, the display device includes a multiplexer for directing image data from a data driver to a data line of a pixel circuit system. In a reduced resolution mode, the multiplexer can operate at a reduced frequency that is only a portion of the operating frequency during a higher resolution mode. For example, the multiplexer can operate at a reduced frequency that is half the operating frequency during a higher resolution mode. In order to reduce the frequency of multiplexer operation, the multiplexer signal can be controlled to switch for a time that is less than the line time of all pixel rows. In some cases, the multiplexer signal can be switched only for odd pixel rows or only for even pixel rows.

[0007] The multiplexer circuit may have parasitic capacitance, including parasitic capacitance resulting from including parallel-connected TFT switches. The multiplexer switch control signal may frequently alternate between a high voltage state and a low voltage state. Therefore, the multiplexer may consume a large amount of power in the display. In some examples, the multiplexer consumes 6.7% of the total drive power consumption in the always-on display. Advantages of the disclosed technology include reducing the power consumption of the display device in the always-on display mode. In some examples, the power consumption in the reduced resolution mode is reduced by 3.4% or more compared to the higher resolution mode.

[0008] As additional description to the embodiments described below, the present disclosure describes the following embodiments.

[0009] Embodiment 1 relates to a method for operating a display device, which includes a pixel array addressed by a data line set and a scan line set, the method including: presenting a first frame of image content by the display device, including presenting by the following operations: addressing the data line set with a first image data for a first part of the first frame of image content; using a first scan line in the scan line set to send a first scan signal to a first row of pixels in a pixel array to move the first image data from the data line set to the first row of pixels; after the first scan signal has been sent to the first row of pixels, activating the first row of pixels to emit light; after the data line set has been addressed with the first image data, using a second scan line in the scan line set to send a second scan signal to a second row of pixels in the pixel array without addressing the data line set with image data; and after the second scan signal has been sent to the second row of pixels, activating the second row of pixels to emit light.

[0010] Embodiment 2 is a method as described in any of the preceding embodiments, wherein: after a first scan signal is sent to a first row of pixels, first image data addressed to a set of data lines is attenuated in intensity to an attenuated version of the first image data; and a second scan signal is sent to a second row of pixels to move the attenuated version of the first image data to the second row of pixels.

[0011] Embodiment 3 is a method as described in any of the preceding embodiments, wherein the first image data includes a set of voltages, each voltage in the set of voltages defining an intensity at which a corresponding pixel in the first row of pixels will emit light.

[0012] Embodiment 4 is a method as described in any of the preceding embodiments, wherein the second row of pixels is the next row of pixels immediately following the first row of pixels in the pixel array.

[0013] Embodiment 5 is a method as described in any of the preceding embodiments, wherein: the first part of the first frame image content is the first row of image content from the first frame image content; and the second part of the first frame image content is the second row of image content from the first frame image content.

[0014] Embodiment 6 is a method as described in any of the preceding embodiments, wherein: addressing a data line set with first image data includes using multiple multiplexers to direct the first image data to the data line set, each of the multiple multiplexers being configured to direct the image data to a corresponding subset of data lines within the data line set, such that the data line set includes multiple subsets of data lines corresponding to the multiple multiplexers.

[0015] Embodiment 7 is the method of embodiment 6, wherein the plurality of multiplexers receive the first image data from a display device integrated circuit that is a component of the display device.

[0016] Embodiment 8 is a method as described in any one of Embodiments 6 or 7, wherein sending a second scanning signal to a second row of pixels is performed by the display device after addressing a set of data lines with first image data, without the need for multiple multiplexers to direct the image data to the set of data lines.

[0017] Embodiment 9 is a method as described in Embodiment 6, wherein: the display device includes a display driver integrated circuit; addressing a data line set with a first image data includes the display driver integrated circuit sending a control signal to a plurality of multiplexers to direct the first image data to the data line set; and the display driver integrated circuit does not send a control signal to the plurality of multiplexers to direct the image data to the data line set between sending a first scanning signal and sending a second scanning signal.

[0018] Embodiment 10 is a method as described in Embodiment 9, wherein: the display driver integrated circuit receives second image data, which is for a second portion of the first frame image content and is designated for a second row of pixels; and the second image data is not directed to the data line set by multiple multiplexers at least in part because the display driver integrated circuit does not send a control signal to the multiplexer between the sending of the first scan signal and the sending of the second scan signal to direct the image data to the data line set.

[0019] Embodiment 11 is a method as described in any of the aforementioned embodiments, wherein presenting a first frame of image content includes: addressing a data line set with a third image data for a third portion of the first frame of image content; using a third scan line in the scan line set to send a third scan signal to a third row of pixels in a pixel array to move the third image data from the data line set to the third row of pixels; after the third scan signal has been sent to the third row of pixels, activating the third row of pixels to emit light; after the data line set has been addressed with the third image data, using a fourth scan line in the scan line set to send a fourth scan signal to a fourth row of pixels in the pixel array without addressing the data line set with image data; and after the fourth scan signal has been sent to the fourth row of pixels, activating the fourth row of pixels to emit light.

[0020] Embodiment 12 is a method as described in any of the preceding embodiments, wherein, because the display device operates in a reduced resolution operating mode, the display device sends a second scan signal to a second row of pixels without addressing the data line set with image data.

[0021] Embodiment 13 is a method as described in Embodiment 12, wherein the display device receives a signal indicating that the display device is to switch from a higher resolution operating mode to a reduced resolution operating mode because a battery of the device housing the display device is determined to have a charge level that has dropped below a threshold charge level.

[0022] Embodiment 14 is a method as described in any one of Embodiments 1 to 10, wherein: when the display device is in a reduced resolution operating mode, the display device presents a first frame of image content; the method includes receiving a signal indicating that the display device will switch from the reduced resolution operating mode to a higher resolution operating mode, the higher resolution operating mode being suitable for presenting image content at a higher resolution than when the display device is in the reduced resolution mode; and the method includes presenting a second frame of image content by the display device when the display device is in the higher resolution operating mode, including presenting by the following operations: addressing a set of data lines with a third image data for a first part of the second frame of image content; using a first scan line in the scan line set to send a third scan signal to a first row of pixels to move the third image data from the data line set to the first row of pixels; after the third scan signal has been sent to the first row of pixels, activating the first row of pixels to emit light; addressing a set of data lines with a fourth image data for a second part of the second frame of image content; using a second scan line in the scan line set to send a fourth scan signal to a second row of pixels to move the fourth image data from the data line set to the second row of pixels; and after the fourth scan signal has been sent to the second row of pixels, activating the second row of pixels to emit light.

[0023] Embodiment 15 is a method as described in any of Embodiments 13 or 14, wherein: the reduced resolution operating mode of the display device provides the same horizontal resolution as the higher resolution operating mode; and the reduced resolution operating mode of the display device provides a reduction in vertical resolution relative to the higher resolution operating mode.

[0024] Embodiment 16 is a method as described in Embodiment 15, wherein: the reduction in vertical resolution provided by the reduced resolution operating mode relative to the higher resolution operating mode is caused by the following situation: the display device does not address the data line set with image data after the first scan signal is sent to the first row of pixels and before the second scan signal is sent to the second row of pixels.

[0025] Embodiment 17 is a method as described in any of Embodiments 14, 15 or 16, wherein: addressing a set of data lines with image data involves using a multiplexer to direct the image data to the set of data lines; and because the multiplexer does not direct the image data to the set of data lines for a portion of the pixel rows in the pixel array, the reduced resolution operating mode is suitable for consuming fewer power resources than a higher resolution operating mode.

[0026] Embodiment 18 relates to a display device, comprising: a pixel array, the pixel array comprising a plurality of pixel rows; a set of data lines; a set of scan lines, each scan line corresponding to one of the plurality of pixel rows; and a controller, the controller being configured to perform operations, the operations comprising: operating the display device in a first resolution mode, comprising using the set of data lines and the set of scan lines to address all of the plurality of pixel rows with first image data for a first frame of image content; and operating the display device in a second resolution mode, comprising using the set of data lines and the set of scan lines to address less than all of the plurality of pixel rows with second image data for a second frame of image content.

[0027] Embodiment 19 is a display device as described in Embodiment 18, wherein addressing all pixel rows in a plurality of pixel rows with first image data for a first frame of image content includes: using a scan line set to sequentially send scan signals to each pixel row in the plurality of pixel rows; and writing a portion of the first image data to the data line set before sending each scan signal and after sending the immediately preceding scan signal.

[0028] Embodiment 20 is a display device as described in Embodiment 18, wherein addressing all pixel rows in a plurality of pixel rows with first image data for a first frame of image content includes: using a scan line set to sequentially send scan signals to each pixel row in a plurality of pixel rows, including: sending a first scan signal to a first pixel row in a plurality of pixel rows; and between sending the first scan signal and sending the second scan signal, sending a second scan signal to a second pixel row in a plurality of pixel rows, without writing the image data into the data line set, the second pixel row being the next pixel row immediately following the first pixel row.

[0029] In another embodiment, a display device is provided, which includes: a pixel array, the pixel array including multiple pixel rows; a set of data lines; a set of scan lines, each scan line corresponding to one pixel row among the multiple pixel rows; and a controller, which is configured to perform operations including the method described in Example 1 and its optional features.

[0030] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A diagram of an example display system for an electronic device is shown.

[0032] FIG. 2A to FIG. 2B A diagram of a pixel circuit of a display device and a corresponding timing diagram are shown.

[0033] Figure 3A A diagram of a portion of an example display panel circuit including a set of multiplexers is shown.

[0034] Figure 3B Shows the higher resolution mode Figure 3A 0047] An example timing diagram for this portion of an example pixel circuit.

[0035] Figure 4 shows the reduced resolution mode Figure 3A 0047] An example timing diagram for this portion of an example pixel circuit.

[0036] Figure 5 A diagram of a portion of an example pixel circuit in a reduced resolution mode is shown.

[0037] FIG. 6A to FIG. 6B A flow chart showing a process for operating display devices having different resolutions.

[0038] Like reference numerals in the various drawings indicate like elements. DETAILED DESCRIPTION

[0039] This document generally describes mechanisms for providing a display device that can operate at different resolutions.

[0040] Figure 1 is an illustration of an example display system 100 of a computing device 190. The display system 100 is an OLED display system that includes an array of light-emitting pixels 112. Each light-emitting pixel includes an OLED. The OLED display is driven by drivers that include a SCAN / EM driver 108 and a data driver 110. The SCAN / EM driver 108 can be an integrated (i.e., stacked) row line driver. In general, the data driver 110 provides data signals (e.g., voltage data (VDATA)) to data lines (e.g., D1-D3), the SCAN / EM driver 108 provides a SCAN signal to a selected scan line (e.g., SCAN1) of the scan lines to move the data signal from the data line to the pixels in the selected scan line, and the SCAN / EM driver 108 provides an EMISSION signal to a selected emission line (e.g., E1) of the emission lines to illuminate the OLEDs in the selected row according to the image data specified by the data signal. Although Figure 1 The display system 100 is shown with the SCAN / EM driver 108 on a single side of the display, but the SCAN / EM driver 108 can be placed on both the left and right sides of the display to improve driving performance (e.g., increasing speed by having the SCAN driver on the left side of the display and the EM driver on the right side of the display).

[0041] Pixel array 112 includes a plurality of light-emitting pixels, for example, pixels P11 to P34. A pixel is a small element of a display that can change color based on image data provided to the pixel. Each pixel includes an OLED and circuitry (e.g., Figure 2A ), the circuit system is used to address the OLED with a data value, store the data value, and drive the OLED with an intensity based on the data value. Each pixel within the pixel array 112 can be individually addressed to produce various intensities of the color produced by the pixel.

[0042] Each pixel maintains a substantially constant brightness throughout the frame time, displaying light corresponding to the image data provided. The frame time or frame period is the amount of time between the start of one frame and the start of the next frame. The frame time can be the inverse of the frame rate of the display system. For example, a frame rate of 60 frames per second (fps) corresponds to a frame time of one sixtieth of a second, or 0.0167 seconds.

[0043] Pixel array 112 extends in a plane and includes rows and columns. Each row extends horizontally across pixel array 112. For example, first row 120 of pixel array 112 includes pixels P11, P21, and P31. Each column extends vertically downward along pixel array 112. For example, first column 130 of pixel array 112 includes pixels P11, P12, P13, and P14. For simplicity, Figure 1 Only a few pixels are shown. In reality, there may be thousands or millions of pixels in pixel array 112. Increasing the number of pixels while maintaining the same size display produces higher image resolution.

[0044] The display system 100 includes a display driver integrated circuit (DDIC) 106 that receives display input data 102. In some examples, the DDIC 106 receives the display input data 102 from a system on chip (SoC) 105. The DDIC 106 can be, for example, a semiconductor integrated circuit or a state machine. The DDIC 106 generates signals with appropriate voltage, current, timing, and division to cause the display panel 104 to display an image according to the display input data 102. In some examples, the DDIC 106 can be a microcontroller and can be combined with RAM, flash memory, EEPROM, ROM, etc.

[0045] DDIC 106 includes a timing controller 134, a clock signal generator 136, and a data signal generator 138. DDIC 106 generates control signals 142. Control signals 142 may include, for example, signals that control a display frame start time and a display frame stop time for each frame presented by display panel 104, where a frame represents a single image in a sequence of images presented by display panel 104. In examples where each frame presented by the display panel includes multiple emission cycles, control signals 142 or Figure 1 Other signals not shown in the figure may control the display emission start time and the display emission stop time of each emission cycle of the display panel 104 .

[0046] In some examples, the SCAN / EM driver 108, the data driver 110, or both can be integrated with the DDIC 106. The SCAN / EM driver provides SCAN and EM signals to rows of the pixel array 112. For example, the SCAN / EM driver 108 provides scan signals to the pixel rows via scan lines S1 to S4, and provides EM signals to the pixel rows via EM lines E1 to E4, wherein each pixel row in the pixel array 112 is addressed by a scan line and a corresponding emission line. For example, the first row 120 of the pixel array 112 is addressed by the scan line SCAN1 and the emission line E1.

[0047] The data driver 110 provides signals to the columns of the pixel array 112. For example, based on the image data signal 144 from the data signal generator 138, the data driver 110 outputs data values ​​to a set of multiplexers 114 in the panel 104 via source amplifier output signal lines SAN (e.g., a set of source amplifier signal lines SA1, SA2, and SA3). The set of multiplexers 114 in the panel 104 receives the data values ​​from the corresponding set of source amplifier output signal lines SAN and routes the received data values ​​between a larger number of data lines. For example, Figure 1 A single MUX 114 is shown, which is configured to receive a stream of data values ​​from the data driver 110 via a source output signal line SA1 and distribute the stream of data values ​​one at a time between the data signal lines D1-D3. In practice, there may be multiple MUXs, each fed with a data value from the data driver 110 via a corresponding source control signal line. Figure 3A The operation of multiplexer 114 is described in more detail.

[0048] The data driver 110 provides data voltages via data lines D1 to D3. In some examples, each of the data lines D1 to D3 represents a plurality of data lines. For example, the pixel P11 may include three sub-pixels (e.g., P11R represents a red sub-pixel, P11G represents a green sub-pixel, and P11B represents a blue sub-pixel), and the data line D1 may represent three corresponding data lines, each of which addresses a corresponding sub-pixel of the pixel P11.

[0049] The control signal 142 may be used to drive the SCAN / EM driver 108 and the data driver 110. Thus, the DDIC 106 controls the timing of the scan signals, the EM signals, and the data signals.

[0050] Display system 100 includes power supply 150. Power supply 150 provides a first supply voltage ELVDD and a second supply voltage ELVSS, both of which are provided to each pixel in pixel array 112. In some examples, power supply 150 can be integrated with DDIC 106.

[0051] Each pixel in the pixel array 112 can be addressed by a horizontal scan line, a horizontal EM line, and a vertical data line. For example, pixel P11 can be addressed by data line D1, scan line S1, and EM line E1. In another example, pixel P23 can be addressed by data line D2, scan line S3, and EM line E3.

[0052] For each frame, the scan lines are addressed sequentially. The scan direction determines the order in which the scan lines are addressed (e.g., the direction in which the pixel rows receive data values ​​and are then lit up with intensities based on the received data values). In the display system 100, the scan direction is from the top of the pixel array 112 to the bottom of the pixel array 112. For example, scan line S1 is addressed first, then scan line S2 is addressed, then scan line S3 is addressed, and so on. In some implementations, the SCAN signal is used to program all pixel rows with data values ​​(one row at a time) before the display device activates all pixel rows with intensities based on the programmed data values. In some implementations, the display device can activate pixel rows while other pixel rows are still being programmed, so that there is a gap of several rows between the row currently receiving the SCAN signal and the pixel row that is activated and begins to emit light.

[0053] Although Figure 1 Each row is shown to be addressed by a single scan line, but each row may be addressed by multiple scan lines (e.g., nSCAN and pSCAN). Figure 1 An example component of an OLED display is shown, but the described technology can be applied to other flat panel display technologies including pixel arrays. For example, the technology can be applied to light emitting diodes (LEDs), liquid crystal displays (LCDs), and plasma display panels (PDPs).

[0054] Figure 2A A diagram of a pixel circuit of a display device is shown, the pixel circuit comprising an LED and corresponding drive circuitry for the pixel circuit. Figure 2A It can be shown from Figure 1 A more detailed view of a single pixel of the pixel array shown in FIG. Figure 2A The components shown in are referred to as "pixel circuits", but the present disclosure may also refer to such components simply as "pixels". Figure 2A The pixels shown in may represent sub-pixels.

[0055] The pixel circuit may be an active matrix OLED (AMOLED) pixel circuit. The pixel circuit receives an emission signal (EM) on an emission line, a SCAN signal on a scan signal line, and a data voltage (VDATA) signal on a data line. The pixel circuit 200 receives a first supply voltage ELVDD on a first voltage supply line, a second supply voltage ELVSS on a second voltage supply line, and an initial reference voltage VINIT on an initial voltage supply line.

[0056] The pixel circuit includes an organic light emitting diode (OLED). The OLED includes an organic compound layer that emits light in response to a current IOLED. The organic layer is located between two electrodes (anode and cathode). The OLED is driven by a driving transistor T1 that receives a supply voltage ELVDD and serves as a current source to drive the OLED to emit light.

[0057] The pixel also includes a storage capacitor CST and transistors T2 to T7. The operation of the pixel is defined by the states of the control signals SCAN, EM and VDATA. The amount / level of the OLED current (IOLED) is set by the voltage present at the gate terminal (referred to herein as the "G" node) of the drive transistor T1.

[0058] The driving transistor T1 has a threshold voltage VTH between the gate terminal of the driving transistor T1 and the source terminal of the driving transistor T1. If the voltage between the gate terminal and the source terminal is higher than the threshold voltage VTH, the driving transistor T1 forms a conductive path from the source terminal to the drain terminal. The amount of the current IOLED flowing through the conductive path through the driving transistor T1 corresponds to the amount by which the voltage between the gate terminal and the source terminal is higher than the threshold voltage VTH.

[0059] Figure 2B Shows the provided Figure 2A 1 and 2. The control signals are repeatedly switched between the initialization phase, the programming phase and the emission phase during the operation of the display system 100.

[0060] At the end of the emission phase, the EM signal transitions to an off state (e.g., by changing from a low state to a high state). This transition turns off transistors T5 and T6, which interrupts the current provided to the OLED from ELVDD, thereby stopping the light emission of the OLED. Since the EM signal can be provided to an entire pixel row, this transition can turn off all pixels in the pixel row.

[0061] During the initialization phase, the SCAN[n-1] signal becomes an on state (e.g., by changing from a high state to a low state), which turns on transistor T4 for a period of time and initializes the G node to an initialization voltage VINIT. Since the SCAN[n-1] signal can be provided to the entire pixel row, this initialization phase can erase the data value previously stored at each pixel in the pixel row. The SCAN[n-1] signal can be the SCAN[n] signal provided by the state machine of the SCAN / EM driver 108 to the previous row.

[0062] During the programming phase, the SCAN[n] signal becomes an on state (e.g., by going low), which turns on transistors T2, T3, and T7 for a period of time. This causes the voltage value at the voltage data VDATA line to pass through transistors T2, T1, and T3 to the G node, thereby setting the G node to a value based on the VDATA line (e.g., the voltage at VDATA minus the effect of the transistor threshold voltage). Since the SCAN signal can be provided to the entire pixel row, this programming phase can cause each pixel in the pixel row to move the data voltage value from the corresponding data line of each pixel to the G node of the corresponding pixel.

[0063] During the emission phase, the EM signal becomes an on state (e.g., by going low), which turns on transistors T5 and T6. Current flows from ELVDD through transistors T5, T1, and T6 to the anode of the OLED. Since the EM signal is provided to the entire pixel row, all pixels in the pixel row can be activated.

[0064] The current level supplied to the OLED in each pixel is determined by the voltage present at the G node of the pixel (e.g., where the G node voltage level has been programmed by the voltage data VDATA line). The intensity or brightness of the light emitted by the OLED is directly related to the amount of current IOLED applied to the OLED, with a higher current corresponding to a greater light intensity than a lower current. The storage capacitor CST maintains the voltage at the G node so that the OLED continues to emit approximately the same level of light for the duration of the emission phase.

[0065] The voltage at the G node may be slightly reduced during the emission phase. Therefore, the current IOLED applied to the OLED and the intensity of the light emitted by the OLED may be slightly reduced or increased during the emission phase, depending on the type of pixel circuit design (e.g., in the case of a p-channel transistor in the pixel circuit, a lower voltage level at the G node results in a higher IOLED and a higher intensity of the OLED light).

[0066] Figure 3A 1 shows a diagram of a portion of an example display panel circuit 300 including a set of multiplexers 114. The set of multiplexers 114 includes each of Figure 3A1 and 114b are represented by circuit systems within corresponding dashed boxes in FIG. Multiplexer 114a receives a sequence of image data values ​​as input on source amplifier signal line SA1 and selectively routes the sequence of image data values ​​between data lines D11 to D23 (e.g., routes one data value to D11, then the next data value to D12, then the next data value to D13, and so on, one data value to one data line at a time). Similarly, multiplexer 114b receives a sequence of image data values ​​as input on source amplifier signal line SA2 and selectively routes the sequence of image data values ​​to data lines D31 to D43.

[0067] The display panel circuit 300 includes pixel rows r1, r2, r3, and r4. Each pixel row is shown as including two pixels, each pixel including a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). A set of three sub-pixels forms a pixel. For example, Figure 1 The pixel P11 includes Figure 3A Sub-pixels R11, G11 and B11. Figure 1 The pixel P23 includes Figure 3A Sub-pixels R23, G23 and B23.

[0068] The display panel circuit 300 includes data lines D11 to D43. Each data line addresses a column of sub-pixels, which includes a single sub-pixel from each row. For example, data line D11 addresses sub-pixel R11 of row r1, sub-pixel R12 of row r2, sub-pixel R13 of row r3, and sub-pixel R14 of row r4. Data line D23 addresses sub-pixel B21 of row r1, sub-pixel B22 of row r2, sub-pixel B23 of row r3, and sub-pixel B24 of row r4.

[0069] A high resolution flat panel display may include a large number of column data lines. For example, in a watch display having a pixel array of 384 pixels by 384 pixels, a total of 1152 column data lines may be used to matrix address the pixel array, with each column data line connected to a DDIC 106. If each column data line is directly connected to a DDIC, the DDIC may be physically large to provide 1152 column data line connections. In such a design, a large display bezel for a trace design may also be required. To reduce the size of the DDIC 106 and the bezel, a multiplexer may be used.

[0070] refer to Figure 3A, the display panel circuit 300 includes multiplexer activation lines M1 to M6, each of which is used to control the operation (e.g., on / off state) of one or more transistor switches of one or more corresponding multiplexers based on an activation signal received from another component (e.g., DDIC 106). For example, multiplexer activation line M3 controls the on / off state of switch SW13 in multiplexer 114a and switch SW33 in multiplexer 114b. Multiplexer activation line M6 controls the on / off state of switch SW23 in multiplexer 114a and switch SW43 in multiplexer 114b.

[0071] DDIC 106 outputs image data values ​​on source amplifier signal lines SA1 and SA2. Figure 3A In the example of , each source amplifier signal line is connected to a set of six adjacent data lines via a multiplexer (e.g., 114a, 114b). For example, multiplexer 114a connects SA1 to data lines D11 to D23 via switches controlled by multiplexer activation lines M1 to M6, respectively. Similarly, multiplexer 114b connects SA2 to data lines D31 to D43 via switches controlled by multiplexer activation lines M1 to M6, respectively. Although not shown, additional source amplifier output lines may be connected to additional corresponding sets of six adjacent data lines.

[0072] During operation of the display, DDIC 106 outputs image data (e.g., VDATA) to source amplifier signal lines SA1 and SA2 for controlling the value of the pixel. For example, DDIC 106 may output image data for subpixel B11 to first source amplifier signal line SA1, while multiplexer activation line M3 is activated to cause switch SW13 to be in an on state. Thus, the image data provided by source amplifier signal line SA1 is written to data line D13. When the scan signal is turned on for row r1, the image data is moved from data line D13 to subpixel B11. When the emission signal activates row r1, subpixel B11 emits light at the brightness and color specified by the image data.

[0073] An example set of multiplexers 114 includes two multiplexers, such as multiplexers 114a, 114b, each of which is a one-to-six multiplexer. A one-to-six multiplexer has six outputs for each input. Some embodiments include multiplexers with more or fewer outputs per input. For example, a display system may include a one-to-ten multiplexer with ten outputs for each input, or a one-to-two multiplexer with two outputs for each input.

[0074] The number of multiplexers included in the set of multiplexers may be proportional to the number of sub-pixels in a row of the pixel array, the number of data lines in the display, or both. For example, an example display system having six hundred sub-pixels per row may have six hundred data lines. The display system may include one hundred one to six multiplexers, each of which has an output connected to six of the data lines.

[0075] Figure 3B shows the operation in higher resolution mode Figure 3A 3. An example timing diagram 350 of signals sent on lines of a portion of the example display panel circuit 300 is shown. During operation in the high resolution mode, the DDIC 106 outputs (on source amplifier signal lines SA1 and SA2) image data for sub-pixels of the pixel circuit 300. The DDIC 106 sends activation signals through multiplexer activation lines M1 to M6 to direct the image data sent through the source amplifier signal lines SA1 and SA2 between the data lines of the associated pixels.

[0076] For example, at time t1, DDIC 106 outputs image data for sub-pixel R11 on source amplifier line SA1 and outputs image data for sub-pixel R31 on source amplifier line SA2. At time t1, DDIC 106 outputs an activation signal on multiplexer activation line M1 to turn on a switch that connects source amplifier line SA1 to data line D11 and connects source amplifier line SA2 to data line D31. Thus, image data for sub-pixel R11 is written to data line D11, and image data for sub-pixel R31 is written to data line D31.

[0077] At time t2, MUXs 114a and 114b have already routed image data between all of their respective outputs, thus writing the image data for row r1 to the data lines across the pixel array. The scan driver then turns on scan signal SCAN1, for example, by setting SCAN1 to a low value. Figure 2A and Figure 2B As described, the scan signal SCAN1 turns on transistors T2, T3, and T7 for a period of time for the sub-pixels in row r1. The scan signal SCAN1 causes a plurality of image data values ​​on a plurality of corresponding data lines to be moved from the data lines to the corresponding pixels of row r1. For example, the scan signal SCAN1 causes a first image data value to be moved from data line D11 to sub-pixel R11, and causes a second image data value to be moved from data line D31 to sub-pixel R31. At time t3, the source amplifier signals SA1 and SA2 begin to output image data for the next successive row, for example, output image data values ​​for the sub-pixels of row r2.

[0078] The duration between time t1 and time t3 is the row line time 310 of row r1. In the higher resolution mode, image data for a row of pixels is written to the data line at each row line time interval. Therefore, the operation of the pixel circuit 300 during the row line time 312 between time t3 and time t5 is similar to the operation of the pixel circuit 300 during the previous row line time 310.

[0079] During the higher resolution mode, DDIC 106 continues to write image data for sub-pixels of each successive row from the first row in the pixel array to the last row in the pixel array. At the end of each row line time, a new row line time begins as image data for the next row is written to the data line.

[0080] The multiplexer activation lines M1 to M6 may have large parasitic capacitances due to the inclusion of TFT switches connected in parallel. In addition, the multiplexer activation signal frequently alternates between a high voltage state and a low voltage state. The voltage difference between the high voltage (off) and low voltage (on) states may be, for example, twelve volts or more. Therefore, the multiplexer may consume a large amount of power in the display. In some examples, the multiplexer consumes 6.7% of the total drive power consumption in a display operating in the always-on display mode.

[0081] When a device (e.g., computing device 190) experiences low battery power, the device can enter a battery saver mode. In some examples, computing device 190 can enter a battery saver mode in response to receiving a user input indicating a selection of a battery saver mode. In some examples, in the battery saver mode, the display screen content can be simplified and can include non-color images. This can reduce the power consumption of computing device 190. However, if the display remains in an AOD condition, the amount of power consumed by the display circuitry may not be reduced, in part due to multiplexers in the display continuing to switch transistors to conduct image data between data lines.

[0082] Figure 4 shows an operation in reduced resolution mode Figure 3A An example timing diagram 400 of a portion of the example panel display circuit 300 is shown. In the timing diagram 400, during the first row line time 410 between t6 and t8, the operation of the pixel circuit 300 is similar to that of the pixel circuit 300. Figure 3B310. For example, at time t6, DDIC output line SA1 includes image data for subpixel R11, and output line SA2 includes image data for subpixel R31. At time t6, DDIC 106 outputs an activation signal on multiplexer activation line M1 to turn on switches that connect source amplifier line SA1 to data line D11 and source amplifier line SA2 to data line D31. Thus, image data for subpixel R11 is written to data line D11, and image data for subpixel R31 is written to data line D31.

[0083] At time t7 of timing diagram 400, similar to time t2 of timing diagram 350, all MUX switches have cycled on and off, thereby writing image data for row r1 to the data lines across the pixel array. The scan driver turns on scan signal SCAN1. Scan signal SCAN1 causes image data to move from the data lines to the corresponding sub-pixels of row r1. For example, scan signal SCAN1 causes image data to move from data line D11 to sub-pixel R11, and causes image data to move from data line D31 to sub-pixel R31.

[0084] At time t8, source amplifier signal lines SA1 and SA2 do not provide any image data to the sub-pixels of row r2, which is the next consecutive row after row r1. DDIC 106 controls source amplifier signal lines SA1 and SA2 to remain in an off or idle state during row line time 412 between time t8 and time t10. In some examples, setting source amplifier signal lines SA1 and SA2 to an off state may include disconnecting source amplifier signal lines SA1 and SA2 so that the source amplifier signal lines are not connected to multiplexer 114 (or source amplifier signal lines SA1 and SA2 are connected to multiplexer 114, but disconnected from DDIC 106 so that corresponding output terminals of DDIC 106 are disconnected from the internal circuit system and thus "float").

[0085] DDIC 106 controls the multiplexer enable line to remain in the "off" state during row line time 412 between time t8 and time t10. Therefore, the multiplexer switch remains open or off and does not switch during row line time 412. Therefore, during row line time 412, no image data is written to the data line of row r2.

[0086] At time t9, the scan driver turns on scan signal SCAN2, which is sent to each pixel in row r2 through the scan signal line. Scan signal SCAN2 turns on transistors T2, T3, and T7 for a period of time for the sub-pixels in row r2. Since no new image data is written to the data lines during row line time 412, the image data that can be moved from the data lines to the sub-pixels of row r2 can represent an attenuated version of the image data provided to the data lines between time t6 and t7. For example, the data values ​​provided to the data lines between time t6 and t7 can remain on those data lines after SCAN1 activates temporarily connecting those data lines to the corresponding pixels of row r1 to program those pixels with corresponding data values.

[0087] When scan signal SCAN2 is on, and no new data is written to the data lines of the sub-pixels in row r2, the sub-pixels in row r2 receive residual voltages from the data lines that are left over from previous image data (e.g., image data that was written to the data lines of row r1 and that may have decayed by an amount that is imperceptible to an end user viewing the display). Figure 5 The effects of scanning a row without first writing new data for the row are described in more detail.

[0088] At time t10, DDIC 105 resumes writing image data to the next successive row (e.g., the sub-pixels of row r3) on source amplifier signal lines SA1 and SA2. During row line time 414 between time t10 and time t11, the multiplexer switches controlled by multiplexer activation lines M1 to M6 are sequentially cycled on and off, thereby writing image data for the sub-pixels of row r3 to the data lines.

[0089] During the reduced resolution mode, the pattern shown in the timing diagram 400 repeats, with the DDIC 106 writing image data for alternating rows of pixels. In the example pixel circuit 300, the DDIC 106 writes image data for rows r1 and r3, and skips writing image data for rows r2 and r4. Thus, in the reduced resolution mode, the display system operates at half the frequency for multiplexer operation and half the frequency at which the DDIC 106 outputs image data using the source amplifier signal lines SA1 and SA2. The circuitry in the multiplexer 114 and the DDIC 106 that pushes image data to the source amplifier signal lines SA1 and SA2 is idle during alternating row line times.

[0090] Operating the display in a reduced resolution mode—including operating at half the frequency for multiplexer operation and half the frequency for DDIC source amplifier signals—can reduce power consumption of the multiplexer and source amplifiers, e.g., to about half the power consumption used in a higher resolution mode. Operating the display in a reduced resolution mode can cause a reduction in visual quality by reducing the vertical resolution of the displayed image by half (e.g., such that each set of two lines can display the same / copied lines of image content with half less unique pixel content presented by the display). The reduced resolution mode can be implemented in a battery saving mode so that the reduced visual quality of the image is imperceptible to the user.

[0091] Although the example timing diagram 400 shows that image data is written to alternating pixel rows starting with the first row r1, other variations of the reduced resolution mode are possible. In some examples, image data may be written to alternating pixel rows starting with the second row r2. For example, the DDIC 106 may write image data for rows r2 and r4 and skip writing image data for rows r1 and r3. In some examples, the multiplexer signal switches only for odd pixel rows or only for even pixel rows.

[0092] In some examples, DDIC 106 may skip writing image data for two or more consecutive rows. For example, DDIC 106 may write image data for row r1, may skip writing image data for rows r2 and r3, and may write image data for row r4. Skipping writing image data for two or more consecutive rows can reduce power consumption by reducing image resolution compared to skipping only every other row. In some examples, DDIC 106 may enter a first reduced resolution mode in which individual rows are skipped between rows of new image data. The SoC may determine that further power consumption reduction is required, and may instruct DDIC 106 to enter a second reduced resolution mode in which more than one row is skipped between rows of new image data.

[0093] In some examples, DDIC 106 may write image data for two or more consecutive rows. For example, DDIC 106 may write image data for rows r1 and r2, and may skip writing image data for row r3. Writing image data for two or more consecutive rows may improve image resolution by increasing power consumption compared to writing image data for a single alternating row.

[0094] Although the example timing diagram 400 shows that both the multiplexer switches and the source amplifier signals are idle during the row line time 412, other variations are possible. In some examples, the DDIC 106 may idle the multiplexer switches during the row line time 412 without idling the source amplifier outputs. For example, the multiplexer circuits M1 to M6 may maintain the multiplexer switches in an off state while the DDIC 106 continues to output data values ​​on the source amplifier signal lines SA1 and SA2. In these examples, the multiplexer 114 receives the data values ​​on the source amplifier signal lines SA1 and SA2 but does not direct the image data to any of the data lines.

[0095] In some examples, DDIC 106 may idle the source amplifier outputs without idling the multiplexer switches during row line time 412. For example, DDIC 106 may shut down circuitry that outputs image data on source amplifier signal lines SA1 and SA2 while sending activation signals on multiplexer activation lines M1 to M6 to sequentially turn on and off the multiplexer switches. In these examples, the MUX continues to cycle, but no new image data is provided to the data lines.

[0096] When the scan signal is turned on for a specific row, and no new data is written to the data lines of the sub-pixels in the specific row, the sub-pixels in the specific row receive residual voltages left over from previous image data from the data lines.

[0097] The data lines D11-D43 of the example pixel circuit 300 each have a parasitic capacitance (CDATA). The CDATA of each data line D11-D43 can be used as temporary storage for image data (VDATA) before the SCAN signal becomes active. For example, image data is written to data line D11 at time t6, and the scan signal SCAN1 is turned on at time t7. Between time t6 and t7, the image data for sub-pixel R11 is stored by CDATA of D11.

[0098] After the image data is written to the pixel circuit by the SCAN signal, CDATA may continue to store the image data because CDATA is typically much larger than CST in the pixel circuit, and the charge transferred from CDATA to CST may cause a small decay in the voltage level in CDATA. For example, after the scan signal SCAN1 is turned off at t12, CDATA of D11 continues to store a certain amount (e.g., voltage) of image data written for sub-pixel R11. The image data stored by CDATA may decay over time.

[0099] When the next row SCAN becomes active, the remaining charge in CDATA can be reused to charge the storage capacitor (CST) of the subpixel in the next row. For example, scan signal SCAN2 is turned on at time t9. The residual image data from data line D11 is moved to subpixel R12. Similarly, the residual image data from data line D12 is moved to subpixel G12, which is attenuated from the image data written for subpixel G11. In this way, the subpixels in row r2 receive an attenuated version of the image data written for the subpixels in row r1 from their corresponding data lines. Similarly, the subpixels in row r4 receive an attenuated version of the image data written for the subpixels in row r3 from their corresponding data lines.

[0100] Figure 5 A diagram of a portion of an example pixel circuit 500 in a reduced resolution mode is shown. In the example display panel circuit 500, new image data is written to the data lines during the row line times of rows r1 and r3. During the row line times of rows r2 and r4, no new image data is written to the data lines. Therefore, each sub-pixel in row r2 receives an attenuated version of the image data written for the sub-pixel in row r1 connected to the same data line from its corresponding data line. Similarly, each sub-pixel in row r4 receives an attenuated version of the image data written for the sub-pixel in row r3 connected to the same data line from its corresponding data line.

[0101] Because new image data is written for alternate rows of pixels in the reduced resolution mode, the pixels of pixel circuit 500 have half the vertical image resolution compared to the higher resolution mode in which new image data is written for each row of pixels. Figure 5 In , different pixel values ​​(such as pixel brightness values) are represented by different patterns. Figure 5 As shown, the sub-pixels in row r2 emit light with substantially the same pixel value as the sub-pixels in row r1. Therefore, the appearance of the sub-pixels in row r2 is similar to the appearance of the sub-pixels in row r1. The sub-pixels in row r4 emit light with substantially the same pixel value as the sub-pixels in row r3. Therefore, the appearance of the sub-pixels in row r4 is similar to the appearance of the sub-pixels in row r3.

[0102] While circuitry in DDIC 106 may be configured to operate in a reduced resolution mode, there may also be circuitry in and / or programming performed by a system on a chip (SOC) that provides image data to DDIC 106 that is configured to operate in a reduced resolution mode. For example, the SOC may make a determination to enter a reduced resolution mode (e.g., due to a drop in remaining battery capacity below a threshold level), and the SOC may therefore: (1) send a signal to DDIC 106 to cause DDIC 106 to enter a reduced resolution mode, and (2) generate a frame of image content having reduced horizontal resolution such that the frame of image content sent by the SOC to DDIC 106 has half the number of rows of unique image content. DDIC 106 may use the techniques described herein to vertically spread the reduced amount of image content across the display. At least in part because the SOC generates image content frames having a lower resolution to send to DDIC 106 (e.g., because half of the image content is prepared by the processing circuitry and because half of the image content is upscaled for transmission over the signal lines to DDIC 106), SOC power consumption can be reduced during its reduced resolution mode.

[0103] FIG. 6A to FIG. 6B A flow chart of a process for operating a display device or system with different resolutions is shown. The process may be implemented by a display system or a computing device (eg, computing device 190) including the display system.

[0104] At block 600, the display device operates in a reduced resolution mode. For example, DDIC 106 may receive a signal from SoC 105 instructing DDIC 106 to enter a reduced resolution mode. In some examples, DDIC 106 receives a signal from SoC 105 indicating that device 190 has entered a battery conservation mode. In response to receiving the signal indicating that device 190 has entered a battery conservation mode, the DDIC may determine to operate in a reduced resolution mode. When the display device operates in a reduced resolution mode, the operations of blocks 610-630 (as discussed below) may be performed.

[0105] At block 610, the display device addresses a set of data lines with image data for a portion of a frame of image content. For example, DDIC 106 may address a set of data lines including data lines D11 to D43 ( Figure 3A ) is addressed by a set of data lines of the first frame. In some examples, the first portion of the first frame of image content is a first row of image content from the first frame of image content.

[0106] In some examples, addressing the set of data lines with image data includes using a plurality of multiplexers to direct the image data to the set of data lines. For example, the DDIC may use a set of multiplexers 114 to address the set of data lines. Each multiplexer in the set of multiplexers 114 is configured to direct the image data to a corresponding subset of data lines within the set of data lines. For example, multiplexer 114a ( Figure 3A ) receives the image data stream via source amplifier line SA1 and directs the image data to a subset of data lines including data lines D11 to D23 (e.g., where each image data value in the image data stream is directed one at a time to a different data line in the set of data lines in a round-robin manner). A multiplexer that receives the image data via source amplifier line SA2 directs the image data to a subset of data lines including data lines D31 to D43.

[0107] A plurality of multiplexers receive first image data from a DDIC as a component of a display device. For example, a set of multiplexers 114 receive first image data from a DDIC 106 via source amplifier lines SA1 and SA2. The display device addresses a set of data lines D11 to D43 with the first image data. In some examples, the DDIC 106 sends a control signal 142 (e.g., the multiplexer activation signal discussed above) to a plurality of multiplexers to direct the first image data to the set of data lines. In some examples, the first image data includes a set of voltages (VDATA), each voltage in the set of voltages defining the intensity at which a corresponding pixel in a first row of pixels will emit light. For example, a series of image data values ​​provided to the multiplexer 114a via the source amplifier signal line SA1 includes a set of voltages defining the intensity at which sub-pixels R11 to G21 of row r1 will emit light.

[0108] At block 620, the display device sends a first scan signal to the first row of pixels to move image data from the set of data lines to the first row of pixels using the first scan line. For example, the display device may send a scan signal SCAN1 to the sub-pixels of row r1 to move image data from the data lines D11 to D23 to the sub-pixels of row r1 (e.g., to the "G" node of each corresponding sub-pixel).

[0109] At block 622, the display device activates the first row of pixels to emit light after the first scan signal has been sent to the first row of pixels. For example, the display device activates the sub-pixels of row r1 to emit light after the scan signal SCAN1 has been sent to the sub-pixels of row r1. The display device may activate the sub-pixels of row r1 to emit light by using emission lines (e.g., Figure 1The EM line E1 shown sends an emission signal to activate the sub-pixels of row r1. After the first scan signal has been sent to the first row of pixels, the first row of pixels emit light at a defined / programmed intensity. After the scan signal SCAN1 has been sent to the sub-pixels of row r1, the sub-pixels R11 to G21 of row r1 emit light at a defined / programmed intensity.

[0110] At block 624, the display device sends a second scan signal to a second row of pixels. The second row of pixels may be a next row of pixels in the pixel array immediately following the first row of pixels. For example, the second row of pixels may include sub-pixels of row r2. In some examples, after addressing the set of data lines with the first image data, the display device sends the second scan signal using a second scan line (e.g., a conductor different from the conductor of the first scan line) without addressing the set of data lines with the image data. For example, after sending the scan signal SCAN1, the display device may send the scan signal SCAN2 without addressing the set of data lines with the image data.

[0111] In some examples, the DDIC 106 does not send a control signal to the set of multiplexers 114 between sending the first scan signal SCAN1 and sending the second scan signal SCAN2. Therefore, the multiplexer switches controlled by the multiplexer activation lines M1 to M6 can remain off between the first scan signal SCAN1 and the second scan signal SCAN2. In examples where each multiplexer switch includes a transistor, the voltage present at the gate of the transistor remains below a threshold voltage defined between the gate of the transistor and the source of the transistor during the duration between SCAN1 and SCAN2, so that the transistor does not establish a conductive path between the source of the transistor and the gate of the transistor. In some examples, after the first scan signal SCAN1 is sent to the first row of pixels (e.g., sub-pixels in row r1), the intensity of the first image data addressed to the set of data lines is attenuated to an attenuated version of the first image data.

[0112] At block 626, the attenuated version of the image data is moved to the second row of pixels. In some examples, sending a second scan signal SCAN2 to the second row of pixels (e.g., subpixels of row r2) moves the attenuated version of the first image data to the second row of pixels. Sending the second scan signal SCAN2 to the second row of pixels is performed by the display device after addressing the set of data lines with the first image data, without requiring multiple multiplexers to direct the image data to the set of data lines.

[0113] At block 630, the display device activates the second row of pixels to emit light. For example, the display device may activate the sub-pixels of row r2 to emit light after the scan signal SCAN2 has been sent to the sub-pixels of row r2. The display device may activate the sub-pixels of row r2 by sending a transmit signal using an emission line (e.g., EM line E2). The second row of pixels emits light with an intensity defined by an attenuated version of the image data received from the corresponding data line. The sub-pixels R12 to G22 of row r2 emit light with a defined intensity after the scan signal SCAN2 has been sent to the sub-pixels of row r2. The SCAN2 signal may be sent through the second scan line immediately after the SCAN1 signal is sent to the first scan line, in a sequence of sending scan lines to the scan lines one by one from the top of the display to the bottom of the display.

[0114] At box 640, the display device determines whether to switch resolution modes. For example, the display device may receive a signal indicating that the display device is to switch from a reduced resolution operating mode to a higher resolution operating mode, for example due to (i) a battery of the device in which the display device is housed being determined to have a charge level that has risen above a threshold charge level; or (ii) the device receiving a user input to shut down the reduced resolution operating mode. The computing device or the display device located therein may determine to switch to a higher resolution mode. If the display device is not to switch resolution modes, the operations of box 600 are performed again. If the display device is to switch to a different resolution mode, and the different resolution mode is to be a higher resolution mode, the operations of box 650 are performed, such as Figure 6B shown.

[0115] At block 650, the display device operates in a higher resolution mode. For example, the higher resolution mode is suitable for presenting image content at a higher resolution than when the display device is in a reduced resolution mode. In some examples, the higher resolution mode may be a normal display operating resolution mode. In some examples, DDIC 106 may receive a signal from SoC 105 instructing DDIC 106 to enter the higher resolution mode. In some examples, DDIC 106 receives a signal from SoC 105 indicating that device 190 has exited the battery conservation mode. In response to receiving the signal indicating that device 190 has exited the battery conservation mode, DDIC may determine to operate in the higher resolution mode.

[0116] At block 660, the display device addresses a set of data lines with image data for a first portion of a frame of image content. For example, DDIC 106 may address a set of data lines including data lines D11 to D43 with image data for a portion of a frame of image content. In some examples, the first portion of the frame of image content is a first row of image content from the frame of image content.

[0117] At block 666, the display device sends a third scan signal to the first row of pixels to move image data from the set of data lines to the first row of pixels using the first scan line. For example, the display device may send a scan signal to the sub-pixels of row r1 to move image data from data lines D11 to D23 to the sub-pixels of row r1.

[0118] At block 670, the display device activates the first row of pixels to emit light after the third scan signal has been sent to the first row of pixels. For example, the display device may activate subpixels of row r1 to emit light after the third scan signal has been sent to row r1.

[0119] At block 672, the display device addresses the set of data lines with image data for a second portion of the frame of image content. In some examples, the second portion of the frame of image content is a second row of image content from the frame of image content.

[0120] At block 674, the display device sends a fourth scan signal to the second row of pixels to use the second scan line to move the image data from the data line set to the second row of pixels. For example, the display device may send a fourth scan signal to the subpixels of row r2 to move the image data from the data line to the subpixels of row r2.

[0121] At block 680, the display device activates the second row of pixels to emit light after the fourth scan signal has been sent to the second row of pixels. For example, the display device may activate subpixels of row r2 to emit light after the fourth scan signal has been sent to row r2.

[0122] At block 690, the display device determines whether to switch resolution modes. For example, the display device may receive a signal indicating that the display device is to switch from a higher resolution mode of operation to a reduced resolution mode of operation due to, for example, (i) a battery of the device in which the display device is housed is determined to have a charge level that has fallen below a threshold charge level, or (ii) the device receives a user input to activate a different resolution mode (e.g., activate a reduced resolution mode). The computing device or a display device located therein may determine to switch to a reduced resolution mode. If the display device does not switch resolution modes, the operations of block 650 are performed again. If the display device is to switch to a different resolution mode, and the different resolution mode is a reduced resolution mode, the operations of block 600 are performed.

[0123] A reduced resolution operating mode of a display device may provide the same horizontal resolution as a higher resolution operating mode (e.g., the same number of unique vertical image data lines). The reduced resolution operating mode of a display device may provide a reduction in vertical resolution relative to the higher resolution operating mode (e.g., a reduced number of unique horizontal data lines). The reduction in vertical resolution provided by the reduced resolution operating mode relative to the higher resolution operating mode may be caused by the display device not addressing a set of data lines with image data after a first scan signal is sent to a first row of pixels and before a second scan signal is sent to a second row of pixels. In some examples, addressing the set of data lines with image data involves using a multiplexer to direct the image data to the set of data lines, and because the multiplexer does not direct the image data to the set of data lines for a portion of the rows of pixels in the pixel array, the reduced resolution operating mode is adapted to consume fewer power resources than the higher resolution operating mode.

[0124] In some examples, a dynamic multiplexer control process can be used. The operation of the multiplexer can be dynamically controlled according to the image content. For example, when two or more consecutive two pixel rows are the same color (e.g., black) in the image content, the multiplexer circuit can be maintained in an idle state, where the multiplexer switch is turned off. The multiplexer switch can be turned off starting from the second row of the black area until the next non-black content. Thus, row-by-row dynamic control of the multiplexer circuit can be achieved.

[0125] In some examples, the image content analysis performed to identify successive black rows may be performed by DDIC 106, and the DDIC dynamically controls the multiplexer signal. In some examples, the image content analysis performed to identify successive black rows may be performed by SoC 105. SoC 105 may send a signal to DDIC 106 indicating that the multiplexer is to hold idle rows. In the examples described below, DDIC 106 performs the image content analysis.

[0126] The DDIC 106 receives the display input data 102 from the SoC. The DDIC may analyze the display input data 102 and determine that the display input data 102 includes more than two consecutive black lines.

[0127] DDIC 106 may write data to the data lines for the first row of all black pixels, and then may turn off the multiplexer switch during the row line time of the remaining black lines. Black values ​​are written to the data lines during the row line time of the first black row. During the row line time of the second black row, an attenuated version of the image data will be moved from the data lines to the sub-pixels of the second black row. Therefore, although no new image data is written to the data lines for the second row, the second row will still appear black.

[0128] Depending on the capacitance difference between the parasitic capacitance of the data line (CDATA) and the capacitance of the storage capacitor CST of the subpixel, the maximum number of rows that can be charged to the black data voltage without recharging CDATA can be varied. In some examples, CDATA may need to be recharged at intervals of every tenth, fifteenth, or twentyth row in order to maintain a high enough VDATA on the data line to cause the pixel to appear black.

[0129] For example, the display input data 102 may include twenty-five consecutive rows of black pixels, followed by a twenty-sixth row having at least one non-black pixel. The DDIC may be configured to refresh the CDATA at intervals of ten pixels. Thus, the DDIC may control the multiplexer 114 to write the image data to the data line during the row line time of the first black row. The DDIC may control the multiplexer 114 to remain idle during the row line time of the second black row to the eleventh black row. During the row line time of the second black row to the tenth black row, the image data on the data line decays.

[0130] DDIC 106 may switch multiplexer 114 during the row line time of the eleventh black row, causing new black image data to be written to the data line. DDIC 106 may control multiplexer 114 to remain idle during the row line time of the twelfth black row to the twentieth black row. DDIC may switch multiplexer 114 during the row line time of the twenty-first black row, refreshing the black image data on the data line again.

[0131] DDIC 106 may control multiplexer 114 to remain idle during the 22nd to 25th black rows. The 26th row includes at least one non-black pixel. Therefore, DDIC 106 may switch multiplexer 114 during the row line time of the 26th row, thereby moving the image data for the 26th row to the data line.

[0132] By keeping multiplexer 114 in an idle state during the row line time of all black rows, the power consumption of multiplexer 114 can be reduced. In some examples, instead of or in addition to idling multiplexer 114, DDIC 106 can also idle the source amplifier signals (e.g., SA1 and SA2) for multiple consecutive black rows. In addition to idling the multiplexer switches, idling the source amplifier signals can also increase power savings.

[0133] Embodiments of the subject matter and functional operations described in this specification may be implemented in any suitable electronic device, such as a personal computer, a mobile phone, a smart phone, a smart watch, a smart TV, a mobile audio or video player, a game console, or a combination of one or more of these devices.

[0134] An electronic device may include various components, such as a memory, a processor, a display, and an input / output unit. The input / output unit may include, for example, a transceiver that can communicate with one or more networks to send and receive data. The display may be any suitable display for displaying an image, including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), or a light emitting diode (LED) display.

[0135] Various implementations of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system that includes at least one programmable processor that can be either special purpose or general purpose and can be coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device.

[0136] Embodiments may be implemented as one or more computer program products, for example, one or more modules of computer program instructions encoded on a computer-readable medium, for data processing equipment to execute or control the operation of the data processing equipment. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material composition that affects a machine-readable propagation signal, or a combination of one or more of them. The term "data processing equipment" encompasses all devices, devices, and machines for processing data, including, for example, a programmable processor, a computer, or a plurality of processors or computers. In addition to hardware, the device may also include code that creates an execution environment for the computer program in question, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagation signal is an artificially generated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode information for transmission to a suitable receiver device.

[0137] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple collaborative files (e.g., files that store portions of one or more modules, subroutines, or codes). A computer program may be deployed to execute on one computer or on multiple computers (which are located at one location or distributed at multiple locations and interconnected by a communications network).

[0138] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory, or both.

[0139] Elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. In general, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or be operably coupled to receive data from or transfer data to the one or more mass storage devices, or both. However, a computer may not have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example: semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit system.

[0140] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of the content that can be claimed, but should be interpreted as descriptions of features that may be peculiar to a particular embodiment. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Although features may be described above as working in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may involve a sub-combination or a change in the sub-combination.

[0141] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0142] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method of operating a display device, the display device comprising an array of pixels addressed by a set of data lines and a set of scan lines, the method comprising: The display device presents the first frame of image content, including presenting the first frame of image content through the following operations: addressing the set of data lines with first image data for a first portion of the first frame of image content; Using a first scan line in the set of scan lines to send a first scan signal to a first row of pixels in the pixel array to move the first image data from the set of data lines to the first row of pixels; activating the first row of pixels to emit light after the first scan signal has been sent to the first row of pixels; After the set of data lines has been addressed with the first image data, using a second scan line in the set of scan lines to send a second scan signal to a second row of pixels in the pixel array without addressing the set of data lines with image data; and After the second scan signal has been sent to the second row of pixels, the second row of pixels is activated to emit light.

2. The method of claim 1, wherein: After the first scan signal is sent to the first row of pixels, the first image data addressed to the set of data lines decays in intensity to an attenuated version of the first image data; and Sending the second scan signal to the second row of pixels moves the attenuated version of the first image data to the second row of pixels.

3. The method according to any one of claims 1 or 2, wherein: The first image data includes a set of voltages, each voltage in the set of voltages defining an intensity at which a corresponding pixel in the first row of pixels is to emit light.

4. The method according to any one of claims 1, 2 or 3, wherein: The second row of pixels is a next row of pixels immediately following the first row of pixels in the pixel array.

5. A method as claimed in any one of the preceding claims, wherein: The first part of the first frame of image content is a first line of image content from the first frame of image content; and The second part of the first frame image content is a second line of image content from the first frame image content.

6. A method as claimed in any one of the preceding claims, wherein: Addressing the set of data lines with the first image data includes using a plurality of multiplexers to direct the first image data to the set of data lines, each of the plurality of multiplexers being configured to direct the image data to a corresponding subset of data lines within the set of data lines, such that the set of data lines includes a plurality of subsets of data lines corresponding to the plurality of multiplexers.

7. The method of claim 6, wherein: The plurality of multiplexers receive the first image data from a display device integrated circuit that is a component of the display device.

8. The method according to any one of claims 6 or 7, wherein: Sending the second scan signal to the second row of pixels is performed by the display device after addressing the set of data lines with the first image data without requiring the plurality of multiplexers to direct the image data to the set of data lines.

9. The method of claim 6, wherein: The display device includes a display driver integrated circuit; Addressing the set of data lines with the first image data comprises the display driver integrated circuit sending control signals to the plurality of multiplexers to direct the first image data onto the set of data lines; and The display driver integrated circuit does not send a control signal to the plurality of multiplexers to direct image data onto the set of data lines between the sending of the first scan signal and the sending of the second scan signal.

10. The method of claim 9, wherein: The display driver integrated circuit receives second image data for a second portion of the first frame image content and designated for the second row of pixels; and The second image data is not directed to the set of data lines by the multiple multiplexers at least in part because the display driver integrated circuit does not send a control signal to the multiplexer to direct the image data to the set of data lines between the sending of the first scan signal and the sending of the second scan signal.

11. A method as claimed in any one of the preceding claims, wherein: Presenting the first frame of image content includes: addressing the data line set with third image data for a third portion of the first frame of image content; Using a third scan line in the set of scan lines to send a third scan signal to a third row of pixels in the pixel array to move the third image data from the set of data lines to the third row of pixels; After the third scan signal has been sent to the third row of pixels, activating the third row of pixels to emit light; After the set of data lines has been addressed with the third image data, using a fourth scan line in the set of scan lines to send a fourth scan signal to a fourth row of pixels in the pixel array without addressing the set of data lines with image data; and After the fourth scan signal has been transmitted to the fourth row of pixels, the fourth row of pixels is activated to emit light.

12. A method as claimed in any one of the preceding claims, wherein: Since the display device operates in a reduced resolution operating mode, the display device sends the second scan signal to the second row of pixels without addressing the set of data lines with image data.

13. The method of claim 12, wherein: The display device receives a signal indicating that the display device is to switch from a higher resolution operating mode to the reduced resolution operating mode due to a battery of a device in which the display device is housed being determined to have a charge level that has fallen below a threshold charge level.

14. The method of any one of claims 1 to 10, wherein: When the display device is in a reduced resolution operation mode, the display device presents the first frame of image content; The method includes receiving a signal indicating that the display device is to switch from the reduced resolution mode of operation to a higher resolution mode of operation, the higher resolution mode of operation being adapted to present image content at a higher resolution than when the display device is in the reduced resolution mode; and The method includes presenting a second frame of image content by the display device when the display device is in the higher resolution operation mode, including presenting by the following operations: addressing the set of data lines with third image data for a first portion of the second frame of image content; Using the first scan line in the scan line set to send a third scan signal to the first row of pixels to move the third image data from the data line set to the first row of pixels; activating the first row of pixels to emit light after the third scan signal has been sent to the first row of pixels; addressing the set of data lines with fourth image data for a second portion of the second frame of image content; Using the second scan line in the scan line set to send a fourth scan signal to the second row of pixels to move the fourth image data from the data line set to the second row of pixels; as well as The second row of pixels is activated to emit light after the fourth scan signal has been sent to the second row of pixels.

15. The method of any one of claims 13 or 14, wherein: the reduced resolution operating mode of the display device providing the same horizontal resolution as the higher resolution operating mode; and The reduced resolution operating mode of the display device provides a reduction in vertical resolution relative to the higher resolution operating mode.

16. The method of claim 15, wherein: The reduction in vertical resolution provided by the reduced resolution operating mode relative to the higher resolution operating mode is caused by the display device not addressing the set of data lines with image data after the first scan signal is sent to the first row of pixels and before the second scan signal is sent to the second row of pixels.

17. The method of any one of claims 14, 15 or 16, wherein: Addressing the set of data lines with image data involves using a multiplexer to direct the image data to the set of data lines; and Because the multiplexer does not direct image data to the set of data lines for a portion of the rows of pixels in the pixel array, the reduced resolution operating mode is adapted to consume fewer power resources than the higher resolution operating mode.

18. A display device comprising: a pixel array, the pixel array comprising a plurality of pixel rows; Data line collection; a set of scan lines, each scan line corresponding to one of the plurality of pixel rows; as well as A controller configured to perform operations, the operations comprising: Operating the display device in a first resolution mode includes using the set of data lines and the set of scan lines to address all of the plurality of pixel rows with first image data for a first frame of image content; and Operating the display device in a second resolution mode includes addressing less than all of the plurality of pixel rows with second image data for a second frame of image content using the set of data lines and the set of scan lines.

19. The display device according to claim 18, wherein: Addressing all pixel rows in the plurality of pixel rows with the first image data for the first frame image content includes: sequentially sending a scan signal to each of the plurality of pixel rows using the set of scan lines; and A portion of the first image data is written to the set of data lines before each scan signal is sent and after the immediately preceding scan signal is sent.

20. The display device according to claim 18, wherein: Addressing all pixel rows in the plurality of pixel rows with the first image data for the first frame image content includes: Using the scan line set to sequentially send a scan signal to each pixel row in the plurality of pixel rows includes: Sending a first scanning signal to a first pixel row among the plurality of pixel rows; and A second scanning signal is sent to a second pixel row among the multiple pixel rows without writing image data to the data line set between sending the first scanning signal and sending the second scanning signal, and the second pixel row is the next pixel row immediately after the first pixel row.

Images