Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of improving moisture resistance reliability. A laminated ceramic capacitor (1) is provided with a laminated body (2) and an external electrode (3). The laminated body (2) has: an inner layer section (11); a first side edge section (20A) and a second side edge section (20B) respectively disposed on both sides of the inner layer section (11) in the width direction (W); and a pair of outer layer sections (12) respectively disposed on both sides of the inner layer section (11) in the lamination direction (T) and respectively disposed so as to be sandwiched by the side edge sections (20). The laminated ceramic capacitor (1) is provided with a first cover region (4A) and a second cover region (4B) which are formed of an inorganic material and are disposed on the outer surface of the laminated body (2) so as to straddle the boundary between the first side edge section (20A) or the second side edge section (20B) and the outer layer section (12). Each of the end surfaces (C) of the multilayer ceramic capacitor (1) has an uncovered portion (Ca) that is not covered by the covered region (4), and is connected to each of the external electrodes (3) at the uncovered portion (Ca).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In recent years, multilayer ceramic electronic components such as multilayer ceramic capacitors have been sought to be miniaturized and have a higher capacity. In order to achieve the miniaturization and higher capacity of multilayer ceramic capacitors, it is effective to increase the area of ​​the internal electrode layers facing each other by thinning the side edges of the stacked body in which a plurality of dielectric ceramic layers and a plurality of internal electrode layers are stacked.

[0003] For example, Patent Documents 1 and 2 describe a method of forming side edges for ensuring insulation around the internal electrodes by post-installation on a laminated chip with internal electrodes exposed on the side. This makes it possible to make the side edges thinner and relatively increase the intersecting area of ​​the internal electrodes.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2012-191159

[0007] Patent Document 2: Japanese Patent Application Publication No. 2014-204116 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] However, in the multilayer ceramic capacitors of Patent Documents 1 and 2, there is a possibility that moisture may penetrate into the interior of the multilayer body through the boundary between the multilayer body and the side edge, and therefore, there is a concern that the moisture resistance reliability of the multilayer ceramic capacitor may be reduced.

[0010] An object of the present invention is to provide a multilayer ceramic capacitor capable of improving moisture resistance reliability.

[0011] Technical solutions to solve problems

[0012] The multilayer ceramic capacitor of the present invention comprises: a stacked body, comprising an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately stacked, having a pair of main surfaces opposed to each other in a stacking direction, a pair of end surfaces opposed to each other in a length direction orthogonal to the stacking direction, and a pair of side surfaces opposed to each other in a width direction orthogonal to either the stacking direction and the length direction; and a pair of external electrodes, respectively arranged on each of the end surfaces and connected to the internal electrode layers, wherein the stacked body comprises a pair of side edge portions respectively arranged on both sides of the width direction of the inner layer portion, and an outer layer portion respectively arranged on both sides of the stacking direction of the inner layer portion and respectively arranged to be sandwiched by each of the side edge portions, The pair of side surfaces are the first side surface and the second side surface, the pair of side edge portions are the first side edge portion arranged on the first side surface and the second side edge portion arranged on the second side surface, and the stacked ceramic capacitor comprises: a first covering region, composed of an inorganic material, arranged on the outer surface of the stacked body and arranged to cross the boundary between the first side edge portion and each of the outer layer portions; and a second covering region, composed of an inorganic material, arranged on the outer surface of the stacked body and arranged to cross the boundary between the second side edge portion and each of the outer layer portions, each of the end faces respectively has a non-covered portion that is not covered by either the first covering region or the second covering region, and each of the non-covered portions is connected to each of the external electrodes respectively.

[0013] Effects of the Invention

[0014] According to the present invention, since moisture can penetrate into the interior of the multilayer ceramic capacitor through the boundaries between the side edge portions and the outer layer portions, the moisture resistance reliability of the multilayer ceramic capacitor can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic perspective view of a multilayer ceramic capacitor.

[0016] Figure 2 It is a multilayer ceramic capacitor along Figure 1 Cross-sectional view along line II-II.

[0017] Figure 3 It is a multilayer ceramic capacitor along Figure 1 Cross-sectional view along line III-III.

[0018] Figure 4 This is a schematic perspective view of a state where a masking region is provided on a stacked body.

[0019] Figure 5 It is a diagram showing the manufacturing process of a laminated ceramic capacitor.

[0020] Figure 6It is a diagram showing the manufacturing process of a laminated ceramic capacitor.

[0021] Figure 7 It is a diagram showing the manufacturing process of a laminated ceramic capacitor.

[0022] Figure 8 FIG. 1 is a diagram showing the structure of a multilayer ceramic capacitor according to a modified example of the present invention. Figure 2 The corresponding figure. DETAILED DESCRIPTION

[0023] The following is based on Figure 1 to Figure 4 Embodiments of the present invention will be described.

[0024] (Multilayer ceramic capacitor 1)

[0025] like Figure 1 to Figure 3 As shown, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2 .

[0026] In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the length direction L. The direction in which the dielectric layer 14 and the internal electrode layer 15 are stacked is referred to as the stacking direction T. The direction intersecting either the length direction L or the stacking direction T is referred to as the width direction W. In the embodiment, the width direction W is orthogonal to either the length direction L or the stacking direction T.

[0027] In addition, in the following description, Figure 1 Among the six outer peripheral surfaces of the stacked body 2 shown, a pair of outer surfaces facing each other in the stacking direction T are set as two main surfaces A, a pair of outer surfaces facing each other in the width direction W are set as two side surfaces B, and a pair of outer surfaces facing each other in the length direction L are set as two end surfaces C. One of the two main surfaces A is set as a first main surface AA, and the other is set as a second main surface AB (refer to Figure 2 ). One of the two end faces C is referred to as the first end face CA, and the other is referred to as the second end face CB. When there is no need to distinguish between the first main face AA and the second main face AB, they are collectively referred to as the main face A. When there is no need to distinguish between the first end face CA and the second end face CB, they are collectively referred to as the end face C.

[0028] (Laminate 2)

[0029] The laminate 2 includes a laminate small piece 10 and a side edge portion 20. The laminate 2 is in a rectangular parallelepiped shape. The laminate 2 preferably has rounded corners and ridges. The corner is where three faces of the laminate intersect, and the ridge is where two faces of the laminate intersect.

[0030] (Laminate small piece 10)

[0031] The laminated body small piece 10 includes an inner layer portion 11 and outer layer portions 12 respectively arranged on the two main surface A sides of the inner layer portion 11. In addition, the outer layer portion arranged on the first main surface AA side of the outer layer portion 12 is referred to as the first outer layer portion 12A, and the outer layer portion arranged on the second main surface AB side is referred to as the second outer layer portion 12B. Hereinafter, when no special distinction is required, the first outer layer portion 12A and the second outer layer portion 12B are collectively referred to as the "outer layer portion 12".

[0032] (Inner layer portion 11)

[0033] The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 .

[0034] (Dielectric layer 14)

[0035] The dielectric layer 14 is made of a ceramic material, specifically, a dielectric ceramic material. The dielectric layer 14 contains ceramic particles. The ceramic particles are particles (main crystal particles) that are the main components of the dielectric layer 14, and are composed of a compound having a perovskite structure containing Ba and Ti. That is, the dielectric layer 14 is a sintered polycrystal having a compound having a perovskite structure as the main component.

[0036] The dielectric layer 14 may contain other components other than the main component as additives. The additive is, for example, at least one element selected from the group consisting of Si, Mg, Ba, and Mn. In the dielectric layer 14, the additive exists between the ceramic particles, for example.

[0037] The thickness of the dielectric layer 14 is preferably 0.2 μm to 0.8 μm, more preferably 0.2 μm to 0.55 μm. This increases the number of laminated sheets 2 of the same size, thereby ensuring capacitance.

[0038] (Internal electrode layer 15)

[0039] The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are alternately arranged. In addition, the first internal electrode layers 15A and the second internal electrode layers 15B are collectively described as the internal electrode layers 15 when there is no need to distinguish them in particular.

[0040] The internal electrode layer 15 is preferably formed of a metal material represented by, for example, Ni, Cu, Ag, Pd, Ag—Pd alloy, Au, or the like.

[0041] The first internal electrode layer 15A includes a first opposing portion 152a opposing the second internal electrode layer 15B and a first lead portion 151a led out from the first opposing portion 152a toward the first end surface CA. The end of the first lead portion 151a is exposed at the first end surface CA and is electrically connected to a first external electrode 3A described later.

[0042] The second internal electrode layer 15B includes a second opposing portion 152b opposing the first internal electrode layer 15A and a second lead portion 151b led from the second opposing portion 152b to the second end surface CB. The end of the second lead portion 151b is electrically connected to a second external electrode 3B described later.

[0043] According to the internal electrode layer 15 described above, electric charges are accumulated in the first opposing portion 152a of the first internal electrode layer 15A and the second opposing portion 152b of the second internal electrode layer 15B, thereby exhibiting capacitor characteristics.

[0044] Each end of the internal electrode layer 15 on the first side face BA side is flush with the surface of the inner layer portion 11 on the first side face BA side. Each end of the internal electrode layer 15 on the second side face BB side is flush with the surface of the inner layer portion 11 on the second side face BB side.

[0045] The thickness of each internal electrode layer 15 is preferably set to 0.2 μm or more and 2.0 μm or less, and more preferably set to 0.2 μm or more and 0.5 μm or less. Thus, even if the stacked body 2 has the same size, the number of stacked sheets can be increased, so that the electrostatic capacitance can be ensured. In addition, the number of sheets of the internal electrode layer 15 is preferably 15 or more and 1000 or less.

[0046] (Outer layer 12)

[0047] The outer layer 12 can be made of a dielectric ceramic material. In addition, the outer layer 12 can be made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer 11, or can be made of a dielectric ceramic material different from the dielectric layer 14 of the inner layer 11. The thickness of the outer layer 12 is set to be greater than 15 μm and less than 60 μm.

[0048] The outer layer portion 12 may also be a multilayer structure. In addition, when the outer layer portion 12 contains Si, the outer layer portion 12 may also have a segregated portion of Si. In these cases, it is preferred that among the multiple layers constituting one outer layer portion 12, the layer located farther from the inner layer portion 11 has more segregated portions of Si than the layer located closest to the inner layer portion 11. As a result, the bending strength of the laminated ceramic capacitor 1 in the stacking direction T can be improved.

[0049] The total number of dielectric layers 14 , internal electrode layers 15 , and outer layer portions 12 (ie, the number of laminated layers of the laminate 2 ) is preferably, for example, 15 or more and 1000 or less.

[0050] (Side edge portion 20)

[0051] The side edge portion 20 can be made of a dielectric ceramic material. The side edge portion 20 can be made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer portion 11, or can be made of a dielectric ceramic material different from the dielectric layer 14 of the inner layer portion 11. The side edge portions 20 are respectively provided on both side surfaces B of the portion where the inner layer portion 11 and the outer layer portion 12 are stacked. The side edge portions 20 sandwich the outer layer portion 12 in the stacking direction T. The side edge portions 20 cover the end portions on the width direction W side of the internal electrode layer 15 exposed on both side surfaces of the stacked body small piece 10.

[0052] In addition, the side edge portion 20 disposed on the first side surface BA side is referred to as the first side edge portion 20A, and the side edge portion disposed on the second side surface BB side is referred to as the second side edge portion 20B. The first side edge portion 20A and the second side edge portion 20B are sometimes collectively referred to as "side edge portion 20" when there is no need to distinguish them.

[0053] The dimension of the first side edge portion 20A in the width direction W is preferably set to 5 μm or more and 40 μm or less, and more preferably set to 5 μm or more and 20 μm or less. The dimension of the second side edge portion 20B in the width direction W is preferably set to 5 μm or more and 40 μm or less, and more preferably set to 5 μm or more and 20 μm or less. Thus, the capacitance of the multilayer ceramic capacitor 1 can be increased while ensuring the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0054] The dimensions of the first side edge 20A and the second side edge 20B in the width direction W can be measured by, for example, observing the WT cross section of the laminate 2 exposed by grinding with a scanning electron microscope. Each value is obtained by averaging the measured values ​​at a plurality of locations in the lamination direction T.

[0055] The first side edge portion 20A is composed of multiple layers, specifically, two layers (see Figure 3 The first side edge portion 20A includes a first inner layer 21A disposed closer to the inner layer portion 11 among the two layers, and a first outer layer 22A disposed farther from the inner layer portion 11 among the multiple layers.

[0056] The second side edge portion 20B is composed of a plurality of layers, specifically, two layers. The second side edge portion 20B includes a second inner layer 21B disposed closer to the inner layer portion 11 and a second outer layer 22B disposed farther from the inner layer portion 11 .

[0057] In the following, the first inner layer 21A and the second inner layer 21B are sometimes collectively referred to as the "inner layer 21" when there is no need to distinguish them. The first outer layer 22A and the second outer layer 22B are sometimes collectively referred to as the "outer layer 22" when there is no need to distinguish them.

[0058] The side edge portion 20 is not limited to a two-layer structure, and may be a single-layer structure or may be composed of three or more layers. When the side edge portion 20 is composed of three or more layers, the layer disposed closest to the inner layer portion 11 among the multiple layers of the side edge portion 20 is set as the inner layer, and the layer disposed on the side farthest from the inner layer portion 11 among the multiple layers is set as the outer layer. In addition, the first side edge portion 20A and the second side edge portion 20B may have different numbers of layers.

[0059] When the side edge portion 20 is a two-layer structure including an inner layer and an outer layer, due to the difference in sinterability between the inner layer and the outer layer, it is possible to confirm that it is a two-layer structure and the interface between the layers by observing it under a dark field using an optical microscope. The same is true when the side edge portion 20 is a structure of more than three layers. In addition, there may also be a situation where the inner layer and the outer layer cannot be identified as a two-layer structure after sintering. Even when it cannot be identified as a two-layer structure, it is sometimes possible to distinguish between two regions based on the difference in the type of element or the content of the element.

[0060] (Ceramic particles)

[0061] The dielectric layer 14, the outer layer portion 12, and the side edge portion 20 may also contain ceramic particles. In this case, interface resistance is generated at the interface between the ceramic particles, so that the insulation resistance between the internal electrode layers 15 can be increased. Therefore, the occurrence of short circuits in the multilayer ceramic capacitor 1 can be suppressed.

[0062] At the interface of ceramic particles, rare earths are preferably present. The presence of rare earths at the interface of ceramic particles can be confirmed by elemental analysis based on TEM-EDX. As rare earths, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y, etc. can be listed. By the presence of rare earths at the interface of ceramic particles, the interface resistance of the dielectric ceramic layer can be further improved. Therefore, the reliability of the stacked ceramic capacitor can be further improved. In addition, Mg, Mn, Si, etc. can also be present.

[0063] The rare earth is preferably present in an amount of 0.2 mol% or more and 5 mol% or less relative to 100 mol of Ti. Regarding 100 mol of Ti mentioned here, the amount of rare earth relative to 100 mol of Ti is determined on the premise that the dielectric ceramic material constituting the dielectric ceramic layer has a compound having a perovskite structure (a structure represented by ABO3, B=Ti) as a main component. The amount of rare earth can be confirmed by TEM-EDX.

[0064] (Composition of Laminated Body 2)

[0065] When the dielectric layer 14, the outer layer portion 12 and the side edge portion 20 are composed of dielectric ceramics, the composition of at least one of the dielectric ceramic layers constituting the dielectric layer 14, the dielectric ceramic layers constituting the outer layer portion 12 and the dielectric ceramic layers constituting the side edge portion 20 may be different from the composition of the other dielectric ceramic layers.

[0066] The dielectric layer 14, the outer layer 12, and the side edge 20 have different properties required for their placement purposes and manufacturing methods. Therefore, by making the composition of at least one of the dielectric ceramic layers constituting the dielectric layer 14, the outer layer 12, and the side edge 20 different from the composition of the others, it is possible to achieve an optimal composition according to the location where they are placed. Therefore, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0067] Furthermore, when the side edge portion 20 is formed of a plurality of dielectric ceramic layers, the plurality of dielectric ceramic layers forming the side edge portion 20 may have the same composition or different compositions.

[0068] When the composition of any one of the plurality of dielectric ceramic layers constituting the side edge portion 20 is different from that of the dielectric layer 14, it can be said that the composition of the side edge portion 20 is different from that of the dielectric layer 14. In addition, when the composition of any one of the plurality of dielectric ceramic layers constituting the side edge portion 20 is different from that of the outer layer portion 12, it can be said that the composition of the side edge portion 20 is different from that of the outer layer portion 12.

[0069] The dielectric ceramic layers with different compositions among the dielectric ceramic layers constituting the dielectric layer 14, the dielectric ceramic layers constituting the outer layer 12, and the dielectric ceramic layers constituting the side edge portion 20 are preferably the same main component as the other dielectric ceramic layers, and the types of additives are different. As the main component, BaTiO3, CaTiO3, or SrTiO3 can be listed. The elements of the additives are preferably Si, Mg, Mn, Sn, Cu, rare earths, Ni, and Al. In addition, the dielectric ceramic layers constituting the dielectric layer 14, the dielectric ceramic layers constituting the outer layer 12, and the dielectric ceramic layers constituting the side edge portion 20 may also contain two or more elements of the above-mentioned additives.

[0070] In addition, the term "same composition" means that the types of elements contained in the dielectric ceramics constituting each dielectric ceramic layer are the same, and the contents (molar ratios) of other elements based on Ti are all within ±0.5%. It is assumed that the difference in diameter of the ceramic particles constituting each dielectric ceramic layer and the difference in porosity are not included in the difference in the composition of the dielectric ceramic layer.

[0071] The composition of each dielectric ceramic layer can be determined by performing elemental analysis based on wavelength dispersive X-ray analysis (WDX) or transmission electron microscope-energy dispersive X-ray analysis (TEM-EDX) on the cut surface where the laminated ceramic capacitor 1 is cut to expose the dielectric ceramic layer. In this case, the composition of each dielectric ceramic layer is measured at five locations and the average value is determined.

[0072] When the side edge portion 20 has a multilayer structure, the composition of each layer measured at each of the five locations is multiplied by the ratio of the thickness (i.e., the dimension in the width direction W) of each layer in the side edge portion 20. In addition, when segregation of elements is observed near the interface with other dielectric ceramic layers or the internal electrode layer 15, the location where segregation of elements is observed is not used as the measurement object of WDX.

[0073] (Elements of Additives)

[0074] As an element of an additive added to the dielectric layer 14 and the outer layer 12, Mg is preferably used. The content of Mg in the dielectric layer 14 and the outer layer 12 is preferably 0.05 mol% or more and 3.0 mol% or less relative to Ti 100 mol. As a result, the relative dielectric constant of the dielectric layer 14 can be increased, so that the electrostatic capacitance of the multilayer ceramic capacitor 1 can be increased. In addition, it is sometimes preferred that the content of Mg in the dielectric layer 14 and the outer layer 12 is infinitely small.

[0075] As an element of the additive added to the side edge portion 20, Si is preferred. The content of Si in the side edge portion 20 is preferably 0.05 mol% or more and 5.0 mol% or less relative to Ti100 mol. The content of Si in the side edge portion 20 is preferably higher than the content of Si in the dielectric layer 14 and the outer layer portion 12. By making the content of Si in the side edge portion 20 higher, the sintering property of the side edge portion 20 can be improved, so that it is possible to suppress the intrusion of moisture or the like from the side surface B of the stacked body 2 and the deterioration of the internal electrode layer 15.

[0076] As an element of the additive added to the side edge portion 20, Mg is preferred. The content of Mg in the side edge portion 20 is preferably 0.05 mol% or more and 5.0 mol% or less relative to the mole of Ti100. The content of Mg in the side edge portion 20 is preferably higher than the content of Mg in the dielectric layer 14 and the outer layer portion 12. By increasing the content of Mg in the side edge portion 20, the grain growth of the ceramic particles included in the side edge portion 20 can be suppressed, so that short circuits between the internal electrode layers 15 are less likely to occur.

[0077] As an element of the additive added to the side edge portion 20, Mn is preferred. The content of Mn in the side edge portion 20 is preferably 0.01 mol% or more and 3.0 mol% or less relative to the mole of Ti100. The content of Mn in the side edge portion 20 is preferably higher than the content of Mn in the dielectric layer 14 and the outer layer portion 12. By increasing the content of Mn in the side edge portion 20, the grain growth of the ceramic particles included in the side edge portion 20 can be suppressed, so that it is difficult to generate a short circuit between the internal electrode layers 15.

[0078] (Segregation of elements)

[0079] Elements derived from the dielectric layer 14 may be segregated near the interface between the side edge portion 20 and the dielectric layer 14. Elements derived from the outer layer 12 may be segregated near the interface between the side edge portion 20 and the outer layer 12.

[0080] The element derived from the dielectric layer 14 may be segregated near the interface between the internal electrode layer 15 and the dielectric layer 14. The segregated element is preferably Ni. The element derived from the outer layer 12 may be segregated near the interface between the internal electrode layer 15 and the outer layer 12. The segregated element is preferably Ni.

[0081] Si segregates near the interface with the side edge portion 20 in the internal electrode layer 15. In the internal electrode layer 15, a Si segregation region is formed within a range of 0.5 μm from the end portion on the side of the side edge portion 20 to the center portion side in the width direction W. As a result, the bending strength of the internal electrode layer 15 is improved.

[0082] (Porosity of Laminated Body 2)

[0083] The porosity of the dielectric layer 14 , the porosity of the outer layer portion 12 , and the porosity of the side edge portion 20 may be the same or different from each other.

[0084] When calculating these porosities, a scanning electron microscope (SEM) was used to observe the cut surface of the laminated ceramic capacitor 1 at 20,000 times to expose the dielectric layer 14, the outer layer 12, and the side edge 20. An area with a field size of 6.3 μm × 4.4 μm was photographed at 5 locations so that the areas did not overlap with each other, and the ratio of the area occupied by the voids to the entire field of view was calculated by image analysis based on each of the obtained SEM images. The average value of the calculated ratios in the 5 fields of view was set as the porosity.

[0085] However, when the side edge portion 20 is composed of multiple layers, after the porosity of each layer is calculated separately, the sum of the product of the value obtained by dividing the dimension of each layer in the width direction W by the dimension of the width direction W of the side edge portion 20 and the porosity of each layer is set as the porosity of the side edge portion 20.

[0086] (Comparison between inner layer 21 and outer layer 22)

[0087] (About the content of elements)

[0088] The Si content of the outer layer 22 is greater than that of the inner layer 21. This can improve the bending strength of the side edge portion 20. In addition, cracks and defects in the side edge portion 20 can be suppressed, thereby improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0089] In the outer layer 22, Si is added so that the molar ratio of Si to Ti1 is 3.0 or more and 7.0 or less, and in the inner layer 21, Si is added so that the molar ratio of Si to Ti1 is 1.0 or more and 4.0 or less. In particular, the segregated portion of Si in the outer layer 22 is larger than the segregated portion of Si in the inner layer 21.

[0090] The content of Ba as an additive in the inner layer 21 is greater than the content of Ba as an additive in the outer layer 22. In addition, the content of Ba as an additive in the outer layer 22 is greater than the content of Ba as an additive in the dielectric layer 14. In this way, the content of Ba as an additive in the inner layer 21, the content of Ba as an additive in the outer layer 22, and the content of Ba as an additive in the dielectric layer 14 are different from each other. In addition, the difference in the content of Ba can be confirmed by TEM analysis.

[0091] The Ba content in the inner layer 21 is adjusted so that the molar ratio of Ba to Ti1 is greater than 1.020 and less than 1.040 at the center value. The Ba content in the outer layer 22 is adjusted so that the molar ratio of Ba to Ti1 is greater than 1.01 and less than 1.020 at the center value. In addition, the Ba content in the dielectric layer 14 is adjusted so that the molar ratio of Ba to Ti1 is greater than 0.99 and less than 1.01 at the center value.

[0092] These molar ratios can be confirmed by scraping off the inner layer 21 , the outer layer 22 , or the vicinity of the surface of the dielectric layer 14 from the multilayer ceramic capacitor 1 , dissolving the obtained powder in an acid, and subjecting the solution to ICP analysis.

[0093] The content of Ba as an additive in the inner layer 21 is in a range of more than 100% and less than 140% relative to the content of Ba as an additive in the outer layer 22 .

[0094] (About the gap)

[0095] The side edge portion 20 is formed so that the number of voids decreases from the inner layer portion 11 side toward the side away from the inner layer portion 11. The outer layer 22 has fewer voids than the inner layer 21. Thus, it is possible to suppress moisture and the like from penetrating into the interior of the laminated body 2 through the side edge portion 20, thereby improving the moisture resistance reliability of the laminated ceramic capacitor 1.

[0096] (About additives)

[0097] The element of the additive contained in the inner layer 21 and the element of the additive contained in the outer layer 22 are preferably different from each other. In this case, the inner layer 21 can improve the adhesion between the side edge portion 20 and the inner layer portion 11, while the outer layer 22 can suppress the intrusion of moisture into the multilayer ceramic capacitor 1.

[0098] In addition, it is considered that sometimes it is impossible to visually distinguish the inner layer 21 and the outer layer 22. Even in such a case, the inner layer 21 and the outer layer 22 can be distinguished based on the difference in the type of element contained in each layer, the content of the element, and the like.

[0099] (Dimensions in the width direction W)

[0100] The dimension of the outer layer 22 in the width direction W is preferably larger than the dimension of the inner layer 21 in the width direction W. Thereby, the effect of suppressing the intrusion of water by the outer layer 22 can be made significant.

[0101] The width W of the outer layer 22 is preferably 5 μm or more and 20 μm, and the width W of the inner layer 21 is preferably 0.1 μm or more and 20 μm. This can effectively improve the adhesion between the side edge portion 20 and the inner layer portion 11 and improve the moisture resistance reliability of the laminated ceramic capacitor 1.

[0102] (External electrode 3)

[0103] The external electrode 3 includes a first external electrode 3A provided on the first end surface CA of the stacked body 2, and a second external electrode 3B provided on the second end surface CB of the stacked body 2. In addition, when there is no need to distinguish between the first external electrode 3A and the second external electrode 3B, they are collectively described as the external electrode 3. The external electrode 3 covers not only the end surface C, but also a portion of the main surface A and the side surface B on the end surface C side.

[0104] The external electrode 3 includes a base electrode layer 31 and a plating layer 32 (see Figure 2 ).

[0105] The base electrode layer 31 may include at least one of a sintered layer, a conductive resin layer, and a thin film layer. The base electrode layer 31 may be disposed at least on the end surface C and may not extend to the main surface A or the side surface B.

[0106] When the sintered layer is used as the base electrode layer 31, the sintered layer contains a glass component and a metal. The sintered layer will be described in detail later, but is formed by applying and sintering a conductive paste containing a conductive metal and glass.

[0107] The glass component of the sintered layer may also include an oxide, which includes at least one element selected from the group consisting of B, Si, Ba, Mg, Al, and Ti. The oxide is preferably SiO2, Al2O3, TiO2, BaO2, or ZrO2. The glass component of the sintered layer more preferably includes an oxide containing Ba or Ti, which is preferably BaO2 or TiO2. When the glass component includes BaO2 or TiO2, the content of impurities is small and the flexibility becomes excellent.

[0108] The metal of the sintered layer can be at least one metal selected from the group consisting of Cu, Ni, Ag, Pd, Ag-Pd alloy, and Au.

[0109] The thickness of the portion of the sintered layer disposed on the end surface C at the center in the stacking direction T (the dimension in the longitudinal direction L) is preferably 3 μm or more and 100 μm or less.

[0110] The thickness of the portion of the sintered layer disposed on the main surface A at the center in the longitudinal direction L (the dimension in the stacking direction T) is preferably 3 μm or more and 70 μm or less.

[0111] The thickness of the portion of the sintered layer disposed on the side surface B at the center portion in the longitudinal direction L is preferably 3 μm or more and 70 μm or less.

[0112] When the conductive resin layer is used as the base electrode layer 31 , the conductive resin layer contains a metal and a thermosetting resin.

[0113] The metal of the conductive resin layer is responsible for the conductivity of the conductive resin layer. The metal of the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these.

[0114] In addition, the metal of the conductive resin layer can also be obtained by coating the surface of the metal powder with Ag. In addition, the coated metal powder (parent material) is preferably Cu, Ni, Sn, Bi or an alloy containing them. In this case, the performance of the base electrode layer 31 can be improved by the characteristics of Ag such as low resistivity and difficulty in oxidation. In addition, the cost increase can be suppressed by using an inexpensive metal as a parent material.

[0115] Furthermore, the metal of the conductive resin layer may be Cu or Ni subjected to an oxidation prevention treatment.

[0116] The metal of the conductive resin layer may be obtained by coating the surface of metal powder with Si, Ni or Cu. The coated metal powder (base material) is preferably Ag, Cu, Ni, Sn, Bi or an alloy containing these.

[0117] The metal of the conductive resin layer can be, for example, spherical metal powder or flat metal powder. As the metal of the conductive resin layer, it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0118] The thermosetting resin imparts flexibility to the conductive resin layer. Thus, when a physical impact or a thermal cycle impact is applied to the multilayer ceramic capacitor 1, the conductive resin layer can function appropriately as a buffer layer. Therefore, the occurrence of cracks in the multilayer ceramic capacitor 1 can be suppressed.

[0119] The thermosetting resin can be various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. The thermosetting resin is preferably epoxy resin. Epoxy resin is excellent in heat resistance, moisture resistance, adhesion, etc., and thus can further improve the performance of the conductive resin layer.

[0120] The conductive resin layer preferably contains a curing agent. For example, when the thermosetting resin is an epoxy resin, the curing agent can be various known compounds such as phenol compounds, amine compounds, acid anhydride compounds, imidazole compounds, active ester compounds, and amide-imide compounds.

[0121] Regarding the conductive resin layer, the thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0122] In addition, the conductive resin layer may be directly provided on the laminate 2, or may be provided on the outside of the sintered layer after the sintered layer is provided on the laminate 2. When the conductive resin layer is provided on the outside of the sintered layer, the conductive resin layer may completely cover the outside of the sintered layer, or may only cover a portion of it.

[0123] The conductive resin layer may have a single-layer structure or a multi-layer structure.

[0124] When the base electrode layer 31 is a thin film layer, the thin film layer is a layer in which metal particles are deposited. The thin film layer has a thickness of 1 μm or less. The thin film layer is described in detail later, but is formed by a thin film forming method such as sputtering or vapor deposition.

[0125] The plating layer 32 includes, for example, at least one metal selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0126] The plating layer 32 includes a first plating layer 321 disposed on the base electrode layer 31 and a second plating layer 332 disposed on the first plating layer 321. The plating layer 32 does not need to be a two-layer structure, and may be a single-layer structure or a multi-layer structure of three or more layers.

[0127] The first plating layer 331 is preferably a Ni plating layer. In this case, when the multilayer ceramic capacitor 1 is mounted on the circuit board 50, the base electrode layer 31 can be prevented from being corroded by solder. The first plating layer 331 preferably has a thickness of 1 μm or more and 15 μm or less.

[0128] The second plating layer 332 is preferably a Sn plating layer. This improves solder wettability when the multilayer ceramic capacitor 1 is mounted on the circuit board 50, making it easier to mount the multilayer ceramic capacitor 1. The second plating layer 332 preferably has a thickness of 1 μm to 15 μm.

[0129] (covered area 4)

[0130] In the multilayer ceramic capacitor 1, water or the like may penetrate into the interior of the multilayer ceramic capacitor 1 through the boundary between the side edge portion 20 and the multilayer body piece 10. Therefore, the multilayer ceramic capacitor 1 includes a shielding region 4. In each figure, the shielding region 4 is shaded with dots.

[0131] The cover region 4 is made of an inorganic material. The inorganic material constituting the cover region 4 contains at least one element selected from the group consisting of Si, Ti, Ba and Zr. Thus, the compactness of the cover region 4 can be ensured, so that water and the like can be suppressed from penetrating the cover region 4. In addition, the inorganic material constituting the cover region 4 is preferably Si. Thus, the effect of improving moisture resistance can be obtained by sintering at a lower temperature.

[0132] The masking region 4 includes a first masking region 4A and a second masking region 4B. Hereinafter, the first masking region 4A and the second masking region 4B may be collectively referred to as "masking region 4" when there is no need to distinguish them in particular.

[0133] The first masking region 4A is in a band shape and is arranged to cross the boundary between the first side edge portion 20A and the outer layer portion 12 on the main surface A of the laminate 2, and is arranged to cross the boundary between the first side edge portion 20A and the inner layer portion 11 on the end surface C of the laminate 2. The first masking region 4A is in a ring shape that surrounds the longitudinal direction L (see Figure 4 ). The first covering region 4A covers the entire region of the boundary between the first side edge portion 20A and the outer layer portion 12. The first covering region 4A covers the entire region of the boundary between the first side edge portion 20A and the inner layer portion 11.

[0134] The second covering area 4B is in a band shape, and is arranged to cross the boundary between the second side edge portion 20B and the outer layer portion 12 on the outer surface of the laminate 2, and is arranged to cross the boundary between the second side edge portion 20B and the inner layer portion 11 on the end surface C of the laminate 2. The second covering area 4B is in a ring shape that surrounds along the length direction L. The second covering area 4B covers the boundary between the second side edge portion 20B and the outer layer portion 12 over the entire area. The second covering area 4B covers the boundary between the second side edge portion 20B and the inner layer portion 11 over the entire area.

[0135] This can prevent moisture and the like from penetrating into the interior of the multilayer ceramic capacitor 1 through the boundary between the side edge portion 20 and the small multilayer body piece 10 , thereby improving the moisture resistance reliability of the multilayer ceramic capacitor 1 .

[0136] The thickness of first cover region 4A is preferably 1 μm to 10 μm. The thickness of second cover region 4B is preferably 1 μm to 10 μm. This can improve the moisture resistance reliability of multilayer ceramic capacitor 1 and reduce the height of multilayer ceramic capacitor 1.

[0137] The first end surface CA has a first non-covered portion CAa which is not covered by any of the first cover region 4A and the second cover region 4B. The first end surface CA is connected to the first external electrode 3A at the first non-covered portion CAa.

[0138] The second end surface CB has a second uncovered portion CBa which is not covered by any of the first cover region 4A and the second cover region 4B. The second end surface CB is connected to the second external electrode 3B at the second uncovered portion CBa.

[0139] In addition, hereinafter, the first non-covered portion CAa and the second non-covered portion CBa may be collectively referred to as “non-covered portion Ca” when there is no need to distinguish them in particular.

[0140] The dimension of the first cover region 4A in the width direction W is preferably not less than 10% of the dimension of the stack 2 in the width direction W and not more than 20% of the dimension of the stack 2 in the width direction W. The dimension of the second cover region 4B in the width direction W is preferably not less than 10% of the dimension of the stack 2 in the width direction W and not more than 20% of the dimension of the stack 2 in the width direction W. Thus, while the connection between the end face C and the external electrode 3 is sufficiently ensured, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be improved.

[0141] In addition, the shape of the boundary line between the masking area 4 and the laminate 2 is not particularly limited. Sometimes, the boundary line between the masking area 4 and the laminate 2 can be confirmed by observing the masking area 4 and the laminate 2 under a dark field using an optical microscope. In the case where the boundary line can be confirmed, the masking area 4 can also be identified as a masking layer. On the other hand, sometimes the masking area 4 and the laminate 2 are integrated, so that the boundary line between the masking area 4 and the laminate 2 cannot be confirmed. In this case, the main surface A and the side surface B of the laminate 2 are respectively regarded as flat surfaces, and it is judged that the portion protruding from these flat surfaces is the masking area 4.

[0142] (Method for manufacturing multilayer ceramic capacitor)

[0143] Next, refer to Figure 5 to Figure 7 A method for manufacturing the multilayer ceramic capacitor 1 will be described. Figure 5 to Figure 7 Each of them is a diagram showing a manufacturing process of a multilayer ceramic capacitor.

[0144] The manufacturing process of the multilayer ceramic capacitor 1 includes a multilayer body manufacturing process, a cover region forming process, and an external electrode forming process.

[0145] (Laminate manufacturing process)

[0146] The laminate production step includes a laminate small piece production step and a side edge portion forming step.

[0147] (Laminate small piece manufacturing process)

[0148] First, a ceramic green sheet for lamination is prepared by forming a ceramic slurry into a sheet. The ceramic green sheet for lamination includes a ceramic raw material including a dielectric ceramic material, a binder, and a solvent. An additive including a rare earth element may also be added to the ceramic raw material. By changing the elements included in the additive, the compositions of the dielectric layer 14, the outer layer portion 12, and the side edge portion 20 can be made different from each other.

[0149] On the laminated ceramic green sheet, a conductive paste to be an internal electrode layer is printed. The conductive paste is printed on the surface of the laminated ceramic green sheet so that a plurality of stripes are arranged in the width direction of the stripes. In addition, as a printing method of the conductive paste, for example, a screen printing method or a gravure printing method can be used.

[0150] The ceramic green sheets without the conductive paste printed thereon are stacked a predetermined number of times. Next, the ceramic green sheets printed with the conductive paste are alternately staggered in the arrangement direction in which the conductive pastes are printed side by side and stacked a predetermined number of times. Next, the ceramic green sheets without the conductive paste printed thereon are stacked a predetermined number of times. Thus, a mother laminate is obtained.

[0151] The mother laminate is pressed. As a method for pressing the mother laminate, for example, a method such as rigid body pressing or isostatic pressing can be used.

[0152] The pressed mother laminate is cut into small pieces. Figure 5 As shown in (a), a small laminated body piece 10 is obtained. As a method of cutting the mother laminated body, for example, a method such as press cutting, scribing, or laser cutting can be used.

[0153] In addition, only the conductive paste that becomes the first internal electrode layer 15A among the internal electrode layers 15 is exposed at one of the pair of end faces of the laminated body small piece 10, and only the conductive paste that becomes the second internal electrode layer 15B among the internal electrode layers 15 is exposed at the other end face. The conductive paste that becomes the first internal electrode layer 15A and the conductive paste that becomes the second internal electrode layer 15B are both exposed at the pair of side faces of the laminated body small piece 10. At the pair of side faces of the laminated body small piece 10, the ends of these conductive pastes on the side faces of the laminated body small piece 10 are flush with the side faces of the laminated body small piece 10.

[0154] (Side edge forming process)

[0155] The ceramic slurry for the inner layer is used to make the ceramic green sheet for the inner layer. The ceramic slurry for the inner layer contains a dielectric ceramic material with BaTiO3 as the main component, a binder, and a solvent. Si as a sintering aid can also be added to the ceramic slurry for the inner layer. In addition, a liquid phase type metal can also be added to the ceramic slurry for the inner layer. It is also possible to add more rare earth elements, Mg, and Mn to the ceramic slurry for the inner layer than to the ceramic green sheet used to form the laminated body small piece 10.

[0156] The outer layer ceramic slurry is used to prepare the outer layer ceramic green sheet. The outer layer ceramic slurry contains a dielectric ceramic material mainly composed of BaTiO3, a binder, and a solvent. Si can also be added to the outer layer ceramic slurry as a sintering aid.

[0157] In addition, the Si contained in the inner layer ceramic sheet is preferably greater than the Si contained in the outer layer ceramic sheet. The cross-sections of the inner layer ceramic sheet and the outer layer ceramic sheet are photographed by WDX, and the amount of Si contained in the inner layer ceramic sheet and the outer layer ceramic sheet is determined based on the size of the area where Si is detected.

[0158] The outer layer ceramic slurry is applied to the surface of the resin film and dried. Thus, the outer layer ceramic green sheet 22a is formed on the resin film. The inner layer ceramic slurry is applied to the surface of the outer layer ceramic green sheet and dried. Thus, the inner layer ceramic green sheet 21a is formed on the outer layer ceramic green sheet. Figure 5 As shown in (b), a side edge ceramic green sheet 20a having a two-layer structure is obtained.

[0159] Alternatively, the side edge ceramic green sheet 20a having a two-layer structure may be obtained by, for example, bonding together the outer layer ceramic green sheet 22a and the inner layer ceramic green sheet 21a which are formed separately in advance.

[0160] The side edge ceramic green sheet 20a is peeled off from the resin film.

[0161] The side edge ceramic green sheet 20a is pressed against the laminated body small sheet 10 and punched through the laminated body small sheet 10 in a state where the surface on the inner layer side faces the surface on the side B side of the laminated body small sheet 10. Thus, the side edge portion 20 is formed on the laminated body small sheet 10. Figure 5 As shown in (c), a laminate 2 is obtained. In addition, it is preferable that an organic solvent serving as an adhesive is applied in advance to the side surfaces of the small laminate pieces 10 .

[0162] It is preferable to perform barrel polishing or the like on the laminated body 2. Thereby, the corners and ridges of the laminated body 2 are rounded.

[0163] The laminate 2 is degreased in a nitrogen atmosphere. Next, the laminate 2 is fired in a mixed atmosphere of nitrogen, hydrogen, and water vapor. The temperature when firing the laminate 2 is preferably, for example, 900° C. or higher and 1300° C. or lower.

[0164] (Masking area forming process)

[0165] First, if Figure 6 As shown in (a) of FIG. 1 , the laminate 2 is in a state where the second side surface BB faces downward.

[0166] like Figure 6 As shown in (b), a paste bath filled with a masking area paste P that becomes a masking area 4 is prepared. The masking area paste P contains at least one of Si, Ti, Ba, and Zr as an inorganic material. The laminate 2 is immersed in the masking area paste P with the second side surface BB facing downward. At this time, a portion of the second side surface BB side of the laminate 2 is immersed in the masking area paste P, and in detail, at least a portion of the laminate 2 including the boundary between the laminate small piece 10 and the second side edge portion 20B is immersed in the masking area paste P. At this time, by adjusting the depth of immersion of the laminate 2 in the masking area paste P, the dimension of the width direction W of the masking area 4 can be adjusted.

[0167] like Figure 6 As shown in (c), the laminate 2 is lifted from the paste bath filled with the masking area paste P. The laminate 2 is set in a state where the masking area paste P is applied to the entire area of ​​the second side surface BB, a portion of the second side surface BB side of the main surface A, and a portion of the second side surface BB side of the end surface C. The masking area paste P is configured to span the boundary between the second side edge portion 20B and the outer layer portion 12. The masking area paste P is configured to span the boundary between the second side edge portion 20B and the inner layer portion 11.

[0168] like Figure 7 As shown in (a), unnecessary portions of the masking area paste P arranged on the laminate 2 are scraped off. For example, the masking area paste P arranged on the second side BB is scraped off. In addition, the thickness of the masking area 4 and the dimensions in the width direction W are adjusted to the desired dimensions. In addition, the scraping off of the masking area paste P is not necessary and can be performed as needed. Next, the masking area paste P is dried to form the second masking area 4B. The drying temperature and drying time at this time are appropriately set according to the type of masking area paste P. Based on the above, the second masking area 4B is formed on the laminate 2. In addition, Figure 7 The orientation of the stacked body 2 in (a) is set so that Figure 6 The laminated body 2 of (c) is rotated 180 degrees about the longitudinal direction L as an axis.

[0169] Thereafter, the above-mentioned process in the masking region forming process is performed again by changing the orientation of the stacked body 2, thereby forming the first masking region 4A on the first side surface BA side of the stacked body 2. Figure 7 As shown in (b), the first cover region 4A and the second cover region 4B are formed on the laminate 2. In addition, the order of forming the first cover region 4A and the second cover region 4B on the laminate 2 is not limited to the above order. In addition, Figure 7 The orientation of the laminate 2 in (b) is set so that Figure 7 The laminated body 2 of (a) is rotated 180 degrees about the longitudinal direction L as an axis.

[0170] (External electrode forming process)

[0171] First, a base electrode layer 31 is formed on the end face C of the stack 2. For example, the base electrode layer 31 is formed as a sintered layer. The end face C of the stack 2 is sequentially immersed in a conductive paste as an electrode material for the base electrode. Thus, the conductive paste is applied to the end faces C of the stack 2. Thereafter, these conductive pastes are fired together with the stack 2. The firing temperature is, for example, set to 700° C. or more and 900° C. or less. Thus, the base electrode layer 31 is formed on the end faces C of the stack 2. The end face of the stack 2 and the base electrode layer 3 are connected in the non-covered portion Ca.

[0172] The sintered layer may contain a ceramic component. In this case, the sintered layer may contain a ceramic component instead of a glass component, or may contain both a glass component and a ceramic component. In addition, the ceramic component is preferably the same as that of the laminate 2. In addition, when the sintered layer contains a ceramic component, it is preferred that a conductive paste for the base electrode is applied to the laminate 2 before firing, and the laminate 2 and the conductive paste for the base electrode are fired simultaneously. The firing temperature is preferably set to 900° C. or more and 1300° C. or less.

[0173] Next, the first plating layer 321 is formed on the base electrode layer 31. The first plating layer 321 is formed so that the end portions on the main surface A and the side surface B of the first plating layer 321 cover the end portions on the main surface A and the side surface B of the base electrode layer 31. The first plating layer 321 is, for example, a Ni plating layer. The first plating layer 321 can be formed, for example, by a barrel plating method.

[0174] Next, the second plating layer 332 is formed on the first plating layer 32. The second plating layer 332 is formed so that the end portions on the main surface A and the side surface B of the second plating layer 332 cover the end portions on the main surface A and the side surface B of the first plating layer 321 and the adhesion relaxation layer 35. The second plating layer 322 is, for example, a Sn plating layer. The second plating layer 332 can be formed, for example, by a barrel plating method.

[0175] After the above process, Figure 7 As shown in (c), the multilayer ceramic capacitor 1 in which the external electrodes 3 are formed on the multilayer body 2 is manufactured.

[0176] In addition, the base electrode layer 31 may be formed as a conductive resin layer. The conductive resin layer may be formed on the surface of the sintered layer or directly on the surface of the laminate 2.

[0177] First, a conductive paste containing a thermosetting resin and a metal component is applied to the sintered layer or the laminate 2. Then, a heat treatment is performed at a temperature of 250°C or more and 550°C or less. Thus, the thermosetting resin is cured to form a conductive resin layer. The atmosphere during the heat treatment is preferably a nitrogen atmosphere. During the heat treatment, the oxygen concentration is preferably set to 100 ppm or less. Thus, the scattering of the resin can be suppressed, and the oxidation of the metal can be suppressed.

[0178] The base electrode layer 31 may be formed as a thin film layer. In this case, a layer of deposited metal particles is formed by a thin film forming method such as sputtering or evaporation. Thus, a thin film layer is formed. The thickness of the thin film layer is set to 1 μm or less.

[0179] In addition, the base electrode layer 31 is not a necessary structure, and a plated layer can also be formed directly on the laminate 2. In this case, a base plated film is formed on the end surface C of the laminate 2 by plating. The plating process can be an electrolytic plating method or an electroless plating method. However, the electrolytic plating method is preferably used for the plating process in that the process is simpler. The plating method is preferably a drum plating method. In addition, a plated electrode can be further formed on the surface of the plated layer in the same way as needed.

[0180] (Effect)

[0181] According to the above-described embodiment, the following effects can be obtained.

[0182] According to the above embodiment, the first cover region 4A is made of an inorganic material and is arranged to straddle the boundary between the first side edge portion 20A and the outer layer portion 12 on the outer surface of the laminate 2. The second cover region 4B is made of an inorganic material and is arranged to straddle the boundary between the second side edge portion 20B and the outer layer portion 12 on the outer surface of the laminate 2. Thus, moisture can penetrate into the interior of the laminated ceramic capacitor 1 through the boundary between the side edge portion 20 and the outer layer portion 12, and the moisture resistance reliability of the laminated ceramic capacitor 1 can be improved.

[0183] According to the above embodiment, the inorganic material constituting the cover region 4 contains at least one element selected from the group consisting of Si, Ti, Ba and Zr. As a result, the density of the cover region 4 can be improved. Therefore, it is possible to appropriately suppress the infiltration of moisture into the interior of the multilayer ceramic capacitor 1, so that the moisture resistance reliability of the multilayer ceramic capacitor 1 can be appropriately improved.

[0184] According to the above embodiment, the first covering area 4A is in the shape of a ring surrounding the length direction L. The second covering area 4B is in the shape of a ring surrounding the length direction L. In this case, the covering area 4 can cover the boundary between the side edge portion 20 and the outer layer portion 12 throughout the entire area. In addition, the boundary between the side edge portion 20 and the inner layer portion 11 can also be covered throughout the entire area. Thus, it is possible to appropriately suppress the infiltration of moisture into the interior of the multilayer ceramic capacitor, and thus it is possible to appropriately improve the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0185] According to the above embodiment, the thickness of the first cover region 4A is preferably 1 μm or more and 10 μm or less. The thickness of the second cover region 4B is preferably 1 μm or more and 10 μm or less. In this case, the height of the multilayer ceramic capacitor 1 can be reduced while improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0186] According to the above embodiment, the dimension of the first cover region 4A in the width direction W is preferably not less than 10% of the dimension of the width direction W of the laminate 2 and not more than 20% of the dimension of the width direction W of the laminate 2. The dimension of the second cover region 4B in the width direction W is preferably not less than 10% of the dimension of the width direction W of the laminate 2 and not more than 20% of the dimension of the width direction W of the laminate 2. In this case, while the connection between the end face C and the external electrode 3 is sufficiently ensured, the moisture resistance reliability of the laminated ceramic capacitor 1 can be improved.

[0187] According to the above embodiment, the dimension of the first side edge portion 20A in the width direction W is preferably 5 μm or more and 40 μm or less. The dimension of the second side edge portion 20B in the width direction W is preferably 5 μm or more and 40 μm or less. In this case, the capacity of the multilayer ceramic capacitor 1 can be increased while improving the moisture resistance reliability of the multilayer ceramic capacitor 1.

[0188] In the side edge portion 20, for example, in order to reliably fix the side edge portion 20 to the inner layer portion 11, it is desirable that the surface of the side edge portion 20 on the inner layer portion 11 side has high adhesion to the inner layer portion 11. The surface of the side edge portion 20 on the side opposite to the inner layer portion 11 side does not need to have close adhesion to the inner layer portion 11, and on the other hand, it is desirable to be able to appropriately suppress the intrusion of moisture into the laminated ceramic capacitor 1. In this way, the side edge portion 20 has different functions required of the portion on the inner layer portion 11 side and the portion on the side away from the inner layer portion 11.

[0189] According to the above embodiment, the side edge portion 20 is composed of two layers, and each of the two layers includes an inner layer 21 disposed on the inner layer portion 11 side and an outer layer 22 disposed on the side away from the inner layer portion 11. Therefore, for example, by making the amount of resin contained in the inner layer 21 and the outer layer 22 different, different properties can be given to the inner layer 21 and the outer layer 22. Thus, for example, while the inner layer 21 improves the adhesion between the side edge portion 20 and the inner layer 11, the outer layer 22 can appropriately suppress the infiltration of moisture into the inner layer 11.

[0190] According to the above embodiment, the element as an additive of the inner layer 21 and the element as an additive of the outer layer 22 are preferably different from each other. In this case, different properties can be imparted to the inner layer 21 and the outer layer 22, respectively, so that the side edge portion 20 can be more highly functionalized.

[0191] According to the above embodiment, the dimension of the outer layer 22 in the width direction W is preferably larger than the dimension of the inner layer 21 in the width direction W. In this case, the effect of suppressing the intrusion of water by the outer layer 22 can be made significant.

[0192] According to the above embodiment, the dimension of the width direction W of the inner layer 21 is preferably 0.1 μm or more and 20 μm or less. The dimension of the width direction W of the outer layer 22 is preferably 5 μm or more and 20 μm or less. In this case, the adhesion between the side edge portion 20 and the inner layer portion 11 can be effectively improved, and the moisture resistance reliability of the laminated ceramic capacitor 1 can be improved.

[0193] According to the above embodiment, the thickness of each internal electrode layer 15 is preferably 0.8 μm or less. In this case, the number of laminated sheets 2 can be increased even with the same size, so the capacitance of the laminated ceramic capacitor 1 can be ensured.

[0194] According to the above embodiment, the thickness of each dielectric layer 14 is preferably 0.55 μm or less. In this case, the number of laminated sheets 2 can be increased even with the same size, so the capacitance of the laminated ceramic capacitor 1 can be ensured.

[0195] (Experimental example)

[0196] Using the manufacturing method involved in the above-mentioned embodiment, a laminated ceramic capacitor was produced as a sample. A moisture resistance test was performed on the sample. As an example, a laminated ceramic capacitor having a first covering area and a second covering area was prepared. As a comparative example, a laminated ceramic capacitor not having either the first covering area or the second covering area was prepared.

[0197] 50 samples of each of the examples and comparative examples were prepared.

[0198] A moisture resistance test was conducted based on the PCBT test method. More specifically, each sample was mounted on a wiring board using eutectic solder, placed in a high temperature and high humidity tank at 125[°C] and 95[%RH], and a 2[V] DC current was applied between a pair of external electrodes, and this state was maintained for 72 hours. In addition, samples whose insulation resistance values ​​dropped by more than two digits before and after the test were judged as "defective".

[0199] (Structure of Embodiment)

[0200] · Dimensions of multilayer ceramic capacitors: L×W×T=1.0mm×0.5mm×0.5mm

[0201] Ceramic material of dielectric layer: BaTiO3

[0202] Capacitance: 22μF

[0203] Rated voltage: 4V

[0204] Metal material of internal electrode layer: Ni

[0205] ·Construction of external electrodes:

[0206] Base electrode layer: sintered layer

[0207] Material of base electrode layer: Electrode containing conductive metal (Cu) and glass components

[0208] Thickness of base electrode layer:

[0209] End face thickness: 20 μm (thickness at the center of the height direction of the base electrode layer disposed on the end face C)

[0210] Main surface thickness: 0.25 μm (thickness at the center of the base electrode layer arranged on the main surface A in the longitudinal direction)

[0211] Plating layer: 2-layer structure of Ni plating and Sn plating

[0212] Ni plating thickness:

[0213] End face thickness: 4 μm (thickness at the center of the height direction of the Ni plating layer disposed on the end face C)

[0214] Main surface thickness: 4 μm (thickness of the Ni plating layer disposed on the main surface A at the center in the longitudinal direction)

[0215] Sn plating thickness:

[0216] End face thickness: 4 μm (thickness at the center of the height direction of the Sn plating layer disposed on the end face C)

[0217] Main surface thickness: 4 μm (thickness at the center of the Sn plating layer arranged on the main surface A in the longitudinal direction)

[0218] · Structure of the first covering area and the second covering area

[0219] Material of the first and second covering areas: SiO2

[0220] Thickness of the first and second masking regions: 5 μm

[0221] Width dimension of the first masking area: 15% of the width dimension of the laminate

[0222] The width dimension of the second masking area is 15% of the width dimension of the laminate.

[0223] (Structure of Comparative Example)

[0224] The comparative example has the same configuration as that of the example, except that it does not include any of the first masking region and the second masking region.

[0225] (result)

[0226] In the case of the example, 0 out of 50 samples were defective. In the case of the comparative example, 4 out of 50 samples were defective.

[0227] Comparison between the examples and the comparative examples shows that the moisture resistance reliability of the multilayer ceramic capacitor is improved by providing the multilayer ceramic capacitor with the cover region.

[0228] (Deformation method)

[0229] As mentioned above, although the preferred embodiment of the present invention was described, the present invention is not limited thereto, and includes the following scope.

[0230] The multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a multiple-layer structure. Figure 8 The structure of the multilayer ceramic capacitor 1 will be described. Figure 8 FIG. 1 is a diagram showing the structure of a multilayer ceramic capacitor 1 according to a modified example. Figure 2 The corresponding figure.

[0231] like Figure 8 As shown, the multilayer ceramic capacitor 1 may include a floating internal electrode layer 16 which is not extended to either the first end face CA or the second end face CB in addition to the first internal electrode layer 15A and the second internal electrode layer 15B.

[0232] For example, Figure 8 The multilayer ceramic capacitor 1 shown in (a) is a multilayer ceramic capacitor of a two-layer structure including a first floating internal electrode layer 16A as the floating internal electrode layer 16 . Figure 8 The multilayer ceramic capacitor 1 shown in (b) is a multilayer ceramic capacitor of a triple structure including a first floating internal electrode layer 16A and a second floating internal electrode 16B as floating internal electrode layers 16 . Figure 8 The multilayer ceramic capacitor 1 shown in (c) is a multilayer ceramic capacitor of a quadruple structure including a first floating internal electrode layer 16A, a second floating internal electrode 16B, and a floating internal electrode 16C as floating internal electrode layers 16 .

[0233] The multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into a plurality of parts by providing a floating internal electrode layer 16. Thus, a plurality of capacitor components are formed between the opposing internal electrode layers, and the capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the multilayer ceramic capacitor 1 can achieve a high withstand voltage. In addition, the multilayer ceramic capacitor 1 can also be a multi-unit structure of 4 or more units.

[0234] In the above embodiment, the first cover area 4A and the second cover area 4B are both formed in an annular shape, but the present invention is not limited thereto. The first cover area and the second cover area may be configured to at least cross the boundary between the side edge portion and the outer layer portion. However, from the viewpoint of further improving the moisture resistance reliability, the first cover area and the second cover area are preferably configured to also cross the boundary between the side edge portion and the inner layer portion, and more preferably each is formed in an annular shape.

[0235] In the above-mentioned embodiment, the laminated ceramic capacitor 1 uses dielectric ceramics, but is not limited to this. For example, the laminated ceramic capacitor may use piezoelectric ceramics, semiconductor ceramics, or magnetic ceramics. When piezoelectric ceramics are used, the laminated ceramic capacitor functions as a piezoelectric component. As piezoelectric ceramics, PZT-based ceramics and the like can be cited. When semiconductor ceramics are used, the laminated ceramic capacitor functions as a thermistor. As semiconductor ceramics, spinel-based ceramics and the like can be cited. When magnetic ceramics are used, the laminated ceramic capacitor functions as an inductor. As magnetic ceramics, ferrites and the like can be cited.

[0236] As mentioned above, although the preferred embodiment and the modification of this invention were described, it is not limited to these, and this invention includes the following scope.

[0237] <1> A laminated ceramic capacitor comprises: a laminated body, comprising an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, the laminated body having a pair of main surfaces opposed to each other in a lamination direction, a pair of end surfaces opposed to each other in a length direction orthogonal to the lamination direction, and a pair of side surfaces opposed to each other in a width direction orthogonal to either the lamination direction and the length direction; and a pair of external electrodes, respectively arranged on each of the end surfaces and connected to the internal electrode layers, wherein the laminated body comprises a pair of side edge portions respectively arranged on both sides of the width direction of the inner layer portion, and an outer layer portion respectively arranged on both sides of the lamination direction of the inner layer portion and respectively arranged to be sandwiched by each of the side edge portions, wherein the laminated body comprises a pair of side edge portions respectively arranged on both sides of the lamination direction of the inner layer portion, The pair of side surfaces are the first side surface and the second side surface, the pair of side edge portions are the first side edge portion arranged on the first side surface and the second side edge portion arranged on the second side surface, and the stacked ceramic capacitor comprises: a first covering region, composed of an inorganic material, arranged on the outer surface of the stacked body and arranged to cross the boundary between the first side edge portion and each of the outer layer portions; and a second covering region, composed of an inorganic material, arranged on the outer surface of the stacked body and arranged to cross the boundary between the second side edge portion and each of the outer layer portions, each of the end faces respectively has a non-covered portion that is not covered by either the first covering region or the second covering region, and each of the non-covered portions is connected to each of the external electrodes respectively.

[0238] <2> exist <1> In the multilayer ceramic capacitor,

[0239] The inorganic material contains at least one element selected from the group consisting of Si, Ti, Ba, and Zr.

[0240] <3> exist <1> or <2> In the multilayer ceramic capacitor,

[0241] The first covering area is in a ring shape surrounding the length direction, and the second covering area is in a ring shape surrounding the length direction.

[0242] <4> exist <1> ~ <3> In any one of the multilayer ceramic capacitors,

[0243] The thickness of the first masking region is greater than or equal to 1 μm and less than or equal to 10 μm, and the thickness of the second masking region is greater than or equal to 1 μm and less than or equal to 10 μm.

[0244] <5> exist <1> ~ <4> In any one of the multilayer ceramic capacitors,

[0245] The stacked ceramic capacitor is roughly rectangular in shape, the dimension of the first covering area in the width direction is greater than 10% and less than 20% of the dimension of the stacked body in the width direction, and the dimension of the second covering area in the width direction is greater than 10% and less than 20% of the dimension of the stacked body in the width direction.

[0246] <6> exist <1> ~ <5> In any one of the multilayer ceramic capacitors,

[0247] The dimension of the first side edge portion in the width direction is greater than or equal to 5 μm and less than or equal to 40 μm, and the dimension of the second side edge portion in the width direction is greater than or equal to 5 μm and less than or equal to 40 μm.

[0248] <7> exist <1> ~ <6> In any one of the multilayer ceramic capacitors,

[0249] Each of the side edge portions is composed of a plurality of layers, and includes an inner layer disposed closest to the inner layer portion among the plurality of layers, and an outer layer disposed farthest from the inner layer portion among the plurality of layers.

[0250] <8> exist <7> In the multilayer ceramic capacitor,

[0251] The inner layer and the outer layer are both made of ceramics, and each includes dielectric ceramic particles and an element as an additive existing between the dielectric ceramic particles. The element as the additive in the inner layer and the element as the additive in the outer layer are different from each other.

[0252] <9> exist <7> or <8> In the multilayer ceramic capacitor,

[0253] The width dimension of the outer layer is greater than the width dimension of the inner layer.

[0254] <10> exist <9> In the multilayer ceramic capacitor,

[0255] The dimension of the inner layer in the width direction is greater than or equal to 0.1 μm and less than or equal to 20 μm, and the dimension of the outer layer in the width direction is greater than or equal to 5 μm and less than or equal to 20 μm.

[0256] <11> exist <1> ~ <10> In any one of the multilayer ceramic capacitors,

[0257] The thickness of each of the internal electrode layers is 0.8 μm or less.

[0258] <12> exist <11> In the multilayer ceramic capacitor,

[0259] The thickness of each of the dielectric layers is 0.55 μm or less.

[0260] Description of Reference Numerals

[0261] 1 Multilayer Ceramic Capacitors

[0262] 2 Laminated body

[0263] 3 External electrodes

[0264] 4A 1st Covering Area

[0265] 4B Second Covering Area

[0266] 11 Inner layer

[0267] 12 Outer layer

[0268] 14 Dielectric layer

[0269] 15 Internal electrode layer

[0270] 20 Side edge

[0271] 20A 1st side edge

[0272] 20B Second side edge

[0273] 21 Inner layer

[0274] 21A 1st inner layer

[0275] 21B 2nd inner layer

[0276] 22 Outer layer

[0277] 22A 1st outer layer

[0278] 22B 2nd outer layer

[0279] A main surface

[0280] B Side

[0281] BA Side 1

[0282] BB Side 2

[0283] C end face

[0284] Ca uncoated part.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and having a pair of main surfaces opposed to each other in a lamination direction, a pair of end surfaces opposed to each other in a length direction orthogonal to the lamination direction, and a pair of side surfaces opposed to each other in a width direction orthogonal to either the lamination direction or the length direction; and a pair of external electrodes, respectively disposed on each of the end surfaces and connected to the internal electrode layer; in, The stacked body has a pair of side edge portions respectively arranged on both sides of the inner layer portion in the width direction, and a pair of outer layer portions respectively arranged on both sides of the inner layer portion in the stacking direction and respectively arranged to be sandwiched by the side edge portions. The pair of side surfaces are a first side surface and a second side surface, The pair of side edges are a first side edge disposed on the first side surface and a second side edge disposed on the second side surface. The multilayer ceramic capacitor comprises: a first covering region, which is made of an inorganic material and is disposed on the outer surface of the stacked body and is disposed so as to straddle the boundary between the first side edge portion and each of the outer layer portions; and The second masking region is made of an inorganic material and is disposed on the outer surface of the stacked body and is disposed across the boundary between the second side edge portion and each of the outer layer portions. Each of the end faces has a non-covered portion that is not covered by any one of the first covering region and the second covering region, and is connected to each of the external electrodes at each of the non-covered portions.

2. The multilayer ceramic capacitor according to claim 1, wherein The inorganic material contains at least one element selected from the group consisting of Si, Ti, Ba, and Zr.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The first covering area is in a ring shape surrounding along the length direction, The second covering area is in a ring shape surrounding along the length direction.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The thickness of the first masking region is greater than or equal to 1 μm and less than or equal to 10 μm. The second masking region has a thickness of not less than 1 μm and not more than 10 μm.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The multilayer ceramic capacitor is substantially in the shape of a rectangular parallelepiped. The dimension of the first covering area in the width direction is not less than 10% of the dimension of the stack in the width direction and not more than 20% of the dimension of the stack in the width direction. A dimension of the second covering region in the width direction is not less than 10% of a dimension of the stacked body in the width direction and not more than 20% of a dimension of the stacked body in the width direction.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein The dimension of the first side edge portion in the width direction is 5 μm or more and 40 μm or less, A dimension of the second side edge portion in the width direction is not less than 5 μm and not more than 40 μm.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein Each of the side edge portions is composed of a plurality of layers, and includes an inner layer disposed closest to the inner layer portion among the plurality of layers, and an outer layer disposed farthest from the inner layer portion among the plurality of layers.

8. The multilayer ceramic capacitor according to claim 7, wherein: The inner layer and the outer layer are both made of ceramics, and each includes dielectric ceramic particles and an element as an additive existing between the dielectric ceramic particles. The element as the additive of the inner layer and the element as the additive of the outer layer are different from each other.

9. The multilayer ceramic capacitor according to claim 7 or 8, wherein: The width dimension of the outer layer is greater than the width dimension of the inner layer.

10. The multilayer ceramic capacitor according to claim 9, wherein The dimension of the inner layer in the width direction is 0.1 μm or more and 20 μm or less, The dimension of the outer layer in the width direction is 5 μm or more and 20 μm or less.

11. The multilayer ceramic capacitor according to any one of claims 1 to 10, wherein The thickness of each of the internal electrode layers is 0.8 μm or less.

12. The multilayer ceramic capacitor according to claim 11, wherein The thickness of each of the dielectric layers is 0.55 μm or less.

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