Manufacturing method of semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device according to one embodiment of the present invention may comprise the steps of: forming an insulating layer; forming a barrier layer on the insulating layer; performing a nitriding process on the barrier layer; and forming a metal electrode on the barrier layer. In one embodiment of the present invention, the step of performing the nitriding process may include a step of performing a high pressure nitriding (HPN) process. According to the embodiment of the invention, in the manufacturing process of the semiconductor device, the electrical characteristics of the barrier layer and the metal electrode can be improved by improving the quality of the barrier layer, so that the electrical characteristics of the semiconductor device can be improved.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] Semiconductor devices are mainly used as components of devices similar to electronic circuits that utilize the conductive properties of semiconductors. Semiconductors can be divided into memory semiconductors and non-memory semiconductors. Memory semiconductors can be divided into volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM) and non-volatile memories such as mask read-only memory (Mask ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory.

[0003] Figure 1 Shows the structure of a general semiconductor device.

[0004] Reference Figure 1 The semiconductor device may include: an insulating layer 12 formed on a substrate 11 having a prescribed structure; and a metal electrode 14 formed on the insulating layer 12 .

[0005] Illustratively, the metal electrode 14 may include metal materials such as aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and ruthenium (Ru). As metal ions, oxygen, or moisture contained in the metal electrode 14 diffuse into the insulating layer 12, the insulating layer 12 may be contaminated or have spikes. In order to prevent such problems, a barrier layer 13 that acts as a barrier may be formed between the insulating layer 12 and the metal electrode 14 during the semiconductor manufacturing process. The barrier layer 13 may include a metal material (e.g., Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0006] However, after forming the barrier layer 13, if the metal electrode 14 is formed on the upper portion of the barrier layer 13, there arises a problem that the conformality of the barrier layer 13 is reduced and foreign matter (for example, H2 or D2) exists inside the barrier layer 13. The reduction in electrical characteristics due to the reduction in the quality of the barrier layer 13 may lead to the reduction in electrical characteristics of the metal electrode 14. Therefore, there arises a problem that the electrical characteristics of the semiconductor device are reduced. Summary of the invention

[0007] Technical issues

[0008] The object of the present invention is to provide a method for manufacturing a semiconductor device, that is, in the process of manufacturing the semiconductor device, the electrical properties of the barrier layer and the metal electrode can be improved by improving the quality of the barrier layer.

[0009] The purpose of this specification is not limited to the above purpose, and other purposes and advantages of this specification not mentioned are more clearly understood through the embodiments of this specification described below. In addition, the purposes and advantages of this specification can be achieved through the structural elements and their combinations recorded in the scope of the patent application.

[0010] Technical Solution

[0011] According to an embodiment of the present invention, a method for manufacturing a semiconductor device may include the following steps: forming an insulating layer; forming a barrier layer on the insulating layer; performing a nitridation process on the barrier layer; and forming a metal electrode on the barrier layer.

[0012] In one embodiment of the present invention, the step of performing the nitridation process may include the step of performing a high pressure nitridation (HPN) process.

[0013] In one embodiment of the present invention, the high pressure nitridation process may be performed in an inert atmosphere in a chamber injected with a nitrogen-containing reactive gas.

[0014] In one embodiment of the present invention, when the high pressure nitridation process is performed, the concentration of the reactive gas in the chamber may be greater than 5%.

[0015] In one embodiment of the present invention, when performing the high pressure nitridation process, the internal pressure of the chamber may be maintained at 2 atmospheres to 50 atmospheres.

[0016] In one embodiment of the present invention, when performing the high pressure nitridation process, the internal temperature of the chamber may be maintained at 200° C. to 1000° C.

[0017] According to an embodiment of the present invention, the method for manufacturing a semiconductor device may further include the following step: performing a high pressure annealing (HPA) process on the barrier layer.

[0018] In one embodiment of the present invention, the high pressure annealing process may be performed in an inert atmosphere in a chamber injected with a hydrogen-containing reactive gas.

[0019] In one embodiment of the present invention, when the high pressure annealing process is performed, the concentration of the reactive gas in the chamber may be greater than 5%.

[0020] In one embodiment of the present invention, when the high pressure annealing process is performed, the internal pressure of the chamber may be maintained at 2 atmospheres to 50 atmospheres.

[0021] In one embodiment of the present invention, when the high pressure annealing process is performed, the internal temperature of the chamber may be maintained at 200° C. to 1000° C.

[0022] Effects of the Invention

[0023] According to the embodiment of the present invention, the present invention has the following effect, that is, in the manufacturing process of the semiconductor device, the electrical properties of the barrier layer and the metal electrode can be improved by improving the quality of the barrier layer, thereby improving the electrical properties of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A diagram showing the structure of a common semiconductor device.

[0025] Figure 2 and Figure 3 FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0026] Figures 4 to 8 FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to still another embodiment of the present invention.

[0027] Fig. 9 The graph is a graph showing the resistance value of the barrier layer measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to an embodiment of the present invention.

[0028] Fig.10 The graph is a graph showing the resistance value of the metal electrode measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] With reference to the accompanying drawings, the above-mentioned objects, features and advantages will be described in detail, so that ordinary technicians in the technical field to which this specification belongs can easily implement the embodiments of this specification. In the process of describing this specification, if it is determined that the specific description of the relevant known technology makes the subject of this specification unclear, the detailed description thereof will be omitted. Below, with reference to the accompanying drawings, the preferred embodiments of this specification will be described in detail. In the accompanying drawings, the same reference numerals represent the same or similar structural elements.

[0030] Figure 2 and Figure 3 FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0031] like Figure 2 and Figure 3 As shown, according to a method for manufacturing a semiconductor device according to an embodiment of the present invention, an insulating layer 22 is formed on a substrate 21 , and a barrier layer 23 is formed on the insulating layer 22 .

[0032] In one embodiment of the present invention, the substrate 21 may be a silicon substrate, a germanium substrate or a silicon germanium substrate.

[0033] In one embodiment of the present invention, the insulating layer 22 may be a silicon oxide film formed by a thermal oxidation process or a silicon oxide film formed by an evaporation technique.

[0034] In one embodiment of the present invention, the barrier layer 23 may include a metal material (eg, Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0035] When the barrier layer 23 is formed, a nitridation process 24 is performed on the barrier layer 23. By performing the nitridation process on the barrier layer 23, the content of nitrogen (N) components in the barrier layer 23 can be increased and impurities in the barrier layer 23 can be removed. In addition, by performing the nitridation process on the barrier layer 23, the conformality of the barrier layer 23 can be improved.

[0036] In one embodiment of the present invention, the nitridation process performed on the barrier layer 23 may include a high pressure nitridation (HPN) process.

[0037] In one embodiment of the present invention, the high pressure nitridation process may be performed in an inert atmosphere in a chamber injected with a nitrogen-containing reactive gas.

[0038] For example, the inert gas may be N 2 , Ar, or He, but the type of the inert gas is not limited thereto.

[0039] For example, the nitrogen-containing reactive gas may be NH 2 or NH 3 , but the type of the nitrogen-containing reactive gas is not limited thereto.

[0040] In one embodiment of the present invention, when performing the high pressure nitridation process, the concentration of the nitrogen-containing reactive gas in the chamber may be above 5%. For example, when performing the high pressure nitridation process, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% to 100%.

[0041] In one embodiment of the present invention, when the high pressure nitridation process is performed, the internal pressure of the chamber may be maintained at 2 atmospheres to 50 atmospheres.

[0042] In one embodiment of the present invention, when the high pressure nitridation process is performed, the internal temperature of the chamber may be maintained at 200° C. to 1000° C.

[0043] As described above, when the barrier layer 23 is subjected to the nitridation process, the conformality of the barrier layer 23 is improved, and thus the electrical characteristics of the barrier layer 23 can be improved. Furthermore, if the barrier layer 23 has high conformality, the conformality of the metal electrode 24 formed on the barrier layer 23 is also improved, and thus the electrical characteristics of the metal electrode 24 can be improved.

[0044] After the barrier layer 23 is subjected to a nitridation process 24 , a metal electrode 25 may be formed on the nitrided barrier layer 23 .

[0045] The metal electrode 25 can be formed by a physical vapor deposition (PVD) process such as plasma sputtering or evaporation. However, the formation method of the metal electrode 25 is not limited thereto. The metal electrode 25 may include metal materials such as W, Al, Ti, Ta, Co, Mo, Ru or Cu.

[0046] On the other hand, according to yet another embodiment of the present invention, a high pressure annealing (HPA) process may be performed on the barrier layer 23 .

[0047] In one embodiment of the present invention, the high pressure annealing process may be performed in an inert atmosphere in a chamber injected with a hydrogen-containing reactive gas.

[0048] For example, the inert gas may be N 2 , Ar, or He, but the type of the inert gas is not limited thereto.

[0049] For example, the hydrogen-containing reactive gas may be H 2 or D 2 , but the type of the hydrogen-containing reactive gas is not limited thereto.

[0050] In one embodiment of the present invention, when the high pressure annealing process is performed, the concentration of the hydrogen-containing reactive gas in the chamber may be above 5%. For example, when the high pressure annealing process is performed, the concentration of the hydrogen-containing reactive gas in the chamber may be 5% to 100%.

[0051] In one embodiment of the present invention, when the high pressure annealing process is performed, the internal pressure of the chamber may be maintained at 2 atmospheres to 50 atmospheres.

[0052] In one embodiment of the present invention, when the high pressure annealing process is performed, the internal temperature of the chamber may be maintained at 200° C. to 1000° C.

[0053] In one embodiment of the present invention, the barrier layer 23 may be subjected to a high pressure nitridation process after a high pressure annealing process is performed on the barrier layer 23. In another embodiment of the present invention, the barrier layer 23 may be subjected to a high pressure annealing process after a high pressure nitridation process is performed on the barrier layer 23.

[0054] If the barrier layer 23 is subjected to both the high-pressure annealing process and the high-pressure nitridation process, the conformality of the barrier layer 23 and the conformality of the metal electrode 25 can be further improved compared to the case where only the high-pressure nitridation process is performed on the barrier layer 23. Thus, the electrical properties of the barrier layer 23 and the electrical properties of the metal electrode 25 can be further improved.

[0055] Figures 4 to 8FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to still another embodiment of the present invention.

[0056] Reference Figure 4 , a plurality of sacrificial layers 112 and a plurality of insulating layers 110 may be repeatedly and alternately deposited on the substrate 100 to form a thin film structure TS.

[0057] In one embodiment of the present invention, the substrate 100 may be a silicon substrate, a germanium substrate or a silicon germanium substrate.

[0058] In one embodiment of the present invention, the plurality of sacrificial layers 112 may have the same thickness. Moreover, according to another embodiment of the present invention, among the plurality of sacrificial layers 112, the thickness of the bottommost sacrificial layer 112 and the topmost sacrificial layer 112 may be greater than the thickness of the sacrificial layer 112 therebetween.

[0059] In one embodiment of the present invention, the plurality of insulating layers 110 may have the same thickness. In another embodiment of the present invention, some of the plurality of insulating layers 110 may also have different thicknesses.

[0060] In one embodiment of the present invention, the plurality of sacrificial layers 112 and the plurality of insulating layers 110 may be formed by thermal chemical vapor deposition (Thermal CVD), plasma enhanced CVD, physical CVD or atomic layer deposition (ALD, Atomic Layer Deposition) processes.

[0061] In one embodiment of the present invention, the plurality of sacrificial layers 112 and the plurality of insulating layers 110 may include materials with different etching selectivities. As an example, the plurality of sacrificial layers 112 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film. The plurality of insulating layers 110 may be at least one of a silicon film, a silicon oxide film, a silicon carbide film, a silicon oxynitride film, and a silicon nitride film, and may be a material different from the sacrificial layer 112. As an example, the sacrificial layer 112 may be a silicon oxide film, and the insulating layer 110 may be a silicon oxide film. However, according to another embodiment of the present invention, the sacrificial layer 112 may be made of a conductive material, and the insulating layer 110 may be made of an insulating material.

[0062] A through hole H may be formed through the thin film structure TS to expose the substrate 100. In a planar perspective, the through hole H may be formed two-dimensionally on the upper surface of the thin film structure TS. According to an embodiment of the present invention, the through holes H may be arranged along the first direction D1. However, according to another embodiment of the present invention, the through holes H may also be arranged in a zigzag shape along the first direction D1.

[0063] The through hole H can be formed by the following steps: forming a first mask pattern (not shown) having a plurality of openings, the openings defining the region where the through hole H is formed on the thin film structure TS; and anisotropically etching the thin film structure TS using the first mask pattern (not shown) as an etching mask. The first mask pattern can be made of a material that is selective to the sacrificial layer 112 and the insulating layer 110. The upper surface of the substrate 100 can be overetched by the etching process, so that the upper portion of the substrate 100 is recessed.

[0064] Then, if Figure 5 As shown, a charge storage structure 150 and a first semiconductor pattern 160 may be formed to cover each inner wall of the through hole H, so that the substrate 100 is exposed.

[0065] Specifically, a charge storage structure film (not shown) and a first semiconductor film (not shown) may be sequentially formed to cover each inner wall of the through hole H. The charge storage structure film and the first semiconductor film may fill a portion of each through hole H. Each through hole H may not be completely filled with the charge storage structure film and the first semiconductor film.

[0066] The charge storage structure film may cover the upper surface of the substrate 100 exposed through the through hole H. As an example, the charge storage structure film may be formed by evaporation using plasma enhanced CVD, physical CVD or atomic layer deposition (ALD).

[0067] The first semiconductor film may be formed on the charge storage structure film. According to an embodiment of the present invention, the first semiconductor film may be a semiconductor material formed by one of atomic layer deposition (ALD) and chemical vapor deposition (CVD). As an example, the first semiconductor film may be a polycrystalline silicon film. According to an embodiment of the present invention, when evaporated, the first semiconductor film may be amorphous, but may be crystallized by an annealing process or the like.

[0068] After the charge storage structure film and the first semiconductor film are sequentially formed, the substrate 100 may be exposed by anisotropically etching the charge storage structure film and the first semiconductor film. Thus, the first semiconductor pattern 160 and the charge storage structure 150 may be formed on each inner wall of the through hole H. That is, the charge storage structure 150 and the first semiconductor pattern 160 may be formed in a cylindrical shape with both ends open. In the process of anisotropically etching the first semiconductor film and the charge storage structure film, as a result of over-etching, the upper surface of the substrate 100 exposed by the first semiconductor pattern 160 and the charge storage structure 150 may be recessed.

[0069] In one embodiment of the present invention, the charge storage structure 150 may include a tunnel insulating layer, a charge storage layer, and an adhesion insulating layer, which are sequentially stacked between the first semiconductor pattern 160 and the thin film structure TS. The adhesion insulating layer, the charge storage layer, and the tunnel insulating layer may be sequentially evaporated on each inner wall of the through hole H by plasma enhanced CVD (Plasma enhanced CVD), physical CVD (physical CVD) or atomic layer deposition (ALD, Atomic Layer Deposition) technology.

[0070] Subsequently, a second semiconductor pattern 165 filling the remaining portion of each through hole H and a buried insulating pattern 170 may be formed.

[0071] Specifically, a second semiconductor film (not shown) and a buried insulating film (not shown) may be sequentially formed on the substrate 100 on which the charge storage structure 150 and the first semiconductor pattern 160 are formed.

[0072] The second semiconductor film may be formed to a thickness that does not completely fill each through hole H. The second semiconductor film may cover each inner wall of the through hole H and may cover the upper surface of the substrate 100 exposed by the charge storage structure 150 and the first semiconductor pattern 160. The second semiconductor film may connect the substrate 100 and the first semiconductor pattern 160.

[0073] The second semiconductor film may be a semiconductor material formed by one of atomic layer deposition (ALD) and chemical vapor deposition (CVD). As an example, the second semiconductor film may be a polycrystalline silicon film. According to an embodiment of the present invention, when evaporating, the second semiconductor film may be amorphous, but may be crystallized by an annealing process or the like. The buried insulating film may completely fill the interior of the through hole H. The buried insulating film may be at least one of an insulating material formed by SOG technology and a silicon oxide film.

[0074] As the buried insulating film and the second semiconductor film are planarized, the second semiconductor pattern 165 and the buried insulating pattern 170 may be formed in each through hole H. The second semiconductor pattern 165 and the buried insulating pattern 170 may be partially formed in each through hole H through the planarization process. The first semiconductor pattern 160 and the second semiconductor pattern 165 may be defined as a semiconductor pattern SP.

[0075] Then, if Figure 6 As shown, a trench T for exposing the substrate 100 may be formed between adjacent through holes H by patterning the thin film structure TS.

[0076] The trench T forming step may include the steps of: forming a second mask pattern (not shown) for defining a plane position for forming the trench T on the thin film structure TS; and anisotropically etching the thin film structure TS using the second mask pattern as an etching mask.

[0077] The trench T is separated from the semiconductor pattern SP, and the sidewalls of the sacrificial layer 112 and the insulating layer 110 are exposed. In a planar perspective, the trench T may be linear or rectangular, and in a vertical depth perspective, the trench T may expose the upper surface of the substrate 100. During the etching process, the upper portion of the substrate 100 is overetched, and the upper portion of the substrate 100 may be recessed.

[0078] Different from the drawings, the trench T may be formed to have different widths according to the distances from the substrate 100 through an anisotropic etching process. That is, the lower width of the trench T may be narrower than the upper width of the trench T.

[0079] Next, a recessed region R may be formed between the insulating layers 110 by removing the sacrificial layer 112 exposed by the trench T. The recessed region R may be formed by isotropically etching the sacrificial layer 112 under an etching condition having an etching selectivity for the insulating layer 110, the charge storage structure 150, the semiconductor pattern SP, the lower insulating portion 105, and the substrate 100. The sacrificial layer 112 may be completely removed by isotropic etching. As an example, when the sacrificial layer 112 is a silicon nitride film and the insulating layer 110 is a silicon oxide film, the etching process may be performed using an etching solution containing phosphoric acid.

[0080] Then, if Figure 7 As shown in the enlarged view 300 of FIG. 1 , a barrier layer 200 is formed inside each recessed region R. The barrier layer 200 may be formed on the insulating layer 110 and the charge storage structure 150 .

[0081] In one embodiment of the present invention, the barrier layer 200 may include a metal material (eg, Ti, Ta, TiN, TaN, TiOx, TaOx, W, WN, WO, etc.).

[0082] When the barrier layer 200 is formed, a nitridation process 202 is performed on the barrier layer 200. As the barrier layer 200 is subjected to the nitridation process, the content of nitrogen (N) components in the barrier layer 200 may be increased and impurities in the barrier layer 200 may be removed. Also, the conformality of the barrier layer 200 may be improved by performing the nitridation process on the barrier layer 200.

[0083] In one embodiment of the present invention, the nitridation process performed on the barrier layer 200 may include a high pressure nitridation process.

[0084] In one embodiment of the present invention, the high pressure nitridation process may be performed in an inert atmosphere in a chamber injected with a nitrogen-containing reactive gas.

[0085] For example, the inert gas may be N 2 , Ar, or He, but the type of the inert gas is not limited thereto.

[0086] For example, the nitrogen-containing reactive gas may be NH 2 or NH 3 , but the type of the nitrogen-containing reactive gas is not limited thereto.

[0087] In one embodiment of the present invention, when performing the high pressure nitridation process, the concentration of the nitrogen-containing reactive gas in the chamber may be above 5%. For example, when performing the high pressure nitridation process, the concentration of the nitrogen-containing reactive gas in the chamber may be 5% to 100%.

[0088] In one embodiment of the present invention, when the high pressure nitridation process is performed, the internal pressure of the chamber may be maintained at 2 atmospheres to 50 atmospheres.

[0089] In one embodiment of the present invention, when the high pressure nitridation process is performed, the internal temperature of the chamber may be maintained at 200° C. to 1000° C.

[0090] As described above, when the barrier layer 200 is subjected to the nitridation process, the conformality of the barrier layer 200 is improved, and thus the electrical characteristics of the barrier layer 200 can be improved. Furthermore, if the barrier layer 200 has high conformality, the conformality of the metal electrode 204 formed on the barrier layer 200 is also improved, and thus the electrical characteristics of the metal electrode 204 can be improved.

[0091] After the barrier layer 200 is subjected to the nitridation process 24 , a metal electrode 204 may be formed on the nitrided barrier layer 200 .

[0092] The metal electrode 204 can be formed by a physical vapor deposition (PVD) process such as plasma sputtering or evaporation. However, the formation method of the metal electrode 204 is not limited thereto. The metal electrode 204 may include metal materials such as W, Al, Ti, Ta, Co, Mo, Ru or Cu.

[0093] On the other hand, according to yet another embodiment of the present invention, a high pressure annealing process may be performed on the barrier layer 200 .

[0094] In one embodiment of the present invention, the high pressure annealing process may be performed in an inert atmosphere in a chamber injected with a hydrogen-containing reactive gas.

[0095] For example, the inert gas may be N 2 , Ar, or He, but the type of the inert gas is not limited thereto.

[0096] For example, the hydrogen-containing reactive gas may be H 2 or D 2 , but the type of the hydrogen-containing reactive gas is not limited thereto.

[0097] In one embodiment of the present invention, when the high pressure annealing process is performed, the concentration of the hydrogen-containing reactive gas in the chamber may be above 5%. For example, when the high pressure annealing process is performed, the concentration of the hydrogen-containing reactive gas in the chamber may be 5% to 100%.

[0098] In one embodiment of the present invention, when the high pressure annealing process is performed, the internal pressure of the chamber may be maintained at 2 atmospheres to 50 atmospheres.

[0099] In one embodiment of the present invention, when the high pressure annealing process is performed, the internal temperature of the chamber may be maintained at 200° C. to 1000° C.

[0100] In one embodiment of the present invention, the barrier layer 200 may be subjected to a high pressure nitridation process after a high pressure annealing process is performed on the barrier layer 200. In another embodiment of the present invention, the barrier layer 200 may be subjected to a high pressure annealing process after a high pressure nitridation process is performed on the barrier layer 200.

[0101] If the barrier layer 200 is subjected to both the high-pressure annealing process and the high-pressure nitridation process, the conformality of the barrier layer 200 and the conformality of the metal electrode 204 can be further improved compared to the case where only the high-pressure nitridation process is performed on the barrier layer 200. Thus, the electrical properties of the barrier layer 200 and the electrical properties of the metal electrode 204 can be further improved.

[0102] This can be accomplished through the above process Figure 8 The semiconductor device shown.

[0103] Fig. 9 The graph is a graph showing the resistance value of the barrier layer measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to an embodiment of the present invention.

[0104] exist Fig. 9 In the example, M1 is Figure 1 The conventional semiconductor device shown is a semiconductor device in which the barrier layer 13 is not subjected to a high-pressure nitridation process or a high-pressure annealing process. Fig. 9 In the example, M2 is Figure 3 A semiconductor device having a structure as shown and performing a high-pressure nitridation process on the barrier layer 23. Fig. 9 In the example, M3 has Figure 3 The semiconductor device has the structure shown in FIG. 1 and performs a high-pressure annealing process and a high-pressure nitridation process on the barrier layer 23 .

[0105] like Fig. 9As shown, the resistance value of the barrier layer 13 when a voltage is applied to the semiconductor device M1 is greater than the resistance value of the barrier layer 23 when a voltage is applied to the semiconductor device M2. Based on the above results, if a high-pressure nitridation process is applied to the barrier layer, the resistance of the barrier layer can be reduced by improving the conformality of the barrier layer.

[0106] And, if Fig. 9 As shown, the resistance value of the barrier layer 23 when a voltage is applied to the semiconductor device M2 is greater than the resistance value of the barrier layer 23 when a voltage is applied to the semiconductor device M3. Based on the above results, if the high-pressure annealing process and the high-pressure nitridation process are applied to the barrier layer, the resistance of the barrier layer can be further reduced by improving the conformality of the barrier layer, compared with the case where only the high-pressure nitridation process is applied to the barrier layer.

[0107] Fig.10 The graph is a graph showing the resistance value of the metal electrode measured when a voltage is applied to a conventional semiconductor device and a semiconductor device according to an embodiment of the present invention.

[0108] exist Fig.10 In the example, M1 is Figure 1 The conventional semiconductor device shown is a semiconductor device in which the barrier layer 13 is not subjected to a high-pressure nitridation process or a high-pressure annealing process. Fig.10 In the example, M2 is Figure 3 A semiconductor device having a structure as shown and performing a high-pressure nitridation process on the barrier layer 23. Fig.10 In the example, M3 has Figure 3 The semiconductor device has the structure shown in FIG. 1 and performs a high-pressure annealing process and a high-pressure nitridation process on the barrier layer 23 .

[0109] like Fig.10 As shown, the resistance value of the metal electrode 14 when a voltage is applied to the semiconductor device M1 is greater than the resistance value of the metal electrode 25 when a voltage is applied to the semiconductor device M2. Based on the above results, if a high-pressure nitridation process is applied to the barrier layer, the resistance of the metal electrode can be reduced by improving the conformality of the metal electrode.

[0110] And, if Fig.10 As shown in FIG. 1 , the resistance value of the metal electrode 25 when a voltage is applied to the semiconductor device M2 is greater than the resistance value of the metal electrode 25 when a voltage is applied to the semiconductor device M3. Based on the above results, if the high-pressure annealing process and the high-pressure nitridation process are applied to the barrier layer at the same time, the resistance of the metal electrode can be further reduced by forming the conformality of the metal electrode, compared with the case where only the high-pressure nitridation process is applied to the barrier layer.

[0111] As described above, although the present specification is described with reference to the illustrative drawings, the present specification is not limited to the embodiments and drawings disclosed in the present specification, and a person skilled in the art of the present invention can make various modifications. Moreover, in the process of describing the embodiments of the present specification, although the effects based on the structure of the present specification are not explicitly recorded, the effects that can be predicted by the structure should also be recognized.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The steps include: forming an insulating layer; forming a barrier layer on the insulating layer; performing a nitridation process on the barrier layer; and forming a metal electrode on the barrier layer, The step of performing the above-mentioned nitriding process includes the step of performing a high-pressure nitriding process.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The high pressure nitridation process is performed in an inert atmosphere in a chamber into which a nitrogen-containing reactive gas is injected.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: When the high pressure nitriding process is performed, the concentration of the reactive gas in the chamber is greater than 5%.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: When the high pressure nitriding process is performed, the internal pressure of the chamber is maintained at 2 atmospheres to 50 atmospheres.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: When the high pressure nitriding process is performed, the internal temperature of the chamber is maintained at 200° C. to 1000° C.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further comprises the following step: performing a high pressure annealing process on the barrier layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The high pressure annealing process is performed in an inert atmosphere in a chamber injected with a reactive gas containing hydrogen.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: When the high pressure annealing process is performed, the concentration of the reactive gas in the chamber is greater than 5%.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: When the high pressure annealing process is performed, the internal pressure of the chamber is maintained at 2 atmospheres to 50 atmospheres.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: When the high pressure annealing process is performed, the internal temperature of the chamber is maintained at 200° C. to 1000° C.

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