Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a plurality of first active patterns (C11) located in a display area (AA); the first active pattern (C11) comprises a first part (CA) extending along a first direction, a second part (CB) extending from one end of the first part (CA), and a plurality of first metal wires (M11) extending along the first direction; a plurality of conductive portions (D11) located in the display area (AA); the orthographic projection of at least one conductive part (D11) in the plurality of conductive parts (D11) on the substrate (11) is located between the orthographic projections of the adjacent first metal wires (M11) on the substrate (11); a second conductive layer (D2) comprising: a plurality of first electrodes (D21) located in the display area (AA); wherein the first metal wire (M11) on two adjacent sides of the conductive part (D11) comprises a first sub-metal wire (MA) and a second sub-metal wire (MB); wherein the first sub-metal line (MA) is electrically connected to the second portion (CB); the first part (CA) is electrically connected with the first electrode (D21) through the conductive part (D11); the distance between the orthographic projection of the conductive part (D11) on the substrate (11) and the orthographic projection of the first sub-metal wire (MA) on the substrate (11) is larger than the distance between the orthographic projection of the conductive part (D11) and the orthographic projection of the second sub-metal wire (MB) on the substrate (11).

Description

Array substrate, display panel and display device

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device.

[0002] Virtual reality technology is a new technology that "seamlessly" integrates real-world information and virtual-world information. Compared with conventional display products, the most obvious feature of virtual reality display products is their ultra-high resolution. The best choice for ultra-high PPI is currently liquid crystal display (LCD) technology, because in the LCD display structure, the pixel area circuit has only one switching transistor (Thin Film Transistor, TFT), which is very conducive to achieving high PPI.

[0003] Summary of the invention

[0004] The embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate has a display area and a non-display area located outside the display area, and includes:

[0005] substrate;

[0006] The first active layer is located on one side of the substrate, and includes: a plurality of first active patterns located in the display area; the first active pattern includes: a first portion extending along a first direction, and a second portion extending from one end of the first portion;

[0007] The first metal layer comprises: a plurality of first metal wires extending in a first direction; the orthographic projection of the first portion on the substrate is located between orthographic projections of adjacent first metal wires on the substrate, and the orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the first metal wire on the substrate;

[0008] The first conductive layer comprises: a plurality of conductive parts located in the display area; an orthographic projection of at least one of the plurality of conductive parts on the substrate is located between orthographic projections of adjacent first metal lines on the substrate;

[0009] The second conductive layer includes: a plurality of first electrodes located in the display area;

[0010] Among them, the first metal wires on the adjacent two sides of the conductive part include: a first sub-metal wire, and a second sub-metal wire; wherein the first sub-metal wire is electrically connected to the second part; the first part is electrically connected to the first electrode through the conductive part; the distance between the conductive part's orthographic projection on the substrate and the first sub-metal wire's orthographic projection on the substrate is greater than the distance between the conductive part and the second sub-metal wire's orthographic projection on the substrate.

[0011] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0012] 15%≤b / a≤75%, wherein a represents the minimum distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate, and b represents the minimum distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the second sub-metal line on the substrate.

[0013] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0014] 3%≤(ab) / c≤15%, wherein c represents the minimum distance between adjacent first sub-metal lines and second sub-metal lines.

[0015] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0016] 60%≤d / c≤95%, wherein d represents the length of the conductive portion in a direction perpendicular to the first direction.

[0017] In a possible implementation manner, the first portion has a first symmetry axis extending along the first direction, and the conductive portion has a second symmetry axis extending along the first direction;

[0018] The second symmetry axis is located on a side of the first symmetry axis away from the first sub-metal line.

[0019] In a possible implementation manner, the first electrode has a first outer edge extending along the first direction; between two adjacent first metal lines, the first outer edge is located at a part of the substrate orthogonal projection, on a side of the first portion of the substrate orthogonal projection away from the first sub-metal line;

[0020] The conductive portion has a second outer edge extending along the first direction; between two adjacent first metal lines, the second outer edge is located at a part of the substrate orthogonal projection, on a side of the substrate orthogonal projection of the first portion away from the first sub-metal line;

[0021] Between two adjacent first metal lines, the second outer edge is located at a portion of the positive projection of the substrate and is located on a side of the first outer edge away from the first sub-metal line.

[0022] In a possible implementation manner, the first electrode has a third outer edge extending along the first direction; between two adjacent first metal lines, the third outer edge is located at a part of the orthographic projection of the substrate, on a side of the orthographic projection of the first portion on the substrate close to the first sub-metal line;

[0023] The conductive portion has a fourth outer edge extending along the first direction; between two adjacent first metal wires, the fourth outer edge is located at a part of the orthographic projection of the substrate, on a side of the orthographic projection of the first portion on the substrate close to the first sub-metal wire;

[0024] Between two adjacent first metal lines, the portion of the orthographic projection of the third outer edge on the substrate is located on a side of the orthographic projection of the fourth outer edge on the substrate away from the first sub-metal line.

[0025] In a possible implementation manner, the first electrode has a third outer edge extending along the first direction; between two adjacent first metal lines, the third outer edge is located at a part of the orthographic projection of the substrate, on a side of the orthographic projection of the first portion on the substrate close to the first sub-metal line;

[0026] The conductive portion has a fourth outer edge extending along the first direction; between two adjacent first metal wires, the fourth outer edge is located at a part of the orthographic projection of the substrate, on a side of the orthographic projection of the first portion on the substrate close to the first sub-metal wire;

[0027] Between two adjacent first metal lines, a portion of the third outer edge on the substrate being an orthographic projection coincides with a portion of the fourth outer edge on the substrate being an orthographic projection.

[0028] In a possible implementation, the array substrate further includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer including: a plurality of second metal wires extending along a second direction;

[0029] The first portion includes: a first sub-portion, a second sub-portion, and a third sub-portion sequentially distributed along the first direction; wherein the orthographic projection of the second sub-portion on the substrate overlaps with the orthographic projection of the second metal line on the substrate; the first sub-portion is located on a side of the second sub-portion facing the second portion, and the third sub-portion is located on a side of the second sub-portion away from the second portion;

[0030] An orthographic projection of the first sub-portion on the substrate has an overlapping area with an orthographic projection of the conductive portion on the substrate.

[0031] In a possible implementation, the array substrate further includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer including: a plurality of second metal wires extending along a second direction; the second portion includes: a fourth sub-portion connected to the first portion and extending along a third direction, and a fifth sub-portion connected to the fourth sub-portion, the first metal wire is electrically connected to the fifth sub-portion; the second direction intersects the first direction, and the third direction intersects the first direction;

[0032] The conductive portion includes: a fifth outer edge extending along the second direction and facing the fifth sub-portion;

[0033] The orthographic projection of the second metal line on the substrate covers the orthographic projection of the fifth outer edge on the substrate.

[0034] In a possible implementation, the distance between the orthographic projection of the sixth outer edge on the substrate and the orthographic projection of the fifth outer edge on the substrate in the first direction is one fifth to four fifths of the length of the orthographic projection of the second metal line on the substrate in the first direction.

[0035] In a possible implementation manner, the second metal wire has a sixth outer edge extending along the second direction and facing the fifth sub-portion;

[0036] The orthographic projection of the sixth outer edge on the substrate is located on a side of the orthographic projection of the fifth outer edge on the substrate that faces the orthographic projection of the fifth sub-portion on the substrate.

[0037] In a possible implementation manner, the first conductive layer is located on a side of the first active layer facing away from the substrate;

[0038] The array substrate further includes: a first insulating layer located between the first active layer and the first conductive layer, and a first via hole penetrating the first insulating layer, wherein the conductive portion is electrically connected to the first portion through the first via hole;

[0039] Between two adjacent first metal lines, the first via hole is located at the center of the substrate projection, and the minimum distance between the first sub-metal line and the substrate projection is greater than the minimum distance between the first sub-metal line and the substrate projection.

[0040] In a possible implementation manner, the first electrode is located on a side of the first conductive layer facing away from the substrate;

[0041] The array substrate further includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via hole penetrating the second insulating layer; the first electrode is electrically connected to the conductive portion through the second via hole;

[0042] Between two adjacent first metal lines, the second via hole is located at the center of the substrate projection, and the minimum distance between the second via hole and the first sub-metal line in the substrate projection is greater than the minimum distance between the second sub-metal line and the substrate projection.

[0043] In a possible implementation manner, at least a portion of the orthographic projection of the first via hole on the substrate does not overlap with at least a portion of the orthographic projection of the second via hole on the substrate.

[0044] In a possible implementation manner, the first insulating layer includes one or a combination of the following:

[0045] a first gate insulating layer;

[0046] a first interlayer dielectric layer;

[0047] The second interlayer dielectric layer.

[0048] In a possible implementation manner, the thickness of at least one of the first gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer is greater than

[0049] In a possible embodiment, the array substrate further includes: a third metal layer located on the side of the first active layer facing the substrate; the third metal layer includes: a plurality of third metal wires extending along the second direction, the orthographic projection of the third metal wire on the substrate covering the orthographic projection of the second metal wire on the substrate.

[0050] In a possible implementation, the array substrate includes: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas include: a plurality of pixel light-transmitting area rows extending along the first direction and arranged along the second direction; at least one pixel light-transmitting area row among the plurality of pixel light-transmitting area rows includes: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; a light band range emitted by the third pixel light-transmitting area is smaller than a light band range emitted by the first pixel light-transmitting area, and smaller than a light band range emitted by the second pixel light-transmitting area;

[0051] The third metal wire includes: a third metal wire main portion extending along the second direction, and a first shielding structure connected to the third metal wire main portion; the maximum length of the first shielding structure in the first direction is greater than the maximum length of the third metal wire main portion in the first direction; the orthographic projection of the first shielding structure on the substrate is located in the gap between the orthographic projections of at least partially adjacent two third pixel light-transmitting areas on the substrate in the first direction.

[0052] In a possible implementation manner, the array substrate further includes: a spacer; and an orthographic projection of the first shielding structure on the substrate covers the orthographic projection of the spacer on the substrate.

[0053] In a possible implementation, the third metal wire further includes: a second blocking structure connected to the main portion of the third metal wire; a maximum length of the second blocking structure in the first direction is greater than a maximum length of the main portion of the third metal wire in the first direction, and less than a maximum length of the first blocking structure in the first direction;

[0054] The orthographic projection of the second shielding structure on the substrate is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas on the substrate in the second direction, and the orthographic projection of the second shielding structure on the substrate does not overlap with the orthographic projection of the first shielding structure on the substrate.

[0055] In a possible implementation, the array substrate further includes, located in the non-display area: a second active layer located on a side of the first active layer facing the substrate, a driving source and drain located on a side of the second active layer away from the substrate, and a driving gate.

[0056] In a possible implementation manner, the material of the first active layer includes: metal oxide; and the material of the second active layer includes: low-temperature polysilicon.

[0057] In a possible implementation, the second active layer is located between the third metal layer and the substrate; the driving gate is located in the third metal layer; and the driving source and drain are located in the first metal layer.

[0058] In a possible implementation, the second active layer is located between the third metal layer and the first active layer; the driving source and drain are located in the second metal layer; and the driving gate is located in the third metal layer.

[0059] In a possible implementation, the array substrate further includes: a third conductive layer located on a side of the second conductive layer away from the substrate, the third conductive layer including a plurality of hollows, the hollows overlapping a portion of the orthographic projection of the substrate with a portion of the first electrode on the substrate.

[0060] In a possible implementation manner, the array substrate further includes: a fourth metal layer located on a side of the third conductive layer facing the substrate and in contact with the third conductive layer;

[0061] The fourth metal layer includes: a fourth metal line extending along the first direction, wherein an orthographic projection of the fourth metal line on the substrate covers an orthographic projection of the first metal line on the substrate.

[0062] The embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate.

[0063] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0064] FIG. 1A is a schematic diagram showing a crosstalk problem in a display panel;

[0065] FIG. 1B is a second schematic diagram of a display panel having crosstalk failure;

[0066] FIG. 1C is a third schematic diagram of a display panel having a crosstalk problem;

[0067] FIG. 1D is a fourth schematic diagram of a display panel having a crosstalk problem;

[0068] FIG2A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0069] FIG2B is a schematic diagram of a single film layer of the third metal layer in FIG2A ;

[0070] FIG2C is a schematic diagram of a single film layer of the first active layer in FIG2A ;

[0071] FIG2D is a schematic diagram of a single film layer of the second metal layer in FIG2A ;

[0072] FIG2E is a schematic diagram of a single film layer of the first metal layer in FIG2A ;

[0073] FIG2F is a schematic diagram of a single film layer of the first conductive layer in FIG2A ;

[0074] FIG2G is a schematic diagram of a single film layer of the second conductive layer in FIG2A ;

[0075] FIG3 is a schematic cross-sectional view of the dashed line A1A2 in FIG2A ;

[0076] FIG. 4A is a schematic diagram of only a portion of the film layer in FIG. 2A ;

[0077] FIG4B is a second schematic diagram of only a portion of the film layer in FIG2A;

[0078] FIG5A is a schematic diagram of a pixel electrode and associated structures provided by an embodiment of the present disclosure;

[0079] FIG5B is a schematic diagram of a first metal line M11 and associated structures provided in an embodiment of the present disclosure;

[0080] FIG5C is a schematic diagram of adjacent pixel electrodes and associated structures provided by an embodiment of the present disclosure;

[0081] FIG. 5D is a diagram of the first coupling capacitor C corresponding to FIG. 5A dp1 Schematic diagram of the composition;

[0082] FIG. 5E is a diagram of the second coupling capacitor C corresponding to FIG. 5A dp2 Schematic diagram of the composition;

[0083] FIG6 is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0084] FIG7A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0085] FIG. 7B is a diagram of the first coupling capacitor C corresponding to FIG. 7A dp1 Schematic diagram of the composition;

[0086] FIG. 7C is a diagram of the second coupling capacitor C corresponding to FIG. 7B dp2 Schematic diagram of the composition;

[0087] FIG8 is a schematic diagram of a stack of only a portion of the film layers in FIG7A ;

[0088] FIG9 is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0089] FIG10A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0090] FIG. 10B may be a schematic diagram of a single film layer of the third metal line M31 in FIG. 10A ;

[0091] FIG10C is a schematic diagram of a larger scope of FIG10B ;

[0092] FIG11 is a cross-sectional schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0093] FIG12 is a second cross-sectional schematic diagram of the array substrate provided in an embodiment of the present disclosure;

[0094] FIG13A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0095] FIG13B is a schematic diagram of a single film layer of the third conductive layer in FIG13A;

[0096] FIG13C is a schematic diagram of a larger area of ​​FIG13B ;

[0097] FIG. 14 is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure.

[0098] The present invention can be implemented in different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other arbitrarily.

[0099] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0100] The ordinal numbers such as "first", "second", "third" and the like in this specification are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0101] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0102] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0103] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0104] In this specification, a transistor refers to an element including at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, a channel region refers to a region where current mainly flows.

[0105] In addition, the gate of a transistor may be referred to as a control electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0106] In this specification, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle may be greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle may be greater than 85° and less than 95°.

[0107] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0108] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0109] In this specification, "about" or "substantially" means that the limit is not strictly defined and the process and measurement errors are allowed. In this specification, "substantially the same" may refer to the situation where the numerical value differs by less than 10%.

[0110] Virtual Reality (VR) head-mounted display panels and Augmented Reality (AR) head-mounted display panels use LTPO (Low Temperature Polycrystalline Oxide) technology. LTPO technology integrates two types of TFTs (Thin Film Transistor, thin film field effect transistors), LTPS (Low Temperature Poly-Silicon) and oxide. Specifically, the display area uses oxide TFT, and the surrounding non-display area uses LTPS TFT.

[0111] In the AR and VR display panels, as shown in FIG. 1A , there is a first coupling capacitor C between the data line and its own pixel electrode (the own pixel electrode can be understood as a pixel electrode electrically connected to the data line) inside the pixel. dp1 , and a second coupling capacitor C with an adjacent pixel electrode (a pixel electrode not electrically connected to the data line) dp2 , when C dp1 >C dp2 When the difference is large, there will be a conventional crosstalk problem. For example, when displaying the image with white in the middle and black at the edges as shown in FIG1B, the image will be bright at the top and dark at the bottom with the middle as the boundary, as shown in FIG1C. Specifically, as shown in FIG1B, FIG1C and FIG1D, pixel A1 and pixel A2 are two pixels at different positions on the same data line, pixel B1 and pixel B2 are two pixels at different positions on the same data line, pixel B1 and pixel A1 are two pixels in the same row on adjacent data lines, and pixel B2 and pixel A2 are two pixels in the same row on adjacent data lines; when the pixel self-coupling effect (the first coupling capacitor C dp1 ) and mutual coupling effect (second coupling capacitor C dp2 ) are inconsistent, the charging voltage of pixel A1 is the positive voltage of L127, which will be pulled up by the voltage of L255 in the middle of the screen, thereby increasing the voltage difference between pixel A1 and the common electrode voltage (Vcom), and displaying as bright; the charging voltage of pixel A2 is still the negative voltage of the previous frame, which will be pulled up by the voltage of L255 in the middle of the screen, thereby decreasing the voltage difference between pixel A2 and the common electrode voltage (Vcom), and displaying as dark, that is, the undesirable phenomenon of Crosstalk screen being bright on the top and dark on the bottom occurs.

[0112] In view of this, referring to FIGS. 2A-2G, 3 and 4A, wherein FIG. 2B is a schematic diagram of a single film layer of the third metal layer in FIG. 2A, FIG. 2C is a schematic diagram of a single film layer of the first active layer in FIG. 2A, FIG. 2D is a schematic diagram of a single film layer of the second metal layer in FIG. 2A, FIG. 2E is a schematic diagram of a single film layer of the first metal layer in FIG. 2A, FIG. 2F is a schematic diagram of a single film layer of the first conductive layer in FIG. 2A, FIG. 2G is a schematic diagram of a single film layer of the second conductive layer in FIG. 2A, FIG. 3 is a schematic diagram of a cross-section at a dotted line A1A2 in FIG. 2A, and FIG. 4A is a schematic diagram of only a portion of the film layers in FIG. 2A. An embodiment of the present disclosure provides an array substrate having a display area AA, and a non-display area BB located outside the display area AA, wherein the array substrate comprises:

[0113] Substrate 11;

[0114] The first active layer C1 is located on one side of the substrate 11 and includes: a plurality of first active patterns C11 located in the display area AA; the first active pattern C11 includes: a first portion CA extending along the first direction X, and a second portion CB extending from one end of the first portion CA;

[0115] The first metal layer M1 includes: a plurality of first metal lines M11 extending along a first direction X; an orthographic projection of a first portion CA on a substrate 11 is located between orthographic projections of adjacent first metal lines M11 on the substrate; a portion of an orthographic projection of a second portion CB on the substrate 11 overlaps with a portion of an orthographic projection of the first metal line M11 on the substrate 11; specifically, the first metal line M11 may be a data line; specifically, the display area AA may have a plurality of first transistors, and a position where the second portion CB overlaps with the first metal line M11 may serve as a first electrode of the first transistor; and the second portion CB may be turned on at a position where it overlaps with the first metal line M11 to achieve electrical connection between the first transistor and the data line;

[0116] The first conductive layer D1 includes: a plurality of conductive parts D11 located in the display area AA; the orthographic projection of at least one of the plurality of conductive parts D11 on the substrate 11 is located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the first conductive layer D1 may be a transparent conductive layer, and the conductive part D11 may serve as the second electrode of the first transistor to conduct the first active pattern C11 with the first electrode D21; specifically, the orthographic projection shape of the conductive part D11 on the substrate 11 may be a rectangle, and the length of the conductive part D11 in the first direction X may be greater than the length in the second direction Y; specifically, the length of the conductive part D11 in the first direction X may also be equal to the length in the second direction Y;

[0117] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 may be a transparent conductive layer, and the material of the second conductive layer D2 may be the same as the material of the first conductive layer D1; specifically, the first electrode D21 may be a pixel electrode; specifically, the orthographic projection of the first electrode D21 on the substrate 11 may be located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the orthographic projection shape of the first electrode D21 on the substrate 11 may be a rectangle; the length of the first electrode D21 in the first direction X is greater than the length in the second direction Y;

[0118] Among them, the first metal wire M11 on the two adjacent sides of the conductive part D11 includes: a first sub-metal wire MA, and a second sub-metal wire MB; wherein the first sub-metal wire MA is electrically connected to the second part CB, that is, the first metal wire M11 electrically connected to the second part CB is used as the first type of metal wire MA; the first part CA is electrically connected to the first electrode D21 through the conductive part D11; the distance a between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the conductive part D11 and the second sub-metal wire MB on the substrate 11.

[0119] The first metal line M11 and its associated structure, together with its own pixel electrode and its associated structure, can form a first coupling capacitor C dp1 The first metal line M11 and its associated structure can form a second coupling capacitor C with the adjacent pixel electrode and its associated structure. dp2; Wherein, the pixel electrode itself and the associated structure may be the area shown in the dotted box in FIG. 5A , and may specifically include: the first electrode D21 (as shown in the dotted box S1 in FIG. 5A ), and the conductive portion D11 connected to the first electrode D21 through the second via K2 (as shown in the dotted box S2 in FIG. 5A ), and the portion of the first active pattern C11 connected to the conductive portion D11 through the first via K1 and located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S3 in FIG. 5A , that is, the portion of the first active pattern C11 located on the lower side of the second metal line M21. Since the time during which each row of pixels is turned on is very short within one frame of display, it can be considered that the gate of the first transistor in the pixel is turned off for most of the time, and the portion of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator); the first metal line M11 and the associated structure may be the area shown in the dotted box in FIG. 5B , and may specifically include: the first metal line M11 (as shown in FIG. 5 B), and a portion of the first active pattern C11 electrically connected to the first metal line M11 through the third via K3, located on the side of the second metal line M21 close to the second metal line M21 in the first direction X ((as shown in the dotted box S5 in FIG. 5B , that is, the portion of the first active pattern C11 located on the upper side of the second metal line M21); the adjacent pixel electrodes and associated structures may be the area shown in the dotted box in FIG. 5C , and may specifically include: an adjacent first electrode D21 (as shown in the dotted box S6 in FIG. 5C ), and an adjacent conductive portion D11 connected to the adjacent first electrode D21 through the second via K2 (as shown in the dotted box S7 in FIG. 5C ), and a portion of the adjacent first active pattern C11 connected to the adjacent conductive portion D11 through the first via K1, located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S8 in FIG. 5C , that is, the portion of the first active pattern C11 located on the lower side of the second metal line M21); the first coupling capacitor C dp1 The structure can be shown in FIG. 5D, where the second coupling capacitor C dp2 The composition may be as shown in FIG5E ;

[0120] After research by the inventor of this application, the first coupling capacitor C dp1 The second coupling capacitor C dp2 The main reason for the difference is the asymmetry of the design of the first active pattern C11, and the thin film between the first active layer C1 and the first conductive layer D1, and the first coupling capacitor C dp1 The first active pattern C11 in the conductive portion D11 overlaps with the conductive portion D11 (as shown in the area of ​​the thick solid line frame S in FIG. 5D ), and the positive capacitance is larger, while the second coupling capacitor C dp2 There is no overlap in the first coupling capacitor C dp1 The second coupling capacitor C dp2The main part of the difference (in addition, although the first coupling capacitor C dp1 In the figure, the overlapping area of ​​the first active pattern C11 and the first electrode D21 is larger than the overlapping area of ​​the first active pattern C11 and the conductive portion D11, but since there is a thicker film layer between the first active pattern C11 and the first electrode D21, the overlapping capacitance is very small and the difference can be ignored); and since there is only one film layer between the first metal wire M11 and the conductive portion D11, the lateral capacitance formed by the first metal wire M11 and the conductive portion D11 is greater than the second coupling capacitor C dp2 Dominant in the middle.

[0121] In the embodiment of the present disclosure, the distance a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal line MB on the substrate 11, which can increase the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C dp2 , and due to the first coupling capacitor C dp1 In the embodiment, the overlap capacitance between the first active pattern C11 and the conductive portion D11 (the area shown by the thick solid frame S in FIG. 5D ) accounts for the main part, and the distance between the conductive portion D11 and the second sub-metal line MB is reduced, which will not affect the first coupling capacitor C dp1 This has a significant impact, thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference can be reduced to improve the vertical crosstalk problem.

[0122] It should be noted that, when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is linear, the spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 may be the minimum spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11; when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is non-linear (for example, due to process manufacturing, the edge has some unevenness) or when the orthographic projection of the conductive portion D11 on the substrate 11 is non-rectangular, the spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 may be the average spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11. similarly, when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is linear, the spacing b between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be the minimum spacing b between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11; when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is non-linear (for example, due to process manufacturing, the edge has some unevenness) or when the orthographic projection of the conductive portion D11 on the substrate 11 is non-rectangular, the spacing b between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be the average spacing between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0123] It should be noted that the first sub-metal wire MA is electrically connected to the second part CB, which can be understood as the first sub-metal wire MA is electrically connected to the second part CB through the first transistor; when the shape of the orthographic projection of the conductive part D11 on the substrate 11 is a rectangle, the minimum distance a between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be the distance between the left edge of the conductive part D11 and the right edge of the first sub-metal wire MA; the minimum distance b between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be the distance between the right edge of the conductive part D11 and the left edge of the second sub-metal wire MB.

[0124] In a possible implementation, in combination with FIG. 2A or FIG. 4A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0125] 15%≤b / a≤75%, wherein a represents the minimum distance between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11, and b represents the minimum distance between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11.

[0126] In a possible implementation, in combination with FIG. 2A or FIG. 4A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0127] 3%≤(ab) / c≤15%, wherein c represents the minimum distance between adjacent first sub-metal lines MA and second sub-metal lines MB.

[0128] Specifically, as shown in FIG. 4A , the minimum spacing c between adjacent first sub-metal lines MA and second sub-metal lines MB may be the spacing between the right edge of the first sub-metal line MA and the left edge of the second sub-metal line MB.

[0129] In a possible implementation, in combination with FIG. 2A or FIG. 4A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0130] 60%≤d / c≤95%, wherein d represents the length of the conductive portion D11 in a direction perpendicular to the first direction X.

[0131] In a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 70%≤d / c≤90%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 75%≤d / c≤85%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 78%≤d / c≤85%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: d / c=78%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: d / c=79%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: d / c=79.64%; In a possible implementation manner, the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy: d / c=80%; In a possible implementation manner, the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy: d / c=81%.

[0132] In a possible implementation, the minimum spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be 0.35 μm to 1.15 μm; the minimum spacing b between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be 0.05 μm to 0.85 μm.

[0133] In a possible implementation, the minimum spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be 0.3 μm to 1.5 μm; the minimum spacing b between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be 0.2 μm to 1 μm.

[0134] In a possible embodiment, the minimum spacing c between adjacent first sub-metal wires MA and second sub-metal wires MB may be 2μm to 10μm; in a possible embodiment, the minimum spacing c between adjacent first sub-metal wires MA and second sub-metal wires MB may be 4μm to 8μm; in a possible embodiment, the minimum spacing c between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5μm to 6μm; in a possible embodiment, the minimum spacing c between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.1μm, 5.2μm, 5.3μm, 5.4μm, 5.5μm, 5.6μm, 5.7μm, 5.8μm, 5.8μm or 6.0μm; in a possible embodiment, the minimum spacing c between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65μm.

[0135] In a possible embodiment, the length d of the conductive portion D11 in the direction perpendicular to the first direction X may be 2 μm to 8 μm; in a possible embodiment, the length d of the conductive portion D11 in the direction perpendicular to the first direction X may be 3 μm to 6 μm; in a possible embodiment, the length d of the conductive portion D11 in the direction perpendicular to the first direction X may be 4 μm to 5 μm; in a possible embodiment, the length d of the conductive portion D11 in the direction perpendicular to the first direction X may be 4.1 μm, 4.2 μm, 4.3 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.7 μm, 4.8 μm, 4.9 μm or 5.0 μm.

[0136] In a possible implementation, the length d of the conductive portion D11 in the direction perpendicular to the first direction X may be 4.5 μm; and the minimum spacing c between adjacent first sub-metal lines MA and second sub-metal lines MB may be 5.65 μm.

[0137] In a possible embodiment, in combination with Figures 2A, 2C and 2F, the first portion CA has a first symmetry axis e1 extending along the first direction X, and the first portion CA is symmetrical about the first symmetry axis e1; the conductive portion D11 has a second symmetry axis e2 extending along the first direction X, and the conductive portion D11 is symmetrical about the second symmetry axis e2; the second symmetry axis e2 is located on the side of the first symmetry axis e1 away from the first sub-metal wire MA.

[0138] In a possible implementation, in combination with Figures 2A, 2F and 2G, the first electrode D21 has a first outer edge f1 extending along the first direction X; between two adjacent first metal wires M11, the first outer edge f1 is located in the part of the positive projection of the substrate 11, on the side of the first portion CA on the substrate 11 away from the first sub-metal wire MA; specifically, as shown in Figure 2F, the first outer edge f1 may be the right edge of the first electrode D21; the conductive portion D11 has a second outer edge f2 extending along the first direction X; between two adjacent first metal wires M11, the second outer edge f2 is located in the part of the positive projection of the substrate 11, on the side of the first portion CA on the substrate 11 away from the first sub-metal wire MA; specifically, as shown in Figure 2G, the second outer edge f2 may be the right edge of the conductive portion D11; between two adjacent first metal wires M11, the second outer edge f2 is located in the part of the positive projection of the substrate 11, on the side of the first outer edge f1 away from the first sub-metal wire MA.

[0139] In a possible implementation, in combination with Figures 2A, 2F and 2G, the first electrode D21 has a third outer edge f3 extending along the first direction X; between two adjacent first metal wires M11, the third outer edge f3 is located at the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in Figure 2F, the third outer edge f3 may be the left edge of the first electrode D21; the conductive portion D11 has a fourth outer edge f4 extending along the first direction X; between two adjacent first metal wires M11, the fourth outer edge f4 is located at the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in Figure 2G, the fourth outer edge f4 may be the left edge of the conductive portion D11; between two adjacent first metal wires M11, the fourth outer edge f4 is located at the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the third outer edge f3 on the substrate 11 away from the first sub-metal wire MA. In the embodiment of the present disclosure, the conductive portion D11 is moved away from the first sub-metal line MA to increase the second coupling capacitor C dp2 , thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference can be reduced to improve the vertical crosstalk problem.

[0140] In a specific implementation, as shown in FIG. 2A , the conductive portion D11 may be moved to a side away from the first sub-metal line MA, thereby increasing the second coupling capacitor C dp2In another possible implementation, as shown in FIG. 6 , the conductive portion D11 may not be moved, but the edge of the conductive portion D11 away from the first sub-metal line MA may be moved toward the side away from the first sub-metal line MA, that is, the width of D11 along the second direction Y is increased, and the orthographic projection of the conductive portion D11 on the substrate 11 is reduced, and the minimum spacing b between the orthographic projection of the conductive portion D11 and the second sub-metal line MB on the substrate 11 is reduced, which can also achieve the purpose of increasing the second coupling capacitor C. dp2 .

[0141] Specifically, as shown in FIG6 , the first electrode D21 has a third outer edge f3 extending along the first direction X; between two adjacent first metal wires M11, the portion of the third outer edge f3 on the substrate 11 is located on the side of the orthographic projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in FIG6 , the third outer edge f3 may be the left edge of the first electrode D21; the conductive portion D11 has a fourth outer edge f4 extending along the first direction X; between two adjacent first metal wires M11, the portion of the fourth outer edge f4 on the substrate 11 is located on the side of the orthographic projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in FIG6 , the fourth outer edge f4 may be the left edge of the conductive portion D11; between two adjacent first metal wires M11, the portion of the third outer edge f3 on the substrate 11 overlaps with the portion of the orthographic projection of the fourth outer edge f4 on the substrate 11. In the embodiment of the present disclosure, the second coupling capacitor C is increased by moving the conductive portion D11 away from the edge of the first sub-metal line MA and away from the first sub-metal line MA. dp2 , thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference can be reduced to improve the vertical crosstalk problem.

[0142] It should be noted that, in order to clearly illustrate the positional relationship of the various structures of the embodiments of the present disclosure, Figures 2A to 9 are used to mark and illustrate the edges and positional relationship between the first electrode D21 of the second row and the conductive part D11, the first active pattern C11, the first sub-metal line MA, and the second sub-metal line MB. In a specific implementation, the first electrode D21 of each row and the conductive part D11, the first active pattern C11, the first sub-metal line MA, and the second sub-metal line MB corresponding to the current row also satisfy the relevant edge and positional relationships, but the embodiments of the present disclosure are not limited to this.

[0143] In addition, it should be noted that, for example, in FIG. 2G , the second row of first electrodes D21 from top to bottom only illustrates part of the complete first electrode D21 due to the limitation of the illustration range, and the complete pattern of the first electrode D21 can be as shown in the first row of first electrodes D21 from top to bottom, and the embodiments of the present disclosure are not limited to this.

[0144] In a possible implementation, as shown in combination with FIG. 2C and FIG. 4B , the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1 , the second metal layer M2 including: a plurality of second metal wires M21 extending along the second direction Y;

[0145] The first portion CA includes: a first sub-portion CA1, a second sub-portion CA2, and a third sub-portion CA3 sequentially distributed along the first direction X; wherein the orthographic projection of the second sub-portion CA2 on the substrate overlaps with the orthographic projection of the second metal line M21 on the substrate 11; the first sub-portion CA1 is located on the side of the second sub-portion CA2 facing the second portion CB, and the third sub-portion CA3 is located on the side of the second sub-portion CA2 away from the second portion CB; that is, the portion of the first portion CA overlapping with the projection of the second metal line M21 is taken as the second sub-portion CA2;

[0146] The orthographic projection of the first sub-portion CA1 on the substrate 11 has an overlapping area with the orthographic projection of the conductive portion D11 on the substrate 11. Specifically, the orthographic projection of the first sub-portion CA1 on the substrate 11 has an overlapping area with the orthographic projection of the conductive portion D11 on the substrate 11, as shown in the thick solid line frame S in FIG. 4B.

[0147] In a possible implementation, in combination with FIG. 2A, FIG. 3, FIG. 7A and FIG. 8, where FIG. 8 is a schematic diagram of the stacking of some film layers in FIG. 7A, the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1, the second metal layer M2 including: a plurality of second metal wires M21 extending along the second direction Y; the second portion CB including: a fourth sub-portion CB1 connected to the first portion CA and extending along the third direction, and a fifth sub-portion CB2 connected to the fourth sub-portion CB1, the first metal wire M11 being electrically connected to the fifth sub-portion CB2; the second direction Y intersects the first direction X, and the third direction Y intersects the first direction X. Direction Z intersects with the first direction X; the conductive portion D11 includes: a fifth outer edge f5 extending along the second direction Y and toward the fifth sub-portion CB2, specifically, as shown in FIG7A, the fifth outer edge f5 can be the upper edge of the conductive portion D11; the second metal wire M21 has a sixth outer edge f6 extending along the second direction Y and toward the fifth sub-portion CB2, specifically, as shown in FIG7A, the sixth outer edge f6 can be the upper edge of the second metal wire M21; the orthographic projection of the sixth outer edge f6 on the substrate 11 is located on the side of the orthographic projection of the fifth outer edge f5 on the substrate 11 toward the orthographic projection of the fifth sub-portion CB2 on the substrate 11.

[0148] In the embodiment of the present disclosure, the second metal line M21 has a sixth outer edge f6 extending along the second direction Y and toward the fifth sub-portion CB2, that is, the second metal line M21 is moved up (after the second metal line M21 is moved up, the first coupling capacitor C dp1The structure can be as shown in FIG. 7B, the second coupling capacitor C dp2 The structure can be as shown in FIG. 7C ), the second metal line M21 can shield the overlap capacitance between the first active pattern C11 and the conductive portion D11 (that is, it can shield the capacitance of the area shown by the thick solid line frame S in FIG. 5D ), thereby reducing the first coupling capacitance C dp1 The overlap capacitance accounts for a large proportion in the first coupling capacitance C dp1 The second metal line M21 moves upward, and the lateral capacitance between the first metal line M11 and the conductive portion D11 (constituting the second coupling capacitor C dp2 The main part of the second coupling capacitor C dp2 With the first coupling capacitor C dp1 The difference can be reduced to improve the vertical crosstalk problem.

[0149] Specifically, the second metal line M21 may be a gate line.

[0150] Specifically, the second direction Y may be perpendicular to the first direction X; the angle formed by the third direction Z and the first direction X may be 0 to 90°; specifically, the angle formed by the third direction Z and the first direction X may be 30 to 60°; specifically, the angle formed by the third direction Z and the first direction X may be 45°.

[0151] In a possible implementation, as shown in FIG. 2A , FIG. 2C , FIG. 2F , and FIG. 2G , the length g1 of the orthogonal projection of the first electrode D21 on the substrate 11 along the second direction Y may be equal to the length g2 of the orthogonal projection of the conductive portion D11 on the substrate 11 along the second direction Y. The length g1 of the orthogonal projection of the first electrode D21 on the substrate 11 along the second direction Y may be less than the minimum spacing c between adjacent first sub-metal wires MA and second sub-metal wires MB. In a possible implementation, as shown in FIG. 2A , FIG. 2C , FIG. 2F , and FIG. 2G , the length g4 of the orthogonal projection of the first electrode D21 on the substrate 11 along the first direction X may be greater than the length g5 of the orthogonal projection of the conductive portion D11 on the substrate 11 along the first direction X. In a possible embodiment, in combination with Figures 2A, 2C, 2F and 2G, the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X may be one-fifth to four-fifths of the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X; in a possible embodiment, the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X may be one-half of the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X.

[0152] In a possible implementation, as shown in FIG. 2A , the orthographic projection of the conductive portion D11 on the substrate 11 may cover the orthographic projection of the gap between two adjacent first electrodes D21 on the substrate 11 in the first direction X. In a possible implementation, as shown in FIG. 2A , the overlapping area of ​​the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first electrode D21 on the substrate 11 may account for one-fifth to four-fifths of the orthographic projection area of ​​the conductive portion D11 on the substrate 11; in a possible implementation, as shown in FIG. 2A , the overlapping area of ​​the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first electrode D21 on the substrate 11 may account for one-third of the orthographic projection area of ​​the conductive portion D11 on the substrate 11.

[0153] In a possible implementation, in combination with Figures 2A, 2C, 2F and 2G, the distance g6 between two adjacent first electrodes D21 in the first direction X may be one-fifth to four-fifths of the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 in the first direction X; in a possible implementation, in combination with Figures 2A, 2C, 2F and 2G, the distance g6 between two adjacent first electrodes D21 in the first direction X may be one-third of the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 in the first direction X.

[0154] In a possible implementation, in combination with Figures 2A, 2C, 2F and 2G, the maximum length g3 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the second direction Y may be smaller than the length g2 of the orthographic projection of the conductive portion D11 on the substrate 11 along the second direction Y.

[0155] In a possible implementation, in combination with FIG. 2C , the maximum length g7 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X may be one third to three thirds of the maximum length g8 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X; in a possible implementation, in combination with FIG. 2C , the maximum length g7 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X may be one half of the maximum length g8 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X.

[0156] In a possible implementation, in combination with FIG. 2C , a maximum length g9 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-third to three-thirds of a maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X; in a possible implementation, in combination with FIG. 2C , a maximum length g9 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-half of a maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X; a maximum length g11 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the first direction X may be one-half of a maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X.

[0157] In a possible embodiment, in combination with FIG. 2C , a maximum length g12 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the second direction Y may be equal to a maximum length g3 of the orthographic projection of the first portion CA of the first active pattern C11 on the substrate 11 along the second direction Y; in a possible embodiment, in combination with FIG. 2C , a maximum length g12 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the second direction Y may be greater than a length g13 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the second direction Y.

[0158] In a possible implementation, in combination with Figures 7A and 8, the spacing d1 between the orthographic projection of the sixth outer edge f6 on the substrate 11 and the orthographic projection of the fifth outer edge f5 on the substrate 11 in the first direction X is one-fifth to four-fifths of the length d2 of the orthographic projection of the second metal wire M21 on the substrate 11 in the first direction X.

[0159] In a possible implementation, as shown in FIG7A and FIG8 , the orthographic projection of the second metal line M21 on the substrate 11 covers the orthographic projection of the fifth outer edge f5 on the substrate 11. That is, the maximum upward movement of the second metal line M21 does not exceed the upper edge of the conductive portion D11.

[0160] In a possible implementation manner, a distance d1 between an orthographic projection of the sixth outer edge f6 on the substrate 11 and an orthographic projection of the fifth outer edge f5 on the substrate 11 in the first direction X is 1 μm to 3 μm. In a possible implementation manner, a distance d1 between an orthographic projection of the sixth outer edge f6 on the substrate 11 and an orthographic projection of the fifth outer edge f5 on the substrate 11 in the first direction X is 1.5 μm.

[0161] In a specific implementation, as shown in FIG. 2A , the second coupling capacitance C may be reduced by only making the minimum spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 larger than the minimum spacing b between the orthographic projection of the conductive portion D11 on the substrate 11 and the second sub-metal line MB on the substrate 11 (i.e., the conductive portion D11 is shifted to the right). dp2 With the first coupling capacitor C dp1 7A and 8, the second coupling capacitance C can be reduced by only making the orthographic projection of the sixth outer edge f6 on the substrate 11 located on the side where the orthographic projection of the fifth outer edge f5 on the substrate 11 faces the orthographic projection of the fifth sub-portion CB2 on the substrate 11 (that is, moving the second metal line M21 upward). dp2 With the first coupling capacitor C dp1 9, the minimum spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the minimum spacing b between the orthographic projection of the conductive portion D11 and the second sub-metal wire MB on the substrate 11 (i.e., the conductive portion D11 is moved to the right), and at the same time, the orthographic projection of the sixth outer edge f6 on the substrate 11 is located on the side where the orthographic projection of the fifth outer edge f5 on the substrate 11 faces the orthographic projection of the fifth sub-portion CB2 on the substrate 11 (i.e., the second metal wire M21 is moved upward), so as to reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0162] In a possible implementation, as shown in FIG. 2A and FIG. 3 , the first conductive layer D1 is located on the side of the first active layer C1 away from the substrate 11; the array substrate further includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via K1 penetrating the first insulating layer F1, the conductive portion D11 is electrically connected to the first portion CA through the first via K1; between two adjacent first metal wires M11, the first via K1 is at the center O1 of the orthographic projection of the substrate 11, and the minimum spacing d3 between the first via K1 and the first sub-metal wire MA on the orthographic projection of the substrate 11 is greater than the minimum spacing d4 between the first via K1 and the second sub-metal wire MB on the orthographic projection of the substrate 11. In the embodiment of the present disclosure, when the conductive portion D11 is moved rightward, the first via K1 that conducts the conductive portion D11 and the first active pattern C11 is also moved rightward to avoid affecting the conduction effect between the conductive portion D11 and the first active pattern C11 when the conductive portion D11 is moved rightward while the first via K1 is not moved rightward.

[0163] In a possible implementation, as shown in FIG. 2A and FIG. 3 , the first electrode D21 is located on a side of the first conductive layer D1 away from the substrate 11; the array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 penetrating the second insulating layer F2; the first electrode D21 is electrically connected to the K2 conductive portion D11 through the second via; between two adjacent first metal wires M11, the second via K2 is at the center O2 of the orthographic projection of the substrate 11, and the minimum spacing d5 between the second via K2 and the first sub-metal wire MA on the orthographic projection of the substrate 11 is greater than the minimum spacing d6 between the second sub-metal wire MB on the orthographic projection of the substrate 11. In the disclosed embodiment, when the conductive portion D11 is moved to the right, the second via K2 that conducts the first electrode D21 and the conductive portion D11 is also moved to the right, so as to avoid affecting the conduction effect between the first electrode D21 and the conductive portion D11 when the conductive portion D11 is moved to the right but the second via K2 is not moved to the right.

[0164] In a possible implementation, at least a portion of the orthographic projection of the first via K1 on the substrate 11 does not overlap with at least a portion of the orthographic projection of the second via K2 on the substrate 11. In a possible implementation, in combination with FIG. 2A and FIG. 3 , the entire orthographic projection of the first via K1 on the substrate 11 does not overlap with the entire orthographic projection of the second via K2 on the substrate 11.

[0165] In a possible implementation manner, the first insulating layer F1 includes one or a combination of the following:

[0166] A first gate insulating layer 15;

[0167] A first interlayer dielectric layer 16;

[0168] The second interlayer dielectric layer 17 .

[0169] Specifically, as shown in FIG. 3 , the first interlayer dielectric layer 16 may be located on a side of the first gate insulating layer 15 away from the substrate 11 ; the second interlayer dielectric layer 17 may be located on a side of the first interlayer dielectric layer 16 away from the substrate 11 .

[0170] In a possible implementation, as shown in FIG. 3 , the first insulating layer F1 includes: a first gate insulating layer 15 , a first interlayer dielectric layer 16 , and a second interlayer dielectric layer 17 .

[0171] In a possible implementation, in combination with FIG. 2A and FIG. 3 , the array substrate further includes: a third via hole K3 penetrating the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17 , and the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via hole K3 .

[0172] In a possible implementation, as shown in FIG. 2A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11; specifically, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In a possible implementation, the orthographic projection of the second via K2 on the substrate 11 is located at the overlapping region of the first electrode D21 and the conductive portion D11 on the substrate 11, so that the first electrode D21 is electrically connected to the conductive portion D11 at the overlapping region through the second via K2.

[0173] In a possible implementation, the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the first via K1 on the substrate 11. The orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. In a possible implementation, the orthographic projection of the first via K1 on the substrate 11 is located at the overlapping region of the orthographic projection of the first portion CA of the first active pattern C11 and the conductive portion D11 on the substrate 11, so as to realize the electrical connection of the first portion CA and the conductive portion D11 at the overlapping region through the first via K1.

[0174] In a possible implementation, the orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. Specifically, the orthographic projection of the third via K3 on the substrate 11 is located at the overlapping region of the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 on the substrate 11, so that the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3.

[0175] In a possible implementation, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 are both located between the orthographic projections of the first sub-metal wire MA and the second sub-metal wire MB on the substrate 11. In a possible implementation, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 have a gap in the first direction X. Specifically, the length of the gap between the first via K1 and the second via K2 in the first direction X may be one quarter to three quarters of the length of the conductive portion D11 in the first direction X.

[0176] In a possible embodiment, the third via K3 has a third via symmetry axis e3 extending along the second direction Y; the first electrode D21 has a first electrode outer edge f7 extending along the second direction Y and facing the side of the electrically connected conductive portion D11; the distance between the third via symmetry axis e3 and the first electrode outer edge f7 in the first direction X may be one quarter to three quarters of the length of the first electrode D21 along the first direction X; in a possible embodiment, the distance between the third via symmetry axis e3 and the first electrode outer edge f7 in the first direction X may be one half of the length of the first electrode D21 along the first direction X, and the third via symmetry axis e3 is located at a position where the length of the first electrode D21 along the first direction X is half.

[0177] In a specific implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17, and the conductive portion D11 can be moved rightward and / or the second metal trace M21 can be moved upward, so as to achieve accurate capacitance difference control and reduce the second coupling capacitor C dp2 With the first coupling capacitor C dp1 difference.

[0178] In a possible implementation manner, as shown in FIG. 3 , the thickness of at least one of the first gate insulating layer 15 , the first interlayer dielectric layer 16 , and the second interlayer dielectric layer 17 is greater than

[0179] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0180] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0181] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0182] In a possible implementation, as shown in FIG3 , the array substrate further includes: a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11; the third metal layer M3 includes: a plurality of third metal wires M31 extending along the second direction Y, and the orthographic projection of the third metal wires M31 on the substrate 11 covers the orthographic projection of the second metal wires M21 on the substrate 11. Specifically, the third metal wires M31 can be used to shield at least part of the first active pattern C11 of the first transistor to prevent the external ambient light from affecting the illumination of the first active pattern C11 and affecting the characteristics of the first transistor.

[0183] In a possible implementation, as shown in FIG. 2A , the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the gap between two adjacent first electrodes D21 in the first direction X on the substrate 11. In a possible implementation, as shown in FIG. 2A , the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the first portion CA of the first active pattern C11 on the substrate 11, and the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11. The orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the conductive portion D11 on the substrate 11.

[0184] In a possible implementation, as shown in FIG2A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In the disclosed embodiment, the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11, that is, the third metal wire M31 of the array substrate is used to cover the second via K2, which can reduce the risk of light leakage from the second via K2 on the array substrate.

[0185] Since virtual reality (VR) headsets are near-eye displays, and the images displayed on the LCD screen need to be magnified many times by the imaging system before they can enter the human eye, even if the current VR display resolution has reached more than 1000PPI, the screen door effect caused by the shading structure can still be seen in the display of the entire device. In view of this, in a possible implementation, referring to FIG. 10A, FIG. 10B and FIG. 10C, wherein FIG. 10B may be a single film layer schematic diagram of the third metal line M31 in FIG. 10A, FIG. 10B may also be a local schematic diagram at the dotted frame J1 in FIG. 10C, and FIG. 10C may be a schematic diagram of a larger range of FIG. 10B, the array substrate includes: a plurality of pixel light-transmitting areas P, the plurality of pixel light-transmitting areas P include: a plurality of pixel light-transmitting area rows H extending along a first direction X and arranged along a second direction Y; at least one pixel light-transmitting area row H of the plurality of pixel light-transmitting area rows H includes: a first pixel light-transmitting area P1, a second pixel light-transmitting area P2, and a third pixel light-transmitting area P3; the light band range emitted by the third pixel light-transmitting area P3 is smaller than the light band range emitted by the first pixel light-transmitting area P1 , and a light band range smaller than that of the second pixel light-transmitting area P2; specifically, the first pixel light-transmitting area P1 can be a pixel light-transmitting area emitting red light, the second pixel light-transmitting area P2 can be a pixel light-transmitting area emitting green light, and the third pixel light-transmitting area P3 can be a pixel light-transmitting area emitting blue light; the third metal wire M31 includes: a third metal wire main portion M310 extending along the second direction Y, and a first shielding structure Z1 connected to the third metal wire main portion M310; the maximum length h1 of the first shielding structure Z1 in the first direction X is greater than the maximum length h3 of the third metal wire main portion M310 in the first direction X; the orthographic projection of the first shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of at least partially adjacent two third pixel light-transmitting areas P3 on the substrate 11 in the first direction X.

[0186] Specifically, the array substrate further includes: a spacer (not shown in the figure, and specifically, the orthographic projection shape and position on the substrate 11 can be as shown in FIG. 10C, that is, the orthographic projection shape of the spacer on the substrate 11 can be an octagon, and can be located in the gap between the orthographic projections of at least two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the first direction X); the orthographic projection of the first shielding structure Z1 on the substrate 11 covers the orthographic projection of the spacer on the substrate 11. That is, the orthographic projection of the spacer on the substrate 11 is located in the gap between the orthographic projections of at least two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the first direction X.

[0187] In the disclosed embodiment, spacers are placed in the gaps between light-transmitting areas of adjacent blue pixels, which effectively reduces the human eye's sensitivity to compensation of obstructions (such as a black matrix) at the position of the spacers (blue pixels have lower brightness than green and red pixels, so placing spacers in the gaps between light-transmitting areas of adjacent blue pixels will give the human eye a smaller visual difference in light and dark than placing them on green and red pixels).

[0188] In a possible embodiment, referring to Figures 10A, 10B and 10C, the third metal wire M31 also includes: a second shielding structure Z2 connected to the third metal wire main portion M310; a maximum length h2 of the second shielding structure Z2 in the first direction X is greater than a maximum length h3 of the third metal wire main portion M310 in the first direction X, and less than a maximum length h1 of the first shielding structure Z1 in the first direction X; the orthographic projection of the second shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the second direction Y, and the orthographic projection of the second shielding structure Z2 on the substrate 11 does not overlap with the orthographic projection of the first shielding structure Z1 on the substrate 11.

[0189] In the disclosed embodiment, the orthographic projection of the second shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the second direction Y, and the orthographic projection of the second shielding structure Z2 on the substrate 11 does not overlap with the orthographic projection of the first shielding structure Z1 on the substrate 11, that is, the second shielding structure Z1 can be set at a position without spacers between adjacent blue pixels, which reduces the brightness difference between the positions of the blue pixels with spacers and without spacers, and makes the brightness more evenly distributed in the entire pixel area, thereby reducing the screen window effect and improving the visual effect.

[0190] In a possible implementation, a length m3 of the third pixel light-transmitting area P3 in the first direction X is smaller than a length m1 of the first pixel light-transmitting area P1 in the first direction X, and smaller than a length m2 of the second pixel light-transmitting area P2 in the first direction X.

[0191] Specifically, the pixel light-transmitting area P can be understood as the effective display area of ​​the pixel, which can be an area in the pixel area that is not blocked by a blocking structure (such as a light-shielding layer, a gate line, a data line, a black matrix, etc.). Specifically, in a possible implementation, as shown in FIG. 10C , the pixel light-transmitting area P can be shown as a white area.

[0192] In a possible implementation, the length m1 of the first pixel light-transmitting area P1 in the first direction X is equal to the length m2 of the second pixel light-transmitting area P2 in the first direction X. In the disclosed embodiment, the second shielding structure Z2 is set by setting the length m3 of the third pixel light-transmitting area P3 in the first direction X to be shorter, and the third pixel light-transmitting area P3 with a smaller light-emitting band range has a lower brightness than the first pixel light-transmitting area P1 and the second pixel light-transmitting area P2 with a longer light-emitting band range, which can effectively reduce the sensitivity of the human eye to the second shielding structure Z2, and can reduce the brightness difference between the position with spacers and the position without spacers between the third pixel light-transmitting area P3, so that the brightness is more evenly distributed in the entire pixel area, thereby reducing the screen window effect and improving the visual effect.

[0193] In the disclosed embodiment, the spacers can be placed at the gap between the light-transmitting areas of adjacent blue pixels, which effectively reduces the human eye's sensitivity to compensation of the shielding objects (such as black matrix) at the spacer position (the blue pixel has lower brightness than the green pixel and the red pixel, so placing the spacers at the gap between the light-transmitting areas of adjacent blue pixels will bring a smaller visual difference of light and dark to the human eye than placing them on the green pixel and the red pixel). In addition, the second shielding structure Z2 can be set at the position without spacers between adjacent blue pixels, which reduces the brightness difference between the position with spacers and the position without spacers of the blue pixels, making the brightness distribution in the entire pixel area more uniform, thereby reducing the screen door effect and improving the visual effect.

[0194] In a possible implementation, the wavelength range of light emitted by the third pixel light-transmitting area P3 may also be greater than the wavelength range of light emitted by the first pixel light-transmitting area P1, and greater than the wavelength range of light emitted by the second pixel light-transmitting area P2. Specifically, the third pixel light-transmitting area P3 may be a red pixel light-transmitting area, the first pixel light-transmitting area P1 may be a blue pixel light-transmitting area, and the second pixel light-transmitting area P2 may be a green pixel light-transmitting area. That is, the second shielding structure Z2 may be provided in at least part of the gap between two adjacent red pixel light-transmitting areas, and a spacer may be placed in the gap between two adjacent red pixel light-transmitting areas.

[0195] In a possible implementation, as shown in FIG10C , the orthographic projections of the first shielding structure Z1 and the second shielding structure Z2 on the substrate 11 are alternately distributed along the first direction X. Specifically, the first shielding structure Z1 and the second shielding structure Z2 may be located in the same column upward, such as both located in the column where the third pixel light-transmitting area P3 is located.

[0196] In a possible embodiment, the orthographic projection shape of the first shielding structure Z1 on the substrate 11 may be the same as the orthographic projection shape of the spacer on the substrate 11. For example, the orthographic projection shape of the spacer on the substrate 11 may be a hexagon, an octagon, a circle, or an ellipse; the orthographic projection shape of the first shielding structure Z1 on the substrate 11 may also be a hexagon, an octagon, a circle, or an ellipse.

[0197] Specifically, the orthographic projection shape of the second shielding structure Z2 on the substrate 11 may be a rectangle. The maximum length of the second shielding structure Z2 in the first direction X may be greater than the maximum length in the second direction Y.

[0198] Specifically, the ratio of the maximum length h2 of the second shielding structure Z2 in the first direction X to the maximum length h1 of the first shielding structure Z1 in the first direction X is greater than or equal to 0.78.

[0199] Specifically, the orthographic projection shape of the second shielding structure Z2 on the substrate 11 is a rectangle, and the maximum length h2 of the second shielding structure Z2 in the first direction X may be the length of the vertical side of the rectangle along the first direction X; the orthographic projection shape of the first shielding structure Z1 on the substrate 11 is an octagon, and the maximum length h1 of the first shielding structure Z1 in the first direction X may be the distance between two opposite sides of the octagon parallel to the second direction Y.

[0200] In a possible implementation, referring to FIG. 10C , in the pixel light-transmitting area row H, the first pixel light-transmitting area P1, the second pixel light-transmitting area P2, and the third pixel light-transmitting area P3 are arranged in sequence along the second direction Y; the pixel light-transmitting areas P with the same output light wavelength band range are located in the same first direction X, that is, the first pixel light-transmitting area P1 is located in the same column, the second pixel light-transmitting area P2 is located in the same column, and the third pixel light-transmitting area P3 is located in the same column.

[0201] In a possible embodiment, the maximum length h2 of the second shielding structure Z2 in the first direction X may be in the range of 8μm to 12μm, specifically, for example, 8μm, 9μm, 10μm, 10.5μm, 11μm, 12μm; the maximum length h1 of the first shielding structure Z1 in the first direction X may be in the range of 10μm to 15μm, specifically, for example, 10μm, 11μm, 12μm, 13μm, 13.5μm, 14μm, 15μm; the maximum length h3 of the third metal wire main portion M310 in the first direction X may be in the range of 5μm to 10μm, specifically, for example, 5μm, 6μm, 7μm, 7.5μm, 8μm, 9μm, 10μm.

[0202] In a possible implementation, as shown in FIG. 11 and FIG. 12, the array substrate further includes: a second active layer C2 located on the side of the first active layer C1 facing the substrate 11, a driving source drain (including a driving source MQ2 and a driving drain MQ3) located on the side of the second active layer C2 away from the substrate 11, and a driving gate MQ1. Specifically, the array substrate may include a gate driving circuit in the non-display area BB, and the gate driving circuit board includes: a plurality of second transistors, and the second transistor may include: a second active layer C2, a driving source drain (including a driving source MQ2 and a driving drain MQ3), and a driving gate MQ1. In the disclosed embodiment, the array substrate uses LTPO (Low Temperature Polycrystalline Oxide) technology, integrating two TFTs (Thin Film Transistor, Thin Film Field Effect Transistor) of LTPS (Low Temperature Poly-Silicon) and Oxide (oxide), which can enable AR and VR products to have high resolution (PPI, Pixel Per Inch), high aperture ratio and high transmittance.

[0203] In a possible implementation, referring to FIG. 11 and FIG. 12, the array substrate further includes: a first drive electrode MD1, a second drive electrode MD2, a third drive electrode MD3, and a fourth drive electrode MD4 located in the non-display area BB, wherein the first drive electrode MD1 is electrically connected to the second drive electrode MD2, and the third drive electrode MD3 is electrically connected to the fourth drive electrode MD4. Specifically, the first drive electrode MD1 can be used as a first signal line, and the third drive electrode MD3 can be used as a second signal line. The first signal line may include a signal line electrically connected to a gate drive circuit, and / or a signal line electrically connected to a multiplexer; the second signal line may include a signal line electrically connected to a gate drive circuit, and / or a signal line electrically connected to a multiplexer. The first signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line. The second signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line.

[0204] In a possible implementation, as shown in FIG. 11 , the second active layer C2 is located between the third metal layer M3 and the substrate 11; the driving gate MQ1 is located in the third metal layer M3; and the driving source and drain (including the driving source MQ2 and the driving drain MQ3) are located in the first metal layer M1. In the disclosed embodiment, the driving gate MQ1 is located in the third metal layer M3; and the driving source and drain are located in the first metal layer M1. The driving gate MQ1 and the driving source and drain corresponding to the non-display area can be formed while the third metal layer M3 and the first metal layer M1 are formed in the display area AA, thereby simplifying the manufacturing process of the display panel.

[0205] In a possible implementation, referring to FIG. 11 , the first driving electrode MD1 and the third driving electrode MD3 may be located in the first metal layer M1; the second driving electrode MD2 may be located in the third metal layer M3, and the fourth driving electrode MD4 may be located in the second metal layer M2; and thus, while forming the first metal layer M1 in the display area AA, the first driving electrode MD1 and the third driving electrode MD3 corresponding to the non-display area may be formed; while forming the second metal layer M2 in the display area AA, the fourth driving electrode MD4 corresponding to the non-display area may be formed; and while forming the third metal layer M3 in the display area AA, the second driving electrode MD2 corresponding to the non-display area may be formed, thereby simplifying the manufacturing process of the display panel.

[0206] In one possible implementation, at least part of the routing of the second metal layer M2 and at least part of the routing of the third metal layer M3 can be electrically connected by jumping layers in the non-display area BB. For example, the second metal line M21 and the third metal line M31 can be electrically connected in the non-display area BB to enable the transistors in the display area AA to form a dual-gate structure.

[0207] In a possible implementation, as shown in FIG. 12 , the second active layer C2 is located between the third metal layer M3 and the first active layer C1; the driving source and drain (including the driving source MQ2 and the driving drain MQ3) are located in the second metal layer M2; and the driving gate MQ1 is located in the third metal layer M3. In the disclosed embodiment, the driving source and drain are located in the second metal layer M2; and the driving gate MQ1 is located in the third metal layer M3. When the third metal layer M3 and the second metal layer M2 are formed in the display area AA, the corresponding driving gate MQ1 and the driving source and drain in the non-display area can be formed, which can simplify the manufacturing process of the display panel.

[0208] In a possible implementation, referring to FIG. 12 , the first driving electrode MD1 may be located in the first metal layer M1; the second driving electrode MD2 may be located in the second metal layer M2, and the third driving electrode MD3 may be located in the third metal layer M3; and thus, while forming the first metal layer M1 in the display area AA, the first driving electrode MD1 corresponding to the non-display area may be formed; while forming the second metal layer M2 in the display area AA, the second driving electrode MD2 corresponding to the non-display area may be formed; and while forming the third metal layer M3 in the display area AA, the third driving electrode MD3 corresponding to the non-display area may be formed, thereby simplifying the manufacturing process of the display panel.

[0209] In a possible implementation, in combination with FIG. 11, FIG. 13A-FIG. 13C, where FIG. 13B is a pattern of the third conductive layer corresponding to FIG. 13A, and FIG. 13B may also be a partial schematic diagram of the dotted frame in FIG. 13C, that is, FIG. 13C is a schematic diagram of a larger range of FIG. 13B, the array substrate further includes: a third conductive layer D3 located on the side of the second conductive layer D2 away from the substrate, the third conductive layer D3 includes a plurality of hollows L, and the orthographic projection of the hollows L on the substrate 11 overlaps with the portion of the first electrode D21 on the substrate 11. In the disclosed embodiment, the array substrate further includes a third conductive layer D3, the third conductive layer D3 includes a plurality of hollows L, and the orthographic projection of the hollows L on the substrate 11 overlaps with the portion of the first electrode D21 on the substrate 11, so that the first electrode D21 and the third conductive layer D3 can form a fringe electric field at the hollows L, thereby driving the liquid crystal to deflect. In the disclosed embodiment, the driving mode of the display panel may be a novel Fringe Field Switching (FFS) mode, or an Advanced Super Dimension Switch (ADS) mode.

[0210] It should be noted that, in order to clearly illustrate the various film layers, Figure 13A only illustrates the hollow L shape of the third conductive layer D3. The complete pattern of the third conductive layer D3 can be shown in Figure 13B, and the pattern of a larger area of ​​Figure 13B can be shown in Figure 13C.

[0211] Specifically, the third conductive layer D3 may be a common electrode layer, which forms an electric field with the first electrode D21 to drive the liquid crystal molecules between the array substrate and the opposite substrate.

[0212] In a possible implementation, the third conductive layer D3 may include: a plurality of hollow rows extending along the first direction X and arranged along the second direction Y; the hollow rows include: a plurality of hollows L sequentially arranged along the first direction X. In a possible implementation, as shown in FIG. 13A to FIG. 13C , the hollows L may correspond one-to-one to the first electrodes D21 .

[0213] In a possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the first metal wire M11 projected on the substrate 11; in a possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the third metal wire M31 projected on the substrate 11; in a possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the third metal wire M31 projected on the substrate 11.

[0214] In a possible implementation manner, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the gap between two adjacent hollow rows on the substrate 11 .

[0215] In a possible embodiment, referring to FIG. 11 and FIG. 12 , the array substrate further includes: a fourth metal layer M4 located on the side of the third conductive layer D3 facing the substrate 11 and in contact with the third conductive layer D3; the fourth metal layer M4 includes: a plurality of fourth metal wires M41 extending along the first direction X, the orthographic projection of the fourth metal wires M41 on the substrate 11 covering the orthographic projection of the first metal wires M11 on the substrate 11.

[0216] Specifically, the conductivity of the fourth metal layer M4 may be better than that of the third conductive layer D3. The plurality of fourth metal wires M41 disposed on the array substrate and in contact with the third conductive layer D3 may reduce the resistance of the third conductive layer D3.

[0217] In a possible implementation, as shown in FIG11 , the display panel may further include at least one of the following:

[0218] A buffer layer 12 located between the substrate 11 and the second active layer C2;

[0219] A second gate insulating layer 13 located between the second active layer C2 and the third metal layer M3;

[0220] A third interlayer dielectric layer 14 located between the third metal layer M3 and the first active layer C1;

[0221] A first gate insulating layer 15 located between the first active layer C1 and the second metal layer M2;

[0222] A first interlayer dielectric layer 16 located between the second metal layer M2 and the first metal layer M1;

[0223] A second interlayer dielectric layer 17 located between the first metal layer M1 and the first conductive layer D1;

[0224] A first planar layer 18 located between the first conductive layer D1 and the second conductive layer D2;

[0225] The second planar layer 19 is located between the second conductive layer D2 and the fourth metal layer M4.

[0226] In some examples, at least one of the buffer layer 12, the second gate insulating layer 13, the third interlayer dielectric layer 14, the first gate insulating layer 15, the first interlayer dielectric layer 16, the second interlayer dielectric layer 17, the first planarizing layer 18, and the second planarizing layer 19 may be an inorganic insulating layer, for example, any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) may be used, and may be a single layer, a multilayer, or a composite layer.

[0227] In a possible implementation, the material of the first active layer C1 includes: metal oxide doped with rare earth elements. Specifically, the material of the first active layer C1 is a metal oxide semiconductor material, and the metal oxide semiconductor material may include: any one or more of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element doped metal oxide (RE-OS), wherein the rare earth element doped metal oxide may include lanthanide doped metal oxide (Ln-OS); the crystal state of the active layer material may be amorphous, partially crystalline or polycrystalline. In the embodiment of the present disclosure, the material of the first active layer C1 is a metal oxide doped with rare earth elements, and the first active layer C1 may have stable performance even when exposed to light, and thus, no light shielding layer may be provided in the light-transmitting area P, which may further improve the aperture ratio of the display panel. In the embodiment of the present disclosure, the first active layer C1 of the display region transistor may be an oxide active layer, that is, the thin film transistor of the oxide active layer has advantages such as low leakage current.

[0228] In a possible implementation, the material of the second active layer C2 includes: low temperature polysilicon. That is, considering that the current high-transition oxide gate drive circuit design is not mature enough, the transistor size in the gate drive circuit will be larger, resulting in an excessively large frame. In the disclosed embodiment, the gate drive circuit of the non-display area can adopt a low temperature polysilicon transistor design.

[0229] In the embodiment of the present disclosure, the first active layer C1 of the first transistor in the display area can be an oxide active layer, and the second active layer C2 of the second transistor in the non-display area can be a polysilicon active layer. Since the oxide thin film transistor has the advantages of low leakage current, and the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display panel to form a low-temperature polycrystalline oxide display panel. By utilizing the advantages of both, high resolution (Pixel Per Inch, PPI) and low-frequency driving can be achieved, which can reduce power consumption and improve display quality. For example, the array substrate provided in the embodiment of the present disclosure combines the technical effects of high mobility and narrow frame of the second transistor of the second active layer C2 made of polysilicon material, and the display effect of high transmittance of the first transistor of the first active layer C1 made of metal oxide semiconductor material. When the array substrate is used in a display panel, the display effect of virtual reality can be further improved.

[0230] In a possible implementation, the first active layer C1 and the second active layer C2 may also be the same layer and the same material; specifically, the first active layer C1 and the second active layer C2 may both be oxide active layers. Specifically, for example, the materials of the first active layer C1 and the second active layer C2 may include: amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO). In the disclosed embodiment, when the active layers of the transistors in the display area and the non-display area are both oxide active layers, the second transistor in the non-display area and the first transistor in the display area may both adopt an oxide double-gate structure, and the bottom gate size of the second transistor in the non-display area is larger than the top gate size (the single-side package size may be 0.5μm to 2μm), which can effectively improve the on-state current and device stability of the second transistor in the non-display area; for the first transistor in the display area, the bottom gate size may be smaller than the top gate size (the bottom gate is 0.3μm to 0.6μm smaller than the top gate on one side), which can avoid affecting the aperture ratio.

[0231] In a possible implementation, the material of the first conductive layer D1 may include: metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0232] In a possible implementation, the material of the second conductive layer D2 may include: metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0233] In a possible implementation, the material of the third conductive layer D3 may include: metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0234] In a possible implementation, at least two of the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 are made of the same material. In a possible implementation, the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 may also be made of different materials.

[0235] In a possible embodiment, the material of at least one of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may include: any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0236] In a possible implementation, at least two of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are made of the same material. In a possible implementation, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may also be made of different materials.

[0237] In some examples, the substrate 11 may be a flexible substrate, or may be a rigid substrate. For example, the rigid substrate may include a glass substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-Si). However, the embodiments of the present disclosure are not limited to this.

[0238] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes an array substrate as provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate.

[0239] In a possible implementation, the opposing substrate may include an opposing substrate, a black matrix located on one side of the opposing substrate, and an optical adhesive layer located on a side of the black rectangle away from the opposing substrate.

[0240] In a possible implementation, the display panel further includes: a color filter layer; the color filter layer may be located on the opposite substrate, or the color filter layer may be located on the array substrate.

[0241] FIG14 is a schematic diagram of the structure of a display panel of at least one embodiment of the present disclosure. In some examples, as shown in FIG14, the display panel may include: a timing controller 20, a data driver 40, a gate drive circuit, and a sub-pixel array 10. The gate drive circuit may include at least one driver, for example, a scan driver 30. The timing controller 20, the data driver 40, and the gate drive circuit may be located in a non-display area outside the display area of ​​the display panel. The sub-pixel array 10 located in the display area may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driver 30 may be configured to provide a scan signal to the sub-pixel PX along a scan line; the data driver 40 may be configured to provide a data signal to the sub-pixel PX along a data line; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.

[0242] In some examples, the timing controller 20 may provide the data driver 40 with a grayscale value and a control signal suitable for the specifications of the data driver 40; the timing controller 20 may provide the scan driver 30 with a clock signal, an initial signal, etc. suitable for the specifications of the scan driver 30. The data driver 40 may generate a data voltage to be provided to the data lines D1 to Dn using the grayscale value and the control signal received from the timing controller 20. For example, the data driver 40 may sample the grayscale value using the clock signal, and apply the data signal corresponding to the grayscale value to the data lines D1 to Dn in units of sub-pixel rows. The scan driver 30 may generate a scan signal to be provided to the scan lines G1 to Gm using the clock signal, the initial signal, etc. received from the timing controller 20. For example, the scan driver 30 may sequentially provide a scan signal having an on-level pulse to the scan line. In some examples, the scan driver 30 may include a shift register, and may sequentially transmit the scan initial signal provided in the form of an on-level pulse to the next level circuit under the control of the clock signal to generate a scan signal. Wherein, n and m are both natural numbers.

[0243] In some examples, the gate driver circuit can be directly disposed on the substrate. For example, the gate driver can be disposed in the peripheral areas on the left and right sides of the display area. In some examples, the gate driver can be formed together with the sub-pixel in the process of forming the sub-pixel. However, the present embodiment does not limit the position or formation method of the gate driver. In some examples, the gate driver can be disposed on a separate chip or printed circuit board to connect to a pad or pad formed on the substrate substrate.

[0244] In some examples, the data driver 40 may be disposed on a separate chip or printed circuit board to be connected to the sub-pixel PX through a signal access pin disposed on the substrate. For example, the data driver 40 may be formed by a chip on glass, a chip on plastic, a chip on a film, etc. to be connected to a signal access pin on the substrate. The timing controller 20 may be disposed separately from the data driver 40 or integrally with the data driver 40. However, this embodiment is not limited thereto.

[0245] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0246] In the embodiment of the present disclosure, the minimum spacing a between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the minimum spacing b between the orthographic projection of the second sub-metal line MB on the substrate 11, which can increase the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C dp2 , and due to the first coupling capacitor C dp1 In the embodiment, the overlap capacitance between the first active pattern C11 and the conductive portion D11 (the area shown by the thick solid frame S in FIG. 5D ) accounts for the main part, and the distance between the conductive portion D11 and the second sub-metal line MB is reduced, which will not affect the first coupling capacitor C dp1 This has a significant impact, thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference can be reduced to improve the vertical crosstalk problem.

[0247] It should be noted that in the present disclosure, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask plate through a single patterning process. That is, one patterning process corresponds to a mask plate (mask, also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0248] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0249] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

An array substrate comprises a display area and a non-display area located outside the display area, wherein: include: substrate; The first active layer is located on one side of the substrate, and includes: a plurality of first active patterns located in the display area; the first active pattern includes: a first portion extending along a first direction, and a second portion extending from one end of the first portion; the first metal layer includes: a plurality of first metal wires extending along the first direction; the orthographic projection of the first portion on the substrate is located between the orthographic projections of adjacent first metal wires on the substrate, and the orthographic projection of the second portion on the substrate overlaps with the orthographic projection of the first metal wire on the substrate; the first conductive layer includes: a plurality of conductive portions located in the display area; the orthographic projection of at least one of the plurality of conductive portions on the substrate is located between the orthographic projections of adjacent first metal wires on the substrate; the second conductive layer includes: a plurality of first electrodes located in the display area; wherein the first metal wires on adjacent sides of the conductive portion include: a first sub-metal wire and a second sub-metal wire; wherein the first sub-metal wire is electrically connected to the second portion; the first portion is electrically connected to the first electrode through the conductive portion; the orthographic projection of the conductive portion on the substrate is spaced apart from the orthographic projection of the first sub-metal wire on the substrate by a greater distance than the orthographic projection of the conductive portion on the substrate by the second sub-metal wire on the substrate. The array substrate according to claim 1, wherein: The conductive part, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 15%≤b / a≤75%, wherein a represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the first sub-metal wire on the substrate, and b represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the second sub-metal wire on the substrate. The array substrate according to claim 2, wherein: The conductive portion, the first sub-metal line, and the second sub-metal line satisfy the following relationship: 3%≤(ab) / c≤15%, wherein c represents the minimum spacing between adjacent first sub-metal lines and second sub-metal lines. The array substrate according to claim 3, wherein: The conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 60%≤d / c≤95%, wherein d represents the length of the conductive portion in a direction perpendicular to the first direction. The array substrate according to any one of claims 1 to 4, wherein: The first portion has a first symmetry axis extending along the first direction, and the conductive portion has a second symmetry axis extending along the first direction; the second symmetry axis is located on a side of the first symmetry axis away from the first sub-metal line. The array substrate according to any one of claims 1 to 5, wherein: The first electrode has a first outer edge extending along the first direction; between two adjacent first metal wires, the first outer edge is located on a side of the first portion in the substrate projection away from the first sub-metal wire at the part of the substrate projection; the conductive portion has a second outer edge extending along the first direction; between two adjacent first metal wires, the second outer edge is located on a side of the first portion in the substrate projection away from the first sub-metal wire at the part of the substrate projection; between two adjacent first metal wires, the second outer edge is located on a side of the first outer edge away from the first sub-metal wire at the part of the substrate projection. The array substrate according to claim 6, wherein: The first electrode has a third outer edge extending along the first direction; between two adjacent first metal wires, the third outer edge is located in the part of the orthogonal projection of the substrate, on the side of the orthogonal projection of the first portion on the substrate close to the first sub-metal wire; the conductive portion has a fourth outer edge extending along the first direction; between two adjacent first metal wires, the fourth outer edge is located in the part of the orthogonal projection of the substrate, on the side of the orthogonal projection of the first portion on the substrate close to the first sub-metal wire; between two adjacent first metal wires, the fourth outer edge is located in the part of the orthogonal projection of the substrate, on the side of the third outer edge on the orthogonal projection of the substrate away from the first sub-metal wire. The array substrate according to claim 6, wherein: The first electrode has a third outer edge extending along the first direction; between two adjacent first metal wires, the third outer edge is located in the part of the orthogonal projection of the substrate, on the side of the orthogonal projection of the first part on the substrate close to the first sub-metal wire; the conductive part has a fourth outer edge extending along the first direction; between two adjacent first metal wires, the fourth outer edge is located in the part of the orthogonal projection of the substrate, on the side of the orthogonal projection of the first part on the substrate close to the first sub-metal wire; between two adjacent first metal wires, the third outer edge is overlapped with the fourth outer edge in the part of the orthogonal projection of the substrate. The array substrate according to any one of claims 1 to 8, wherein: The array substrate also includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer including: a plurality of second metal wires extending along a second direction; the first portion includes: a first sub-portion, a second sub-portion, and a third sub-portion sequentially distributed along the first direction; wherein the orthographic projection of the second sub-portion on the substrate overlaps with the orthographic projection of the second metal wire on the substrate; the first sub-portion is located on a side of the second sub-portion facing the second portion, and the third sub-portion is located on a side of the second sub-portion away from the second portion; the orthographic projection of the first sub-portion on the substrate has an overlapping area with the orthographic projection of the conductive portion on the substrate. The array substrate according to any one of claims 1 to 8, wherein: The array substrate also includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer includes: a plurality of second metal wires extending along a second direction; the second portion includes: a fourth sub-portion connected to the first portion and extending along a third direction, and a fifth sub-portion connected to the fourth sub-portion, the first metal wire is electrically connected to the fifth sub-portion; the second direction intersects with the first direction, and the third direction intersects with the first direction; the conductive portion includes: a fifth outer edge extending along the second direction and toward the fifth sub-portion; the orthographic projection of the second metal wire on the substrate covers the orthographic projection of the fifth outer edge on the substrate. The array substrate according to claim 10, wherein: The distance between the orthographic projection of the sixth outer edge on the substrate and the orthographic projection of the fifth outer edge on the substrate in the first direction is one fifth to four fifths of the length of the orthographic projection of the second metal line on the substrate in the first direction. The array substrate according to claim 10, wherein: The second metal line has a sixth outer edge extending along the second direction and facing the fifth sub-portion; The orthographic projection of the sixth outer edge on the substrate is located on a side of the orthographic projection of the fifth outer edge on the substrate that faces the orthographic projection of the fifth sub-portion on the substrate. The array substrate according to any one of claims 1 to 12, wherein: The first conductive layer is located on the side of the first active layer away from the substrate; the array substrate also includes: a first insulating layer located between the first active layer and the first conductive layer, and a first via hole penetrating the first insulating layer, and the conductive part is electrically connected to the first part through the first via hole; between two adjacent first metal wires, the first via hole is at the center of the orthographic projection of the substrate, and the minimum spacing with the first sub-metal line on the orthographic projection of the substrate is greater than the minimum spacing with the second sub-metal line on the orthographic projection of the substrate. The array substrate according to claim 13, wherein: The first electrode is located on a side of the first conductive layer away from the substrate; the array substrate also includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via hole penetrating the second insulating layer; the first electrode is electrically connected to the conductive portion through the second via hole; between two adjacent first metal wires, the second via hole is at the center of the orthographic projection of the substrate, and the minimum spacing from the first sub-metal line on the orthographic projection of the substrate is greater than the minimum spacing from the second sub-metal line on the orthographic projection of the substrate. The array substrate according to claim 14, wherein: At least a portion of an orthographic projection of the first via hole on the substrate does not overlap with at least a portion of an orthographic projection of the second via hole on the substrate. The array substrate according to any one of claims 13 to 15, wherein: The first insulating layer includes one or a combination of the following: a first gate insulating layer; a first interlayer dielectric layer; and a second interlayer dielectric layer. The array substrate according to claim 16, wherein: The thickness of at least one of the first gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer is greater than The array substrate according to any one of claims 9 to 17, wherein: The array substrate further includes: a third metal layer located on the side of the first active layer facing the substrate; the third metal layer includes: a plurality of third metal wires extending along the second direction, the orthographic projection of the third metal wire on the substrate covering the orthographic projection of the second metal wire on the substrate. The array substrate according to claim 18, wherein: The array substrate comprises: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas comprising: a plurality of pixel light-transmitting area rows extending along the first direction and arranged along the second direction; at least one of the plurality of pixel light-transmitting area rows comprises: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; the light band range emitted by the third pixel light-transmitting area is smaller than the light band range emitted by the first pixel light-transmitting area, and smaller than the light band range of the second pixel light-transmitting area; the third metal wire comprises: a third metal wire main part extending along the second direction, and a first shielding structure connected to the third metal wire main part; the maximum length of the first shielding structure in the first direction is greater than the maximum length of the third metal wire main part in the first direction; the orthographic projection of the first shielding structure on the substrate is located in the gap between the orthographic projections of at least partially adjacent two third pixel light-transmitting areas on the substrate in the first direction. The array substrate according to claim 19, wherein: The array substrate further includes: a spacer; and an orthographic projection of the first shielding structure on the substrate, covering the orthographic projection of the spacer on the substrate. The array substrate according to claim 18 or 19, wherein: The third metal wire also includes: a second blocking structure connected to the main portion of the third metal wire; the maximum length of the second blocking structure in the first direction is greater than the maximum length of the main portion of the third metal wire in the first direction, and less than the maximum length of the first blocking structure in the first direction; the orthographic projection of the second blocking structure on the substrate is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas on the substrate in the second direction, and the orthographic projection of the second blocking structure on the substrate does not overlap with the orthographic projection of the first blocking structure on the substrate. The array substrate according to any one of claims 18 to 21, wherein: The array substrate further comprises, located in the non-display area: a second active layer located on a side of the first active layer facing the substrate, a driving source and drain located on a side of the second active layer away from the substrate, and a driving gate. The array substrate according to claim 22, wherein: The material of the first active layer includes: metal oxide; the material of the second active layer includes: low temperature polysilicon. The array substrate according to claim 22 or 23, wherein: The second active layer is located between the third metal layer and the substrate; the driving gate is located in the third metal layer; and the driving source and drain are located in the first metal layer. The array substrate according to claim 24, wherein: The second active layer is located between the third metal layer and the first active layer; the driving source and drain are located in the second metal layer; and the driving gate is located in the third metal layer. The array substrate according to any one of claims 1 to 25, wherein: The array substrate further includes: a third conductive layer located on a side of the second conductive layer away from the substrate, the third conductive layer including a plurality of hollows, and the hollows overlap with a portion of the first electrode on the substrate at a portion of the orthographic projection of the substrate. The array substrate according to claim 26, wherein: The array substrate also includes: a fourth metal layer located on the side of the third conductive layer facing the substrate and in contact with the third conductive layer; the fourth metal layer includes: a fourth metal wire extending along the first direction, the orthographic projection of the fourth metal wire on the substrate covering the orthographic projection of the first metal wire on the substrate. A display panel, wherein It comprises the array substrate as described in any one of claims 1 to 27, and also comprises an opposite substrate arranged opposite to the array substrate. A display device, wherein Comprising the display panel as claimed in claim 28.

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