Semiconductor device and forming method thereof

Abstract

The method includes: adding a first additive to the electroplating solution, where the first additive is a relatively weak inhibitor; adding a second additive to the electroplating solution, where the second additive is a relatively strong inhibitor; adding a third additive to the electroplating solution, the third additive being a leveling agent; and depositing copper using the electroplating solution wherein a majority of the copper is nano-twin grains having a (111) orientation. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography techniques to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be solved. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: adding a first additive to an electroplating solution, wherein the first additive is a relatively weak inhibitor; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong inhibitor; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper includes nanotwin grains having a (111) orientation.

[0005] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming an opening in a dielectric layer; depositing copper in the opening using an electroplating process, wherein the copper deposited in the opening is (111) oriented, wherein the electroplating process comprises using an electroplating solution, wherein the electroplating solution comprises: a first additive, wherein the first additive comprises an inhibiting functional group and a metal coordination functional group; and a second additive, wherein the second additive is a polymer.

[0006] Still other embodiments of the present application provide a semiconductor device, comprising: a dielectric layer located above a substrate; and a conductive via located in the dielectric layer, wherein the conductive via comprises a first nanotwinned copper region and a second nanotwinned copper region, wherein the first nanotwinned copper region is separated from a sidewall of the dielectric layer by the second nanotwinned copper region, and wherein the first nanotwinned copper region has a greater (111)-oriented grain density than that of the second nanotwinned copper region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 Cross-sectional views of intermediate steps during a process for forming conductive features are shown in accordance with some embodiments.

[0010] Fig.10 A cross-sectional view of a conductive component is shown in accordance with some embodiments.

[0011] Fig.11 A cross-sectional view of a conductive component is shown in accordance with some embodiments.

[0012] Fig.12 , Fig.13 , Fig.14 and Fig.15 Cross-sectional views of intermediate steps during a process for forming conductive features are shown in accordance with some embodiments.

[0013] Fig.16 A cross-sectional view of an interconnect structure according to some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] According to some embodiments, a process for forming a conductive component includes using an additive in a copper electroplating process. The additive includes a weak inhibitor additive (which includes an inhibitory functional group and a metal coordination functional group), a strong inhibitor additive, and a leveling additive. The use of these additives during the electroplating process promotes the growth of nanotwinned copper, such as (111) oriented copper. In this way, the conductive component can be mainly formed of (111) oriented copper. In addition, the additive can form a conductive component with low surface roughness.

[0017] Figure 1 A cross-sectional view of an intermediate stage in the fabrication of an integrated circuit die 100 is shown in accordance with some embodiments. Figure 1 For example, device regions within which an integrated circuit die 100 is formed may be shown. The integrated circuit die 100 may be a logic device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc., or a combination thereof (e.g., a system on chip (SoC) die). The integrated circuit die 100 may be formed in a wafer, etc., which may include multiple device regions. In some instances, the device regions may be subsequently separated to form separate integrated circuit dies 100. The integrated circuit die 100 is used as an illustrative example, and the embodiments or techniques described herein may be applicable to other structures, such as interposers, packages, interconnects, chips, chiplets, etc., which may or may not include active devices.

[0018] The integrated circuit die 100 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 100 can include a substrate 102, which can be a semiconductor substrate (doped or undoped) such as silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The substrate 102 can include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the substrate 102 can be a wafer, such as a silicon wafer, etc. In some embodiments, the substrate 102 has an active surface sometimes referred to as a front side (e.g., Figure 1 The surface facing upward in the middle) and the passive surface sometimes called the back side (e.g. Figure 1 downward facing surface).

[0019] Device 104 may be formed at the active surface of substrate 102 (at Figure 1 104 is represented by a transistor in the figure). The device 104 can be formed in a front-end-of-line (FEOL) process using applicable manufacturing processes (such as acceptable deposition, lithography, and etching techniques). The device 104 may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. For example, the device 104 may include a gate structure and a source / drain region, wherein the gate structure is located on the channel region and the source / drain region is adjacent to the channel region. The source / drain region may refer to a source or a drain, individually or collectively depending on the context. The channel region may be a patterned region of the substrate 102. For example, the channel region may be a region of a semiconductor fin, a semiconductor nanostructure, a semiconductor nanosheet, a semiconductor nanowire, etc. formed in or on the substrate 102. When the devices 104 are transistors, they may be any suitable type of transistor, such as a nanostructure field effect transistor (nanostructure FET), a fin field effect transistor (FinFET), a planar transistor, etc. Other devices 104 are also possible.

[0020] In some embodiments, an interlayer dielectric (ILD) 106 is formed over the active surface of the substrate 102. The ILD 106 surrounds the device 104 and may cover the device 104. The ILD 106 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., which may be formed by a deposition process such as spin coating, lamination, chemical vapor deposition (CVD), flowable CVD, etc. A contact 108 extending through the ILD 106 may be formed to electrically and physically couple the device 104. For example, when the device 104 is a transistor, the contact 108 may couple the gate and / or source / drain regions of the transistor. The contact 108 may be formed of a suitable conductive material, such as tungsten, cobalt, ruthenium, nickel, copper, silver, gold, aluminum, or the like, or a combination thereof, which may be formed by a deposition process such as physical vapor deposition (PVD) or CVD, a plating process such as electrolytic plating or chemical plating, or the like.

[0021] In some embodiments, an interconnect structure 110 is formed over the ILD 106 and the contacts 108. The interconnect structure 110 can be electrically connected to the device 104 through the contacts 108. In this manner, the interconnect structure 110 provides interconnection and electrical routing for the integrated circuit die 100. In some instances, the interconnect structure 110 can be formed in a back end of line (BEOL) process. In some instances, more than one interconnect structure can be formed, and each of the interconnect structures can include different materials or have other different characteristics.

[0022] The interconnect structure 110 may be formed of, for example, a plurality of conductive features 112 formed in a plurality of dielectric layers 114. Figure 1 The conductive features 112 may include, for example, conductive wires, conductive vias, conductive pads, metallization patterns, redistribution layers, etc. The conductive features 112 include metal lines and vias, which may be formed in the dielectric layer 114 by a deposition process, a damascene process (e.g., a single damascene process, a dual damascene process, etc.), etc. The conductive features 112 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc. The following describes the conductive features 112 in more detail. Figures 2 to 9 Intermediate steps in the formation of conductive features 112 comprising copper are shown in accordance with some embodiments.

[0023] In some embodiments, dielectric layer 114 may be formed of: a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride such as silicon nitride; an oxide such as silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, flowable CVD (FCVD) oxide, etc.; a molding material, a sealant, an epoxy resin, etc.; etc.; or a combination thereof. Dielectric layer 114 may be, for example, a low-k dielectric layer. Dielectric layer 114 may be formed by any acceptable deposition process, such as spin coating, CVD, lamination, etc., or a combination thereof. In some instances, dielectric layer 114 may include an etch stop layer (not shown separately). Dielectric layer 114 may be the same material or may include different materials.

[0024] Figures 2 to 9 The conductive component 112 (see FIG. Fig. 9 ) is an intermediate step in the formation of the conductive member 112. The conductive member 112 may be similar to the previously described Figure 1 For example, the conductive feature 112 may be formed in the dielectric layer 114. In this manner, Figures 2 to 9 The steps shown in can be intermediate steps in the formation of the interconnect structure 110. As an illustrative example, the conductive feature 112 includes an upper portion 113A (e.g., a wire portion) and a lower portion 113B (e.g., a conductive via portion), but other conductive features 112 can be formed using the materials and techniques described herein.

[0025] Figure 2 1 shows a cross-sectional view of a dielectric layer 114 over a substrate 102 according to some embodiments. For example, the dielectric layer 114 may be Figure 1 Thus, the dielectric layer 114 may be similar to that previously described for Figure 1 A dielectric layer 114 is depicted, but other dielectric layers are possible.

[0026] exist Figure 3 In accordance with some embodiments, opening 118 is formed in dielectric layer 114 . Figure 3An opening 118 is shown extending partially through the dielectric layer 114, but in other embodiments, the opening 118 may extend completely through the dielectric layer 114 and may extend into the underlying dielectric layer. In other embodiments, the opening 118 may expose the underlying conductive features or may expose the underlying dielectric layer. In some embodiments, the opening 118 may "stop" on an etch stop layer (not shown) and may expose the etch stop layer. In some embodiments, the opening 118 may be formed from the top surface of the dielectric layer 114 to have a depth D1 in the range of about 0.5 μm to about 200 μm, but other depths are possible. In some embodiments, the opening 118 may be formed to have a width W1 in the range of about 0.2 μm to about 60 μm, but other widths are possible. Figure 3 The opening 118 is shown as having approximately vertical sidewalls, but in other embodiments, the opening 118 may have sloped sidewalls, tapered sidewalls, convex sidewalls, concave sidewalls, or sidewalls having another profile different from these examples.

[0027] The opening 118 can be formed using suitable photolithography and etching techniques. For example, in some embodiments, a photoresist (not shown) is formed and patterned above the dielectric layer 114. The photoresist can be deposited using suitable techniques such as spin coating. The photoresist can then be exposed to light for patterning, for which the pattern of the photoresist corresponds to the opening 118. The photoresist can then be patterned using suitable developing techniques. The opening 118 can then be formed by implementing one or more etching steps using the patterned photoresist as an etching mask. The etching step can include one or more suitable wet etching processes and / or dry etching processes.

[0028] In other embodiments where dielectric layer 114 is formed of a photosensitive material such as PBO, polyimide, BCB, etc., the dielectric layer can be patterned using a photolithographic mask. Patterning can include a suitable process such as exposing and developing dielectric layer 114 to light. Dielectric layer 114 can then be developed to form opening 118.

[0029] According to some embodiments, Figure 4 In the embodiment of the present invention, a seed layer 116 is deposited on the surface of the dielectric layer 114 and within the opening 118. The seed layer 116 is a metal layer, which can be a single layer or a composite layer including multiple layers formed of different materials. In some embodiments, the seed layer 116 includes a titanium layer and a copper layer above the titanium layer, but other materials or combinations thereof are also possible. The seed layer 116 can be conformally deposited using, for example, physical vapor deposition (PVD). In some embodiments, the seed layer 116 also includes one or more liner layers, such as a barrier layer, an adhesion layer, a glue layer, etc.

[0030] Figures 5 to 9An intermediate stage of depositing conductive material to form conductive feature 112 is shown in accordance with some embodiments. Figures 5 to 9 In some embodiments, the conductive material is copper deposited using an electroplating process. In some embodiments, the electroplating process includes using an additive 120 (e.g., additives 121, 122, and 123, depicted below), which promotes bottom-up deposition of copper having a (111) oriented crystal structure. In this way, the conductive component 112 can be primarily formed of (111) oriented copper, which can provide the benefits of (111) oriented copper, such as good mechanical properties (e.g., good tensile strength), good electrical conductivity, or good thermal stability. In some embodiments, the copper is deposited as a polycrystalline structure including a large number of (111) oriented grains. In some instances, a copper layer having a uniform grain orientation can be referred to as nanotwinned copper (nt-Cu), such as (111) oriented nt-Cu. In some instances, the techniques described herein allow for the formation of a copper layer of at least about 97% (111) oriented copper, but other amounts of (111) oriented copper are also possible. For example, scanning electron microscope (SEM) analysis or electron backscatter diffraction (EBSD) analysis of a copper layer formed using the techniques described herein can show that greater than 97% of the copper is (111) oriented. In some examples, the techniques described herein allow for extreme bottom-up filling with good morphology control and low surface roughness.

[0031] The electroplating process includes immersing the structure (including the seed layer 116) in the electroplating solution and applying an electric potential to generate an electric current in the electroplating solution. In some embodiments, the electroplating process is implemented at a temperature in the range of about 10°C to about 50°C. In some embodiments, the current density of the electroplating process is in the range of about 0.1ASD to about 10ASD. In some embodiments, the electroplating process is implemented for a duration in the range of about 30 seconds to about 15 minutes. Other electroplating process parameters or conditions are also possible. In some embodiments, the amount of deposited copper can be controlled by controlling the current and / or duration of the electroplating process.

[0032] In some embodiments, the electroplating solution includes a copper salt, a halogen ion source, an acid, and one or more additives (e.g., additives 121, 122, and / or 123). The copper salt converts copper ions (e.g., Cu 2+) is provided to the electroplating solution, and may include one or more suitable copper salts, such as copper acetate persulfate (II), copper gluconate, copper fluoroborate, copper nitrate, alkyl copper sulfonate, aryl copper sulfonate, etc. or a combination thereof. In other embodiments, other copper salts or functionally similar materials may be used. In some embodiments, the copper salt is present in an amount sufficient to provide an amount of copper ions in the range of about 10 g / L to about 50 g / L in the electroplating solution. In some embodiments, the halogen ion source may be hydrochloric acid (e.g., it provides chloride ions) or the like. In some embodiments, the acid may include sulfuric acid, nitric acid, methanesulfonic acid, benzenesulfonic acid, etc. or a combination thereof. In other embodiments, other copper salts, halogen ion sources, acids or a combination thereof may be used.

[0033] In some embodiments, the electroplating solution may include one or more additives, such as a first additive 121, a second additive 122, and / or a third additive 123, described in more detail below. The first additive 121, the second additive 122, and the third additive 123 may be collectively referred to herein as additives 120. The use of additives 121, 122, and 123 as described herein may result in the deposition of a copper layer that primarily includes (111) oriented grains, as previously described. In some embodiments, the first additive 121 serves to inhibit the deposition of Cu that is not (111) oriented. 2+ growth and / or promote the (111) oriented Cu 2+ In some embodiments, the second additive 122 is used to inhibit the growth of Cu 2+ A relatively strong inhibitor of growth on the sidewall surface (eg, a relatively strong inhibitor). In some embodiments, the third additive 123 acts as a Cu 2+ The leveling agent (eg, leveling agent) grows on the raised surface, thereby promoting overall surface planarity. In some embodiments, the additive 120 and / or the electroplating solution is free of accelerating additives (eg, accelerators).

[0034] The additive 120 may be added to the electroplating solution together before the electroplating process is performed, or the additive 120 may be added to the electroplating solution at different stages or steps during the electroplating process. In this way, the absolute or relative concentrations of the first additive 121, the second additive 122, and the third additive 123 within the electroplating solution may vary throughout the entire electroplating process. As an example, initially, the second additive 122 may be added to the electroplating solution before the electroplating process is performed, and then the first additive 121 and the third additive 123 may be subsequently added to the electroplating solution during the electroplating process. In some examples, adding the second additive 122 first may better inhibit Cu during the electroplating process. 2+Growth on the sidewalls. This is an example, and in other embodiments, the additive 120 may be added to the plating solution in different ways.

[0035] In some embodiments, the first additive 121 includes a molecule having at least one inhibition functional group and at least one metal coordination functional group. The inhibition functional group of the first additive 121 can inhibit the non-(111) oriented Cu during the electroplating process. 2+ In some embodiments, the inhibitory functional group of the first additive 121 may include a hydrogen functional group, an aliphatic functional group, an aromatic functional group, a combination thereof, and the like. In some embodiments, the inhibitory functional group of the first additive 121 may include a hydroxyl functional group, an ether functional group, an amine functional group, a sulfide functional group, a carboxylic acid functional group, an ester functional group, an amide functional group, an imide functional group, an imine functional group, a combination thereof, and the like. Other inhibitory functional groups are also possible. The molecules of the first additive 121 may include multiple inhibitory functional groups, which may be similar or different.

[0036] The metal coordination functional group of the first additive can promote the Cu 2+ The (111) oriented growth can also promote the non-(111) oriented Cu 2+ Become (111) oriented. In some embodiments, the metal coordination functional group of the first additive 121 may include a hydroxyl functional group, an ether functional group, an amine functional group, a sulfide functional group, a carboxylic acid functional group, an ester functional group, an amide functional group, an imide functional group, an imine functional group, a combination thereof, etc. Other metal coordination functional groups are also possible. The molecules of the first additive 121 may include multiple metal coordination functional groups, which may be similar or different. In some instances, Fourier transform infrared (FTIR) spectroscopy analysis may be able to determine the type or composition of the metal coordination functional group of the first additive 121.

[0037] In some embodiments, the first additive 121 may include gelatin, etc. In some embodiments, the first additive 121 may include the following structures:

[0038]

[0039] In this exemplary structure, R1, R2, R3, R4 and R5 represent inhibition functional groups, which may be similar or different, and X1, X2 and X3 represent metal coordination functional groups, which may be similar or different. The inhibition functional groups R1, R2, R3, R4 and / or R5 may be similar to the inhibition functional groups described above, and the metal coordination functional groups X1, X2 and / or X3 may be similar to the metal coordination functional groups described above. However, as will be appreciated by those of ordinary skill in the art, the examples presented above are intended to be illustrative and are not intended to limit the scope.

[0040] The combination of the inhibitory functional group and the metal coordination functional group on the first additive 121 can promote the formation of (111) oriented copper and inhibit the formation of non-(111) oriented copper. In some embodiments, the first additive 121 does not inhibit the formation of Cu as much as the second additive 122 (described below). 2+ growth. Therefore, in some instances, the first additive 121 can be considered a relatively weak inhibitor. In some embodiments, the first additive 121 has an average molecular weight greater than about 5000Da, such as a molecular weight in the range of about 5000Da to about 20000Da, but other molecular weights are also possible. In some embodiments, the first additive 121 has an average molecular weight less than the average molecular weight of the second additive 122. For example, in some embodiments, the average molecular weight of the first additive 121 may be approximately equal to or less than about half of the average molecular weight of the second additive 122. In some embodiments, the molecules of the first additive 121 may be smaller than the molecules of the second additive 122. The molar concentration of the first additive 121 in the electroplating solution may be in the range of about 0.05mol / L to about 50mol / L, but other concentrations are also possible.

[0041] In some embodiments, the second additive 122 includes relatively large molecules that accumulate on the sidewalls and some other surfaces and inhibit the Cu 2+ For example, the second additive 122 can inhibit the growth of Cu 2+ Growth on the sidewalls of the opening 118 and on the top surface of the dielectric layer 114. In some instances, the presence of the second additive 122 on the sidewalls of the opening 118 can form copper with a concave surface in the opening 118. In some embodiments, the second additive 122 is polymeric and includes macromolecules having a linear structure, a branched chain structure, a cross-linked structure, or a combination thereof. In some embodiments, the second additive 122 includes organic molecules, including but not limited to polymers and organic frameworks. In some embodiments, the second additive 122 includes a polyether compound. In some embodiments, the second additive 122 includes: a polyoxyalkylene random copolymer, including two or more oxyalkylene monomers or an oxyethylene-oxypropylene random copolymer as a polymerization unit. In some embodiments, the second additive 122 is derived from polyethylene oxide (PEO), polypropylene oxide (PPO), polyethylene glycol (PEG), polypropylene glycol (PPG), or their derivatives or copolymers. Other second additives 122 are also possible.

[0042] In some examples, the second additive 122 can suppress Cu more than the first additive 121. 2+growth. Therefore, in some instances, the second additive 122 can be considered to be a relatively strong inhibitor. In some embodiments, the second additive 122 has an average molecular weight greater than about 10000Da, such as a molecular weight in the range of about 10000Da to about 100000Da, but other molecular weights are also possible. In some embodiments, the second additive 122 includes repeating units, and each unit has a molecular weight greater than about 50Da. In some embodiments, the second additive 122 has an average molecular weight greater than the average molecular weight of the first additive 121. For example, in some embodiments, the average molecular weight of the second additive 122 can be approximately equal to or greater than about twice the average molecular weight of the first additive 121. In some embodiments, the molecule of the second additive 122 can be greater than the molecule of the first additive 121. The molar concentration of the second additive 122 in the electroplating solution can be in the range of about 0.01mol / L to about 10mol / L, but other concentrations are also possible.

[0043] In some embodiments, the third additive 123 includes a local inhibitory effect on Cu 2+ Molecules of growth on protrusions, edges, etc., which can increase the flatness of deposited copper during the electroplating process. In this way, the third additive 123 can be considered as a leveling material or leveling agent. In certain embodiments, the third additive 123 can include organic molecules, nitrogen-containing molecules, sulfur-containing molecules, etc. In certain embodiments, the molecules of the third additive 123 are positively charged in the electroplating solution. In certain embodiments, the third additive 123 includes one or more nitrogen, amine, imide, imidazole or pyrrolidone groups, and may also include sulfur functional groups. In certain embodiments, the leveling material additive includes one or more five-membered rings, six-membered rings and / or conjugated organic compound derivatives. In certain embodiments, the nitrogen group can form a part of the ring structure. In certain embodiments, in the third additive 123 including one or more amines, the amine is a primary, secondary or tertiary alkylamine. In certain embodiments, the amine is an arylamine or a heterocyclic amine. In some embodiments, amine includes but is not limited to dialkylamine, trialkylamine, arylalkylamine, triazoles, imidazole, triazole, tetrazole, benzimidazole, benzotriazole, piperidine, morpholine, piperazine, pyridine, pyrrolidone, oxazole, benzoxazole, pyrimidine, quinoline, isoquinoline etc. or their combination.In some embodiments, the third additive 123 includes polyvinylpyrrolidone (PVP).In some embodiments, the third additive 123 includes Janus Green B, nitro blue tetrazolium (NBT) etc.In some embodiments, the third additive 123 can be a molecule including positively charged nitrogen.In some instances, nuclear magnetic resonance (NMR) analysis can be able to determine that the third additive 123 is a molecule including positively charged nitrogen.Other third additives 123 are also possible.

[0044] In some embodiments, the third additive 123 has an average molecular weight in the range of about 500Da to about 30,000Da, but other molecular weights are possible. The third additive 123 may have an average molecular weight greater than, less than, or approximately equal to the average molecular weight of the first additive 121. In some embodiments, the third additive 123 has an average molecular weight approximately equal to or less than about twice the average molecular weight of the first additive 121. The molar concentration of the third additive 123 in the electroplating solution may be in the range of about 0.01 mol / L to about 10 mol / L, but other concentrations are possible.

[0045] Figures 5 to 9 1 shows an intermediate stage of forming copper 130 using an electroplating process according to some embodiments. The electroplating process can be similar to the process described above. For example, Figures 5 to 9 Can represent when immersed in the plating solution during the electroplating process Figure 4 The electroplating solution includes additives 120 (e.g., additives 121, 122, 123), which may be similar to those described above. In the figure, the first additive 121 is represented by a rounded rectangle, the second additive 122 is represented by an elongated hexagon, and the third additive is represented by a triangle. Figures 5 to 9 The diagram is intended to be a representative representation for explanation purposes, and therefore some components are not shown for clarity purposes. For example, some portions of the structure that are located below the dielectric layer 114 are not shown. Figures 5 to 9 , and the components of the plating solution other than the additive 120 are not shown in Figures 5 to 9 In addition, the additives 121, 122, and 123 shown in the figure are representative and may be present in other positions than the positions shown.

[0046] Go to Figure 5 According to some embodiments, copper 130 is deposited in the lower portion of opening 118. Figure 5As shown in , in some examples, the first additive 121 may tend to accumulate near the lower portion of the opening 118, and the second additive 122 may tend to accumulate on the sidewalls of the opening 118 and on the top surface of the dielectric layer 114. In some examples, the smaller size of the first additive 121 allows it to diffuse and accumulate on the lower portion of the opening 118 more easily than the larger second additive 122. In addition, because the first additive 121 is a weaker inhibitor than the second additive 122, the growth rate of the copper 130 near the bottom surface of the opening 118 is greater than the growth rate of the copper 130 on the sidewalls of the opening 118 and on the top surface of the dielectric layer 114. In this way, the copper 130 is formed upward from the bottom of the opening 118 to fill the opening 118. Forming the copper 130 with a bottom-up process can reduce the risk of forming voids or cracks in the conductive feature 112. The third additive 123 can promote the planar bottom-up growth of the copper 130.

[0047] Due to the influence of the first additive 121 described above, the copper 130 includes a nanotwin region 132 that is substantially (111) oriented. In some embodiments, a central portion of the copper 130 located within the opening 118 is the nanotwin region 132, and a portion of the copper 130 located near the sidewall of the opening 118 is a transition region 134. The nanotwin region 132 is a region that primarily includes (111) oriented copper grains. Since the sidewall surface affects the growth of copper, the transition region 134 is a region with a smaller proportion of (111) oriented copper grains. In some instances, the transition region 134 may be formed due to subconformal deposition on the sidewall of the opening 118. In some embodiments, at least about 97% (by volume) of the nanotwin region 132 is (111) oriented copper, with the remainder of the copper having other orientations. However, in the transition region 134, the proportion of (111) oriented copper can be as low as about 40% (by volume). The proportion of non-uniform grains in the transition region 134 can be greater than the proportion of non-uniform grains in the nanotwin region 132. In other words, the density of (111) oriented grains in the nanotwin region 132 is greater than the density of (111) oriented grains in the transition region 134. In some embodiments, the crystallized grains in the nanotwin region 132 have an average size larger than the crystallized grains in the transition region 134. In some embodiments, the width WB of the transition region 134 can be between about 0% and about 30% of the width WA of the nanotwin region 132. In some examples, the width WB can be the distance between the edge of the nanotwin region 132 and the sidewall of the opening 118. The width WB may or may not include the seed layer 116.

[0048] Figure 6 1 shows a subsequent intermediate stage in the formation of copper 130 according to some embodiments. Figure 6As shown in , when copper 130 is deposited from the bottom up, copper 130 may also be deposited on the sidewalls of opening 118 and on the top surface of dielectric layer 114. The growth rate of copper 130 on the sidewalls of opening 118 and on the top surface of dielectric layer 114 may be relatively slow. In some embodiments, copper 130 may be deposited on the sidewalls of opening 118 as transition region 134, and copper 130 may be deposited on the top surface of dielectric layer 114 as nanotwin region 132. In some examples, copper 130 may be deposited on the top surface of the dielectric layer as transition region 134.

[0049] In some examples, the surface of copper 130 within opening 118 may have an approximately convex shape, where a central region may be higher than regions near the sidewalls. Figure 7 , where the top surface of the central nanotwin region 132 has a protrusion 131 that is higher than the top surface of the outer transition region 134. In such an example, the third additive 123 can accumulate near the protrusion 131 and hinder growth in the area around the protrusion 131. In this way, the third additive 123 can eliminate protrusions and irregularities and form a more flush surface of the copper 130.

[0050] Figure 8 1 shows a subsequent intermediate stage in the formation of copper 130 according to some embodiments. Figure 8 As shown in , additional copper 130 may be formed on the sidewalls of opening 118 and / or the top surface of dielectric layer 114, but the top surface of copper 130 within opening 118 grows at a faster rate. In this manner, bottom-up formation of copper 130 within opening 118 continues.

[0051] Fig. 9 1 shows a subsequent intermediate stage in the formation of copper 130 according to some embodiments. Fig. 9 In some embodiments, the electroplating process has continued until the copper 130 fills the opening 118. In this way, the conductive feature 112 can be formed by the electroplated copper 130 including the nanotwin region 132. In some embodiments, the upper portion 113A of the conductive feature 112 extending above the dielectric layer 114 can be a wire or the like, and the lower portion 113B of the conductive feature 112 located within the opening 118 can be a conductive via or the like. This is an example, and in other examples, different portions of the conductive feature 112 can be other types of features. Fig. 9As shown in , in some embodiments, the volume of the conductive component 112 can primarily include the nanotwin region 132. Non-nano-twin regions (such as transition regions 132) form a smaller proportion of the conductive component 112 than the nanotwin region 132. In some embodiments, the upper portion 113A above the dielectric layer 114 can primarily include the nanotwin region 132. The transition region 134 can exist near the sidewalls of the opening 118 (e.g., near the sidewalls of the lower portion 113B). In some examples, the transition region 134 can exist in other locations.

[0052] In some embodiments, the width WA of the nanotwin region 132 of the portion 113B may be in the range of about 0.5 μm to about 40 μm. Due to the presence of the transition region 134, the width WA may be smaller than the width W1 of the opening 118 (see Figure 3 ). In some embodiments, the width WB of the transition region 134 is less than the width WA of the nanotwin region 132. The width WB of the transition region 134 may be in the range of about 0 μm to about 12 μm. In some embodiments, the height HA of the copper 130 on the top surface of the dielectric layer 114 (e.g., the height HA of the upper portion 113A) may be in the range of about 0.5 μm to about 10 μm. In some embodiments, the height HB of the transition region 134 may be less than the depth D1 of the opening 118 (see Figure 3 ). In some embodiments, width W2 of upper portion 113A can be in a range of about 0.5 μm to about 50 μm. In some examples, width W2 of conductive feature 112 can be greater than width W1 of opening 118. These are examples, and other absolute or relative dimensions for WA, WB, W2, HA, and / or HB are possible.

[0053] As previously described, the presence of the third additive 123 in the electroplating solution can improve the flatness during the electroplating process, and thus can improve the flatness of the conductive feature 112. For example, in some examples, the techniques described herein can form a conductive feature 112 having a top surface with a roughness Ra of about 20 μm or less. In this way, a conductive feature 112 having a substantially smooth and flat surface can be formed.

[0054] In some embodiments, the copper 130 deposited during the electroplating process includes little or no transition region 134. Fig.10 The conductive feature 112 is shown to include only the nanotwin regions 132 of copper 130. In other words, Fig.10The conductive component 112 includes at least about 97% (by volume) of (111) oriented copper 130. Both the upper portion 113A and the lower portion 113B can be nanotwin regions 132. In such an embodiment, the width WA of the nanotwin region 132 in the lower portion 113B can be about the same as the width W1 of the opening 118. In some examples, one or more transition regions 134 can be present in the conductive component 112, but have a negligible size. In some examples, Fig.10 The surface roughness Ra of the conductive component 112 may be less than about 20 μm.

[0055] In some embodiments, a planarization process may be performed to remove upper portion 113A so that the final conductive feature 112 includes only lower portion 113B. For example, the planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, or a combination thereof. In some embodiments, the planarization process may also remove an upper portion of dielectric layer 114. In some examples, after performing the planarization process, the top surfaces of dielectric layer 114 and copper 130 may be substantially flush or coplanar. The planarization process may expose transition region 134, such as Fig.11 In other embodiments, the nanotwin region 132 may cover the transition region 134 so that the top surface of the transition region 134 is not exposed by the planarization process. In some examples, the conductive component 112 may be formed using a damascene process, and the planarization process may be implemented as part of the damascene process. The damascene process may be a single damascene process, a dual damascene process, etc.

[0056] Figures 12 to 15 The conductive component 112 (see FIG. Fig.15 ) is an intermediate stage in the formation of. Fig.15 The conductive member 112 may be similar to Fig. 9 The conductive member 112 is formed by using some similar processes. For example, Fig.15 The conductive member 112 can be made by using a method similar to that for Figures 5 to 9 The copper 130 is formed by the electroplating process deposited by the described process. Fig.15 The conductive feature 112 may be formed in the dielectric layer 114 and may be part of the interconnect structure 110 or the like. In some examples, Fig.15 The conductive feature 112 may be considered a redistribution layer.

[0057] Fig.12 shows a diagram similar to Figure 4 The structure of the structure. For example, Fig.121 shows a dielectric layer 114 including an opening 118 and a seed layer 116 that has been deposited over the dielectric layer 114 and within the opening 118. The dielectric layer 114, the opening 118, and the seed layer 116 may be similar to Figure 4 those of, and may be formed using similar materials or techniques.

[0058] exist Fig.13 In some embodiments, a photoresist 140 is formed and patterned on the seed layer 116. The photoresist 140 can be patterned using suitable photolithography and etching techniques. For example, the photoresist 140 can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist 140 corresponds to the conductive features 112 that are subsequently formed. Then, the photoresist 140 can be developed to form an opening 142 through the photoresist 140 to expose the seed layer 116. In Fig.13 In the embodiment shown in FIG. 8 , the opening 118 in the dielectric layer 114 is located within the opening 142 in the photoresist 140 .

[0059] exist Fig.14 In some embodiments, copper 130 is deposited in opening 142 using an electroplating process. The electroplating process forms copper 130 on the exposed surface of seed layer 116. The electroplating process may be similar to that previously described for Figures 5 to 9 For example, the electroplating process can utilize an electroplating solution including an additive 120, and the additive 120 can include a first additive 121, a second additive 122, and / or a third additive 123. Thus, the copper 130 can be primarily formed of the nanotwin region 132, and can also include a transition region 134 near the sidewalls of the opening 118. In this manner, the conductive feature 112 can be formed of copper 130 that is primarily (111) oriented.

[0060] exist Fig.15 1, portions of the photoresist 140 and the seed layer 116 are removed to form the conductive feature 112. Then, portions of the photoresist 140 and the seed layer 116 on which the copper 130 is not formed are removed. The photoresist 140 may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist 140 is removed, the exposed portions of the seed layer 116 are removed using, for example, a suitable wet etching process and / or a suitable dry etching process. The remaining portions of the seed layer 116 and the copper 130 form the conductive feature 112. This is an example, and other techniques for forming the conductive feature 112 using the electroplating process described herein are also possible.

[0061] Fig.16 1 shows a portion of an interconnect structure 110 over a substrate 102 according to some embodiments. The interconnect structure 110 may be similar to that previously described with respect to Figure 1The interconnect structure 110 is depicted. For example, the interconnect structure 110 can include a plurality of conductive features 112 formed in a plurality of dielectric layers 114. Fig.16 Three conductive features 112A-112C are shown formed in three dielectric layers 114A-114C, but the interconnect structure 110 may include any suitable number of conductive features 112 or dielectric layers 114. The conductive features 112A-112C may be similar to the conductive features 112 previously described and may be formed using electroplating processes such as those previously described. For example, the conductive features 112A-112C may include primarily (111) oriented copper. The dielectric layers 114A-114C may be similar to the dielectric layer 114 previously described. In some examples, other layers such as etch stop layers may be present in the interconnect structure 110.

[0062] Fig.16 Conductive feature 112B is shown physically and electrically connected to underlying conductive feature 112A and overlying conductive feature 112C. For example, conductive feature 112A can first be formed in dielectric layer 114A using techniques similar to those described above. In some examples, conductive feature 112A can be a contact (e.g., Figure 1 Contact piece 108) etc.

[0063] Then, the conductive component 112B can be formed over the conductive component 112A using techniques similar to those described above. For example, the dielectric layer 114B can be deposited over the conductive component 112A and the dielectric layer 114A. Then, the dielectric layer 114B can be patterned using suitable photolithography and etching techniques to form an opening that exposes the conductive component 112A below. In some embodiments, a seed layer 116 can be deposited over the dielectric layer 114B and on the conductive component 112A. Then, an electroplating process can be implemented to deposit copper 130 over the dielectric layer 114B and the conductive component 112A to form the conductive component 112B. The conductive component 112B can include a nanotwin region 132 and a transition region 134. Then, a dielectric layer 114C can be deposited over the conductive component 112B and the dielectric layer 114B. Then, a conductive component 112C that extends through the dielectric layer 114C to contact the conductive component 112B can be formed. The process described above can be repeated to form any number of additional conductive components or dielectric layers. This is an example, and other processes for forming the interconnect structure 110 are possible.

[0064] Embodiments can achieve advantages. By electroplating copper using additives in an electroplating solution as described herein, a conductive component can be formed that includes regions that are primarily (111) oriented copper, which can be nanotwin regions of (111) oriented copper. In some instances, these regions can be 97% or more (111) oriented copper. By forming a conductive component that is primarily (111) oriented copper, the conductive component can have the benefits of (111) oriented copper, such as improved mechanical and thermal properties. In some instances, the embodiments described herein can form a conductive component having a smooth, flat surface, such as a surface having a roughness of less than 20 μm. This can allow the formation of a conductive component with a reduced risk of forming voids or other defects, and a conductive component with a flat surface can be formed without using a polishing process. In some embodiments, the electroplating solution includes: a weak inhibitor additive, including an inhibitory functional group and a metal coordination functional group; a strong inhibitor additive; and a leveling additive.

[0065] According to some embodiments of the present disclosure, the method includes: adding a first additive to an electroplating solution, wherein the first additive is a relatively weak inhibitor; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong inhibitor; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper is nanotwin grains with a (111) orientation. In an embodiment, the electroplating solution includes a copper salt, a halogen ion source, and an acid. In an embodiment, the first additive is gelatin. In an embodiment, the first additive includes an inhibitory functional group and a metal coordination functional group. In an embodiment, the second additive includes a polymer with an average molecular weight greater than 10,000 Da. In an embodiment, the average molecular weight of the first additive is less than half of the average molecular weight of the second additive. In an embodiment, the nanotwin grains with a (111) orientation form at least 97% of the volume of the copper. In an embodiment, the first additive and the third additive are added to the electroplating solution after the second additive is added to the electroplating solution.

[0066] According to some embodiments of the present disclosure, a method includes: forming an opening in a dielectric layer; depositing copper in the opening using an electroplating process, wherein the copper deposited in the opening is (111) oriented, wherein the electroplating process includes using an electroplating solution, wherein the electroplating solution includes: a first additive, wherein the first additive includes an inhibiting functional group and a metal coordination functional group; and a second additive, wherein the second additive is a polymer. In an embodiment, the copper deposited in the opening includes a first copper region surrounded by a second copper region, wherein the first copper region has a greater (111) oriented copper ratio than the second region. In an embodiment, the inhibiting functional group includes a hydrogen functional group, an aliphatic functional group, or an aromatic functional group. In an embodiment, the metal coordination functional group includes a hydroxyl functional group, an ether functional group, an amine functional group, a sulfide functional group, a carboxylic acid functional group, an ester functional group, an amide functional group, an imide functional group, or an imine functional group. In an embodiment, the second additive has a linear or branched structure. In an embodiment, the electroplating solution includes a third additive, wherein the third additive includes positively charged nitrogen.

[0067] According to some embodiments of the present disclosure, a device includes: a dielectric layer located above a substrate; and a conductive via located in the dielectric layer, wherein the conductive via includes a first nanotwin copper region and a second nanotwin copper region, wherein the first nanotwin copper region is separated from a sidewall of the dielectric layer by the second nanotwin copper region, and wherein the first nanotwin copper region has a greater (111) oriented grain density than the second nanotwin copper region. In an embodiment, at least 97% of the grains in the first nanotwin copper region are (111) oriented, and at least 40% of the grains in the second nanotwin copper region are (111) oriented. In an embodiment, the device includes: a wire located on the top surface of the conductive via and the dielectric layer, wherein at least 97% of the grains in the wire are (111) oriented. In an embodiment, the top surface of the wire has a roughness of less than 20 μm. In an embodiment, the average grain size of the first nanotwin copper region is greater than the average grain size of the second nanotwin copper region.

[0068] Some embodiments of the present application provide a method comprising: adding a first additive to an electroplating solution, wherein the first additive is a relatively weak inhibitor; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong inhibitor; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper comprises nanotwinned grains having a (111) orientation.

[0069] In some embodiments, the electroplating solution further comprises a copper salt, a halogen ion source and an acid. In some embodiments, the first additive is gelatin. In some embodiments, the first additive comprises an inhibition functional group and a metal coordination functional group. In some embodiments, the second additive comprises a polymer having an average molecular weight greater than 10,000 Da. In some embodiments, the average molecular weight of the first additive is less than half of the average molecular weight of the second additive. In some embodiments, the nanotwin grains having a (111) orientation comprise at least 97% of the volume of the copper. In some embodiments, the first additive and the third additive are added to the electroplating solution after the second additive is added to the electroplating solution.

[0070] Other embodiments of the present application provide a method, comprising: forming an opening in a dielectric layer; depositing copper in the opening using an electroplating process, wherein the copper deposited in the opening is (111) oriented, wherein the electroplating process comprises using an electroplating solution, wherein the electroplating solution comprises: a first additive, wherein the first additive comprises an inhibiting functional group and a metal coordination functional group; and a second additive, wherein the second additive is a polymer.

[0071] In some embodiments, the copper deposited in the opening includes a first copper region surrounded by a second copper region, wherein the first copper region has a greater (111) oriented copper ratio than the second region. In some embodiments, the inhibiting functional group includes a hydrogen functional group, an aliphatic functional group, or an aromatic functional group. In some embodiments, the metal coordination functional group includes a hydroxyl functional group, an ether functional group, an amine functional group, a sulfide functional group, a carboxylic acid functional group, an ester functional group, an amide functional group, an imide functional group, or an imine functional group. In some embodiments, the first additive has the following structure: wherein R1, R2, R3, R4 and R5 are inhibitory functional groups, and wherein X1, X2 and X3 are metal coordination functional groups. In some embodiments, the second additive has a linear or branched structure. In some embodiments, the electroplating solution further comprises a third additive, wherein the third additive comprises positively charged nitrogen.

[0072] Still other embodiments of the present application provide a device comprising: a dielectric layer located above a substrate; and a conductive via located in the dielectric layer, wherein the conductive via comprises a first nanotwinned copper region and a second nanotwinned copper region, wherein the first nanotwinned copper region is separated from a sidewall of the dielectric layer by the second nanotwinned copper region, and wherein the first nanotwinned copper region has a greater (111) oriented grain density than the second nanotwinned copper region.

[0073] In some embodiments, at least 97% of the grains in the first nanotwinned copper region are (111) oriented, and wherein at least 40% of the grains in the second nanotwinned copper region are (111) oriented. In some embodiments, the device further comprises: a wire located on a top surface of the conductive via and the dielectric layer, wherein at least 97% of the grains in the wire are (111) oriented. In some embodiments, the top surface of the wire has a roughness of less than 20 μm. In some embodiments, the average grain size of the first nanotwinned copper region is greater than the average grain size of the second nanotwinned copper region.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: adding a first additive to the electroplating solution, wherein the first additive is a relatively weak suppressor; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong suppressor; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and Copper is deposited using the electroplating solution, wherein a majority of the copper comprises nanotwinned grains having a (111) orientation.

2. The method according to claim 1, wherein: The electroplating solution also includes a copper salt, a source of halogen ions, and an acid.

3. The method according to claim 1, wherein: The first additive is gelatin.

4. The method according to claim 1, wherein: The first additive includes an inhibiting functional group and a metal coordinating functional group.

5. The method according to claim 1, wherein: The second additive includes a polymer having an average molecular weight greater than 10,000 Da.

6. The method according to claim 1, wherein: The average molecular weight of the first additive is less than half of the average molecular weight of the second additive.

7. The method according to claim 1, wherein: The nanotwinned grains having a (111) orientation comprise at least 97% by volume of the copper.

8. The method according to claim 1, wherein: The first additive and the third additive are added to the electroplating solution after the second additive is added to the electroplating solution.

9. A method of forming a semiconductor device, comprising: forming an opening in the dielectric layer; Depositing copper in the opening using an electroplating process, wherein the copper deposited in the opening is (111) oriented, wherein the electroplating process includes using an electroplating solution, wherein the electroplating solution includes: a first additive, wherein the first additive comprises an inhibiting functional group and a metal coordinating functional group; and A second additive, wherein the second additive is a polymer.

10. A semiconductor device comprising: a dielectric layer disposed above the substrate; as well as A conductive via is located in the dielectric layer, wherein the conductive via includes a first nanotwinned copper region and a second nanotwinned copper region, wherein the first nanotwinned copper region is separated from a sidewall of the dielectric layer by the second nanotwinned copper region, and wherein the first nanotwinned copper region has a greater (111) oriented grain density than the second nanotwinned copper region.

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