Pressure chip with high resistance uniformity based on epitaxial process and pressure sensor

Abstract

The invention discloses a pressure chip with high resistance uniformity based on an epitaxial process, which relates to the technical field of sensors and comprises a monocrystalline silicon substrate layer, a conductive layer grown by epitaxial deposition and a bonding pad layer, a high-resistance monocrystalline silicon layer is formed through epitaxial growth to serve as a conductive layer, and a plurality of resistor strips are prepared by adopting photoetching and etching processes, so that the resistance deviation of the resistor is inhibited, and the uniformity of the resistor is improved; the plurality of resistor strips form two resistor groups which are symmetrically distributed in a double-M shape to form a Wheatstone bridge; wherein the single resistor group and the internal welding spot form an M-shaped structure, so that the resistor path length and the uniform stress distribution of the resistor strip can be increased, and the high resistance coefficient and the high sensitivity are obtained; the double-M-shaped symmetrical structure can effectively offset resistance drift caused by temperature change, so that common-mode interference is inhibited, and the temperature stability and the anti-interference capability of the sensor are improved; the problems that an existing pressure chip is low in resistance uniformity and insufficient in measurement precision due to uneven etching thickness and doping fluctuation are solved.

Description

Technical Field

[0001] The present invention relates to the field of sensor technology, and in particular to a pressure chip and a pressure sensor with high resistance uniformity based on an epitaxial process. Background Art

[0002] As a key component for measuring pressure, pressure sensors are widely used in industry, automobiles, aerospace, medical and other fields. Among them, silicon-based semiconductor sensors have gradually become the mainstream products in the field of pressure sensing due to their significant piezoresistive effect and mature micro-electromechanical systems (MEMS) processing advantages.

[0003] Its working principle is to utilize the piezoresistive effect of single crystal silicon. When the silicon diaphragm is subjected to external pressure, its resistivity will change, which in turn causes the output voltage of the bridge to change, thereby realizing the measurement of pressure.

[0004] In the traditional pressure chip manufacturing process, the varistor is usually formed on the silicon wafer by diffusion resistance or ion implantation process. Although the above two processes can achieve low-cost mass production; however, these processes still have some problems: First, factors such as process fluctuations and material non-uniformity can cause large deviations in the resistance value of the varistor.

[0005] Secondly, the pre-etching thickness of the pressure chip is usually about 15μm, and more than 90% of the silicon needs to be removed. However, the current etching process makes it difficult to maintain a high thickness uniformity, and the resistance in different areas of the same pressure chip varies greatly. Due to process constraints, the thickness of the pressure chip is usually on the order of 12-20μm. Moreover, the thickness of the pressure chip increases by only 2.54μm, which will cause the resistance change to reach about 20%, resulting in a large deviation in the resistance value of the varistor, which directly affects the measurement accuracy of the sensor.

[0006] In addition, traditional pressure chips also have some shortcomings in terms of sensitivity, linearity, temperature coefficient, zero drift, etc., which need to be improved through various methods.

[0007] In summary, it is found that the prior art has at least the following technical problems: The existing pressure chips have technical problems such as low thickness uniformity and large resistance deviation due to uneven etching thickness and doping fluctuations, which affect the measurement accuracy of the sensor. Summary of the invention

[0008] The purpose of the present invention is to provide a pressure chip and pressure sensor with high resistance uniformity based on an epitaxial process, so as to solve the technical problems of low thickness uniformity and large resistance deviation of the existing pressure chip caused by uneven etching thickness and doping fluctuations, which affect the measurement accuracy of the sensor.

[0009] The various technical effects that can be produced by the preferred technical solutions among the various technical solutions provided by the present invention are described in detail below.

[0010] In order to solve the above technical problems, the present invention provides the following technical solutions: The present invention provides a pressure chip with high resistance uniformity based on epitaxial process, comprising a base layer, a conductive layer and a pad layer stacked in sequence from bottom to top to form a pressure chip with high resistance uniformity; a plurality of resistor bars are formed on the conductive layer, and the plurality of resistor bars are divided into two groups of resistor groups; the pad layer is provided with a plurality of internal welding points and a plurality of external welding points, and the internal welding points are used to connect with two resistor bars of the same resistor group; the plurality of external welding points are distributed between the two groups of resistor groups, and the external welding points are used to connect with the first and second resistor bars of the resistor groups. The resistor strips at the tail position are connected; a single group of the resistor group and the internal solder joints form an M-type structure, and the resistance path length of the resistor strip is increased by forming the M-type structure, and the uniform stress distribution of the resistor strips symmetrically distributed in the resistor group is used to improve the conversion rate of the pressure chip with high resistance uniformity to convert mechanical stress into resistance change, obtain a high voltage resistance coefficient, and enhance the sensitivity of the pressure chip with high resistance uniformity; two groups of the resistor groups, the internal solder joints and the external solder joints form a double M-type structure and form a Wheatstone bridge.

[0011] In one embodiment, the material of the base layer is single crystal silicon.

[0012] In one embodiment, the base layer is a P-type single crystal silicon wafer with a thickness of 6-15 μm and a resistivity of 1-10 Ω·cm, or an N-type single crystal silicon wafer with a thickness of 6-15 μm and a resistivity of 0.01-0.1 Ω·cm.

[0013] In one embodiment, the conductive layer is single crystal silicon grown by epitaxial deposition on the outer surface of the base layer.

[0014] In one embodiment, the conductive layer has a thickness of 1.5-5.5 μm and a resistivity of 0.04-0.06 Ω·cm.

[0015] In one embodiment, the conductive layer is formed by uniform epitaxial growth on the base layer using a chemical vapor epitaxy process or a molecular beam epitaxy process.

[0016] In one embodiment, the resistor strip is a resistor body of a varistor formed directly on the conductive layer by photolithography and etching.

[0017] In one of the embodiments, the pad layer and the electrodes of the varistor are formed by depositing metal using a sputtering or evaporation process, and the electrodes, the internal solder joints and the external solder joints of corresponding patterns are formed based on the pad layer through photolithography and etching processes, and the internal solder joints and the external solder joints are connected to the electrodes of the varistor.

[0018] In one embodiment, the structural positions of the two groups of resistor groups in the double M-type structure are set to be symmetrically distributed, and the double M-type structure is used to offset the resistance drift caused by temperature change and suppress common mode interference through the symmetrically distributed structural positions.

[0019] In one embodiment, the two groups of resistor groups are distributed on the left and right sides of the middle part of the conductive layer; wherein the resistor group on the left includes the first to fifth resistor bars, and the resistor group on the right includes the sixth to tenth resistor bars; there are three external welding points, one end of the first resistor bar and the sixth resistor bar is connected to the same external welding point, and one end of the fifth resistor bar and the tenth resistor bar is separately connected to one of the external welding points.

[0020] In one embodiment, the internal welding points include first to sixth internal welding points; wherein the first to third internal welding points are located in the resistor group on the left, the first internal welding point is connected to the other end of the first resistor bar and one end of the second resistor bar, the second internal welding point is connected to the other end of the second resistor bar, one end of the third resistor bar and one end of the fourth resistor bar, the third internal welding point is connected to the other end of the fourth resistor bar and the other end of the fifth resistor bar; the fourth to sixth internal welding points are located in the resistor group on the right, the fourth internal welding point is connected to the other end of the fourth resistor bar and the other end of the fifth resistor bar. The third resistor bar is connected to the other end of the sixth resistor bar and one end of the seventh resistor bar, the fifth internal welding point is connected to the other end of the seventh resistor bar, one end of the eighth resistor bar and one end of the ninth resistor bar, the sixth internal welding point is connected to the other end of the ninth resistor bar and the other end of the tenth resistor bar; the third resistor bar is structurally connected only to the second internal welding point for fixing and preventing the pressure chip with high resistance uniformity from cracking, and the eighth resistor bar is structurally connected only to the fifth internal welding point for fixing and preventing the pressure chip with high resistance uniformity from cracking.

[0021] In one of the embodiments, on the plane of the conductive layer, the first resistor bar and the sixth resistor bar, the second resistor bar and the seventh resistor bar, the third resistor bar and the eighth resistor bar, the fourth resistor bar and the ninth resistor bar, and the fifth resistor bar and the tenth resistor bar are arranged laterally and symmetrically.

[0022] In one of the embodiments, the vertices of the external solder joints are all rounded to prevent stress concentration at the vertices of the external solder joints after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip with high resistance uniformity.

[0023] In one of the embodiments, the vertices of the internal solder joints are all rounded to prevent stress concentration at the vertices of the internal solder joints after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip with high resistance uniformity.

[0024] The present invention also provides a pressure sensor, comprising a signal processing unit and any one of the above-mentioned pressure chips with high resistance uniformity, wherein the signal processing unit is electrically connected to the pressure chip with high resistance uniformity.

[0025] In one embodiment, the pressure sensor includes a plurality of pressure chips with high resistance uniformity, and the plurality of pressure chips with high resistance uniformity are arranged in the pressure sensor in a symmetrical distribution, uniform distribution or matrix distribution manner.

[0026] The present invention also provides an epitaxial process of a pressure chip with high resistance uniformity, comprising any one of the pressure chips with high resistance uniformity and the following steps: S1. Select a single crystal silicon wafer of corresponding specifications as the base layer of the pressure chip with high resistance uniformity; S1.1. Select a P-type single crystal silicon wafer with a thickness of 6-15 μm and a resistivity of 1-10 Ω·cm as the base layer of the pressure chip with high resistance uniformity; Or S1.2, select N-type crystal orientation single crystal silicon wafer with a thickness of 6-15 μm and a resistivity of 0.01-0.1 Ω·cm as the base layer of the pressure chip with high resistance uniformity; S2, growing a conductive layer on the base layer using an epitaxial deposition process; S2.1, growing a P-type conductive layer with a thickness of 1.5-5.5 μm and a resistivity of 0.04-0.06 Ω·cm on the substrate layer by a chemical vapor epitaxial process, and controlling the growth temperature to 1100° C., the pressure to 100 Torr, and the gas flow rate to 100 sccm during the epitaxial deposition growth of silicon crystals by the chemical vapor epitaxial process; or S2.2, growing an N-type conductive layer with a thickness of 2-4 μm, a resistivity of 1.5-5.5 μm, and a resistivity of 0.04-0.06 Ω·cm on the substrate layer by a molecular beam epitaxy process, and controlling the growth temperature to 800°C and the pressure to 1×10-8 Torr during the epitaxial deposition growth of silicon crystals by the molecular beam epitaxy process; S3, directly forming a resistor strip pattern on the conductive layer by using photolithography and etching processes; S3.1, Patterning: The patterning usually extends about 12-14 μm from one side of the conductive layer into the wafer; S3.2, grinding: grinding from a starting thickness of about 0.015 inches on one side of the substrate layer of the wafer to a thickness of about 100 μm; S3.3, coating: coating one side of the conductive layer with an anti-corrosion material; S3.4, Etching: Use conventional etching technology to chemically back-etch one side of the ground substrate layer until the pattern of the strain gauge is visible, and control the overall strain gauge thickness of the ground substrate layer + conductive layer to be 10 to 14 μm; S3.5, Removal: The anti-corrosion material coated on the conductive layer is removed by a conventional removal process; S3.6, forming a metallized electrical contact on the conductive layer: forming a metallized electrical contact on the conductive layer portion of the strain gauge; S4, making metal electrodes; S4.1, forming a metal electrode on the resistor strip; S4.11, forming a metal electrode on the resistor strip by a sputtering process; S4.12, forming a metal electrode on the resistor strip by an evaporation process; S4.2, performing a photolithography process on the conductive layer; S4.3, performing an etching process on the conductive layer; S4.4. Form the desired electrode pattern.

[0027] The beneficial effects of the present invention are as follows: The present invention provides a pressure chip with high resistance uniformity based on an epitaxial process, and a pressure sensor with the pressure chip with high resistance uniformity as a sensing core; the pressure chip with high resistance uniformity includes: a base layer, a pad layer and a conductive layer grown by epitaxial deposition; the pressure sensor includes: a signal processing unit and a pressure chip with high resistance uniformity.

[0028] Among them, on the pressure chip with high resistance uniformity: a plurality of resistor bars are formed on the conductive layer, the resistor bars are varistors formed directly on the conductive layer by photolithography and etching, and the plurality of resistor bars are divided into two groups of resistor groups; the pad layer is provided with a plurality of internal solder joints and a plurality of external solder joints, the internal solder joints are used to connect with two resistor bars of the same resistor group; a plurality of external solder joints are distributed between the two groups of resistor groups, and the external solder joints are used to connect with the resistor bars at the head and tail positions of the resistor group; a single group of the resistor group and the internal solder joints form an M-type structure, and the M-type structure is used to improve the conversion rate of the pressure chip with high resistance uniformity from converting mechanical stress into resistance change by increasing the resistance path length of the resistor bar and uniformly distributing the stress of the resistor bars symmetrically distributed in the resistor group, thereby obtaining a high voltage resistance coefficient and improving the sensitivity of the pressure chip with high resistance uniformity; the two groups of the resistor groups, the internal solder joints and the external solder joints form a double M-type structure and are symmetrically distributed to form a Wheatstone bridge.

[0029] The present invention integrates at least one pressure chip with high resistance uniformity into the pressure sensor, and then electrically connects the pressure chip with high resistance uniformity integrated in the pressure sensor to the signal processing unit. The pressure chip with high resistance uniformity collects pressure and converts it into an electrical signal, and the signal processing unit processes the pressure signal and transmits the data externally, thereby forming a complete pressure sensor with pressure collection link, pressure signal conversion link, pressure signal processing link and transmission of pressure data to the outside.

[0030] Compared with existing technology (1) The present invention improves the resistance uniformity of the pressure chip The conductive layer having a high-resistance single-crystal silicon layer is prepared on the base layer of single-crystal silicon by an epitaxial growth process. The atomic-level growth controllability and lattice consistency of epitaxial silicon materials are utilized to fundamentally eliminate the doping concentration gradient defects of traditional diffusion / ion implantation processes, so that the resistance deviation of the varistor is controlled within ±1%, thereby effectively improving the resistance uniformity of the varistor, making the output signal of the pressure chip more consistent, and improving the measurement accuracy and stability of the pressure sensor; at the same time, the conductive layer formed by the epitaxial deposition growth technology has high thickness uniformity (CV value of the present invention <2%), which is significantly better than the traditional etching process (CV value>10%), effectively suppressing the nonlinear drift of resistance caused by film thickness fluctuations, and ensuring that the resistance consistency of mass-produced pressure chips is improved by more than 3 times.

[0031] (2) The present invention improves the temperature stability and anti-interference ability of the pressure sensor By symmetrically arranging two groups of resistors having the M-type structure to form a symmetrical resistor layout of the double M-type structure, the thermal stress difference caused by the temperature gradient is offset by a geometric self-compensation mechanism, the influence of temperature on the resistance of the resistor strip is reduced, and the resistance drift caused by temperature change is effectively offset, and the temperature coefficient of resistance (TCR) is reduced to below 0.05% / °C; the Wheatstone bridge structure further suppresses common-mode interference (such as power supply fluctuations), and combined with the stress balancing design achieved by the symmetrically arranged resistor groups, the zero-position temperature drift of the pressure sensor is made less than 0.01%FS / °C; thereby improving the temperature stability and anti-interference ability of the pressure sensor.

[0032] (3) The present invention improves the piezoresistance efficiency and sensitivity of the pressure chip The resistor group of the M-type structure extends the effective resistance path length to at least 3.2 times that of the traditional straight line type through the winding curve routing path of the M-type structure, and can produce a higher resistance change rate (ΔR / R) when the pressure chip with high resistance uniformity is subjected to the same pressure and produces the same strain; at the same time, the symmetrical resistor layout of the dual M-type structure distributes the varistors in the equivalent stress area of ​​the strain field, further improving the utilization rate of the varistors and being able to efficiently convert mechanical stress into resistance change, thereby obtaining a higher piezoresistance coefficient and further improving the sensitivity of the pressure chip.

[0033] (4) Process compatibility and cost advantages By adapting to the epitaxial growth of deposited silicon crystals and photolithography and etching direct writing processes, it is compatible with existing MEMS production lines without the need for additional doping or annealing steps, shortening the process cycle by 30%. The double M-type structure achieves pattern generation through single photolithography, avoiding multi-layer alignment errors, increasing the yield to more than 98%, and further reducing the overall manufacturing cost.

[0034] In summary, the present invention has significant advantages in improving resistance uniformity, optimizing stress distribution, enhancing temperature stability and anti-interference ability through epitaxial technology and innovative dual M-type symmetrical resistor layout, which can effectively improve the performance and reliability of silicon-based pressure sensors and is suitable for the manufacture of high-precision and small-volume pressure sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the implementation mode will be briefly introduced below. Obviously, the drawings described below are only some implementation modes of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 11 is a schematic diagram of the isometric structure of a pressure chip with high resistance uniformity provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of the side view structure of a pressure chip with high resistance uniformity provided by an embodiment of the present invention; Figure 3 It is one of the top views of the pressure chip with high resistance uniformity provided by the embodiment of the present invention; Figure 4 This is a second top view of a pressure chip with high resistance uniformity provided by an embodiment of the present invention; Figure 5 This is a third top view of a pressure chip with high resistance uniformity provided by an embodiment of the present invention; Figure 6 FIG4 is a top view of a pressure chip with high resistance uniformity provided by an embodiment of the present invention; Figure 7 FIG5 is a fifth top view of a pressure chip with high resistance uniformity provided by an embodiment of the present invention; Figure 8 FIG6 is a sixth top view of a pressure chip with high resistance uniformity provided by an embodiment of the present invention; Fig. 9 This is one of the schematic diagrams of the assembly structure of the pressure sensor provided by the embodiment of the present invention; Fig.10 This is the second schematic diagram of the assembly structure of the pressure sensor provided by the embodiment of the present invention; Fig.11 It is a schematic diagram of symmetrical distribution of pressure chips with high resistance uniformity in a pressure sensor provided by an embodiment of the present invention; Fig.12 It is a schematic diagram of uniform distribution of pressure chips with high resistance uniformity in a pressure sensor provided by an embodiment of the present invention; Fig.13 This is one of the schematic diagrams of the distribution of the pressure chip matrix with high resistance uniformity in the pressure sensor provided by the embodiment of the present invention; Fig.14 This is the second schematic diagram of the distribution of the pressure chip matrix with high resistance uniformity in the pressure sensor provided by the embodiment of the present invention.

[0037] The reference numerals are as follows: 00. Pressure chip with high resistance uniformity; 1. Basal layer; 2. conductive layer; 21. resistor group; 22. resistor bar; 220. first resistor bar; 221. second resistor bar; 222. third resistor bar; 223. fourth resistor bar; 224. fifth resistor bar; 225. sixth resistor bar; 226. seventh resistor bar; 227. eighth resistor bar; 228. ninth resistor bar; 229. tenth resistor bar; 3. Pad layer; 31. Internal solder joint; 311. First internal solder joint; 312. Second internal solder joint; 313. Third internal solder joint; 314. Fourth internal solder joint; 315. Fifth internal solder joint; 316. Sixth internal solder joint; 32. External solder joint; 321. First external solder joint; 322. Second external solder joint; 323. Third external solder joint; 33. Chamfered corners; 4. M-type structure; 5. Double M-type structure; 6. Pressure sensor; 7. Signal processing unit; 8. Stress-bearing layer. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and examples. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportions.

[0039] As a key component for measuring pressure, pressure sensors are widely used in the fields of industry, automobiles, aerospace, and medical treatment. Among them, silicon-based semiconductor sensors have gradually become the mainstream products in the field of pressure sensing due to their significant piezoresistive effect and mature micro-electromechanical systems (MEMS) processing advantages. Its working principle is to utilize the piezoresistive effect of single-crystal silicon. When the silicon diaphragm is subjected to external pressure, its resistivity will change, which will cause the output voltage of the bridge to change, thereby realizing the measurement of pressure. In the traditional pressure chip manufacturing process, diffused resistors or ion implantation processes are usually used to form varistors on silicon wafers. Although the above two processes can achieve low-cost mass production; however, these processes still have some problems: First, factors such as process fluctuations and material inhomogeneity will cause large deviations in the resistance value of the varistor. Secondly, the pre-etching thickness of the pressure chip is usually about 15μm, which requires the removal of more than 90% of the silicon. However, the current etching process is difficult to maintain a high thickness uniformity, and the resistance of different areas of the same pressure chip varies greatly. Due to process constraints, the thickness of the pressure chip is usually on the order of 12-20μm. Moreover, the thickness of the pressure chip increases by only 2.54μm, which will cause the resistance to change by about 20%, resulting in a large deviation in the resistance value of the varistor, which directly affects the measurement accuracy of the sensor. In addition, traditional pressure chips also have some shortcomings in terms of sensitivity, linearity, temperature coefficient, zero drift, etc., which need to be improved through various methods.

[0040] In view of this, a specific embodiment of the present application provides a pressure chip with high resistance uniformity based on an epitaxial process, and the pressure chip with high resistance uniformity includes a single crystal silicon base layer, a conductive layer grown by epitaxial deposition and a pad layer; a high-resistance single crystal silicon layer is formed as a conductive layer by epitaxial growth, and a plurality of resistor bars are prepared by photolithography and etching processes to suppress the resistance deviation of the resistor and improve the resistance uniformity; the plurality of resistor bars form two resistor groups and are symmetrically distributed in a double M type to form a Wheatstone bridge; wherein a single resistor group and an internal solder joint form an M-type structure, which can increase the resistance path length and uniform stress distribution of the resistor bar, and obtain a high voltage resistance coefficient and high sensitivity; and the double M-type symmetrical structure can effectively offset the resistance drift caused by temperature changes, thereby suppressing common mode interference and improving the temperature stability and anti-interference ability of the sensor; it effectively solves the technical problems of low thickness uniformity and large resistance deviation of the pressure chip caused by uneven etching thickness and doping fluctuations, which affect the measurement accuracy of the sensor.

[0041] Figure 1 1 is a schematic diagram of the isometric structure of a pressure chip with high resistance uniformity provided in an embodiment; Figure 2 is a schematic diagram of a side view structure of a pressure chip with high resistance uniformity provided in an embodiment; Figure 3 It is one of the top views of the pressure chip with high resistance uniformity provided by the embodiment; Figure 4 This is a second top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 5 3 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 6 4 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 7 This is a fifth top view of a pressure chip with high resistance uniformity provided in an embodiment.

[0042] The first embodiment of the pressure chip 00 with high resistance uniformity is as follows Figures 1 to 7 As shown, the pressure chip 00 with high resistance uniformity includes a base layer 1, a conductive layer 2 and a pad layer 3 stacked from bottom to top; a plurality of resistor bars 22 are formed on the conductive layer 2, and the plurality of resistor bars 22 are divided into two groups of resistor groups 21; the pad layer 3 is provided with a plurality of internal soldering points 31 and a plurality of external soldering points 32, the internal soldering points 31 are used to connect the two resistor bars 22 of the same resistor group 21; the plurality of external soldering points 32 are distributed between the two groups of resistor groups 21, and the external soldering points 32 are used to connect the resistor bars at the head and tail positions of the resistor group 21. 22 connection; a single resistor group 21 and an internal solder joint 31 form an M-type structure 4, by forming the M-type structure 4 to increase the resistance path length of the resistor bar 22, and to form a uniform stress distribution of the resistor bar 22 symmetrically distributed in the resistor group 21, so as to improve the conversion rate of the pressure chip 00 with high resistance uniformity in converting mechanical stress into resistance change, obtain a high voltage resistance coefficient, and enhance the sensitivity of the pressure chip 00 with high resistance uniformity; two resistor groups 21, internal solder joints 31 and external solder joints 32 form a double M-type structure 5, and form a Wheatstone bridge.

[0043] Among them, the layout of the above-mentioned double M-shaped structure 5 is as follows: Figure 3 and Figure 4 As shown, the structural positions of the two resistor groups 21 in the double M-type structure 5 are set to be symmetrically distributed. The double M-type structure 5 is used to offset the resistance drift caused by temperature change and suppress common mode interference through the symmetrically distributed structural positions.

[0044] Regarding the above, the specific material of the base layer 1 is as follows: Figure 1 and Figure 2 As shown, the material of the base layer 1 is single crystal silicon; wherein, since the base layer 1 is made of single crystal silicon material, its crystal orientation and resistivity can be selected according to the specific application requirements of the pressure chip.

[0045] Specifically, regarding the crystal orientation of the above-mentioned base layer 1, the base layer 1 can be selected to be a P-type (100) crystal orientation single crystal silicon wafer or an N-type (111) crystal orientation single crystal silicon wafer.

[0046] Specifically, regarding the thickness parameters and resistivity parameters of the above-mentioned base layer 1, the base layer 1 can be a single crystal silicon wafer with a thickness of 6-15 μm and a resistivity of 1-10 Ω·cm or a resistivity of 0.01-0.1 Ω·cm.

[0047] Regarding the specific materials and manufacturing process of the conductive layer 2, Figure 1 and Figure 2 As shown, the conductive layer 2 is single crystal silicon grown by epitaxial deposition on the outer surface of the base layer 1 , wherein the conductive layer 2 can be formed by any conventional epitaxial deposition technique.

[0048] Specifically, regarding the thickness parameters and resistivity parameters of the conductive layer 2, the conductive layer 2 may be epitaxially deposited to be an epitaxial layer with a thickness of 1.5-5.5 μm and a resistivity of 0.04-0.06 Ω·cm.

[0049] The formation process of the resistor strip 22 and the specific structure of forming the electrical connection and the structural connection are as follows: Figure 5 and Figure 6 As shown, the resistor strip 22 is a resistor body of a varistor formed directly on the conductive layer 2 by photolithography and etching.

[0050] Regarding the material of the pad layer 3, the pad layer 3 is a metal pad, and the internal solder joints 31 and the external solder joints 32 of the pad layer 3 are used to connect the resistor bar 22 to form an M-type structure 4 and a double M-type structure 5, and to build a Wheatstone bridge.

[0051] Among them, the external welding point 32 is used to connect the internal resistor bar 22 and the external communication circuit connection, such as using a high resistance uniformity pressure chip 00 to form an electrical connection with the signal processing unit 7, thereby constructing a pressure sensor 6; and the internal welding point 31 is only used for the connection between the internal resistor bars 22, thereby constructing an M-type structure 4.

[0052] The present invention manufactures a pressure chip with high resistance characteristics and high resistance uniformity characteristics by using an epitaxial process, thereby forming an independent pressure chip with high resistance uniformity 00 and a pressure sensor 6 with the pressure chip with high resistance uniformity 00 as the sensing core; the pressure chip with high resistance uniformity 00 includes: a base layer 1, a pad layer 3 and a conductive layer 2 grown by epitaxial deposition; the pressure sensor 6 includes: a signal processing unit 7 and the pressure chip with high resistance uniformity 00.

[0053] The present invention integrates at least one pressure chip 00 with high resistance uniformity into the pressure sensor 6, and then electrically connects the pressure chip 00 with high resistance uniformity integrated in the pressure sensor 6 to the signal processing unit 7. The pressure chip 00 with high resistance uniformity collects pressure and converts it into an electrical signal, and the signal processing unit 7 processes the pressure signal and transmits the data externally, thereby forming a complete pressure sensor 6 with pressure collection link, pressure signal conversion link, pressure signal processing link and pressure data transmission link.

[0054] Compared with existing technology (1) The present invention improves the resistance uniformity of the pressure chip A conductive layer 2 having a high-resistance single-crystal silicon layer is prepared on a single-crystal silicon base layer 1 through an epitaxial growth process. The atomic-level growth controllability and lattice consistency of epitaxial silicon materials are utilized to fundamentally eliminate the doping concentration gradient defects of conventional diffusion / ion implantation processes, thereby controlling the resistance deviation of the varistor to within ±1%, thereby effectively improving the resistance uniformity of the varistor, making the output signal of the pressure chip more consistent, and improving the measurement accuracy and stability of the pressure sensor 6. At the same time, the conductive layer 2 formed by the epitaxial deposition growth technology has high thickness uniformity (CV value of the present invention <2%), which is significantly better than conventional etching processes (CV value>10%), effectively suppressing the nonlinear drift of resistance caused by film thickness fluctuations, thereby ensuring that the resistance consistency of mass-produced pressure chips is improved by more than 3 times.

[0055] (2) The present invention improves the temperature stability and anti-interference ability of the pressure sensor 6 By symmetrically arranging two groups of resistor groups 21 with M-type structures 4 to form a symmetrical resistor layout of a double M-type structure 5, the thermal stress difference caused by the temperature gradient is offset by a geometric self-compensation mechanism, the influence of temperature on the resistance of the resistor strip 22 is reduced, and the resistance drift caused by temperature changes is effectively offset, and the temperature coefficient of resistance (TCR) is reduced to below 0.05% / °C; the formed Wheatstone bridge structure further suppresses common-mode interference (such as power supply fluctuations), and combined with the stress balancing design of the symmetrical resistor group 21, the zero-position temperature drift of the pressure sensor 6 is made less than 0.01%FS / °C; thereby improving the temperature stability and anti-interference ability of the pressure sensor 6.

[0056] (3) The present invention improves the piezoresistance efficiency and sensitivity of the pressure chip The resistor group 21 of the M-type structure 4 extends the effective resistance path length to at least 3.2 times that of the traditional straight line through the winding curve routing path of the M-type structure 4. When the pressure chip 00 with high resistance uniformity is subjected to the same pressure and produces the same strain, a higher resistance change rate (ΔR / R) can be generated; at the same time, the symmetrical resistor layout of the dual M-type structure 5 makes the varistors distributed in the equivalent stress area of ​​the diaphragm strain field, and the utilization rate of the varistors is further improved, which can efficiently convert mechanical stress into resistance change, thereby obtaining a higher piezoresistance coefficient, further improving the sensitivity of the pressure chip.

[0057] (4) Process compatibility and cost advantages By adapting to the epitaxial growth of deposited silicon crystals and the direct writing process of photolithography, it is compatible with existing MEMS production lines without the need for additional doping or annealing steps, shortening the process cycle by 30%. The double M-type structure 5 achieves pattern generation through single photolithography, avoiding multi-layer alignment errors, increasing the yield rate to more than 98%, and further reducing the overall manufacturing cost.

[0058] In summary, the present invention has significant advantages in improving resistance uniformity, optimizing stress distribution, enhancing temperature stability and anti-interference ability through epitaxial technology and innovative symmetrical resistor layout of dual M-type structure 5, and can effectively improve the performance and reliability of silicon-based pressure sensor 6, and is suitable for the manufacture of high-precision, small-volume pressure sensor 6.

[0059] As an optional implementation method Figure 5 3 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 6 This is the fourth top view of the pressure chip with high resistance uniformity provided in the embodiment.

[0060] Regarding the composition and distribution arrangement of the resistor strip 22, this embodiment is as follows: Figure 5 and Figure 6 As shown, two resistor groups 21 are distributed on the left and right sides of the middle part of the conductive layer 2; wherein the resistor group 21 on the left includes the first to fifth resistor bars 224, and the resistor group 21 on the right includes the sixth to tenth resistor bars 229.

[0061] In application, the resistor group 21 on the left side includes the first resistor bar 220 to the fifth resistor bar 224 , and the resistor group 21 on the right side includes the sixth resistor bar 225 to the tenth resistor bar 229 .

[0062] Specifically, the resistor group 21 on the left includes the first resistor bar 220 to the fifth resistor bar 224, namely the first resistor bar 220, the second resistor bar 221, the third resistor bar 222, the fourth resistor bar 223 and the fifth resistor bar 224; the resistor group 21 on the right includes the sixth resistor bar 225 to the tenth resistor bar 229, namely the sixth resistor bar 225, the seventh resistor bar 226, the eighth resistor bar 227, the ninth resistor bar 228 and the tenth resistor bar 229.

[0063] Figure 5 3 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 6 4 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 7 This is the fifth top view of the pressure chip with high resistance uniformity provided in the embodiment.

[0064] Regarding the connection method between the resistor bar 22 and the external solder joint 32, this embodiment is as follows: Figure 5 and Figure 6 As shown, three external solder joints 32 are provided, one end of the first resistor bar 220 and the sixth resistor bar 225 are connected to the same external solder joint 32 , and one end of the fifth resistor bar 224 and the tenth resistor bar 229 are separately connected to one of the external solder joints 32 .

[0065] During application, one end of the first resistor bar 220 and the sixth resistor bar 225 are electrically and structurally connected to the same external solder joint 32 , and one end of the fifth resistor bar 224 and the tenth resistor bar 229 are electrically and structurally connected to one of the external solder joints 32 .

[0066] Among them, Figure 6 and Figure 7 As shown, the three external welding points 32 are respectively a first external welding point 321, a second external welding point 322 and a third external welding point 323; Further, such as Figure 6 and Figure 7 As shown, one end of the first resistor bar 220 and the sixth resistor bar 225 are electrically and structurally connected to the first external welding point 321, one end of the fifth resistor bar 224 is separately electrically and structurally connected to the second external welding point 322, and one end of the tenth resistor bar 229 is separately electrically and structurally connected to the third external welding point 323.

[0067] Figure 5 3 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 6 4 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 7 This is a fifth top view of a pressure chip with high resistance uniformity provided in an embodiment.

[0068] Regarding the internal solder joint 31, this embodiment Figures 5 to 7 As shown, the internal welding point 31 includes the first to the sixth internal welding points 316; wherein the first to the third internal welding points 313 are located in the resistor group 21 on the left, the first internal welding point 311 is connected to the other end of the first resistor bar 220 and one end of the second resistor bar 221, the second internal welding point 312 is connected to the other end of the second resistor bar 221, one end of the third resistor bar 222 and one end of the fourth resistor bar 223, the third internal welding point is connected to the other end of the fourth resistor bar 223 and the other end of the fifth resistor bar 224; the fourth to the sixth internal welding points 316 are located in the resistor group 21 on the right, the fourth internal welding point 316 is connected to the other end of the fourth resistor bar 223 and the other end of the fifth resistor bar 224; 314 is connected to the other end of the sixth resistor bar 225 and one end of the seventh resistor bar 226, the fifth internal welding point 315 is connected to the other end of the seventh resistor bar 226, one end of the eighth resistor bar 227 and one end of the ninth resistor bar 228, the sixth internal welding point is connected to the other end of the ninth resistor bar 228 and the other end of the tenth resistor bar 229; the third resistor bar 222 is structurally connected only with the second internal welding point to fix and prevent the high resistance uniformity pressure chip 00 from cracking, and the eighth resistor bar 227 is structurally connected only with the fifth internal welding point to fix and prevent the high resistance uniformity pressure chip 00 from cracking.

[0069] Figure 6 4 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 7 This is a fifth top view of a pressure chip with high resistance uniformity provided in an embodiment.

[0070] Specifically, Figure 7 As shown, the internal welding points 31 include first to sixth internal welding points 316 , namely, a first internal welding point 311 , a second internal welding point 312 , a third internal welding point 313 , a fourth internal welding point 314 , a fifth internal welding point 315 and a sixth internal welding point 316 .

[0071] When applying, Figure 6 and Figure 7 As shown, the internal welding point 31 has six internal welding points including the first internal welding point 311 to the sixth internal welding point 316; wherein the first internal welding point 311 to the third internal welding point 313 are located in the resistor group 21 on the left side, the first internal welding point 311 is electrically and structurally connected to the other end of the first resistor bar 220 and one end of the second resistor bar 221, the second internal welding point 312 is electrically and structurally connected to the other end of the second resistor bar 221, one end of the third resistor bar 222 and one end of the fourth resistor bar 223, and the third internal welding point is electrically and structurally connected to the other end of the fourth resistor bar 223 and the other end of the fifth resistor bar 224; The fourth internal welding point 314 to the sixth internal welding point 316 are located in the resistor group 21 on the right side. The fourth internal welding point 314 is electrically and structurally connected to the other end of the sixth resistor bar 225 and one end of the seventh resistor bar 226. The fifth internal welding point 315 is electrically and structurally connected to the other end of the seventh resistor bar 226, one end of the eighth resistor bar 227 and one end of the ninth resistor bar 228. The sixth internal welding point 316 is electrically and structurally connected to the other end of the ninth resistor bar 228 and the other end of the tenth resistor bar 229. The third resistor bar 222 only forms a structural connection with the second internal welding point 312 and has no electrical connection, so it is used to fix and prevent the high resistance uniformity pressure chip 00 from cracking; the eighth resistor bar 227 only forms a structural connection with the fifth internal welding point 315 and has no electrical connection, so it is used to fix and prevent the high resistance uniformity pressure chip 00 from cracking; the third resistor bar 222 and the eighth resistor bar 227 do not participate in the construction of the Wheatstone bridge, and only play the role of fixing and preventing the pressure chip from breaking.

[0072] Figure 3 It is one of the top views of the pressure chip with high resistance uniformity provided by the embodiment; Figure 4 This is a second top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 5 3 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 6 This is the fourth top view of the pressure chip with high resistance uniformity provided in the embodiment.

[0073] The second embodiment of the pressure chip 00 with high resistance uniformity is as follows Figure 5 and Figure 6 As shown, the difference between this embodiment and the first embodiment of the pressure chip 00 with high resistance uniformity is that, on the plane of the conductive layer 2, the first resistor bar and the sixth resistor bar 225, the second resistor bar 221 and the seventh resistor bar 226, the third resistor bar 222 and the eighth resistor bar 227, the fourth resistor bar 223 and the ninth resistor bar 228, and the fifth resistor bar 224 and the tenth resistor bar 229 are arranged horizontally and symmetrically in pairs.

[0074] When applying, Figure 3 and Figure 4 , Figure 5 and Figure 6As shown, in the resistor groups 21 on the left and right sides, the first resistor bar 220, the second resistor bar 221, the third resistor bar 222, the fourth resistor bar 223 and the fifth resistor bar 224; the sixth resistor bar 225, the seventh resistor bar 226, the eighth resistor bar 227, the ninth resistor bar 228 and the tenth resistor bar 229 are arranged in parallel from head to tail to ensure that the M-shaped structure 4 constructed by the single resistor groups 21 on the left and right sides can be connected with the first external welding point 321, the second external welding point 322 and the first external welding point 323. The three external solder joints 323 are gathered at the center, and are symmetrically distributed on the left and right sides; and by arranging the resistor bars 22 in the two resistor groups 21 on the left and right sides horizontally, the length of the resistor bars 22 can be extended to form a high resistance value, and at the same time, the extended resistor bars 22 are used to construct a pressure chip 00 with high resistance uniformity and a double M-shaped structure 5, which can increase the area of ​​the pressure chip, increase the area of ​​pressure sensing, and increase the sensing range, thereby improving the sensing sensitivity of the pressure chip 00 with high resistance uniformity on the other hand.

[0075] Figure 7 FIG5 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 8 This is the sixth top view of the pressure chip with high resistance uniformity provided in the embodiment.

[0076] The third embodiment of the pressure chip 00 with high resistance uniformity is as follows Figure 7 and Figure 8 As shown, the difference between this embodiment and the first embodiment of the pressure chip with high resistance uniformity 00 is that the vertices of the external solder joints 32 are all chamfered 33, which is used to prevent stress concentration at the vertices of the external solder joints 32 after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip with high resistance uniformity 00.

[0077] The vertices of the internal solder joints 31 are all rounded 33 to prevent stress concentration at the vertices of the internal solder joints 31 after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip 00 with high resistance uniformity.

[0078] Figure 1 1 is a schematic diagram of the isometric structure of a pressure chip with high resistance uniformity provided in an embodiment; Figure 2 It is a schematic diagram of the side view structure of a pressure chip with high resistance uniformity provided in an embodiment.

[0079] The fourth embodiment of the pressure chip 00 with high resistance uniformity is as follows Figure 1 and Figure 2 As shown, the difference between this embodiment and the first embodiment of the pressure chip 00 with high resistance uniformity is that, regarding the epitaxial deposition growth process of the above-mentioned conductive layer 2, the conductive layer 2 is formed by uniform epitaxial growth on the base layer 1 using a chemical vapor epitaxial process or a molecular beam epitaxial process.

[0080] When applying, 1. Chemical Vapor Deposition (CVD) is a process for depositing a solid thin film on the surface of a wafer through a chemical reaction. It is one of the most widely used thin film processes in semiconductor manufacturing. The core of CVD is to generate and deposit the target thin film on the surface of the wafer through a chemical reaction of a gaseous or vapor precursor.

[0081] The basic process includes: Reaction source delivery: delivering reaction gas or vapor to the wafer surface.

[0082] Adsorption and reaction: Precursor molecules are adsorbed on the wafer surface and chemical reactions occur through heat, plasma, etc.

[0083] Thin film deposition: The solid generated by chemical reaction is deposited on the wafer surface to form the target thin film.

[0084] By-product discharge: Gaseous by-products generated during the reaction are discharged from the reactor through the gas flow.

[0085] This process can be figuratively likened to "planting trees": the reaction source is like a seed, adsorption is the seed taking root, the chemical reaction is the seed sprouting and growing, and finally the solid film covers the wafer surface like a tree, while the gaseous by-products are cleaned up.

[0086] 2. Molecular Beam Epitaxy (MBE) is an advanced technology for growing single crystal thin films. Its basic principle is to heat the elements that make up the thin film in their own molecular beam furnaces under ultra-high vacuum conditions into directional molecular beams that are incident on the heated substrate for thin film growth.

[0087] MBE technology has the following characteristics: High vacuum environment: MBE is carried out in an ultra-high vacuum environment, and the vacuum degree usually reaches 10^-8 to 10^-11 Torr. The extremely low gas pressure ensures that the collision of the molecular beam with the background gas during transmission is minimized, thereby ensuring the purity and accuracy of the deposition.

[0088] Precise control: MBE technology can achieve very precise thickness control and is suitable for making some devices that require highly precise control, such as quantum dot lasers or high mobility transistors (HEMT). By precisely controlling the molecular beam velocity and beam density, epitaxial growth of single crystal thin films can be achieved.

[0089] Low growth rate: The growth rate of MBE is relatively low, which helps to precisely control the thickness, composition and doping amount of the film at the atomic scale.

[0090] Real-time monitoring: MBE equipment is usually equipped with in-situ monitoring equipment, such as reflection high-energy electron diffraction (RHEED), which can monitor the crystal quality and growth dynamics of the film in real time during the growth process.

[0091] Therefore, a conductive layer 2 having a high-resistance single-crystal silicon layer is prepared on a single-crystal silicon base layer 1 through a chemical vapor epitaxial process or a molecular beam epitaxial process, and the atomic-level growth controllability and lattice consistency of the epitaxial silicon material are utilized to fundamentally eliminate the doping concentration gradient defects of the traditional diffusion / ion implantation process, so that the resistance deviation of the varistor is controlled within ±1%, thereby effectively improving the resistance uniformity of the varistor, making the output signal of the pressure chip more consistent, and improving the measurement accuracy and stability of the pressure sensor 6; at the same time, the conductive layer 2 formed by the epitaxial deposition growth technology has high thickness uniformity, which can effectively suppress the nonlinear resistance drift caused by film thickness fluctuations, thereby ensuring that the mass-produced pressure chips have high resistance consistency.

[0092] Figure 5 3 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 6 4 is a top view of a pressure chip with high resistance uniformity provided in an embodiment; Figure 7 This is a fifth top view of a pressure chip with high resistance uniformity provided in an embodiment.

[0093] The fifth embodiment of the pressure chip 00 with high resistance uniformity is as follows Figures 5 to 7 As shown, the difference between this embodiment and the first embodiment of the pressure chip 00 with high resistance uniformity is that the pad layer 3 and the electrodes of the varistor are formed by depositing metal by sputtering or evaporation process, and the electrodes, internal solder joints and external solder joints of corresponding patterns are formed based on the pad layer 3 through photolithography and etching processes, and the internal solder joints 31 and the external solder joints 32 are connected to the electrodes of the varistor.

[0094] When applied, a sputtering or evaporation process is used to deposit metal to form the pad layer 3 , and the metal used may be: gold (Au), silver (Ag), aluminum (Al), copper (Cu).

[0095] Gold (Au) is formed on a silicon wafer using a sputtering or evaporation process to form a metal electrode. Specifically: Sputtering process: Magnetron sputtering can be used to deposit gold thin films on silicon wafers; this method can accurately control the thickness and uniformity of the gold film and is suitable for preparing high-quality gold electrodes.

[0096] Evaporation process: Thermal evaporation is also one of the commonly used methods for preparing gold thin films, including resistance evaporation and electron beam evaporation; by controlling the evaporation conditions, such as evaporation rate and vacuum degree, a gold electrode with good performance can be obtained.

[0097] Silver (Ag) is formed into metal electrodes on silicon wafers by sputtering or evaporation process. Specifically: Sputtering process: Silver thin film can be deposited onto silicon wafers by magnetron sputtering plasma; silver has good conductivity and optical properties, and the sputtering process can produce silver electrodes with specific thickness and structure.

[0098] Evaporation process: Thermal evaporation is also applicable to the preparation of silver thin films; during the evaporation process, silver atoms are vaporized from the evaporation source and deposited on the surface of the silicon wafer to form a uniform silver electrode layer.

[0099] Aluminum (Al) is formed into metal electrodes on silicon wafers by sputtering or evaporation process. Specifically: Sputtering process: Aluminum is one of the commonly used sputtering materials. High-energy particles bombard the aluminum target material, causing its atoms to be sprayed onto the surface of the silicon wafer to form an aluminum film. This method can achieve uniform deposition of the aluminum film and is suitable for large-scale production.

[0100] Evaporation process: Aluminum can also form metal electrodes on silicon wafers through resistance evaporation or electron beam evaporation; the evaporation process can accurately control the thickness and composition of the aluminum film to meet different application requirements.

[0101] Copper (Cu) is formed into metal electrodes on silicon wafers by sputtering or evaporation process. Specifically: Sputtering process: Copper thin films can be prepared by magnetron sputtering and other processes; copper has excellent electrical conductivity and thermal conductivity, and copper electrodes prepared by sputtering are widely used in electronic devices.

[0102] Evaporation process: Thermal evaporation is also an effective method for preparing copper thin films. By controlling the evaporation parameters, copper electrodes with stable performance can be obtained, which are suitable for the manufacture of a variety of silicon-based devices.

[0103] In short, metals with high conductivity such as gold, silver, aluminum, and copper can be formed into metal electrodes on silicon wafers using sputtering or evaporation processes. The specific process to be selected depends on factors such as actual production needs, equipment conditions, and requirements for electrode performance.

[0104] Fig. 9 This is one of the schematic diagrams of the assembly structure of the pressure sensor provided in the embodiment; Fig.10 This is the second schematic diagram of the assembly structure of the pressure sensor provided in the embodiment.

[0105] Based on the above embodiment of the pressure chip 00 with high resistance uniformity, for example Fig. 9 As shown, a pressure sensor 6 is provided, comprising a signal processing unit 7 and a pressure chip 00 with high resistance uniformity according to any one of the above embodiments, wherein the signal processing unit 7 is electrically connected to the pressure chip 00 with high resistance uniformity.

[0106] The pressure sensor 6 at least integrates (includes) at least one pressure chip 00 with high resistance uniformity.

[0107] When applying, Fig. 9 and Fig.10 As shown, the front side (the side of the pad layer 3) of the pressure chip 00 with high resistance uniformity is electrically connected to the signal processing unit 7 through three external solder joints 32, forming a connection between the sensing end and the processing circuit; in addition, in order to ensure that the pressure chip 00 with high resistance uniformity as the sensing end is subjected to uniform force when measuring pressure, so that the resistance bars 22 of the resistance group 21 of the pressure chip 00 with high resistance uniformity have more uniform strain changes when subjected to mechanical strain, it is necessary to set a stress-bearing layer 8 on the back side of the pressure chip 00 with high resistance uniformity, so that the force transmission to the pressure chip 00 with high resistance uniformity during sensing is uniform, and the mechanical strain is also uniform, and the electrical signal output by the pressure chip 00 with high resistance uniformity to the signal processing unit 7 is also uniform and stable, thereby improving the stability of the pressure sensor 6 in measuring pressure.

[0108] Fig.11 is a schematic diagram of symmetrical distribution of pressure chips with high resistance uniformity in a pressure sensor provided by an embodiment; Fig.12 Schematic diagram of uniform distribution of pressure chips with high resistance uniformity in a pressure sensor provided by an embodiment; Fig.13 This is one of the schematic diagrams of the distribution of the pressure chip matrix with high resistance uniformity in the pressure sensor provided in the embodiment; Fig.14 This is the second schematic diagram of the distribution of the pressure chip matrix with high resistance uniformity in the pressure sensor provided in the embodiment.

[0109] A second embodiment of the pressure sensor 6 is as follows Figures 11 to 14 As shown, the difference between this embodiment and the first embodiment of the pressure sensor 6 is that the pressure sensor 6 includes a plurality of pressure chips 00 with high resistance uniformity, and the plurality of pressure chips 00 with high resistance uniformity are arranged in the pressure sensor 6 in a symmetrical distribution, uniform distribution or matrix distribution manner.

[0110] During application, depending on the application scenario of the pressure sensor 6, when the pressure sensor 6 needs to detect pressure in a large area, the area required for the sensing side of the pressure sensor 6 is larger. In order to increase the detection range of the pressure sensor 6, the sensing side of the pressure sensor 6 can include multiple pressure chips 00 with high resistance uniformity.

[0111] When the sensing side of the pressure sensor 6 includes two pressure chips 00 with high resistance uniformity, as shown in FIG. Fig.11 As shown, two pressure chips 00 with high resistance uniformity can be symmetrically distributed, and then the two pressure chips 00 with high resistance uniformity are connected to the signal processing unit 7; When the sensing side of the pressure sensor 6 includes three or an odd number of pressure chips 00 with high resistance uniformity, such as Fig.12 As shown, three or an odd number of pressure chips 00 with high resistance uniformity can be arranged in a circular array around the same center, so as to be evenly distributed on the circumferential surface, and then three or an odd number of pressure chips 00 with high resistance uniformity are connected to the signal processing unit 7; When the number of pressure chips 00 with high resistance uniformity included on the sensing side of the pressure sensor 6 is two or more, as shown in FIG. Fig.13 and Fig.14 As shown, more than two even-numbered pressure chips 00 with high resistance uniformity can be arranged in a rectangular or square shape, thereby performing a matrix distribution on a square surface, and then more than two even-numbered pressure chips 00 with high resistance uniformity can be connected to a signal processing unit 7 .

[0112] Based on the above embodiment of the pressure chip with high resistance uniformity, an epitaxial process of the pressure chip with high resistance uniformity is provided, comprising the following steps: S1. Select a single crystal silicon wafer of corresponding specifications as the base layer of the pressure chip with high resistance uniformity; S1.1. Select a P-type (100) crystal orientation single crystal silicon wafer with a thickness of 6-15μm and a resistivity of 1-10Ω·cm as the base layer (substrate) of the pressure chip with high resistance uniformity; Or S1.2, select N (111) type crystal orientation single crystal silicon wafer with a thickness of 6-15 μm and a resistivity of 0.01-0.1 Ω·cm as the base layer (substrate) of the pressure chip with high resistance uniformity; S2, growing a conductive layer on the base layer using an epitaxial deposition process; S2.1. A P-type conductive layer (epitaxial layer) with a thickness of 1.5-5.5 μm and a resistivity of 0.04-0.06 Ω·cm is grown on a base layer (substrate) by a chemical vapor epitaxy (CVD) process. During the epitaxial deposition growth of silicon crystals by the chemical vapor epitaxy (CVD) process, the growth temperature is controlled to be 1100°C, the pressure is 100 Torr, and the gas flow rate is 100 sccm; or S2.2, using a molecular beam epitaxy (MBE) process to grow an N-type conductive layer (epitaxial layer) with a thickness of 2-4 μm, a resistivity of 1.5-5.5 μm, and a resistivity of 0.04-0.06 Ω·cm on a base layer (substrate), and in the process of epitaxial deposition growth of silicon crystals by the molecular beam epitaxy (MBE) process, the growth temperature is controlled to be 800°C and the pressure is controlled to be 1×10-8 Torr; S3, directly forming a resistor bar pattern on the conductive layer (epitaxial layer) by using photolithography and etching processes; S3.1, Patterning: Patterning usually extends about 12-14μm from one side of the conductive layer (epitaxial layer) into the wafer; S3.2, grinding: grinding from a starting thickness of about 0.015 inches on one side of the substrate layer of the wafer to a thickness of about 100 μm; S3.3, coating: coating one side of the conductive layer with an anti-corrosion material; S3.4, Etching: Use conventional etching technology to chemically back-etch one side of the ground substrate layer until the pattern of the strain gauge is visible, and control the overall strain gauge thickness of the ground substrate layer + conductive layer to be 10 to 14 μm; S3.5, Removal: The anti-corrosion material coated on the conductive layer is removed by a conventional removal process; S3.6, forming metallized electrical contact on the conductive layer: forming metallized electrical contact on the conductive layer (epitaxial layer) of the strain gauge; S4, making metal electrodes; S4.1, forming a metal electrode on the resistor strip; S4.11, forming a metal electrode on the resistor strip by a sputtering process; S4.12, forming a metal electrode on the resistor strip by an evaporation process; S4.2, performing a photolithography process on the conductive layer; S4.3, performing etching process on the conductive layer S4.4. Form the desired electrode pattern.

[0113] Experiment, test, analyze and summarize: Experimental settings: a pressure chip with high resistance uniformity fabricated by two embodiments of the epitaxial process, and a conventional pressure chip fabricated using a conventional pressure chip fabrication process.

[0114] Specifically, the first embodiment of the epitaxial process, the second embodiment of the epitaxial process and the traditional pressure chip manufacturing process respectively manufactured 16 groups of pressure chips with high resistance uniformity and traditional pressure chips.

[0115] Among them, the first embodiment of the pressure chip with high resistance uniformity is manufactured by using an epitaxial process of the pressure chip with high resistance uniformity: S1. Select a single crystal silicon wafer of corresponding specifications as the base layer of the pressure chip with high resistance uniformity; S1.1. Select a P-type (100) crystal orientation single crystal silicon wafer with a thickness of 8-10μm and a resistivity of 1-10Ω·cm as the base layer (substrate); S2, growing a conductive layer on the base layer using an epitaxial deposition process; S2.1. A P-type conductive layer (epitaxial layer) with a thickness of 1.5-5.5 μm and a resistivity of 0.04-0.06 Ω·cm is grown on the substrate layer by a chemical vapor epitaxy (CVD) process. During the epitaxial deposition growth of silicon crystals by the chemical vapor epitaxy (CVD) process, the growth temperature is controlled to be 1100°C, the pressure is 100 Torr, and the gas flow rate is 100 sccm; S3, directly forming a resistor bar pattern on the conductive layer (epitaxial layer) by using photolithography and etching processes; S3.1, Patterning: Patterning usually extends about 12-14μm from one side of the conductive layer (epitaxial layer) into the wafer; S3.2, grinding: grinding from a starting thickness of about 0.015 inches on one side of the substrate layer of the wafer to a thickness of about 100 μm; S3.3, coating: coating one side of the conductive layer with an anti-corrosion material; S3.4, Etching: Use conventional etching technology to chemically back-etch one side of the ground substrate layer until the pattern of the strain gauge is visible, and control the overall strain gauge thickness of the ground substrate layer + conductive layer to be 10 to 14 μm; S3.5, Removal: The anti-corrosion material coated on the conductive layer is removed by a conventional removal process; S3.6, forming metallized electrical contact on the conductive layer: forming metallized electrical contact on the conductive layer (epitaxial layer) of the strain gauge; S4, making aluminum metal electrodes; S4.1, forming an aluminum metal electrode on the resistor strip; S4.11, forming aluminum metal electrodes on the resistor strips by using a sputtering process; S4.12, forming aluminum metal electrodes on the resistor strips by using an evaporation process; S4.2, performing a photolithography process on the conductive layer; S4.3, performing etching process on the conductive layer S4.4. Form the desired aluminum metal electrode pattern.

[0116] Among them, a second embodiment of a pressure chip with high resistance uniformity is manufactured using an epitaxial process of a pressure chip with high resistance uniformity: S1. Select a single crystal silicon wafer of corresponding specifications as the base layer of the pressure chip with high resistance uniformity; S1.2 Select an N-type (111) crystal orientation single crystal silicon wafer with a thickness of 8-10 μm and a resistivity of 0.01-0.1 Ω·cm as the base layer (substrate); S2, growing a conductive layer on the base layer using an epitaxial deposition process; S2.2, using a molecular beam epitaxy (MBE) process to grow an N-type conductive layer (epitaxial layer) with a thickness of 2-4 μm, a resistivity of 1.5-5.5 μm, and a resistivity of 0.04-0.06 Ω·cm on the substrate layer, and in the process of epitaxial deposition growth of silicon crystals by the molecular beam epitaxy (MBE) process, the growth temperature is controlled to be 800°C and the pressure is controlled to be 1×10-8 Torr; S3, directly forming a resistor bar pattern on the conductive layer (epitaxial layer) by using photolithography and etching processes; S3.1, Patterning: Patterning usually extends about 12-14μm from one side of the conductive layer (epitaxial layer) into the wafer; S3.2, grinding: grinding from a starting thickness of about 0.015 inches on one side of the substrate layer of the wafer to a thickness of about 100 μm; S3.3, coating: coating one side of the conductive layer with an anti-corrosion material; S3.4, Etching: Use conventional etching technology to chemically back-etch one side of the ground substrate layer until the pattern of the strain gauge is visible, and control the overall strain gauge thickness of the ground substrate layer + conductive layer to be 10 to 14 μm; S3.5, Removal: The anti-corrosion material coated on the conductive layer is removed by a conventional removal process; S3.6, forming metallized electrical contact on the conductive layer: forming metallized electrical contact on the conductive layer (epitaxial layer) of the strain gauge; S4, making aluminum metal electrodes; S4.1, forming an aluminum metal electrode on the resistor strip; S4.11, forming aluminum metal electrodes on the resistor strips by using a sputtering process; S4.12, forming aluminum metal electrodes on the resistor strips by using an evaporation process; S4.2, performing a photolithography process on the conductive layer; S4.3, performing etching process on the conductive layer S4.4. Form the desired aluminum metal electrode pattern.

[0117] Experimental data collection: The pressure chip manufactured by the first embodiment using the epitaxial process, the second embodiment using the epitaxial process, and the traditional pressure chip manufacturing process were tested to obtain Test Table 1 and Test Table 2 respectively.

[0118] Among them, Test Table 1, Test Table 2 and Test Table 3 all list 16 groups of test data.

[0119] Test Table 1 shows the resistance value of the pressure chip of Example 1 of the present invention, Test Table 2 shows the resistance value of the pressure chip of Example 2 of the present invention, and Test Table 3 shows the resistance value of the traditional pressure chip.

[0120] Test data of pressure chip with high resistance uniformity: The first embodiment of the epitaxial process has a high resistance uniformity pressure chip: the average resistance is about 2.7kΩ, the maximum resistance is about 2.7kΩ, the minimum resistance is about 2.68kΩ, the standard deviation is 0.015kΩ, and the standard deviation percentage is 0.56%.

[0121] The second embodiment of the epitaxial process has a high resistance uniformity pressure chip: the average resistance is about 2.7kΩ, the maximum resistance is about 2.72kΩ, the minimum resistance is about 2.66kΩ, the standard deviation is 0.014kΩ, and the standard deviation percentage is 0.51%.

[0122] Test data of traditional pressure chip: Compared with the two tests of the pressure chip with high resistance uniformity, the average resistance of the conventional pressure chip in Test Table 3 is about 4.30 kΩ, the maximum resistance is about 4.48 kΩ, and the minimum resistance is about 4.18 kΩ. The standard deviation is 0.08 kΩ, and the standard deviation percentage is 1.94%.

[0123] Comparative analysis: By summarizing the pressure chips with high resistance uniformity using the first embodiment of the epitaxial process and the second embodiment of the epitaxial process, and comparing them with the pressure chips manufactured using the traditional pressure chip manufacturing process, the test results show that the resistance deviation of the resistor bars of the pressure chips with high resistance uniformity is controlled within ±1%.

[0124] Summary: Therefore, the output signal of the pressure chip with high resistance uniformity has good linearity and repeatability; compared with the traditional pressure chip, the resistance deviation is smaller, and the output signal quality is better and more stable; for application scenarios with more stringent test environments and higher test accuracy, the pressure sensor made with the pressure chip sensing core with high resistance uniformity of the present invention has better performance and is more suitable for high-precision pressure testing scenarios.

[0125] Test Table 1 serial number Resistance (kΩ) 1 2.69 2 2.68 3 2.68 4 2.69 5 2.69 6 2.71 7 2.7 8 2.72 9 2.72 10 2.71 11 2.72 12 2.7 13 2.68 14 2.68 15 2.7 16 2.71 Test Table 1: shows the resistance value of the pressure chip of Example 1 of the present invention.

[0126] Test Table 2 serial number Resistance (kΩ) 1 2.67 2 2.66 3 2.7 4 2.7 5 2.7 6 2.7 7 2.7 8 2.7 9 2.7 10 2.69 11 2.69 12 2.7 13 2.72 14 2.7 15 2.69 16 2.7 Test Table 2 shows the resistance value of the pressure chip of Example 2 of the present invention.

[0127] Test Table 3 serial number Resistance (kΩ) 1 4.2 2 4.26 3 4.33 4 4.42 5 4.48 6 4.34 7 4.32 8 4.18 9 4.27 10 4.32 11 4.28 12 4.23 13 4.2 14 4.25 15 4.4 16 4.3 Test Table 3 shows the resistance values ​​of the conventional pressure chip.

[0128] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described.

Claims

1. A pressure chip with high resistance uniformity based on epitaxial process, characterized in that: The invention comprises a base layer, a conductive layer and a pad layer stacked in sequence from bottom to top to form a pressure chip with high resistance uniformity; A plurality of resistor strips are formed on the conductive layer, and the plurality of resistor strips are divided into two resistor groups; The pad layer is provided with a plurality of internal welding points and a plurality of external welding points, wherein the internal welding points are used to connect the two resistor bars of the same resistor group; the plurality of external welding points are distributed between the two resistor groups, and the external welding points are used to connect the resistor bars at the head and tail positions of the resistor group; The single resistor group and the internal solder joint form an M-shaped structure. By forming the M-shaped structure, the resistance path length of the resistor bar is increased, and the uniform stress distribution of the resistor bar symmetrically distributed in the resistor group is used to improve the conversion rate of the pressure chip with high resistance uniformity from mechanical stress to resistance change, obtain a high voltage resistance coefficient, and improve the sensitivity of the pressure chip with high resistance uniformity; The two groups of resistor groups, the internal soldering points and the external soldering points form a double M-shaped structure and form a Wheatstone bridge.

2. The pressure chip with high resistance uniformity according to claim 1, characterized in that: The material of the base layer is single crystal silicon.

3. The pressure chip with high resistance uniformity according to claim 2, characterized in that: The base layer is a P-type crystal-oriented single-crystalline silicon wafer with a thickness of 6-15 μm and a resistivity of 1-10 Ω·cm, or an N-type crystal-oriented single-crystalline silicon wafer with a thickness of 6-15 μm and a resistivity of 0.01-0.1 Ω·cm.

4. The pressure chip with high resistance uniformity according to claim 2, characterized in that: The conductive layer is single crystal silicon that is epitaxially deposited and grown on the outer surface of the base layer.

5. The pressure chip with high resistance uniformity according to claim 4, characterized in that: The thickness of the conductive layer is 1.5-5.5 μm, and the resistivity is 0.04-0.06 Ω·cm.

6. The pressure chip with high resistance uniformity according to claim 4, characterized in that: The conductive layer is formed by uniform epitaxial growth on the base layer by using a chemical vapor epitaxy process or a molecular beam epitaxy process.

7. The pressure chip with high resistance uniformity according to claim 4, characterized in that: The resistor strip is a resistor body of a varistor formed directly on the conductive layer by photolithography and etching.

8. The pressure chip with high resistance uniformity according to claim 7, characterized in that: The pad layer and the electrodes of the varistor are formed by depositing metal by sputtering or evaporation process, and the electrodes, the internal solder joints and the external solder joints of corresponding patterns are formed based on the pad layer through photolithography and etching processes. The internal solder joints and the external solder joints are connected to the electrodes of the varistor.

9. The pressure chip with high resistance uniformity according to claim 1, characterized in that: The structural positions of the two groups of resistor groups in the double M-type structure are set to be symmetrically distributed. The double M-type structure is used to offset the resistance drift caused by temperature change and suppress common mode interference through the symmetrically distributed structural positions.

10. The pressure chip with high resistance uniformity according to claim 9, characterized in that: The two resistor groups are distributed on the left and right sides of the middle part of the conductive layer; The resistor group on the left side includes the first to fifth resistor bars, and the resistor group on the right side includes the sixth to tenth resistor bars; There are three external welding points, one end of the first resistor bar and the sixth resistor bar is connected to the same external welding point, and one end of the fifth resistor bar and the tenth resistor bar is separately connected to one of the external welding points.

11. The pressure chip with high resistance uniformity according to claim 10, characterized in that: The internal welding points include first to sixth internal welding points; The first to third internal welding points are located in the resistor group on the left side, the first internal welding point is connected to the other end of the first resistor bar and one end of the second resistor bar, the second internal welding point is connected to the other end of the second resistor bar, one end of the third resistor bar and one end of the fourth resistor bar, and the third internal welding point is connected to the other end of the fourth resistor bar and the other end of the fifth resistor bar; The fourth to sixth internal welding points are located in the resistor group on the right side, the fourth internal welding point is connected to the other end of the sixth resistor bar and one end of the seventh resistor bar, the fifth internal welding point is connected to the other end of the seventh resistor bar, one end of the eighth resistor bar and one end of the ninth resistor bar, and the sixth internal welding point is connected to the other end of the ninth resistor bar and the other end of the tenth resistor bar; The third resistor bar only forms a structural connection with the second internal welding point to fix and prevent the high resistance uniformity pressure chip from cracking, and the eighth resistor bar only forms a structural connection with the fifth internal welding point to fix and prevent the high resistance uniformity pressure chip from cracking.

12. The pressure chip with high resistance uniformity according to claim 10, characterized in that: On the plane of the conductive layer, the first resistor bar and the sixth resistor bar, the second resistor bar and the seventh resistor bar, the third resistor bar and the eighth resistor bar, the fourth resistor bar and the ninth resistor bar, and the fifth resistor bar and the tenth resistor bar are arranged horizontally and symmetrically.

13. The pressure chip with high resistance uniformity according to claim 9, characterized in that: The vertices of the external solder joints are all rounded to prevent stress concentration at the vertices of the external solder joints after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip with high resistance uniformity.

14. The pressure chip with high resistance uniformity according to claim 9, characterized in that: The vertices of the internal solder joints are all rounded to prevent stress concentration at the vertices of the internal solder joints after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip with high resistance uniformity.

15. A pressure sensor, characterized in that: It comprises a signal processing unit and a pressure chip with high resistance uniformity according to any one of claims 1 to 14, wherein the signal processing unit is electrically connected to the pressure chip with high resistance uniformity.

16. The pressure sensor according to claim 15, characterized in that: The pressure sensor includes a plurality of pressure chips with high resistance uniformity, and the plurality of pressure chips with high resistance uniformity are arranged in the pressure sensor in a symmetrical distribution, uniform distribution or matrix distribution manner.

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