Differentiation test method and system of wafer, electronic equipment and storage medium

Abstract

The invention provides a wafer differentiation test method and system, electronic equipment and a storage medium. The method comprises the following steps: distributing coordinate information of each bare chip needing to be tested to at least one bare chip set based on test requirements of wafers of the same batch and coordinate information of the bare chips needing to be tested; setting an electrical scheme for each bare chip set to form at least one test set; performing combination based on the at least one bare chip set and the corresponding at least one test set to generate at least one test scheme set; obtaining wafers of the same batch, and determining the test content of each wafer based on the at least one test scheme set; and carrying out differential test on the same batch of wafers based on the test content. In the mode, differentiated testing can be carried out on the wafers of each batch and / or the bare chip of each wafer, the customized testing scheme requirement of the FAB is met, the wafer testing time of the wafer-level electrical testing is shortened, and therefore the wafer delivery efficiency of the FAB is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer-level electrical testing, and in particular to a wafer-level differentiated testing method, system, electronic equipment and storage medium. Background Art

[0002] In the field of wafer testing, a test solution set is generally used to perform wafer electrical testing on wafers during the wafer product development phase to test the electrical parameters of specific test structures on the wafer. At present, the existing wafer-level electrical testing equipment can only select the same test solution set for the tested wafer during the wafer testing process. In order to test the electrical parameters of the wafer more comprehensively, a large number of test solutions need to be defined in the test solution set to cover as much as possible. However, if the current solution does not have the conditions for differentiated testing and can only support the test solution of a single test solution set, the test solution has low modifiability and scalability, and cannot meet the needs of some FAB manufacturers for wafer differentiated testing. Summary of the invention

[0003] In view of this, the object of the present invention is to provide a differentiated testing method, system, electronic device and storage medium for wafers, so as to define a set of test schemes (super test spec) specified for each wafer in each batch (lot), so as to perform differentiated wafer-level electrical testing, meet the customized test scheme set requirements of FAB (Fabrication), shorten the time for wafer-level electrical testing of wafers, and thus improve the wafer shipment efficiency of FAB (Fabrication).

[0004] In a first aspect, an embodiment of the present invention provides a differentiated testing method for wafers, the method comprising: allocating the coordinate information of each bare die to be tested to at least one bare die set based on the test requirements of wafers from the same batch and the coordinate information of the bare die to be tested; setting an electrical scheme for each bare die set to form at least one test set; generating at least one test scheme set by combining at least one bare die set and its corresponding at least one test set; obtaining wafers from the same batch of wafers, and determining the test content of each wafer based on at least one test scheme set; and performing differentiated testing on wafers from the same batch based on the test content.

[0005] In an optional embodiment of the present application, based on the test requirements of wafers from the same batch and the coordinate information of the die to be tested, the coordinate information of each die to be tested is allocated to at least one die set; an electrical scheme is set for each die set to form at least one test set, including: defining at least one die set and test coordinate points of the die to be tested according to the test requirements of wafers from the same batch; wherein at least one die set contains the same or different test coordinate points; setting at least one test object for each die set; generating at least one test set by combining at least one test object, and setting at least one electrical scheme for the test object.

[0006] In an optional embodiment of the present application, the above-mentioned combination is based on at least one bare chip set and its corresponding at least one test set, including: classifying and merging at least one test set, and matching the coordinate information of the bare chip set and the required test for each test set to obtain at least one test scheme set, each test scheme set containing completely identical / partially identical / completely identical test sets, test objects and bare chip sets.

[0007] In an optional embodiment of the present application, the above-mentioned combination based on at least one bare chip set and its corresponding at least one test set also includes: when matching the bare chip set for each test set, verifying whether all test objects in the test set are located in at least one test object of the bare chip set; if there is a test object that is not located in at least one test object of the bare chip set, an error prompt is given.

[0008] In an optional embodiment of the present application, the above-mentioned wafers from the same batch are obtained, and the test content of each wafer is determined based on at least one test scheme set, including: selecting wafers to be tested from the same batch of wafers, and obtaining at least one test scheme set; configuring the test scheme set according to the test requirements of the wafers to be tested, and determining the test content of each wafer.

[0009] In an optional embodiment of the present application, the above-mentioned configuration of the test scheme set according to the test requirements of the wafer to be tested includes: loading the test scheme set, checking whether the test content defined in the test scheme set is accurate; if the test content defined in the test scheme set is accurate, determining the test scheme set for each wafer to be tested; if the test content defined in the test scheme set is inaccurate, redetermining the definition content of the test scheme set.

[0010] In an optional embodiment of the present application, the above-mentioned differentiated testing of wafers from the same batch based on the test content includes: obtaining the wafers to be tested and a set of test schemes in the same batch of wafers; traversing the wafers to be tested, and obtaining the required set of test schemes based on the information of the current wafer to be tested; and performing electrical testing on the current wafer to be tested according to the test scheme set.

[0011] In a second aspect, an embodiment of the present invention further provides a differentiated testing system for wafers, the system comprising: a test scheme definition module, for allocating the coordinate information of each die to be tested to at least one die set based on the test requirements of wafers from the same batch and the coordinate information of the die to be tested; setting an electrical scheme for each die set to form a test set; generating at least one test scheme set by combining at least one die set and its corresponding at least one test set; a wafer definition module, for acquiring wafers from the same batch of wafers, and determining the test content of each wafer based on at least one test scheme set; and a wafer differentiated testing module, for performing differentiated testing on wafers from the same batch based on the test content.

[0012] In an optional embodiment of the present application, the above-mentioned test scheme definition module includes a die set definition unit, an electrical scheme definition unit, and a test scheme definition unit; the die set definition unit is used to define the die set and the test coordinate points of the die to be tested according to the test requirements of the same batch of wafers; wherein, at least one die set contains at least one identical or different test coordinate point; at least one test object is set for each die set; the electrical scheme definition unit is used to generate at least one test set by combining at least one test object, and set at least one electrical scheme for the test object; the test scheme definition unit is used to generate at least one test scheme set by combining at least one die set and its corresponding at least one test set.

[0013] In an optional embodiment of the present application, the above-mentioned wafer definition module includes a test wafer determination unit and a test scheme determination unit; the test wafer determination unit is used to obtain wafers from the same batch of wafers, determine the wafers to be tested and set a unique identifier; the test scheme determination unit is used to obtain at least one test scheme set, bind the unique identifier with the required test scheme set, and determine the test content of the wafer to be tested.

[0014] In a third aspect, an embodiment of the present invention further provides an electronic device, including a processor and a memory, wherein the memory stores computer executable instructions that can be executed by the processor, and the processor executes the computer executable instructions to implement the above-mentioned wafer differentiated testing method.

[0015] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned differentiated testing method for wafers.

[0016] The embodiments of the present invention bring the following beneficial effects: Embodiments of the present invention provide a method, system, electronic device and storage medium for differentiated testing of wafers. Based on the test requirements of wafers from the same batch and the coordinate information of the die to be tested, the coordinate information of each die to be tested is allocated to at least one die set; an electrical scheme is set for each die set to form at least one test set; at least one die set and its corresponding at least one test set are combined to generate at least one test scheme set; wafers from the same batch are obtained, and the test content of each wafer is determined based on at least one test scheme set; and differentiated testing is performed on wafers from the same batch based on the test content. In this way, differentiated testing at the wafer level and the die level can be achieved. The existing technology can only achieve the same test for wafers in the same batch, but cannot achieve differentiated testing of different wafers in the same batch and differentiated testing of different dies in a wafer. The technical solution sets multiple die sets containing die coordinate information according to test requirements (such as multiple electrical test schemes), and matches at least one test set to the die set, and forms multiple sets of test scheme sets by freely combining the die sets. Because the die set only contains some coordinate points, by setting multiple die sets corresponding to the test sets, a wafer can perform differentiated testing on different dies. At the same time, the set multiple sets of test scheme sets can be selected for different wafers, so that multiple wafers in the same batch can be tested at the differentiated wafer level, meet the customized test scheme requirements of FAB (wafer factory), shorten the time for wafer-level electrical testing of wafers, and thus improve the wafer shipment efficiency of FAB (wafer factory).

[0017] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by implementing the above-mentioned technology of the present disclosure.

[0018] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A flowchart of a wafer differentiation testing method provided by an embodiment of the present invention; Figure 2A flow chart of another wafer differentiation testing method provided by an embodiment of the present invention; Figure 3 A schematic diagram of the composition relationship of a super test spec provided in an embodiment of the present invention; Figure 4 A schematic diagram of an implementation flow of a wafer definition module for each lot provided in an embodiment of the present invention; Figure 5 A schematic diagram of a wafer differentiation test provided by an embodiment of the present invention; Figure 6 A schematic diagram of a differentiated testing method provided by an embodiment of the present invention; Figure 7 A schematic diagram of a die list editing interface provided by an embodiment of the present invention; Figure 8 A schematic diagram of a die spec editing interface provided by an embodiment of the present invention; Fig. 9 A schematic diagram of a test spec editing interface provided by an embodiment of the present invention; Fig.10 A schematic diagram of a super test spec editing interface provided by an embodiment of the present invention; Fig.11 A schematic diagram of a wafer configuration interface provided by an embodiment of the present invention; Fig.12 A schematic diagram of the structure of a wafer differentiation test system provided by an embodiment of the present invention; Fig.13 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] At present, the existing wafer test scheme generally determines the test time and test electrical parameters of wafers in each batch (lot) by category and quantity. However, the current wafer-level electrical test software does not have the function of differentiated testing, and only supports a single test scheme during software testing. The existing test scheme has low modifiability and scalability, and cannot meet the needs of wafer differentiated testing of some FABs (wafer factories).

[0023] Based on this, a differentiated testing method, system, electronic device and storage medium for wafers provided in an embodiment of the present invention specifically provides a super test spec wafer-level electrical testing differentiated testing method, which aims to solve the problem of a single test scheme for wafer selection in each batch (lot) during existing wafer-level electrical testing. It can satisfy the requirement that different FABs define different test scheme sets for different wafers in each batch (lot), improve the range of electrical test parameters in a single batch (lot), and meet the needs of differentiated testing.

[0024] To facilitate understanding of this embodiment, a wafer differentiation testing method disclosed in an embodiment of the present invention is first introduced in detail.

[0025] Embodiment 1: An embodiment of the present invention provides a wafer differentiation test method. The wafer differentiation test scheme provided in this embodiment includes the following modules: a test scheme definition module, a wafer definition module for each lot (lot) (which may be referred to as a wafer definition module for short), and a wafer differentiation test module.

[0026] Based on the above description, see Figure 1 A flowchart of a wafer differentiation test method is shown, and the wafer differentiation test method includes the following steps: Step S102 , based on the test requirements of wafers in the same batch and the coordinate information of the dies to be tested, the coordinate information of each die to be tested is allocated to at least one die set; and an electrical scheme is set for each die set to form at least one test set.

[0027] The test scheme definition module in this embodiment can set the coordinate information of the die set and the die to be tested based on the test requirements, and can also set the electrical scheme for each die set to form multiple test sets; the test requirements can be multiple electrical test schemes. For example, if multiple tests are required on different die on the same wafer, multiple die sets can be set for multiple tests, and the coordinate information that needs to test the same content can be put into the same die set, so as to achieve differentiated test content settings for the same wafer.

[0028] The coordinate information of each die belongs to at least one die set, that is, multiple die sets may have the same coordinate information. At least one die included in multiple die sets may be the same, that is, the same die may be tested differently.

[0029] In some embodiments, at least one die set and test coordinate points of the die to be tested can be defined according to the test requirements of the same batch of wafers; wherein, at least one die set includes multiple identical or different test coordinate points; at least one test object is set for each die set; at least one test set is generated by combining at least one test object, and at least one electrical scheme is set for the test object.

[0030] Exemplarily, the test object here can be a module. For each bare die set, multiple modules to be tested and corresponding coordinates are set, and then a test set is set according to the test requirements. The test set is formed by setting an electrical scheme for each selected module. Each bare die set can contain multiple test sets according to the test requirements.

[0031] The test scheme definition module in this embodiment may also set an electrical scheme for each die in the plurality of die sets. Specifically, different electrical schemes may be defined for modules to be tested in each die.

[0032] Among them, this embodiment can first define at least one bare die set and test coordinate points of the bare die to be tested according to the test requirements of the same batch of wafers, and then set at least one test object for the bare die set and set an electrical scheme based on the test object, thereby forming a test set associated with the bare die set.

[0033] Step S104 , generating at least one test solution set based on combining at least one die set and at least one test set corresponding thereto.

[0034] The test scheme definition module in this embodiment may also combine at least one bare die set and its corresponding at least one test set to generate at least one test scheme set.

[0035] In some embodiments, at least one test set under the same or different bare die coordinates can be classified and merged, and the coordinate information of the bare die set and the required test can be matched for each test set to obtain at least one test scheme set, each test scheme set containing completely identical, partially identical, or completely different test sets, bare die sets, and test objects.

[0036] The test scheme definition module in this embodiment can classify and merge single or multiple test sets under the same or different die coordinates to obtain multiple test scheme sets. Among them, a test scheme set in this embodiment can include at least one complete or partial test scheme mentioned above. Because there may be coordinate information of the same or different dies when defining a die set, one or more test sets under the same or different die coordinates will be generated when setting the test set based on the module defined by each die set.

[0037] Step S106, obtaining wafers from the same batch of wafers, determining the test content of each wafer based on at least one test scheme set; and performing differentiated testing on the wafers from the same batch based on the test content.

[0038] The wafer definition module in this embodiment can obtain the wafer information of each batch, determine the super test spec (test solution set) of each wafer based on the above test solution set, and thus define the test content specified for each wafer in each batch.

[0039] The wafer differentiation test module in this embodiment can perform differentiated testing on each batch of wafers and / or the bare die of each wafer based on the test content of each wafer, thereby performing differentiated wafer-level electrical testing to meet the FAB's customized test solution requirements, shorten the time for wafer-level electrical testing of wafers, and thus improve the FAB's wafer shipment efficiency.

[0040] An embodiment of the present invention provides a differentiated testing method for wafers. Based on the test requirements of wafers from the same batch and the coordinate information of the bare die to be tested, the coordinate information of each bare die to be tested is distributed to at least one bare die set; an electrical scheme is set for each bare die set to form at least one test set; at least one test scheme set is generated by combining at least one bare die set and its corresponding at least one test set; wafers from the same batch of wafers are obtained, and the test content of each wafer is determined based on at least one test scheme set; and differentiated testing is performed on the wafers from the same batch based on the test content. In this way, differentiated testing at the wafer level and the die level can be achieved. The existing technology can only achieve the same test for wafers in the same batch, but cannot achieve differentiated testing of different wafers in the same batch and differentiated testing of different dies in a wafer. The technical solution sets multiple die sets containing die coordinate information according to test requirements (such as multiple electrical test schemes), and matches at least one test set to the die set, and forms multiple sets of test scheme sets by freely combining the die sets. Because the die set only contains some coordinate points, by setting multiple die sets corresponding to the test sets, a wafer can perform differentiated testing on different dies. At the same time, the set multiple sets of test scheme sets can be selected for different wafers, so that multiple wafers in the same batch can be tested at the differentiated wafer level, meet the customized test scheme requirements of FAB, shorten the time for wafer-level electrical testing of wafers, and thus improve the wafer shipment efficiency of FAB.

[0041] Embodiment 2: This embodiment provides another wafer differentiation test method, which is implemented on the basis of the above embodiment. The above method can be used to perform electrical testing on wafers.

[0042] Electrical testing is the process of testing the electrical performance of electronic components, PCB (Printed Circuit Board) boards or wafers. In the field of semiconductor manufacturing, electrical testing is also an important part of the wafer manufacturing process. Various devices on the wafer will undergo electrical testing to check for defects and measure parameters to ensure that the wafer meets the predetermined electrical performance requirements before packaging and cutting.

[0043] The above method provided in this embodiment can be used to perform electrical testing on wafers. It should be noted that the above method provided in this embodiment can be used not only to perform electrical testing on wafers, but also to perform other tests on wafers, which is not limited in this embodiment.

[0044] Based on the above description, see Figure 2 A flowchart of another wafer differentiation test method is shown, and the wafer differentiation test method includes the following steps: Step S202 , based on the test requirements of wafers in the same batch and the coordinate information of the dies to be tested, the coordinate information of each die to be tested is allocated to at least one die set; and an electrical scheme is set for each die set to form at least one test set.

[0045] Step S204, classify and merge at least one test set, and match the bare die set and the coordinate information of the required test for each test set to obtain at least one test scheme set, each test scheme set containing completely identical / partially identical / completely identical test sets, test objects and bare die sets.

[0046] In some embodiments, when matching each test set to a die set, it is checked whether all test objects in the test set are located in at least one test object in the die set; if there is a test object that is not located in at least one test object in the die set, an error message is given.

[0047] Because when generating a test set, the test set is generally edited based on the modules that exist in the bare chip set, but it does not rule out the addition of previously undefined modules. In the process of generating a test plan set, the test set and the modules in the selected bare chip set will be matched. If there are undefined modules, an alarm will be issued. At the same time, the user can update the previously defined modules (such as adding undefined modules). If no operation is performed, the test content of the undefined modules will be ignored during the test.

[0048] See also Figure 3The schematic diagram of the composition relationship of a super test spec is shown. First, the position coordinate points of the test dies required for the wafer are defined, and at least one test name (diename) of a die is defined for each coordinate, that is, the required test dies are classified to form multiple die sets.

[0049] Secondly, set a test plan for each bare die set, specifically define the module coordinate point positions that need to be tested for each bare die set, and define a module test name (modulename) for each module coordinate point to form a die spec; based on the set module name, select the required module name to set the electrical plan to form multiple test sets, and name the single test set test spec.

[0050] Finally, according to the properties of the electrical test scheme and different test requirements, single and multiple test specs under the same or different die coordinates can be classified and merged to form a set of multiple test schemes under different dies or the same die and defined as a super test spec. Each super test spec can contain completely identical, partially identical, or completely different test specs (test sets) and die specs (sets of test objects) and die lists (lists of die sets), and the different super test spec electrical test schemes defined above are saved to files.

[0051] Step S206, obtaining wafers from the same batch of wafers, determining the test content of each wafer based on at least one test scheme set; and performing differentiated testing on the same batch of wafers based on the test content.

[0052] In some embodiments, wafers to be tested in the same batch of wafers can be selected to obtain at least one test solution set; the test solution set is configured according to the test requirements of the wafers to be tested, and the test content of each wafer is determined.

[0053] In this embodiment, for wafers to be tested in a batch of wafers, at least one test solution set can be obtained first, and then a suitable test solution set can be configured according to the test requirements of the wafers to be tested, so as to determine the test content of the wafers.

[0054] In some embodiments, a test plan set can be loaded to check whether the test content defined in the test plan set is accurate; if the test content defined in the test plan set is accurate, the test plan set for each wafer to be tested is determined; if the test content defined in the test plan set is inaccurate, the definition content of the test plan set is redetermined.

[0055] See also Figure 4 The schematic diagram of the implementation process of the wafer definition module for each lot is shown. First, select 1-25 wafers to be tested in each lot in the wafer configuration interface. Secondly, load the file that saves the electrical test plan to obtain different super test spec sets, check whether the content of the super test spec set definition is correct, and then select different super test spec electrical test plans for different wafers in the electrical test plan configuration interface according to the wafer test requirements.

[0056] In some embodiments, wafers to be tested and a set of test solutions in the same batch of wafers can be obtained; the wafers to be tested are traversed, and the required set of test solutions is obtained based on the information of the current wafer to be tested; and electrical tests are performed on the current wafer to be tested according to the test solution set.

[0057] After obtaining the wafers to be tested and the test solution set in a batch of wafers, the present embodiment can perform differentiated testing on the wafers to be tested. The wafers to be tested can be traversed, and the corresponding test solution set can be obtained according to the information of each wafer to be tested, and electrical testing can be performed on each wafer to be tested according to the test solution set.

[0058] See also Figure 5 The schematic diagram of a wafer differentiation test is shown. Different super test spec differentiation test modules can obtain the number of wafers and IDs to be tested from each batch (lot) of wafer definition modules, obtain the ID (subscript) of the wafer to be tested, obtain the specified super test spec according to the wafer ID, parse all electrical test schemes defined in the super test spec, test each electrical test scheme on the wafer in a loop, and store the test data results in real time.

[0059] In the field of wafer-level electrical testing, since different FABs provide a large number of electrical testing schemes and a single testing scheme requires a long testing time, in specific scenarios, when FAB adds a new electrical testing scheme, it is necessary to only perform this electrical scheme test on the specified single or multiple wafers in each batch (lot). However, the existing method can only perform this electrical scheme test on all wafers in each batch (lot), which cannot meet the differentiated testing needs and affects the analysis efficiency of wafer electrical parameters.

[0060] The above method provided by the embodiment of the present invention specifically provides a differentiated testing method for electrical testing, which can define a test scheme specified for each wafer in each batch, and can perform differentiated wafer-level electrical testing to meet the customized testing scheme requirements of FAB, shorten the time for wafer-level electrical testing of wafers, and thus improve the wafer shipping efficiency of FAB.

[0061] Embodiment three: This embodiment provides a specific implementation of a wafer differentiation test method. This implementation is implemented on the basis of the above embodiment. Figure 6 Schematic diagram of a differentiated testing method.

[0062] like Figure 6 As shown, in order to meet the needs of internal and customer use of supporting tester software to select different sets of electrical test solutions for different wafers during wafer-level electrical testing of wafers in the same lot (same batch), this embodiment can provide a differentiated test method for wafer-level electrical testing based on super test spec.

[0063] If the customer or the internal department adds a single or multiple electrical test solutions, first, in the Super Test Spec definition module, according to the test solution requirements, define the die name and test coordinate points in the die list editing interface. The interface after definition can be seen in Figure 7 A schematic diagram of a die list editing interface is shown.

[0064] Secondly, define diename1-6 in the die spec editing interface, define each module name and coordinate point. The interface after defining diename1 can be seen in Figure 8 A schematic diagram of a die spec editing interface is shown.

[0065] Then, in the test spec interface, define the electrical scheme to be tested in each module. The editing interface after defining test1 (electrical scheme 1, referred to as t1) can be seen in Fig. 9 A schematic diagram of a test spec editing interface is shown in FIG. Fig. 9 As shown, the first column is the module name, xx is the specific content of the electrical solution that must be filled in, and the blank space is optional.

[0066] Finally, in the super test spec interface, according to the specific electrical test solution requirements, the above testspecs are summarized and merged and saved as different super test specs. The editing interface after defining super test spec1 can be seen in Fig.10 A schematic diagram of a super test spec editing interface is shown, where Select Die is an option to select Figure 7 Define different coordinate points named diename1 (all, none, or some can be selected). Fig.10 The SelectedDies in the table are multiple selected dies.

[0067] Different electrical test scheme attributes are summarized and defined as different super test specs and saved as specific files.

[0068] In the wafer definition module for each card lot, first load the file containing the super test spec, and then select the wafers to be inspected in each card lot in the wafer configuration interface. The wafer configuration interface can be seen in Fig.11 A schematic diagram of a wafer configuration interface is shown in FIG. Fig.11 As shown, by moving the wafer subscript defined in the left frame to the right frame, the wafer subscript defined in the right frame corresponds to the actual wafer subscript in each lot, so all wafers in each lot can be tested. Fig.11 Selected Wafers in the table are multiple wafers that have been selected. Fig.11 The Slot in is the position of the wafer.

[0069] Finally, after selecting the required test wafer and entering the electrical test scheme configuration interface, the test scheme file is automatically loaded to obtain all the different defined super test specs (such as defining 4 different super test specs). When the electrical test scheme configuration interface is opened, the same test scheme is defined for all wafers by default (the super test spec defined first by default). In this configuration interface, according to the test needs, manually select the specified Super Test Spec for the wafer to be tested in each card lot for subsequent testing.

[0070] Before performing wafer testing, the super test spec solution content selected for each wafer is loaded, and the wafer selected for each lot is tested according to the test process of different super test spec differentiated test modules to obtain differentiated electrical test parameter result data.

[0071] In summary, this embodiment can configure different wafers per lot and select different super test specs to perform differentiated testing, so that the electrical test parameter range covers a wider range, meets the customized test solution requirements of the FAB, shortens the time for wafer-level electrical testing of wafers, and thus improves the wafer shipment efficiency of the FAB.

[0072] Embodiment 4: Corresponding to the above method embodiment, the present invention provides a wafer differentiation test system, see Fig.12 The structure diagram of a wafer differentiation test system shown in FIG. 1 includes: The test scheme definition module 1201 is used to allocate the coordinate information of each die to be tested to at least one die set based on the test requirements of the same batch of wafers and the coordinate information of the die to be tested; set an electrical scheme for each die set to form a test set; and generate at least one test scheme set based on combining at least one die set and at least one test set corresponding to it; The wafer definition module 1202 is used to obtain wafers of the same batch of wafers and determine the test content of each wafer based on at least one test scheme set; The wafer differentiation test module 1203 is used to perform differentiation tests on wafers of the same batch based on the test contents.

[0073] An embodiment of the present invention provides a differentiated testing system for wafers. Based on the test requirements of wafers from the same batch and the coordinate information of the die to be tested, the coordinate information of each die to be tested is distributed to at least one die set; an electrical scheme is set for each die set to form at least one test set; at least one die set and its corresponding at least one test set are combined to generate at least one test scheme set; wafers from the same batch are obtained, and the test content of each wafer is determined based on at least one test scheme set; and differentiated testing is performed on wafers from the same batch based on the test content. In this way, differentiated testing at the wafer level and the die level can be achieved. The existing technology can only achieve the same test on wafers in the same batch, but cannot achieve differentiated testing of different wafers in the same batch and differentiated testing of different dies in a wafer. The technical solution sets multiple bare die sets containing die coordinate information according to test requirements (such as multiple electrical test schemes), and matches at least one test set to the bare die set, and forms multiple sets of test scheme sets by freely combining bare die sets. Because the bare die set only contains some coordinate points, by setting multiple bare die sets corresponding to test sets, a wafer can perform differentiated testing on different dies. At the same time, the set multiple sets of test scheme sets can be selected by different wafers, so that multiple wafers in the same batch can perform differentiated wafer-level electrical testing, meet the customized test scheme requirements of FAB, shorten the time for wafer-level electrical testing of wafers, and thus improve the wafer shipment efficiency of FAB.

[0074] The test scheme definition module includes a die set definition unit, an electrical scheme definition unit, and a test scheme definition unit; A die set definition unit is used to define die sets and test coordinate points of the die to be tested according to the test requirements of the same batch of wafers; wherein at least one die set includes at least one identical or different test coordinate point; and at least one test object is set for each die set; An electrical scheme definition unit, configured to generate at least one test set by combining at least one test object, and to set at least one electrical scheme for the test object; The test scheme definition unit is used to generate at least one test scheme set based on combining at least one bare die set and at least one test set corresponding thereto.

[0075] The test scheme definition module in this embodiment includes a die set definition unit, an electrical scheme definition unit, and a test scheme definition unit. The die set definition unit is used to define the die set and the test coordinate points of the die to be tested, the electrical scheme definition unit is used to define the electrical scheme, and the test scheme definition unit is used to generate at least one test scheme set.

[0076] The above-mentioned wafer definition module includes a test wafer determination unit and a test scheme determination unit; the test wafer determination unit is used to obtain wafers from the same batch of wafers, determine the wafers to be tested and set a unique identifier; the test scheme determination unit is used to obtain at least one test scheme set, bind the unique identifier with the required test scheme set, and determine the test content of the wafer to be tested.

[0077] The wafer definition module in this embodiment includes a test wafer determination unit and a test scheme determination unit. The test wafer determination unit is used to determine the wafer to be tested and set a unique identifier, and the test scheme determination unit is used to bind the unique identifier with the required test scheme set to determine the test content of the wafer to be tested.

[0078] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the wafer differentiation test system described above can refer to the corresponding process in the aforementioned embodiment of the wafer differentiation test method, and will not be repeated here.

[0079] Embodiment five: The embodiment of the present invention also provides an electronic device for running the above-mentioned wafer differentiation test method; see Fig.13 A structural schematic diagram of an electronic device is shown, which includes a memory 100 and a processor 101, wherein the memory 100 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 101 to implement the above-mentioned wafer differentiation testing method.

[0080] Further, Fig.13 The electronic device shown further includes a bus 102 and a communication interface 103 , and the processor 101 , the communication interface 103 and the memory 100 are connected via the bus 102 .

[0081] The memory 100 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 103 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 102 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.13 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0082] The processor 101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 101. The above processor 101 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module may be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 100, and the processor 101 reads the information in the memory 100 and completes the steps of the method of the above embodiment in combination with its hardware.

[0083] An embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned differentiated testing method for wafers. The specific implementation can be found in the method embodiment, which will not be repeated here.

[0084] The computer program product of the wafer differentiated testing method, system, electronic device and storage medium provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods in the previous method embodiments. The specific implementation can be found in the method embodiments, which will not be repeated here.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the above-described system and / or the specific working process of the system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0086] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0087] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0088] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the system or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0089] Finally, it should be noted that the above embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A wafer differentiation testing method, characterized in that: The method comprises: Based on the test requirements of wafers of the same batch and the coordinate information of the dies to be tested, the coordinate information of each die to be tested is allocated to at least one die set; an electrical scheme is set for each of the die sets to form at least one test set; Generate at least one test solution set based on combining the at least one die set and the at least one test set corresponding thereto; Obtain wafers from the same batch of wafers, determine the test content of each wafer based on the at least one test scheme set; and perform differentiated testing on the same batch of wafers based on the test content.

2. The method according to claim 1, characterized in that: Based on the test requirements of wafers in the same batch and the coordinate information of the bare die to be tested, the coordinate information of each bare die to be tested is allocated to at least one bare die set; Setting an electrical scheme for each of the die sets to form at least one test set includes: Defining at least one die set and test coordinate points of the die to be tested according to the test requirements of the same batch of wafers; wherein the at least one die set includes the same or different test coordinate points; At least one test object is set for each of the die sets; at least one test set is generated by combining the at least one test object, and at least one electrical scheme is set for the test object.

3. The method according to claim 2, characterized in that The combining based on the at least one die set and the at least one test set corresponding thereto comprises: At least one test set is classified and merged, and the coordinate information of the die set and the required test is matched for each test set to obtain at least one test scheme set, each test scheme set containing completely identical / partially identical / completely identical test sets, test objects and die sets.

4. The method according to claim 3, characterized in that: The combining based on the at least one die set and the at least one test set corresponding thereto further includes: When matching each test set to a die set, verify whether all test objects in the test set are located in at least one test object in the die set; If there is a test object that is not located in at least one test object of the die set, an error prompt is given.

5. The method according to claim 1, characterized in that The obtaining of wafers from the same batch of wafers and determining the test content of each wafer based on the at least one test scheme set includes: Selecting wafers to be tested from the same batch of wafers to obtain at least one test solution set; Configure a test solution set according to the test requirements of the wafer to be tested and determine the test content of each wafer.

6. The method according to claim 5, characterized in that The configuration of the test solution set according to the test requirements of the wafer to be tested includes: Load the test solution set and check whether the test content defined in the test solution set is accurate; If the test content defined by the test solution set is accurate, determine the test solution set for each wafer to be tested; if the test content defined by the test solution set is inaccurate, redefine the definition of the test solution set.

7. The method according to claim 5, characterized in that The performing differentiated testing on the wafers of the same batch based on the test content includes: Obtain the wafers to be tested and the set of test plans in the same batch of wafers; Traverse the wafers to be tested and obtain the required test solution set based on the information of the wafers currently to be tested; Conduct electrical testing on the wafer to be tested according to the test plan set.

8. A wafer differentiation test system, characterized in that: The system comprises: A test scheme definition module is used to allocate the coordinate information of each die to be tested to at least one die set based on the test requirements of the same batch of wafers and the coordinate information of the die to be tested; set an electrical scheme for each of the die sets to form a test set; and generate at least one test scheme set based on combining the at least one die set and the at least one test set corresponding to it; A wafer definition module, used for acquiring wafers of the same batch of wafers, and determining the test content of each wafer based on the at least one test scheme set; The wafer differentiation test module is used to perform differentiation test on the wafers of the same batch based on the test content.

9. The system according to claim 8, characterized in that The test scheme definition module includes a die set definition unit, an electrical scheme definition unit, and a test scheme definition unit; The die set definition unit is used to define the die set and the test coordinate points of the die to be tested according to the test requirements of the same batch of wafers; wherein the at least one die set includes at least one identical or different test coordinate point; and at least one test object is set for each of the die sets; The electrical scheme definition unit is used to generate at least one test set by combining the at least one test object, and set at least one electrical scheme for the test object; The test scheme definition unit is used to generate at least one test scheme set by combining the at least one bare die set and the at least one test set corresponding thereto.

10. The system according to claim 8, characterized in that The wafer definition module includes a test wafer determination unit and a test scheme determination unit; The test wafer determination unit is used to obtain wafers from the same batch of wafers, determine the wafers to be tested and set a unique identifier; The test scheme determination unit is used to obtain at least one test scheme set, bind the unique identifier with the required test scheme set, and determine the test content of the wafer to be tested.

11. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the memory stores computer executable instructions that can be executed by the processor, and the processor executes the computer executable instructions to implement the wafer differentiation testing method according to any one of claims 1 to 7.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the wafer differentiation testing method according to any one of claims 1 to 7.

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