A SQUID low-noise acquisition system and method based on flux offset correction technology

Abstract

The present invention relates to the field of geophysical exploration, and provides a SQUID low-noise acquisition system and method based on flux offset correction technology. The system includes a primary differential amplifier circuit, an offset correction circuit, a segmented acquisition circuit, and a data processing module. The offset correction circuit consists of a flux offset extraction circuit and a subtractor circuit. By extracting the flux offset of the input signal and performing subtraction operation on the original signal, real-time correction of the flux offset signal is achieved. Combining with the segmented acquisition circuit and data processing, a magnetic field response signal with a larger dynamic range is obtained. The present invention conditions the SQUID output signal based on the flux offset correction technology, solves the baseline drift problem generated during the operation of the SQUID, thereby meeting the segmented acquisition requirements, realizing high signal-to-noise ratio acquisition of weak magnetic field response signals, and further improving the dynamic range of the SQUID detection system.

Description

Technical Field

[0001] The present invention relates to the field of geophysical exploration, and particularly to a SQUID low-noise acquisition system and method based on flux offset correction technology. Background Art

[0002] A superconducting quantum interference device (SQUID) is a high-precision quantum precision measurement sensor. Compared with an induction coil or a magnetic rod for measuring magnetic field signals conventionally, a SQUID can directly measure B-field information, and has a larger sensor bandwidth, lower noise, and can receive weaker magnetic field signals, which has more advantages for the exploration of deep metal resources.

[0003] Since the 1970s, scholars at home and abroad have successively applied SQUIDs to detection methods such as magnetic methods and transient electromagnetic methods. How to give full play to the advantages of the extremely high sensitivity of SQUIDs has also become an urgent problem to be solved in SQUID acquisition systems. Currently, the dynamic range of existing SQUID acquisition systems is generally below 120 dB, and the noise level is relatively high. At the same time, since the SQUID readout circuit adopts a flux modulation method based on a transformer, the dynamic characteristics are poor, and a baseline drift phenomenon will occur during operation, resulting in a limited amplification factor of the input signal, thereby affecting the signal quality of the acquisition system. Therefore, how to suppress the baseline drift of SQUID signals and further improve the acquisition accuracy of SQUID systems is an urgent problem to be solved currently.

[0004] Currently, there are magnetic field measurement systems or measurement methods with a large dynamic range disclosed in the prior art to achieve magnetic field measurement with a large dynamic range; there are also electromagnetic measurement devices that switch the amplification factor through a zero-crossing comparator and a programmable amplifier to improve the dynamic range of the signals acquired by the measurement device and reduce the influence of noise on the received signals. However, the prior art does not address the problem of baseline drift that will occur during the operation of SQUIDs.

[0005] In summary, current research on SQUID acquisition systems mainly improves the dynamic range of the acquisition system through methods such as polarity transformation and segmented amplification. However, how to solve the problem of baseline drift generated during the operation of SQUIDs is still an urgent technical problem to be solved. Summary of the Invention

[0006] In order to solve the above technical problems, the present invention provides a SQUID low-noise acquisition system based on flux offset correction technology, including a primary differential amplification circuit, an offset correction circuit, a segmented acquisition circuit, and a data processing module.

[0007] The input end of the described primary differential amplifier circuit is connected to the output end of a superconducting quantum interference device (SQUID) readout circuit. The output end of the primary differential amplifier circuit is divided into two paths. One path is connected to the filter circuit in the segmented acquisition circuit, and the other path is connected to the offset correction circuit. The primary differential amplifier circuit performs differential amplification with a fixed gain on the SQUID signal.

[0008] The described offset correction circuit includes a flux offset extraction circuit and a subtractor circuit; to adapt to the dynamic change characteristics of the flux offset amount in the SQUID signal, the flux offset extraction circuit includes two sets of fifth-order Butterworth low-pass filter circuits with the same structure, arranged in a differential input form. The input end of the fifth-order Butterworth low-pass filter circuit is connected to the output end of the primary differential amplifier circuit; the subtractor circuit includes a low-offset operational amplifier, whose non-inverting input end is connected to the output end of the primary differential amplifier circuit, and the inverting input end is connected to the output end of the fifth-order Butterworth low-pass filter circuit; the offset correction circuit realizes the function of flux offset correction for the input signal through subtraction operation; the output end of the offset correction circuit is divided into two paths. One path directly connects to the filter circuit in the segmented acquisition circuit for early signals, and the other path connects to the secondary amplifier circuit in the segmented acquisition circuit for late signals.

[0009] Preferably, the fifth-order Butterworth low-pass filter circuit is composed of two second-order Sallen-key filters connected in series with an active RC filter in sequence to provide a fast step response and stopband roll-off rate, thereby realizing the real-time correction function for the flux offset signal; the cut-off frequency calculation formulas for the flux offset extraction circuit are respectively: , , where f c1 , f c2 are the cut-off frequencies of the second-order Sallen-key filter and the active RC filter respectively, R1 and R2 are the resistors of the second-order Sallen-key filter, C1 and C2 are the capacitors of the second-order Sallen-key filter, and R and C are the resistor and capacitor of the active RC filter respectively.

[0010] Furthermore, by changing the resistance and capacitance values, the cut-off frequency is set to 1 Hz to realize the extraction of the DC offset amount of the input signal.

[0011] The described segmented acquisition circuit includes a secondary amplifier circuit, a filter circuit, and an AD acquisition circuit. The secondary amplifier circuit, the filter circuit, and the AD acquisition circuit are connected in sequence. The AD acquisition circuit synchronously acquires the SQUID original reference signal, the SQUID early signal, and the SQUID late signal output by the filter circuit.

[0012] The data processing module includes an FPGA control unit, a data reception and normalization module, and a data integration and preprocessing module. The FPGA control unit, the data reception and normalization module, and the data integration and preprocessing module are connected in sequence. The FPGA control unit is connected to the output end of the AD acquisition circuit to realize the logical control of the AD acquisition circuit and the transmission of data. The data reception and normalization module realizes the reception, decoding, and normalization processing of data. The data integration and preprocessing module integrates the normalized data and compares it with the original reference signal data to verify the feasibility and effectiveness of the flux offset correction technology, and realizes the preprocessing of data by extracting the secondary field attenuation curve.

[0013] The present invention also provides an SQUID low-noise acquisition method based on the flux offset correction technology. Using the SQUID low-noise acquisition system provided above, the signal processing flow is as follows:

[0014] Step 1: The SQUID signal is input into the primary differential amplification circuit in a differential form. By adjusting the resistance ratio between the input end and the output feedback end of the primary differential amplification circuit, the input differential signal is amplified with an appropriate gain.

[0015] Step 2: The output signal of the primary differential amplification circuit is divided into two paths. One path is input into the filter circuit in the segmented acquisition circuit as the original reference signal, and the other path is input into the offset correction circuit for processing.

[0016] Step 3: The offset correction circuit first extracts the flux offset amount of the input signal, and then performs a subtraction operation on the input signal and the flux offset amount through a subtractor circuit to realize the flux offset correction function of the input signal.

[0017] Step 4: The output signal of the offset correction circuit is divided into two paths. One path directly enters the filter circuit in the segmented acquisition circuit for the early signal, and the other path first undergoes secondary amplification through a secondary amplification circuit for the late signal and then enters the filter circuit.

[0018] Step 5: The filter circuit filters out the high-frequency noise in the three groups of input signals through a low-pass filter and inputs the optimized signal into the AD acquisition circuit.

[0019] Step 6: The AD acquisition circuit is set to a three-channel acquisition mode to synchronously acquire three groups of signals at different stages, namely the SQUID original reference signal, the SQUID early signal, and the SQUID late signal output by the filter circuit, and transmits the acquired data to the upper computer for data processing through the FPGA control unit in the data processing module.

[0020] Step 7: After the host computer receives the data, it first normalizes the data through the data reception and normalization module, then compares the integrated data with the original reference signal data through the data integration and preprocessing module to verify the feasibility and effectiveness of the flux offset correction technology, and finally preprocesses the data through the extraction of the secondary field attenuation curve.

[0021] Advantages of the present invention:

[0022] A SQUID low-noise acquisition system and method based on the flux offset correction technology provided by the present invention. The offset correction circuit is composed of a flux offset extraction circuit and a subtractor circuit. By extracting the flux offset amount of the input signal and performing a subtraction operation on the original signal, real-time correction of the flux offset signal is achieved. Combining the segmented acquisition circuit and data processing to obtain a time-domain electromagnetic response signal with a larger dynamic range. The present invention conditions the SQUID output signal based on the flux offset correction technology, solves the baseline drift problem generated during the operation of the SQUID, thereby meeting the segmented acquisition requirements, achieving high signal-to-noise ratio acquisition of weak magnetic field response signals, and further improving the dynamic range of the SQUID detection system. Description of the drawings

[0023] Figure 1 It is a schematic structural diagram of the SQUID low-noise acquisition system based on the flux offset correction technology of the present invention.

[0024] Figure 2 It is a schematic structural diagram of the primary differential amplification circuit of the present invention.

[0025] Figure 3 It is a schematic structural diagram of the offset correction circuit of the present invention.

[0026] Figure 4 It is a schematic structural diagram of the secondary amplification circuit in the segmented acquisition circuit of the present invention.

[0027] Figure 5 It is a schematic structural diagram of the filter circuit in the segmented acquisition circuit of the present invention.

[0028] Figure 6 It is a schematic structural diagram of the AD acquisition circuit in the segmented acquisition circuit of the present invention.

[0029] Figure 7 It is a schematic diagram of the flux offset correction result of the embodiment of the present invention.

[0030] 1. Primary differential amplifier circuit, 2. Offset correction circuit, 3. Segmented acquisition circuit, 4. Data processing module, 5. Flux offset extraction circuit, 6. Subtractor circuit, 7. Secondary amplifier circuit, 8. Filter circuit, 9. AD acquisition circuit, 10. FPGA control unit, 11. Data reception and normalization module, 12. Data integration and preprocessing module, 13. SQUID signal, 14. Original reference signal, 15. Early signal, 16. Late signal. Detailed implementation

[0031] Embodiment 1

[0032] This embodiment provides a SQUID low-noise acquisition system based on flux offset correction technology, as Figure 1 shown: It includes a primary differential amplifier circuit 1, an offset correction circuit 2, a segmented acquisition circuit 3 and a data processing module 4.

[0033] As Figure 2 shown: The primary differential amplifier circuit 1 includes LT6203 ultra-low noise dual operational amplifiers U1A and U1B, resistors R1 - R4, where R1 = R3 and R2 = R4; the non-inverting input terminal of amplifier U1A is grounded, the inverting input terminal is connected to R1, and the inverting output feedback terminal is connected to R2 to form an inverting amplifier; the non-inverting input terminal of amplifier U1B is grounded, the inverting input terminal is connected to R3, and the inverting output feedback terminal is connected to R4 to form an inverting amplifier; the input terminal of the primary differential amplifier circuit 1 is connected to the output terminal of the superconducting quantum interference device (SQUID) readout circuit, the positive input of the input signal is connected to the R1 terminal, and the negative input is connected to the R3 terminal. According to actual needs, the gain of the primary differential amplifier circuit 1 can be changed by adjusting the resistance values of R1 - R4. The calculation formula is: , where G represents the gain, and R1 - R4 represent the resistance values of the corresponding numbers respectively. One output of the primary differential amplifier circuit 1 is connected to the filter circuit 8 in the segmented acquisition circuit 3, and the other output is connected to the offset correction circuit 2. The primary differential amplifier circuit 1 performs differential amplification with a fixed gain on the SQUID signal.

[0034] The offset correction circuit 2 includes a flux offset extraction circuit 5 and a subtractor circuit 6; as Figure 3As shown in the figure: To adapt to the dynamic change characteristics of the flux offset in the SQUID signal, the flux offset extraction circuit 5 is set in a differential input form and consists of two sets of fifth-order Butterworth low-pass filter circuits with the same structure. The fifth-order Butterworth low-pass filter circuit is composed of two second-order Sallen-key filters and an active RC filter connected in sequence. The input end of the second-order Sallen-key filter is connected to the output end of the primary differential amplifier circuit 1 to provide a fast step response and a stopband roll-off rate, thereby realizing the real-time correction function of the flux offset signal.

[0035] One set of the fifth-order Butterworth low-pass filter circuit includes LT1007 high-speed operational amplifiers U3 - U5, resistors R5 - R9, and capacitors C1 - C11. The other set of the fifth-order Butterworth low-pass filter circuit includes LT1007 high-speed operational amplifiers U6 - U8, resistors R10 - R14, and capacitors C12 - C22. First, after the SQUID signal is differentially amplified, it passes through resistors R5 and R6 and enters the non-inverting input terminal of amplifier U3. One end of capacitor C1 is connected to resistors R5 and R6, and the other end enters the non-inverting output feedback terminal of amplifier U3. One end of capacitor C2 is connected to the non-inverting input terminal of amplifier U3, and the other end is grounded. Capacitors C3 and C4 are respectively connected to the positive and negative power supplies as bypass capacitors to filter out high-frequency noise. The circuit structures of amplifiers U4, U6, and U7 and their surrounding resistors and capacitors are the same as above; the circuit structures of amplifiers U3 and U4 and their surrounding resistors and capacitors respectively form two second-order Sallen-key filters connected in sequence, and the circuit structures of amplifiers U6 and U7 and their surrounding resistors and capacitors respectively form two second-order Sallen-key filters connected in sequence. Secondly, after the signal is output from the output terminal of amplifier U4, it passes through resistor R9 and enters the non-inverting input terminal of amplifier U5. One end of capacitor C9 is connected to the non-inverting input terminal of amplifier U5, and the other end is grounded. Capacitors C10 and C11 are respectively connected to the positive and negative power supplies as bypass capacitors to filter out high-frequency noise. The circuit structure of amplifier U8 and its surrounding resistors and capacitors is the same as that of amplifier U5 above. The circuit structures of amplifiers U5 and U8 and their surrounding resistors and capacitors respectively form active RC filters.

[0036] The cut-off frequency calculation formula of the flux offset extraction circuit 5 is: , ,where f c1 、f c2are the cut-off frequencies of the Sallen-key filter and the active RC filter respectively, Ri and Rj are the resistors of the corresponding second-order Sallen-key filter respectively, Cm and Cn are the capacitors of the corresponding second-order Sallen-key filter respectively, and Rx and Cy are the resistors and capacitors of the corresponding active RC filter respectively. For example, the calculation formulas for the cut-off frequencies of the first second-order Sallen-key filter and the active RC filter are respectively: , , where f c1 、f c2 are the cut-off frequencies of the second-order Sallen-key filter and the active RC filter respectively, and R5, R6, C1, C2 and R9, C9 are the resistors and capacitors of the corresponding circuits respectively. By changing the resistor and capacitor values, the cut-off frequency is set to 1 Hz to extract the DC offset of the input signal.

[0037] The subtractor circuit 6 includes OP07 low-offset operational amplifiers U9, U10, resistors R15-R22 and capacitors C23-C26. Among them, the non-inverting input terminal of amplifier U9 is connected to the output terminal of the primary differential amplification circuit 1 through resistor R15, the inverting input terminal of amplifier U9 is connected to the output terminal of the fifth-order Butterworth low-pass filter circuit through resistor R16, one end of resistor R17 is connected to the non-inverting input terminal of amplifier U9, and the other end is grounded. Resistor R18 is connected to the inverting output feedback terminal of amplifier U9. Capacitors C23 and C24 are respectively connected to the positive and negative power supplies as bypass capacitors, thus constituting one part of the subtractor circuit 6; the other part is composed of amplifier U10 and its surrounding resistors R19-R22, capacitors C25-C26 with the same circuit structure as above; the offset correction circuit 2 realizes the function of flux offset correction for the SQUID signal by subtracting two signals; the voltage calculation formula of one part of the subtractor circuit 6 is: , where R15 = R16, R17 = R18, U i 、U j are the input signals of the non-inverting input terminal and the inverting input terminal of this circuit respectively, and U O is the output signal of this circuit.

[0038] The output terminal of the offset correction circuit 2 is divided into two paths. One path is directly connected to the filter circuit 8 in the segmented acquisition circuit 3 for the early signal, and the other path is connected to the secondary amplification circuit 7 in the segmented acquisition circuit 3 for the late signal.

[0039] The described segmented acquisition circuit 3 includes a secondary amplification circuit 7, a filter circuit 8 and an AD acquisition circuit 9, and the secondary amplification circuit 7, the filter circuit 8 and the AD acquisition circuit 9 are connected in sequence. As Figure 4As shown in the figure: The secondary amplification circuit 7 includes an AD8139 differential amplifier U11 and resistors R23 - R27, where R23 = R25, R24 = R26. R23 and R24 are respectively connected to the non-inverting input terminal and the output feedback terminal of the amplifier U11. R25 and R26 are respectively connected to the inverting input terminal and the output feedback terminal of the amplifier U11. Both ends of R27 are respectively connected to the non-inverting output terminal and the inverting output terminal of the amplifier U11. This circuit realizes high signal-to-noise ratio acquisition of SQUID signals by amplifying weak signals in the late stage. Its voltage calculation formula is: , where V OP , V ON respectively represent the voltages of the non-inverting output terminal and the inverting output terminal, V IP , V IN respectively represent the voltages of the non-inverting input terminal and the inverting input terminal, R F , R G respectively represent the resistance values of the output feedback terminal and the input terminal resistors.

[0040] As Figure 5 shown in the figure: The filtering circuit 8 includes LTC1563 active low-pass filters U12 - U14 and peripheral circuits (which are prior art and the structure will not be described here in detail. Figure 5 The filtering circuit shown in the figure is one group of LTC1563 active low-pass filters and peripheral circuits, and the other two groups have the same structure). This circuit filters out high-frequency noise in three groups of different input signals through low-pass filtering, thereby improving the signal quality of the input signals, and passing the optimized output signals into the AD acquisition circuit 9. The cut-off frequency calculation formula of the filtering circuit 8 is: , where f c is the cut-off frequency of the filtering circuit 8, and R is the resistance value.

[0041] As Figure 6 shown in the figure: The AD acquisition circuit 9 is in a three-channel acquisition mode, and acquires three groups of signals at different stages output by the filtering circuit 8. This circuit includes three groups of ADC drive circuits and analog-to-digital conversion circuits with the same structure. The ADC drive circuit is composed of an ADA4945 fully differential driver and its peripheral circuits (which are prior art and the structure will not be described here in detail), and is used to adjust the amplitude of the input signal to meet the signal input requirements of the analog-to-digital converter. The analog-to-digital conversion circuit is composed of an LTC2380 - 24 analog-to-digital converter and its peripheral circuits (which are prior art and the structure will not be described here in detail), and is used to convert the input analog signal into a digital signal. The AD acquisition circuit 9 synchronously acquires the SQUID original reference signal, the SQUID early signal, and the SQUID late signal output by the filtering circuit 8, thereby realizing full-waveform high-precision acquisition of SQUID signals, and at the same time transmitting the acquired data to the data processing module 4 for subsequent data processing.

[0042] The data processing module 4 includes an FPGA control unit 10, a data receiving and normalization module 11, and a data integration and preprocessing module 12. The FPGA control unit 10, the data receiving and normalization module 11, and the data integration and preprocessing module 12 are connected in sequence. The FPGA control unit 10 is composed of a programmable logic device EP4CE10F17 and its peripheral circuits (which are prior art and the structure will not be described here), and is connected to the output end of the AD acquisition circuit 9 to realize the logical control of the AD acquisition circuit 9 and the transmission of data. The data receiving and normalization module 11 uses Labview software as a platform to realize the reception, decoding, and normalization processing of data through upper computer design (which is prior art and the structure will not be described here). The data integration and preprocessing module 12 integrates the normalized data and compares it with the original reference signal data to verify the feasibility and effectiveness of the flux offset correction technology, and realizes the preprocessing of data by extracting the secondary field attenuation curve.

[0043] Example 2

[0044] This embodiment provides an SQUID low-noise acquisition method based on the flux offset correction technology. An SQUID low-noise acquisition system based on the flux offset correction technology provided in Example 1 is adopted, and the signal processing flow is as follows:

[0045] Step 1: The SQUID signal 13 is input into the primary differential amplifier circuit 1 in a differential form. By adjusting the resistance ratio between the input end and the output feedback end of the primary differential amplifier circuit 1, the input differential signal is amplified with an appropriate gain.

[0046] Step 2: The output signal of the primary differential amplifier circuit 1 is divided into two paths. One path is input into the filter circuit 8 in the segmented acquisition circuit 3 as the original reference signal 14, and the other path is input into the offset correction circuit 2 for processing.

[0047] Step 3: The offset correction circuit 2 first extracts the flux offset amount of the input signal through the flux offset extraction circuit 5, and then performs a subtraction operation on the input SQUID signal and the flux offset amount through the subtractor circuit 6 to realize the flux offset correction function of the input signal.

[0048] Step 4: The output signal of the offset correction circuit 2 is divided into two paths. One path directly inputs the early signal 15 into the filter circuit 8 in the segmented acquisition circuit 3, and the other path first performs secondary amplification on the late signal 16 through the secondary amplifier circuit 7 and then inputs it into the filter circuit 8.

[0049] Step 5: The filter circuit 8 filters out the high-frequency noise in the three groups of input signals, namely the original reference signal 14, the early signal 15, and the late signal 16 output by the secondary amplification circuit 7, through a low-pass filter, and inputs the optimized signal into the AD acquisition circuit 9.

[0050] Step 6: The AD acquisition circuit 9 is set to a three-channel acquisition mode to synchronously acquire the signals at three different stages, namely the SQUID original reference signal, the SQUID early signal, and the SQUID late signal output by the filter circuit 8, and transmits the acquired data to the upper computer for data processing through the FPGA control unit 10 in the data processing module 4.

[0051] Step 7: After receiving the data, the upper computer first normalizes the data through the data reception and normalization module 11, then compares the integrated data with the original reference signal data through the data integration and preprocessing module 12 to verify the feasibility and effectiveness of the flux offset correction technology, and finally preprocesses the data by extracting the secondary field attenuation curve.

[0052] The flux offset correction result of this embodiment is as Figure 7 shown.

[0053] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A SQUID low-noise acquisition system based on flux offset correction technology, characterized in that: It includes a primary differential amplifier circuit, an offset correction circuit, a segmented acquisition circuit and a data processing module; The input end of the primary differential amplifier circuit is connected to the output end of the superconducting quantum interference device readout circuit, and the output end of the primary differential amplifier circuit is divided into two paths, one path is connected to the filter circuit in the segmented acquisition circuit, and the other path is connected to the offset correction circuit; The offset correction circuit includes a magnetic flux offset extraction circuit and a subtractor circuit; the magnetic flux offset extraction circuit includes two groups of fifth-order Butterworth low-pass filter circuits with the same structure, which are set to a differential input form, and the input end of the fifth-order Butterworth low-pass filter circuit is connected to the output end of the primary differential amplifier circuit; the subtractor circuit includes a low-offset operational amplifier, whose non-inverting input end is connected to the output end of the primary differential amplifier circuit, and whose inverting input end is connected to the output end of the fifth-order Butterworth low-pass filter circuit; the output end of the offset correction circuit is divided into two paths, one path is directly connected to the filter circuit in the segmented acquisition circuit for early signals, and the other path is connected to the secondary amplifier circuit in the segmented acquisition circuit for late signals; The segmented acquisition circuit includes a secondary amplifier circuit, a filter circuit and an AD acquisition circuit, which are connected in sequence, and the AD acquisition circuit synchronously acquires the SQUID original reference signal, the SQUID early signal and the SQUID late signal output by the filter circuit; The data processing module includes an FPGA control unit, a data receiving and normalization module, and a data integration and preprocessing module. The FPGA control unit, the data receiving and normalization module, and the data integration and preprocessing module are connected in sequence. The FPGA control unit is connected to the output end of the AD acquisition circuit. The data receiving and normalization module realizes the reception, decoding and normalization processing of data. The data integration and preprocessing module realizes the integration of the normalized data and compares it with the original reference signal data, and realizes the preprocessing of the data by extracting the secondary field attenuation curve.

2. The SQUID low-noise acquisition system based on flux offset correction technology according to claim 1, characterized in that: The fifth-order Butterworth low-pass filter circuit is two second-order Sallen-key filters and an active RC filter connected in sequence. The cutoff frequency calculation formulas of the magnetic flux offset extraction circuit are: , , where f c1 、f c2 are the cut-off frequencies of the second-order Sallen-key filter and the active RC filter, respectively. R1 and R2 are the resistances of the second-order Sallen-key filter, C1 and C2 are the capacitances of the second-order Sallen-key filter, and R and C are the resistance and capacitance of the active RC filter, respectively.

3. The SQUID low noise acquisition system based on flux offset correction technology according to claim 2, characterized in that: By changing the resistor and capacitor values, the cutoff frequency is set to 1 Hz to extract the DC offset of the input signal.

4. A SQUID low-noise acquisition method based on flux offset correction technology, characterized in that: The SQUID low-noise acquisition system based on the flux offset correction technology described in any one of claims 1 to 3 is adopted, and the signal processing process is as follows: Step 1, the SQUID signal is input into the primary differential amplifier circuit in a differential form, and the input differential signal is amplified with an appropriate gain by adjusting the resistance ratio between the input end and the output feedback end of the primary differential amplifier circuit; Step 2, the output signal of the primary differential amplifier circuit is divided into two paths, one path is passed to the filter circuit in the segmented acquisition circuit as the original reference signal, and the other path is passed to the offset correction circuit for processing; Step 3: The offset correction circuit first extracts the magnetic flux offset of the input signal, and then performs a subtraction operation on the input signal and the magnetic flux offset through a subtractor circuit to realize the magnetic flux offset correction function of the input signal; Step 4, the output signal of the offset correction circuit is divided into two paths, one path is for early signals and directly passes into the filter circuit in the segmented acquisition circuit, and the other path is for late signals and first passes through the secondary amplifier circuit for secondary amplification and then passes into the filter circuit; Step 5: The filtering circuit removes high-frequency noise in the three groups of input signals through a low-pass filter, and passes the optimized signals into the AD acquisition circuit; Step 6, the AD acquisition circuit is set to a three-channel acquisition mode, and the three groups of signals at different stages, namely, the SQUID original reference signal, the SQUID early signal and the SQUID late signal output by the filter circuit, are synchronously acquired, and the acquired data are transmitted to the host computer through the FPGA control unit in the data processing module for data processing; Step 7. After the host computer receives the data, it first normalizes the data through the data receiving and normalization module, and then compares the integrated data with the original reference signal data through the data integration and preprocessing module to verify the feasibility and effectiveness of the flux offset correction technology. Finally, the data is preprocessed by extracting the secondary field attenuation curve.

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