Underwater sound signal processing platform

Abstract

The invention belongs to the technical field of underwater acoustic signal processing, and particularly relates to an underwater acoustic signal processing platform, which comprises a bottom plate, a core plate, an AD acquisition plate, a beam forming plate and an expansion function plate, and is characterized in that the bottom plate is used for providing a signal path between the core plate and the AD acquisition plate, the beam forming plate and the expansion function plate and providing 12V isolation power supply. According to the invention, a high-performance underwater acoustic signal processing platform is established based on a DSP + FPGA architecture, and the functions of underwater acoustic signal acquisition, filtering, signal digitization, digital beam forming and the like are realized.

Description

Technical Field

[0001] The invention belongs to the technical field of underwater acoustic signal processing, and in particular relates to an underwater acoustic signal processing platform. Background Art

[0002] With the development of sonar technology, higher and higher requirements are put forward for the signal processing capability of sonar signal processing systems. Traditional active sonar signal processing systems mostly use dedicated hardware structures to complete specific data processing tasks, that is, the back end of the transducer is directly connected to the data conversion collector, and the collected data is sent to the digital signal processor for processing after analog-to-digital conversion. Due to the large amount of system data calculation and the need for real-time processing, the processor performance requirements are very high. A single processor (such as FPGA or DSP) cannot meet the needs of high-speed real-time signal processing. Multi-core DSP has powerful processing performance, but weak parallelism, and it is difficult to adapt to extremely intensive computing applications. In addition, the integrated DSP interface also affects the flexibility of data transmission; FPGA has extremely strong parallelism and is suitable for intensive computing applications. In addition, the configurable I / O and IP core support a variety of data transmission interfaces, but the internal logic resources and storage resources of FPGA are limited, and the development is difficult, and it is also difficult to implement complex algorithms. Therefore, combining the advantages of multi-core DSP and FPGA, building a signal processing system based on heterogeneous processors has become a current development trend.

[0003] To this end, we propose an underwater acoustic signal processing platform to solve the above problems. Summary of the invention

[0004] The purpose of the present invention is to provide an underwater acoustic signal processing platform in view of the above problems.

[0005] To achieve the above object, the present invention provides the following technical solutions: an underwater acoustic signal processing platform, comprising a baseboard, a core board, an AD acquisition board, a beamforming board, and an expansion function board; The baseboard is used to provide a signal path between the core board and the AD acquisition board, beamforming board, and expansion function board, and provides 12V isolated power supply; The core board is based on DSP+FPGA architecture and includes: The digital signal processing module is used to perform demodulation, sampling and digital filtering on the collected digital signals to determine the target distance, direction, speed, heading and other motion elements. The module is connected to the external Gigabit network to send the processed data to the host computer and receive the control commands issued by the host computer to control the transmitting and receiving circuits and the beamforming process. A power supply module, whose input end is connected to a 27V±2.7V DC power supply, provides the required power supply voltage for each module of the system through multiple isolation modules, and the power supply module is set away from the data acquisition and conditioning module; A data storage module includes four DDR3 memory chips and one NORFLASH connected to the DSP chip port. Each of the four DDR3 memory chips has a capacity of 512M bytes and forms a 64-bit data bandwidth. The capacity of NORFLASH is 64Mb and is used to store configuration files of the DSP chip or other user data. The communication module enables DSP to communicate with the host computer through Ethernet and serial port, and FPGA to communicate with the outside by controlling CAN and serial port, and the peripheral expansion has PCIe and 1553B interfaces; Interface module and connector, wherein the interface connecting the signal processing part and the FPGA is led out by the connector; AD acquisition board, used to condition and collect the electrical signals converted by the reflected sound wave signals through the receiving sound array, and transmit the collected signals to the digital signal processing module of the core board; The beamforming board is used to receive the beamforming data from the core board, perform digital-to-analog conversion on it to form a beam, and send it to the transmitter for subsequent processing.

[0006] In the above-mentioned underwater acoustic signal processing platform, the AD acquisition board uses 3 AD7656 chips to form the AD part, which is used to synchronously acquire 16 analog quantities with a sampling frequency of 250kSPS. The analog quantities that do not need to be synchronously acquired are switched through an external multi-way switch. The entire circuit controls the timing through FPGA. The AD7656 chip uses a parallel interface to connect to the external circuit. The operational amplifier selected for its front-end drive circuit has a speed of 550ns and a signal-to-noise ratio of less than 85db. The front-end drive circuit also includes an RC filter circuit for signal filtering and eliminating sampling jitter.

[0007] In the above-mentioned underwater acoustic signal processing platform, a DDS signal generator is also included, which adopts direct digital frequency synthesis technology, including: The waveform adjustment module adjusts the four output waveforms by changing the signal according to the waveform control sent by the DSP through a 4-to-1 data selector; Amplitude adjustment module, which uses a multiplier to multiply the waveform output by the amplification factor to achieve amplitude adjustment, with the maximum gain being 15 times; Phase adjustment module, which realizes phase adjustment in integer multiples of 15° according to the formula P=511N / 360, where N is the phase shift degree; The frequency adjustment module realizes frequency adjustment by changing the interval of ROM data sampling and follows the Nyquist sampling theorem.

[0008] In the above-mentioned underwater acoustic signal processing platform, the digital signal processing module adopts a multi-level parallel processing method when processing signals, including: The first level uses a time-slice-based inter-core pipeline design to control the eight cores to take turns accessing the task data in DDR3, and evenly distribute the task data to the eight C66x cores. Each core further divides the task data into smaller ones, so that each task data transmission only occupies a small time slice; The second level adopts a parallel design of memory data transfer and CPU based on ping-pong storage. Each core opens a ping-pong buffer area in LL2S. EDMA transfers data from MSMS to the ping buffer of LL2S, and then transfers it to the pong buffer in the background. The CPU processes the data in the ping or pong buffer area during the data transmission process. The third level adopts assembly instruction pipeline design to realize the mutual driving of multi-cycle instructions and fully tap the CPU computing power.

[0009] Compared with the prior art, the present invention provides an underwater acoustic signal processing platform, which has the following beneficial effects: 1. This underwater acoustic signal processing platform integrates the advantages of DSP and FPGA. The DSP multi-core parallel processing is combined with FPGA high-speed acquisition and preprocessing, which greatly improves the processing speed and efficiency. In the detection of multiple targets in complex marine environments, it accurately analyzes signal characteristics to achieve efficient target identification and positioning, providing strong technical support for underwater operations and marine monitoring.

[0010] 2. The underwater acoustic signal processing platform has a modular design that integrates multi-functional boards. The baseboard has unified power supply and signal transmission. The core board integrates multiple modules, and can flexibly increase or decrease processing nodes according to demand. It can upgrade marine scientific research equipment and conveniently expand the number of channels from 16 to 32. It is suitable for transducer arrays of different sizes, reducing costs, improving equipment versatility and system integration, and accelerating R&D deployment.

[0011] 3. The underwater acoustic signal processing platform uses high-precision AD acquisition circuits and optimized DDS control to coordinate, with 16 analog channels and 250kSPS synchronous sampling to ensure signal integrity. DDS multi-parameter precise modulation optimizes the waveform. In shallow water high-precision mapping scenarios, it can draw ultra-clear seabed topography maps to assist in the development and management of marine resources.

[0012] 4. The underwater acoustic signal processing platform has isolated power supply modules, reasonable electrical layout, and multi-core processing optimization strategy to ensure system stability. For long-term deep-sea monitoring tasks, it has stable power supply, strong anti-interference, and excellent multi-core collaboration, ensuring that the system continues to accurately collect and process signals and protect the safe operation of marine facilities.

[0013] In summary: the present invention uses DSP+FPGA architecture to establish a high-performance underwater acoustic signal processing platform to achieve functions such as underwater acoustic signal acquisition, filtering, signal digitization and digital beamforming. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The overall hardware design framework of an underwater acoustic signal processing platform proposed by the present invention; Figure 2 This is a block diagram of a data acquisition circuit for an underwater acoustic signal processing platform proposed in the present invention. DETAILED DESCRIPTION

[0015] The following examples are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0016] See also Figure 1-2 , an underwater acoustic signal processing platform, including a baseboard, a core board, an AD acquisition board, a beamforming board, and an expansion function board; The baseboard is used to provide a signal path between the core board and the AD acquisition board, beamforming board, and expansion function board, and provides 12V isolated power supply; The core board is based on DSP+FPGA architecture and includes: The digital signal processing module is used to perform demodulation, sampling and digital filtering on the collected digital signals to determine the target distance, direction, speed, heading and other motion elements. The module is connected to the external Gigabit network to send the processed data to the host computer and receive the control commands issued by the host computer to control the transmitting and receiving circuits and the beamforming process. A power supply module, whose input end is connected to a 27V±2.7V DC power supply, provides the required power supply voltage for each module of the system through multiple isolation modules, and the power supply module is set away from the data acquisition and conditioning module; A data storage module includes four DDR3 memory chips and one NORFLASH connected to the DSP chip port. Each of the four DDR3 memory chips has a capacity of 512M bytes and forms a 64-bit data bandwidth. The capacity of NORFLASH is 64Mb and is used to store configuration files of the DSP chip or other user data. The communication module enables DSP to communicate with the host computer through Ethernet and serial port, and FPGA to communicate with the outside by controlling CAN and serial port, and the peripheral expansion has PCIe and 1553B interfaces; Interface module and connector, wherein the interface connecting the signal processing part and the FPGA is led out by the connector; AD acquisition board, used to condition and collect the electrical signals converted by the reflected sound wave signals through the receiving sound array, and transmit the collected signals to the digital signal processing module of the core board; The beamforming board is used to receive the beamforming data from the core board, perform digital-to-analog conversion on it to form a beam, and send it to the transmitter for subsequent processing.

[0017] The AD acquisition board uses three AD7656 chips to form the AD part, which is used to synchronously acquire 16 analog quantities with a sampling frequency of 250kSPS. The analog quantities that do not need to be synchronously acquired are switched through an external multi-way switch. The entire circuit controls the timing through FPGA. The AD7656 chip uses a parallel interface to connect to the external circuit. The operational amplifier selected for its front-end drive circuit has a speed of 550ns and a signal-to-noise ratio of less than 85db. The front-end drive circuit also includes an RC filter circuit for signal filtering and eliminating sampling jitter.

[0018] Also included is a DDS signal generator, which uses direct digital frequency synthesis technology, including: The waveform adjustment module adjusts the four output waveforms by changing the signal according to the waveform control sent by the DSP through a 4-to-1 data selector; Amplitude adjustment module, which uses a multiplier to multiply the waveform output by the amplification factor to achieve amplitude adjustment, with the maximum gain being 15 times; Phase adjustment module, which realizes phase adjustment in integer multiples of 15° according to the formula P=511N / 360, where N is the phase shift degree; The frequency adjustment module realizes frequency adjustment by changing the interval of ROM data sampling and follows the Nyquist sampling theorem.

[0019] The digital signal processing module adopts a multi-level parallel processing method when processing signals, including: The first level uses a time-slice-based inter-core pipeline design to control the eight cores to take turns accessing the task data in DDR3, and evenly distribute the task data to the eight C66x cores. Each core further divides the task data into smaller ones, so that each task data transmission only occupies a small time slice; The second level adopts a parallel design of memory data transfer and CPU based on ping-pong storage. Each core opens a ping-pong buffer area in LL2S. EDMA transfers data from MSMS to the ping buffer of LL2S, and then transfers it to the pong buffer in the background. The CPU processes the data in the ping or pong buffer area during the data transmission process. The third level adopts assembly instruction pipeline design to realize the mutual driving of multi-cycle instructions and fully tap the CPU computing power.

[0020] The DSP uses the FT-M6678 chip of the National University of Defense Technology. The 1.2GHz main frequency and 8-core architecture give it powerful parallel computing power. It is capable of processing most sonar array signals with a relatively small hardware scale, and has significant advantages in complex multi-target scenarios. Its port is connected to four 512M-byte DDR3 memory chips to build a 64-bit bandwidth, and one 64Mb NORFLASH storage configuration and user data, achieving high-speed data reading and writing and storage management, accelerating the signal processing process; The FPGA uses Shenzhen Guowei Electronics SMQ7K325TFFG900 chip (KINTEX-7 series), which has 326080 logic units, 407600 triggers, 16020kbBlockRAM and 50950 lookup tables. The 16-channel acoustic array data is collected in parallel and transmitted to the DSP for processing via the SRIO high-speed serial port (3.125G4x rate 9.59Gbps). The DSP can accurately control the FPGA to output 7-channel DDS, 1-channel analog, 4-channel transmission signals and 35-channel control codes. The FPGA is responsible for data collection, storage, erasure and external communication (via CAN and serial port). The DSP is connected to the host computer via Ethernet and serial port. The peripheral expansion PCIe and 1553B interfaces improve the system scalability and compatibility, which meets the needs of multiple application scenarios. The power supply is 27V±2.7V DC. The module contains multiple isolation units to generate voltages suitable for each module. After level conversion and isolators, it is connected to the periphery to ensure the electromagnetic compatibility and electrical safety of the system, resist external interference, and ensure reliable operation. The data processing interface is carefully designed. The signal processing part and the FPGA interface are connected with connectors to facilitate the expansion of processing nodes and functional modules as needed. The power supply module is far away from the acquisition and conditioning module to avoid the influence of temperature-sensitive components, maintain the stability of system performance, and reduce the risk of signal drift and error caused by thermal effects. The sonar receiving module converts 16 echo signals into digital differential signals, and the digital signal processing module demodulates and forms beams in turn. The DSP sends and receives host computer commands and beam data via the Gigabit network to achieve system collaborative control. For example, in deep-sea detection scenarios, it accurately processes weak echoes, extracts target features, and provides reliable data for target identification and positioning. Multi-core DSP processing is optimized using a multi-level parallel method. The first-level time-sliced ​​inter-core pipeline overcomes multi-core memory access blocking and balances core loads by task-based time slices. The second-level ping-pong storage is transmitted in parallel. EDMA and CPU operate in parallel to transfer data between MSMS and LL2S. The third-level assembly instruction pipeline taps the potential of the CPU and accelerates instruction execution. This strategy improves overall processing efficiency, enhances the system's real-time response and complex task processing capabilities, and ensures stable and efficient operation of the sonar system.

[0021] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An underwater acoustic signal processing platform, characterized in that: Including baseboard, core board, AD acquisition board, beamforming board, and expansion function board; The baseboard is used to provide a signal path between the core board and the AD acquisition board, beamforming board, and expansion function board, and provides 12V isolated power supply; The core board is based on DSP+FPGA architecture and includes: The digital signal processing module is used to perform demodulation, sampling and digital filtering on the collected digital signals to determine the target distance, direction, speed, heading and other motion elements. The module is connected to the external Gigabit network to send the processed data to the host computer and receive the control commands issued by the host computer to control the transmitting and receiving circuits and the beamforming process. A power supply module, whose input end is connected to a 27V±2.7V DC power supply, provides the required power supply voltage for each module of the system through multiple isolation modules, and the power supply module is set away from the data acquisition and conditioning module; A data storage module includes four DDR3 memory chips and one NORFLASH connected to the DSP chip port. Each of the four DDR3 memory chips has a capacity of 512M bytes and forms a 64-bit data bandwidth. The capacity of NORFLASH is 64Mb and is used to store configuration files of the DSP chip or other user data. The communication module enables DSP to communicate with the host computer through Ethernet and serial port, and FPGA to communicate with the outside by controlling CAN and serial port, and the peripheral expansion has PCIe and 1553B interfaces; Interface module and connector, wherein the interface connecting the signal processing part and the FPGA is led out by the connector; AD acquisition board, used to condition and collect the electrical signals converted by the reflected sound wave signals through the receiving sound array, and transmit the collected signals to the digital signal processing module of the core board; The beamforming board is used to receive the beamforming data from the core board, perform digital-to-analog conversion on it to form a beam, and send it to the transmitter for subsequent processing.

2. The underwater acoustic signal processing platform according to claim 1, characterized in that: The AD acquisition board uses three AD7656 chips to form the AD part, which is used to synchronously acquire 16 analog quantities with a sampling frequency of 250kSPS. The analog quantities that do not need to be synchronously acquired are switched through an external multi-way switch. The entire circuit controls the timing through FPGA. The AD7656 chip uses a parallel interface to connect to the external circuit. The operational amplifier selected for its front-end drive circuit has a speed of 550ns and a signal-to-noise ratio of less than 85db. The front-end drive circuit also includes an RC filter circuit for signal filtering and eliminating sampling jitter.

3. The underwater acoustic signal processing platform according to claim 1, characterized in that: Also included is a DDS signal generator that uses direct digital frequency synthesis technology, including: The waveform adjustment module adjusts the four output waveforms by changing the signal according to the waveform control sent by the DSP through a 4-to-1 data selector; Amplitude adjustment module, which uses a multiplier to multiply the waveform output by the amplification factor to achieve amplitude adjustment, with the maximum gain being 15 times; Phase adjustment module, which realizes phase adjustment in integer multiples of 15° according to the formula P=511N / 360, where N is the phase shift degree; The frequency adjustment module realizes frequency adjustment by changing the interval of ROM data sampling and follows the Nyquist sampling theorem.

4. The underwater acoustic signal processing platform according to claim 1, characterized in that: The digital signal processing module adopts a multi-level parallel processing method when processing signals, including: The first level uses a time-slice-based inter-core pipeline design to control the eight cores to take turns accessing the task data in DDR3, and evenly distribute the task data to the eight C66x cores. Each core further divides the task data into smaller ones, so that each task data transmission only occupies a small time slice; The second level adopts a parallel design of memory data transfer and CPU based on ping-pong storage. Each core opens a ping-pong buffer area in LL2S. EDMA transfers data from MSMS to the ping buffer of LL2S, and then transfers it to the pong buffer in the background. The CPU processes the data in the ping or pong buffer area during the data transmission process. The third level adopts assembly instruction pipeline design to realize the mutual driving of multi-cycle instructions and fully tap the CPU computing power.

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