A bandgap reference circuit and its chip resistant to single-event transient effects

Abstract

This invention belongs to the field of analog circuits, specifically relating to a bandgap reference circuit and its chip resistant to single-event transient effects. The solution includes a reference voltage generation circuit, a pulse width hardening circuit, and an output circuit. The pulse width hardening circuit comprises two stages of inverters and a transmission transistor connected to a critical node in the reference voltage generation circuit. This circuit can accelerate the recovery of the reference voltage generation circuit from abnormal states caused by single-event transients through charge dissipation principles and serves as the startup circuit for the reference voltage generation circuit. The output circuit is connected to the output node of the reference voltage generation circuit and detects the pulse amplitude of the output signal generated by the reference voltage generation circuit through devices such as Schmitt triggers or comparators, thereby cutting off the portion of the output bandgap reference voltage signal exceeding a safe threshold. This invention solves the problem that the output stability of existing bandgap reference circuits is greatly affected by single-event transients, making it difficult to operate normally under radiation environments.

Description

Technical Field

[0001] This invention belongs to the field of analog circuits, specifically relating to a bandgap reference circuit and its chip that resists single-event transient effects. Background Technology

[0002] With the advancement of global science and technology and the vigorous development of the aerospace industry, more and more electronic devices are entering space with spacecraft. In the environment of outer space, spacecraft are exposed to various cosmic rays for extended periods. Particles in the space radiation environment can penetrate the spacecraft's shielding layer, interact with integrated circuits to produce radiation effects, causing performance degradation or malfunction of electronic devices, and even leading to system damage, thus affecting the on-orbit safety of the spacecraft.

[0003] Bandgap reference circuits, as circuits capable of providing a stable and independent voltage reference, are widely used in various circuit modules, such as DC / DC converters, low-dropout linear regulators (LDOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and comparators. Existing bandgap references are quite sensitive to single-event transients (SETs). In the environment of space radiation, when heavy ions bombard the sensitive nodes of a bandgap reference circuit, SET disturbances will be generated along their propagation path, ultimately producing transient pulses at the output DC level. Therefore, all sub-circuit systems relying on this reference voltage will be affected, leading to errors or even global malfunctions. Thus, designing a bandgap reference circuit capable of tolerating SETs is of great significance and necessity. Summary of the Invention

[0004] To address the problem that the output stability of existing bandgap reference circuits is greatly affected by single-event transients and they are difficult to operate normally under radiation environments, this invention provides a bandgap reference circuit and its chip that are resistant to single-event transients.

[0005] The technical solution provided by this invention is as follows:

[0006] A bandgap reference circuit resistant to single-event transient effects includes a reference voltage generation circuit, a pulse width hardening circuit, and an output circuit. The reference voltage generation circuit consists of PMOS transistors P1-P6, NMOS transistors N1-N4, resistors R1-R6, and PNP transistors Q1 and Q2. N1-N4, P1-P4, R4, and R5 form a Cascode current mirror structure. On the ground paths on both sides of the Cascode current mirror structure, the nodes connected to the drains of P3, P1, N3, and N1 are denoted as A, C, E, and G; the nodes connected to the drains of P4, P2, N4, and N2 are denoted as B, D, F, and H.

[0007] The pulse width hardening circuit is used to accelerate the recovery of the reference voltage generation circuit from abnormal states caused by single-event transients through charge dissipation, and serves as the startup circuit for the reference voltage generation circuit. The pulse width hardening circuit consists of PMOS transistors P7-P10 and P12-P15, NMOS transistors N5 and N7-N10, and transistor Q3. Specifically, the gate of P8 is connected to node D, and the drain of P8 is connected to the source of P7; the gate of P7 is connected to node F, and the drain of P7 is connected to the drain of N5. The gate of N5 is connected to node E; the source of N5 is connected to the emitter of Q3, and the connection point is denoted as node K. The base and collector of Q3 are grounded; the sources of P8-P10 and P12-P15 are connected to VDD; the drains of P12 and N7 are connected to the gates of P13 and N8; the drains of P13 and N8 are connected to the gate of P9; and the gates of P12 and N7 and the drain of P9 are connected to node C. The drains of P14 and N9 are connected to the gates of P15 and N10; the drains of P15 and N10 are connected to the gate of P10; the gates of P14 and N9 are connected to the drain of P10 at node E; the sources of N7 to N10 are connected to node K.

[0008] The output circuit is connected to the output node J of the reference voltage generation circuit and is used to output the required bandgap reference voltage through the output port Vout.

[0009] In the bandgap reference circuit for resisting single-event transient effects provided by the present invention, the ratio of the number of Q3 in the pulse width hardening circuit to the number of Q1 in the reference voltage generation circuit is 1:1; and the emitter voltages of Q1 and Q3 are made the same through N5, P7, and P8.

[0010] In the bandgap reference circuit for resisting single-event transient effects provided by this invention, the gate-source voltage of N7 in the pulse width hardening circuit is equal to the voltage difference between the gate of N3 and the emitter of Q1, and the gate-source voltage of N9 is equal to the voltage difference between the gate of N1 and the emitter of Q1. The tolerance of the pulse width hardening circuit to single-event transient effects can be adjusted by modifying the component parameters of N7, N8, P12, and P13, as well as the component parameters of N9, N10, P14, and P15.

[0011] As a further improvement of this invention, the logic for the pulse width hardening circuit to activate the reference voltage generation circuit is as follows: When VDD is powered on, the gate voltages of transistors P9 and P10 are low, and transistors P9 and P10 are turned on; thereby charging the gates of N1 to N4 in the Cascode current mirror structure. After charging is completed, the outputs of nodes C and E are flipped by two stages of inverters in the pulse width hardening circuit, causing the gates of P9 and P10 to be high; at this time, transistors P9 and P10 are turned off, isolating the pulse width hardening circuit from the reference voltage generation circuit.

[0012] As a further improvement of the present invention, the output circuit includes an output unit, a positive pulse detection unit, and a negative pulse detection unit. The output unit includes a PMOS transistor N6 and an NMOS transistor N11; the drain of N6 is connected to node J, the source of N6 and P11 are connected, and the drain of P11 is connected to the output port Vout.

[0013] A positive pulse detection unit is connected between the gate of N6 and node J, and is used to turn off N6 when the output signal of node J in the reference voltage generation circuit exceeds a preset safety threshold. A negative pulse detection unit is connected between the gate of P11 and node J, and is used to turn off P11 when the output signal of node J in the reference voltage generation circuit exceeds a preset safety threshold.

[0014] As a further improvement of the present invention, the positive pulse detection unit and the negative pulse detection unit are implemented using Schmitt triggers or comparator circuits; and the safe threshold of the pulse amplitude of the output bandgap reference voltage is adjusted by adjusting the component parameters in the positive pulse detection unit and the negative pulse detection unit.

[0015] As a further improvement of the present invention, the Schmitt trigger is composed of three PMOS transistors P16 to P18 and three NMOS transistors N11 to N13. The circuit connection relationship is as follows: the gates of P16, P17, N11, and N12 are connected to the output node of the reference voltage generation circuit; the source of P16 and the drain of N13 are connected to VDD; the drain of P16 is connected to the source of P17 and P18; the source of N11 and N13 is connected to the drain of N12; the source of N12 and the drain of P18 are grounded; the drains of P17 and N11 are connected to the gates of N13 and P18, and are used to connect the gates of the PMOS transistor or NMOS transistor to be controlled.

[0016] As a further improvement of the present invention, the circuit connection relationship of the Cascode current mirror in the reference voltage generation circuit is as follows:

[0017] The sources of P3 and P4 are connected to VDD; the drain of P3 is connected to the source of P1, and the connection point is denoted as node A; the drain of P4 is connected to the source of P2, and the connection point is denoted as node B; the drain of P1 is connected to the gates of N3 and N4 and one end of R4, and the connection point is denoted as C; the other end of R4 is connected to the drain of N3 and the gates of N1 and N2, and the connection point is denoted as E; the gates of P3 and P4 are connected to the drain of P2 and one end of R5, and the connection point is denoted as node D; the other end of R5 is connected to the gates of P1 and P2 and the drain of N4, and the connection point is denoted as node F; the source of N3 is connected to the drain of N1, and the connection point is denoted as G; the source of N4 is connected to the drain of N2, and the connection point is denoted as H.

[0018] As a further improvement of the present invention, the circuit connection relationship of the reference voltage generating circuit is as follows: the source of N1 is connected to the emitter of Q1 and grounded through R1; the source of N2 is connected to the emitter of Q1 through R3 and grounded through R2; the collectors and bases of Q1 and Q2 are grounded. The source of P6 is connected to VDD; the gate of P6 is connected to node D; the drain of P6 is connected to the source of P5, and the connection point is denoted as I; the gate of P5 is connected to node F; the drain of P5 is grounded through R6, and the connection point between the two is denoted as node J.

[0019] The present invention also includes a chip that employs a bandgap reference circuit as described above that is resistant to single-event transient effects.

[0020] The technical solution provided by this invention has the following beneficial effects:

[0021] The bandgap reference circuit for resisting single-event transient effects provided by this invention employs a newly designed pulse width hardening circuit. This circuit, on the one hand, utilizes the principle of charge dissipation to accelerate the circuit's recovery process from abnormal states under radiation bombardment, shortening the pulse width of the circuit output when affected by radiation. On the other hand, it can also be used as the startup circuit for the reference voltage generation circuit in the circuit, automatically isolating the two after the latter starts, minimizing the impact on the stability of the output signal.

[0022] The improved bandgap reference circuit provided by this invention also introduces a special pulse amplitude hardening mechanism in the output module. This circuit can detect the pulse amplitude of the output of the reference voltage generation circuit through devices such as Schmitt triggers or comparators, and then automatically cut off the output of the circuit when the amplitude of the output signal exceeds a preset safety threshold, thereby mitigating the influence of radiation bombardment on the amplitude of the circuit output.

[0023] Furthermore, the circuit designed in this invention not only exhibits superior performance compared to traditional circuits but also maintains a smaller area overhead. While effectively suppressing single-particle transient impacts, the circuit avoids increased power consumption, thus possessing outstanding practical value and being suitable for large-scale application. Attached Figure Description

[0024] Figure 1 This is a circuit diagram of a conventional bandgap reference circuit described in Embodiment 1 of the present invention.

[0025] Figure 2 The circuit diagram provided in Embodiment 1 of the present invention is a bandgap reference circuit that employs pulse width hardening circuitry to resist single-event transient effects.

[0026] Figure 3 This is a circuit diagram of the bandgap reference circuit for resisting single-event transient effects, which has both pulse width hardening and pulse amplitude hardening functions, as provided in Embodiment 1 of the present invention.

[0027] Figure 4 This is a signal flow diagram of the circuit of the present invention during the startup phase in a test experiment.

[0028] Figures 5-7 This is a comparison diagram of the output waveforms of the circuit of this invention and three typical nodes in a conventional circuit after being bombarded by a single-particle transient pulse in a test experiment.

[0029] Figure 8 To test the Monte Carlo curve of the output voltage of the circuit of the present invention as a function of temperature from -40℃ to 150℃ in the experiment.

[0030] Figure 9 This is a histogram of the temperature drift coefficient of the output voltage of the circuit of this invention used in the test experiment.

[0031] Figure 10 The output voltage histogram is used to test the output stability of the circuit of the present invention under different process angles during the experiment.

[0032] Figure 11 The layout design of the circuit of this invention is for testing experiments. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0034] Example 1

[0035] This embodiment provides a bandgap reference circuit resistant to single-event transient effects. This circuit is based on... Figure 1 The circuit shown is an improvement upon the traditional bandgap reference circuit employing a Cascode current mirror structure. The technical solution provided in this embodiment, on the one hand, [details about the improvement]. Figure 1 The startup section used in traditional bandgap reference circuits has been upgraded to a more advanced pulse width hardening circuit, which accelerates the dissipation of excess charge generated when the circuit is subjected to radiation bombardment, thus shortening the pulse width generated at the output. Furthermore, this embodiment also... Figure 1 The output of the traditional bandgap reference circuit is improved. The improved circuit detects the actual output of the bandgap reference circuit in real time and isolates the excessively large pulse output at the output until the bandgap reference voltage generation circuit returns to normal operation.

[0036] Specifically, Figure 1The conventional bandgap reference circuit shown consists of two parts: a reference voltage generation circuit and a startup circuit. The reference voltage generation circuit comprises six PMOS transistors P1-P6, four NMOS transistors N1-N4, six resistors R1-R6, and two PNP transistors Q1 and Q2. In the reference voltage generation circuit, N1-N4, P1-P4, R4, and R5 form a Cascode current mirror structure. The circuit connections for the Cascode current mirror are as follows: the sources of P3 and P4 are connected to VDD; the drain of P3 is connected to the source of P1, and the connection point is denoted as node A; the drain of P4 is connected to the source of P2, and the connection point is denoted as node B; the drain of P1 is connected to the gates of N3 and N4 and one end of R4, and the connection point is denoted as C; the other end of R4 is connected to the drain of N3 and the gates of N1 and N2, and the connection point is denoted as E; the gates of P3 and P4 are connected to the drain of P2 and one end of R5, and the connection point is denoted as node D; the other end of R5 is connected to the gates of P1 and P2 and the drain of N4, and the connection point is denoted as node F; the source of N3 is connected to the drain of N1, and the connection point is denoted as G; the source of N4 is connected to the drain of N2, and the connection point is denoted as H.

[0037] Except for the Cascode current mirror, the circuit connections of the rest of the reference voltage generation circuit are as follows: the source of P6 is connected to VDD; the gate of P6 is connected to node D; the drain of P6 is connected to the source of P5, and the connection point is denoted as I; the gate of P5 is connected to node F; the drain of P5 is grounded through R6, and the connection point between the two is denoted as node J. The source of N1 is connected to the emitter of Q1 and grounded through R1; the source of N2 is connected to the emitter of Q1 through R3 and grounded through R2; the collectors and bases of Q1 and Q2 are grounded.

[0038] In the reference voltage generation circuit provided in this embodiment, P5 and P6 provide bias to the reference voltage generation section through a current mirror; the current mirror composed of P1 to P4 ensures that the current flowing through N1 and N2 is the same, thereby making the source terminal voltages of N1 and N2 the same. Figure 1 In the reference voltage generation circuit section, the resistance values ​​of R1 and R2 are equal, and the currents through R1 and R2 are the same, ensuring that the currents flowing through Q1 and Q2 are the same.

[0039] Figure 1 The startup circuit in the conventional bandgap reference circuit shown consists of two PMOS transistors and a capacitor C1; the sources of P7 and P8 are connected to VDD; the drain of P7 and the gate of P8 are connected to the upper plate of C1; the gate of P7 and the lower plate of C1 are grounded; the drain of P8 is connected to node C in the Cascode current mirror. The working principle of this startup circuit is as follows:

[0040] Because the gate of P7 is grounded, its gate voltage is always 0 potential; the gate of P8 is connected to capacitor C1, and its gate voltage is also 0 potential when not powered on. When VDD is powered on, the source voltages V of P7 and P8... GS When the threshold voltage Vth is exceeded, P7 and P8 are turned on. P8 charges the gates of N1 to N4 in the core circuit, completing the normal power-on process of the circuit; P7 charges capacitor C1, ensuring that the circuit is powered on and simultaneously raising the voltage of C1 (i.e., the gate voltage of P8) to a high level after the circuit is powered on and begins normal operation, so that P8 is turned off after the circuit is powered on and begins normal operation, and the start-up circuit will not affect the operation of the core circuit.

[0041] exist Figure 1 Based on the circuit shown, the circuit structure of the bandgap reference circuit resistant to single-event transient effects provided in this embodiment is as follows: Figure 2 As shown, it includes three parts: a reference voltage generation circuit, a pulse width hardening circuit, and an output circuit.

[0042] The reference voltage generation circuit still uses Figure 1 The circuit design shown consists of PMOS transistors P1 to P6, NMOS transistors N1 to N4, resistors R1 to R6, and PNP transistors Q1 and Q2.

[0043] The pulse width hardening circuit is used to accelerate the recovery of the reference voltage generation circuit from abnormal states caused by single-event transients through the principle of charge dissipation, and serves as the startup circuit for the reference voltage generation circuit. Specifically, combined with Figure 2 As can be seen, the pulse width hardening circuit in this embodiment consists of PMOS transistors P7-P10 and P12-P15, NMOS transistors N5 and N7-N10, and transistor Q3. The gate of P8 is connected to node D, and the drain of P8 is connected to the source of P7; the gate of P7 is connected to node F, and the drain of P7 is connected to the drain of N5. The gate of N5 is connected to node E; the source of N5 is connected to the emitter of Q3, and the connection point is denoted as node K. The base and collector of Q3 are grounded; the sources of P8-P10 and P12-P15 are connected to VDD; the drains of P12 and N7 are connected to the gates of P13 and N8; the drains of P13 and N8 are connected to the gate of P9; and the gates of P12 and N7 and the drain of P9 are connected to node C. The drains of P14 and N9 are connected to the gates of P15 and N10; the drains of P15 and N10 are connected to the gate of P10; the gates of P14 and N9 are connected to the drain of P10 at node E; the sources of N7 to N10 are connected to node K.

[0044] The output circuit is connected to the output node J of the reference voltage generation circuit and is used to output the required bandgap reference voltage through the output port Vout. In practical applications, in this embodiment, the output node J of the reference voltage generation circuit can be directly connected to the output port Vout to achieve direct output of the bandgap reference voltage signal generated by the reference voltage generation circuit. Of course, in other more optimized solutions, isolation or filtering devices can be used to select and output the generated bandgap reference voltage signal.

[0045] Specifically, the pulse width hardening circuit in this embodiment can be further divided into a first part consisting of P7, P8, N5, and Q3, and two identical second parts consisting of P9, P12, P13, N7, N8, and P10, P14, P15, N9, and N10. In this embodiment, the ratio of Q3 to Q1 in the pulse width hardening circuit to the number of Q1 in the reference voltage generation circuit is 1:1. The components N5, P7, and P8 in the first part ensure that the emitter voltages of Q1 and Q3 are the same, thereby guaranteeing that the gate-source voltage of N7 is equal to the voltage difference between the gate of N3 and the emitter of Q1, and that the gate-source voltage of N9 is equal to the voltage difference between the gate of N1 and the emitter of Q1.

[0046] As is well known, when a circuit is bombarded by radiation, the voltage at the corresponding nodes changes. Figure 1 In the conventional circuit shown, taking node B as an example, radiation bombardment causes the gate voltages of P1 to P4 to rise and the gate voltages of N1 to N4 to fall. At this time, the current in the branches containing P3 and P4 decreases, the dissipation rate of the large amount of excess charge generated by radiation in the circuit decreases, the dissipation time increases, and ultimately the pulse width of the bandgap reference voltage signal output by the circuit increases.

[0047] In this embodiment, as provided... Figure 2 In the bandgap reference circuit with pulse width hardening circuitry shown, the gate-source voltage of N7 in the second part of the pulse width hardening circuit is equal to the voltage difference between the gate of N3 and the emitter of Q1, and the gate-source voltage of N9 is equal to the voltage difference between the gate of N1 and the emitter of Q1. Taking node B as an example, once the node is bombarded by radiation, node B will generate a large number of holes due to radiation, and the gate voltages of N1 to N4 will drop, that is, the gate-source voltages of N7 and N9 will drop. The two-stage inverter will output a low level, and P9 and P10 will conduct, charging the gates of N1 to N4. This ensures that the drain current on N2 and N4 is large, accelerating the dissipation speed of excess holes in node B through nodes N2 and N4; thereby shortening the pulse width generated at the output terminal due to radiation.

[0048] Based on the functional principle of the pulse width hardening circuit in the bandgap reference circuit against single-event transient effects provided in this embodiment, it can also be found that the component parameters of N7, N8, P12, P13, as well as N9, N10, P14, P15, such as the width-to-length ratio, will affect the circuit's tolerance to single-event transient effects. By matching the parameters of the above-mentioned MOS transistors, the tolerance of the bandgap reference circuit against single-event transient effects to radiation can meet the requirements.

[0049] In addition to suppressing the effect of irradiation on the pulse width of the circuit output, the pulse width hardening circuit in this embodiment can also serve as a startup circuit, thereby activating the reference voltage generation circuit when VDD is powered on. Specifically, the logic for the pulse width hardening circuit to activate the reference voltage generation circuit is as follows:

[0050] When VDD is powered on, the gate voltages of transistors P9 and P10 are low, and P9 and P10 are turned on, thus charging the gates of N1 to N4 in the Cascode current mirror structure. During the charging process, the voltages at nodes C and E continuously increase. When charging is complete, the outputs of nodes C and E are flipped by two stages of inverters in the pulse width hardening circuit, causing the gates of P9 and P10 to be high. At this time, transistors P9 and P10 are turned off, isolating the pulse width hardening circuit from the reference voltage generation circuit.

[0051] Therefore, under normal operating conditions, the pulse width hardening circuit in the bandgap reference circuit that resists single-event transient effects provided in this embodiment will automatically isolate itself from the reference voltage generation circuit after completing the circuit startup task, thereby avoiding its own impact on the normal function of the reference voltage generation circuit.

[0052] Besides increasing the pulse width of the final output bandgap reference voltage signal, the effect of radiation bombardment on the reference voltage generation circuit may also lead to an increase in the amplitude of the output bandgap reference voltage signal. To address this issue, in the more optimized solution provided in this embodiment, the output circuit section of the bandgap reference circuit resistant to single-event transient effects can be further improved as follows: Figure 3 The circuit shown includes an output unit, a positive pulse detection unit, and a negative pulse detection unit. The output unit includes a PMOS transistor N6 and an NMOS transistor N11; the drain of N6 is connected to node J, the source of N6 and P11 are connected, and the drain of P11 is connected to the output port Vout.

[0053] The positive pulse detection unit is connected between the gate of N6 and node J, and is used to turn off N6 when the output signal of node J in the reference voltage generation circuit exceeds a preset safety threshold. The negative pulse detection unit is connected between the gate of P11 and node J, and is used to turn off P11 when the output signal of node J in the reference voltage generation circuit exceeds a preset safety threshold. That is, this output circuit will only output the bandgap reference voltage signal generated by the reference voltage generation circuit whose voltage amplitude is within the safety threshold range. Signal components exceeding the safety threshold will be shielded, thus achieving signal selection.

[0054] Therefore, it can be seen that the embodiment provided is as follows: Figure 3 The output module shown is essentially a pulse amplitude hardening circuit used to strengthen the pulse amplitude of the output signal from the reference voltage generation circuit, thereby mitigating the problem of excessively large output pulse amplitude caused by radiation bombardment. In practical applications, the positive and negative pulse detection units in this pulse amplitude hardening circuit can be implemented using Schmitt triggers or comparator circuits. By adjusting the component parameters (such as dimensions) in the positive and negative pulse detection units, the circuit's high sensitivity to output amplitude can be adjusted, making the safe threshold of the output bandgap reference voltage's pulse amplitude controllable. Specifically, as shown... Figure 4 As shown, the Schmitt trigger used in this embodiment consists of three PMOS transistors P16 to P18 and three NMOS transistors N11 to N13. The circuit connection is as follows: the gates of P16, P17, N11, and N12 are connected to the output node of the reference voltage generation circuit; the source of P16 and the drain of N13 are connected to VDD; the drain of P16 is connected to the source of P17 and P18; the source of N11 and N13 is connected to the drain of N12; the source of N12 and the drain of P18 are grounded; the drains of P17 and N11 are connected to the gates of N13 and P18, and are used to connect to the gate of the PMOS transistor or NMOS transistor to be controlled.

[0055] In summary, the bandgap reference circuit provided in this embodiment, which includes a reference voltage generation circuit, a pulse width hardening circuit, and an output circuit with pulse amplitude hardening function, is designed to resist single-event transient effects. During operation, the pulse width hardening circuit first activates the reference voltage generation circuit. When the reference voltage generation circuit is operating normally, transistors P9 and P10 in the pulse width hardening circuit are turned off, thus partially isolating them from the reference voltage generation circuit to avoid affecting its normal operation. When the reference voltage generation circuit is operating normally, transistors N6 and P11 in the pulse amplitude hardening circuit are turned on, and the bandgap reference voltage signal output by the reference voltage generation circuit is transmitted normally to the output terminal Vout. If the circuit is affected by radiation, causing the bandgap reference voltage signal output by the reference voltage generation circuit to deviate from the ideal value, the Schmitt trigger in the output circuit with pulse amplitude hardening function will detect the situation and turn off N6 or P11, preventing the output terminal from generating pulses with excessive amplitude until the bandgap reference voltage generation circuit returns to normal operation.

[0056] Performance testing

[0057] To verify the performance of the bandgap reference circuit resistant to single-event transient effects provided by this invention, technicians conducted... Figure 3 The bandgap reference circuit scheme of the present invention shown was simulated and compared with existing ones. Figure 1 The unhardened bandgap reference circuit shown is compared to the circuit's performance under radiation pulse bombardment. Specifically, a dual exponential current source is used in the experiment to simulate the circuit's effect under single-particle transients.

[0058] 1. Circuit startup

[0059] This experiment primarily tested the normal function of the circuit provided by this invention. The power supply voltage VDD and the output bandgap reference voltage signals during the power-on process of this circuit were visualized, and the resulting signal flow graph is shown below. Figure 4 As shown.

[0060] analyze Figure 4 It can be observed that the VDD signal starts to power on at 1μs and completes power-on at 2μs. The bandgap reference voltage output by the circuit starts to rise at 2.2μs and stabilizes at 2.78μs. The output bandgap reference voltage remains stable in the subsequent process.

[0061] Therefore, the pulse width hardening circuit in the bandgap reference circuit designed in this invention to resist single-event transient effects can be used as a startup circuit, thereby activating the reference voltage generation circuit after the system is powered on so that the latter can start working, and the startup speed of the circuit of this invention is relatively fast.

[0062] 2. Radiation pulse bombardment

[0063] This experiment further compared... Figure 1 and Figure 3 The outputs of unhardened and hardened bandgap reference circuits were tested after being bombarded by a single-particle transient pulse. To cover various typical radiation bombardment scenarios, the experiment selected node A, which showed relatively small changes in output signal pulse width and amplitude under bombardment; node B, which showed a significant increase in output signal pulse width under bombardment; and node J, which showed a significant increase in output signal amplitude under bombardment, for comparative testing.

[0064] During the testing process, with both the existing unhardened circuit and the hardened circuit of this invention operating normally, radiated bombardment tests were performed on nodes A, B, and J of both circuits at 1 μs. The waveforms of the bandgap reference voltage signals output by the two circuits were compared as follows: Figures 5-7 As shown. Analysis Figures 5-7 It can be observed that the amplitude and width of the SET transient pulse generated by the existing circuit after being subjected to radiation bombardment will increase significantly, while the amplitude and width of the SET transient pulse of the circuit of the present invention will decrease significantly after being subjected to radiation bombardment. Furthermore, when the signal fluctuation is induced by the single-event transient effect, the transient peak value of the final output bandgap reference voltage signal of the circuit of the present invention is no higher than 1.3V. Therefore, the back-end devices using this circuit can be protected.

[0065] 3. Temperature adaptability

[0066] To test the applicable operating temperature range of the bandgap reference circuit resistant to single-event transient effects provided by this invention, technicians tested the signal output variation of the circuit under extreme ambient temperature conditions ranging from -40°C to 150°C. The experimental data were then plotted as follows: Figure 8 The Monte Carlo curve of output voltage versus temperature is shown, and as follows: Figure 9 The histogram of the temperature drift coefficient of the circuit shown.

[0067] Combination Figure 8 and Figure 9 The data shows that the circuit exhibits an average temperature drift coefficient of only 10.9 in 2000 Monte Carlo tests; it demonstrates high output stability under different temperature conditions; and even under a large temperature difference of 190℃, the signal output fluctuation range does not exceed 2.5%, exhibiting outstanding temperature adaptability. Therefore, the circuit provided in this embodiment can operate normally in harsh temperature environments ranging from -40℃ to 150℃.

[0068] 4. Output stability

[0069] This experiment conducted 2000 Monte Carlo tests on the circuit under different process corners and adaptation conditions under the same power supply voltage and room temperature. The circuit output under different conditions was then statistically analyzed and plotted as follows: Figure 10 The histogram of the output voltage of the circuit shown at room temperature.

[0070] Analysis of the data in the figure reveals that the average output voltage of the circuit of the present invention during the test was 1.215V, the variance was 0.004533V, and the 3σ accuracy of the output voltage was 1.12%. This indicates that the circuit of the present invention has outstanding stability of output voltage at room temperature.

[0071] 4. Layout and Power Consumption

[0072] This experiment also targets Figure 3 The circuit layout shown is designed using the circuit scheme shown, and the resulting circuit layout is as follows: Figure 11 As shown, analysis Figure 11 The map shows that:

[0073] The final layout area of ​​this invention is 0.0079 mm². 2 The reinforcement increased by only 392.3 μm compared to before reinforcement. 2 This demonstrates that although the present invention adds a circuit module, it does not require excessive area loss. The power consumption after hardening remains within an acceptable range, and the hardened bandgap reference circuit has virtually no impact on other performance characteristics compared to the unhardened circuit. Therefore, it can be widely applied and promoted.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A bandgap reference circuit resistant to single-event transient effects, characterized in that, It includes: The reference voltage generation circuit consists of PMOS transistors P1-P6, NMOS transistors N1-N4, resistors R1-R6, and PNP transistors Q1 and Q2. N1-N4, P1-P4, R4, and R5 form a Cascode current mirror structure. The sources of P3, P4, and P6 are connected to VDD. The drain of P3 is connected to the source of P1, and the connection point is denoted as node A. The drain of P4 is connected to the source of P2, and the connection point is denoted as node B. The drain of P1 is connected to the gates of N3 and N4, as well as one end of R4, and the connection point is denoted as node C. The gates of P3, P4, and P6 are connected to the drain of P2, as well as one end of R5, and the connection point is denoted as node D. The other end of R4 is connected to N3. The drain of N1 and the gates of N2 are connected at point E; the other end of R5 is connected to the gates of P1, P2, and P5 and the drain of N4 at point F; the source of N3 is connected to the drain of N1 at point G; the source of N4 is connected to the drain of N2 at point H; the drain of P6 is connected to the source of P5 at point I; the drain of P5 is connected through one end of R6 at point J; the source of N1 is connected to the emitter of Q1 and one end of R1; the source of N2 is connected to one end of R2 and R3; the other end of R3 is connected to the emitter of Q2; the other ends of R1, R2, and R6 are grounded to the collector and base of Q1 and the collector and base of Q2. The pulse width hardening circuit is used to accelerate the recovery of the reference voltage generation circuit from abnormal states caused by single-event transients through the principle of charge dissipation, and serves as the startup circuit for the reference voltage generation circuit. The pulse width hardening circuit consists of PMOS transistors P7~P10, P12~P15, NMOS transistors N5, N7~N10, and transistor Q3. Specifically, the gate of P8 is connected to node D, and the drain of P8 is connected to the source of P7; the gate of P7 is connected to node F; the drain of P7 is connected to the drain of N5; the gate of N5 is connected to node E; and N5, N7~ The source of N10 is connected to the emitter of Q3, and the connection point is denoted as node K; the base and collector of Q3 are grounded; the sources of P8~P10 and P12~P15 are connected to VDD; the drains of P12 and N7 are connected to the gates of P13 and N8; the drains of P13 and N8 are connected to the gate of P9; the gates of P12 and N7 and the drain of P9 are connected to node C; the drains of P14 and N9 are connected to the gates of P15 and N10; the drains of P15 and N10 are connected to the gate of P10; the gates of P14 and N9 and the drain of P10 are connected to node E. An output circuit is connected to the output node J of the reference voltage generation circuit and is used to output the required bandgap reference voltage through the output port Vout. The output circuit includes an output unit, a positive pulse detection unit, and a negative pulse detection unit. The output unit includes a PMOS transistor N6 and an NMOS transistor N11. The drain of N6 is connected to node J, and the sources of N6 and P11 are connected. The drain of P11 is connected to the output port Vout. The positive pulse detection unit is connected between the gate of N6 and node J and is used to turn off N6 when the output signal of node J in the reference voltage generation circuit exceeds a preset safety threshold. The negative pulse detection unit is connected between the gate of P11 and node J and is used to turn off P11 when the output signal of node J in the reference voltage generation circuit exceeds a preset safety threshold.

2. The bandgap reference circuit resistant to single-event transient effects as described in claim 1, characterized in that: The ratio of the number of Q3 in the pulse width hardening circuit to the number of Q1 in the reference voltage generation circuit is 1:1; and the emitter voltages of Q1 and Q3 are made the same through N5, P7, and P8.

3. The bandgap reference circuit resistant to single-event transient effects as described in claim 2, characterized in that: In the pulse width hardening circuit, the gate-source voltage of N7 is equal to the voltage difference between the gate of N3 and the emitter of Q1, and the gate-source voltage of N9 is equal to the voltage difference between the gate of N1 and the emitter of Q1. By adjusting the component parameters of N7, N8, P12, and P13, as well as the component parameters of N9, N10, P14, and P15, the tolerance of the pulse width hardening circuit to single-event transient effects can be adjusted.

4. The bandgap reference circuit resistant to single-event transient effects as described in claim 2, characterized in that: The logic for the pulse width hardening circuit to activate the reference voltage generation circuit is as follows: When VDD is powered on, the gate voltages of transistors P9 and P10 are low, and transistors P9 and P10 are turned on; thus, the gates of N1 to N4 in the Cascode current mirror structure are charged; after charging is completed, the outputs of nodes C and E are flipped by two stages of inverters in the pulse width hardening circuit, making the gates of P9 and P10 high; at this time, transistors P9 and P10 are turned off, isolating the pulse width hardening circuit from the reference voltage generation circuit.

5. The bandgap reference circuit resistant to single-event transient effects as described in claim 1, characterized in that: The positive pulse detection unit and the negative pulse detection unit are implemented using Schmitt triggers or comparator circuits; The safe threshold of the pulse amplitude of the output bandgap reference voltage is adjusted by adjusting the component parameters in the positive pulse detection unit and the negative pulse detection unit.

6. The bandgap reference circuit resistant to single-event transient effects as described in claim 5, characterized in that: The Schmitt trigger consists of three PMOS transistors P16~P18 and three NMOS transistors N11~N13, with the circuit connection as follows: The gates of P16, P17, N11, and N12 are connected to the output node of the reference voltage generation circuit; the source of P16 and the drain of N13 are connected to VDD; the drain of P16 is connected to the source of P17 and P18; the source of N11 and N13 is connected to the drain of N12; the source of N12 and the drain of P18 are grounded; the drains of P17 and N11 are connected to the gates of N13 and P18, and are used to connect to the gate of the PMOS or NMOS transistor to be controlled.

7. A chip, characterized in that: It employs a bandgap reference circuit that resists single-event transient effects as described in any one of claims 1-6.

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