Control method of storage device, storage device and electronic device

Abstract

The invention discloses a control method of a storage device, the storage device and an electronic device, and the control method comprises the steps: responding to to-be-written data sent by a host end, and writing the to-be-written data into a storage unit according to a target mode; wherein the target mode at least comprises a first mode and / or a second mode, and the first mode comprises the steps of firstly performing storage by using a first type of storage unit and then migrating to a second type of storage unit; the second mode comprises the step of directly storing by using a second type of storage unit; counting target erasing times according to a target mode; the target erasing times are smaller than the sum of the actual erasing times of the two types of storage units; in response to the condition that the target erasing frequency is greater than an erasing frequency threshold, closing the first mode; according to the method, the data is written in through the target mode, the corresponding target erasing times are obtained, and the writing mode is controlled based on the target erasing times, so that the writing performance of the storage equipment is improved, erasing amplification can be effectively reduced, and the service life of the storage equipment is prolonged.

Description

Technical Field

[0001] The present invention relates to the technical field of storage devices, and in particular to a storage device control method, a storage device and an electronic device. Background Art

[0002] In the application process of storage devices, in order to improve the write performance of the storage devices, data is usually written through cache writing.

[0003] In actual operation, the inventors of the present application found that writing data by cache writing will generate more erase and write operations, thereby generating greater erase amplification and reducing the life of the storage device. Summary of the invention

[0004] The main technical problem solved by the present invention is: to provide a control method for a storage device, a storage device and an electronic device, which combine a cache write mode and a direct write mode to obtain a corresponding target number of erase and write times, and control the write mode based on the target number of erase and write times, thereby improving the write performance of the storage device and effectively reducing erase amplification and extending the life of the storage device.

[0005] To solve the above technical problems, a technical solution adopted by the present invention is: providing a control method for a storage device, comprising: in response to the data to be written sent by the host end, writing the data to be written into the storage unit according to the target mode; wherein the target mode includes at least the first mode and / or the second mode, the first mode includes first storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to the second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the amount of data that can be stored in each of the first type of storage unit is less than the amount of data that can be stored in each of the second type of storage unit; counting the target number of erase and write times according to the target mode; wherein the target number of erase and write times is less than the sum of the actual number of erase and write times of the first type of storage unit and the actual number of erase and write times of the second type of storage unit; in response to the target number of erase and write times being greater than the erase and write times threshold, closing the first mode.

[0006] In one embodiment of the present application, the target number of erase and write operations according to the target mode includes: obtaining the first wear coefficient, wherein the first wear coefficient is determined by a first number of error bits corresponding to a first type of storage unit and a second number of error bits corresponding to a second type of storage unit; wherein the first wear coefficient is a positive number less than 1; determining the product of the first wear coefficient and an actual number of erase and write operations for the first type of storage unit, and determining the sum of the product and the actual number of erase and write operations for the second type of storage unit as the target number of erase and write operations.

[0007] In one embodiment of the present application, the first wear coefficient is obtained in the following manner: the first type of storage unit and the second type of storage unit are erased and written the same number of times to obtain a first number of error bits corresponding to the first type of storage unit and a second number of error bits corresponding to the second type of storage unit; and the first wear coefficient is determined based on the first number of error bits and the second number of error bits.

[0008] In one embodiment of the present application, the step of writing the data to be written into a storage unit according to a target mode includes: writing the data to be written into a storage unit according to a first mode with a first erased state threshold voltage and / or a first programmed state threshold voltage; wherein the first erased state threshold voltage is greater than the second erased state threshold voltage corresponding to the first wear coefficient, and the first programmed state threshold voltage is less than the second programmed state threshold voltage corresponding to the first wear coefficient; the step of counting the target number of erase and write operations according to the target mode includes: obtaining a second wear coefficient, wherein the second wear coefficient is determined by the first erased state threshold voltage and / or the first programmed state threshold voltage; wherein the second wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by a first number of error bits corresponding to a first type of storage unit and a second number of error bits corresponding to a second type of storage unit; the first wear coefficient is a positive number less than 1; determining the product of the second wear coefficient and an actual number of erase and write operations of the first type of storage unit, and determining the sum of the product and the actual number of erase and write operations of the second type of storage unit as the target number of erase and write operations.

[0009] In one embodiment of the present application, the first erased state threshold voltage is 0.2-0.3V higher than the second erased state threshold voltage, and the first programmed state threshold voltage is 0.2-0.3V lower than the second programmed state threshold voltage.

[0010] In one embodiment of the present application, writing the data to be written into the storage unit according to the target mode includes: writing the data to be written into the storage unit according to the first mode based on the first erase start voltage and / or the first programming start voltage; wherein the first erase start voltage is less than the second erase start voltage corresponding to the first wear coefficient, and the first programming start voltage is less than the second programming start voltage corresponding to the first wear coefficient; counting the target number of erase and write times according to the target mode includes: obtaining a third wear coefficient, wherein the third wear coefficient is determined by the first erase start voltage and / or the first programming start voltage; wherein the third wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by the first number of error bits corresponding to the first type of storage unit and the second number of error bits corresponding to the second type of storage unit; the first wear coefficient is a positive number less than 1; determining the product of the third wear coefficient and the actual number of erase and write times of the first type of storage unit, and determining the sum of the product and the actual number of erase and write times of the second type of storage unit as the target number of erase and write.

[0011] In one embodiment of the present application, writing the data to be written into a storage unit according to a target mode includes: writing the data to be written into a storage unit according to a first mode with a first erase step value and / or a first programming step value; wherein the first erase step value is less than the second erase step value corresponding to the first wear coefficient, and the first programming step value is less than the second programming step value corresponding to the first wear coefficient; counting the target number of erase and write times according to the target mode includes: obtaining a fourth wear coefficient, wherein the fourth wear coefficient is determined by the first erase step value and / or the first programming step value; wherein the fourth wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by a first number of error bits corresponding to a first type of storage unit and a second number of error bits corresponding to a second type of storage unit; the first wear coefficient is a positive number less than 1; determining the product of the fourth wear coefficient and the actual number of erase and write times of the first type of storage unit, and determining the sum of the product and the actual number of erase and write times of the second type of storage unit as the target number of erase and write times.

[0012] In one embodiment of the present application, writing the data to be written into the storage unit according to the target mode includes: obtaining available space of the storage device, wherein the storage device includes multiple storage units; in response to the available space of the storage device being greater than or equal to a preset space, writing the data to be written into the storage device according to the first mode; in response to the available space of the storage device being less than the preset space, writing the data to be written into the storage device according to the second mode.

[0013] To solve the above technical problems, another technical solution adopted in the present application is: to provide a storage device, which includes a processor and a storage unit, and the processor is coupled to the storage unit and the host end, and executes instructions when working to implement the above control method.

[0014] To solve the above technical problems, another technical solution adopted in the present application is: to provide an electronic device, including a processor and a storage device, wherein the processor is coupled to the storage device and executes instructions when working to implement the above control method.

[0015] Different from the current technology, the control method of the storage device provided by the present application includes: in response to the data to be written sent by the host, writing the data to be written into the storage unit according to the target mode; wherein the target mode includes at least the first mode and / or the second mode, the first mode includes first storing in the first type of storage unit, and then migrating the data stored in the first type of storage unit to the second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit; counting the target erasure times according to the target mode; wherein the target erasure times is less than the sum of the actual erasure times of the first type of storage unit and the actual erasure times of the second type of storage unit; in response to the target erasure times being greater than the erasure times threshold, closing the first mode. That is, in the present application, the data to be written is written into the storage unit through the target mode including the first mode and / or the second mode, the corresponding target erasure times are obtained, and the writing mode is controlled based on the target erasure times, while improving the write performance of the storage device, it can also effectively reduce the erase amplification and extend the life of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0017] Figure 1 It is a flowchart of a first embodiment of a control method for a storage device of the present application;

[0018] Figure 2 is a flow chart of an embodiment of step S11;

[0019] Figure 3 is a flowchart of a second embodiment of a method for controlling a storage device in the present application;

[0020] Figure 4is a relationship diagram between the number of erasures and the number of error bits corresponding to the first type of storage unit and the second type of storage unit;

[0021] Figure 5 is a flowchart of a third embodiment of a method for controlling a storage device in the present application;

[0022] Figure 6 is a schematic diagram of threshold voltages corresponding to a first type of memory cell and a second type of memory cell in the current technology;

[0023] Figure 7 is a schematic diagram of threshold voltages corresponding to the first type of memory cell in the third embodiment of the present application;

[0024] Figure 8 is a flowchart of a fourth embodiment of a method for controlling a storage device in the present application;

[0025] Fig. 9 is a flowchart of a fifth embodiment of a method for controlling a storage device in the present application;

[0026] Fig.10 It is a principle flow chart of writing the data to be written into the storage unit in the present application;

[0027] Fig.11 It is a structural schematic diagram of an embodiment of a storage device of the present application;

[0028] Fig.12 It is a structural schematic diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0030] Reference to "embodiments" in an application means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] The steps in the embodiments of the present application do not necessarily have to be processed in the described order of steps. The steps can be selectively rearranged, or the steps in the embodiments can be deleted, or the steps in the embodiments can be added as needed. The step descriptions in the embodiments of the present application are only optional sequence combinations and do not represent all step sequence combinations in the embodiments of the present application. The order of steps in the embodiments cannot be considered as a limitation of the present application.

[0032] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0033] In current technology, in order to improve the write performance of storage devices, a cache write method (WBfeature) is usually used to write the data to be written to the storage device, that is, the data to be written is first written to the flash memory, and then the corresponding data is moved to other storage units. Because the write rate to the flash memory is fast, the write performance of the storage device is improved; however, for the same amount of data written, the number of flash memory blocks occupied by the write method to the flash memory is much larger than the number of flash memory blocks occupied by the direct write method, and after writing to the flash memory, it needs to be moved to other storage units, which results in a larger number of side writes, and then a larger erase amplification, which reduces the life of the storage device.

[0034] Therefore, the present application provides a control method for a storage device, which writes the data to be written into a storage unit through a target mode including a first mode and / or a second mode, obtains the corresponding target number of erase and write times, and controls the writing method based on the target number of erase and write times. While improving the write performance of the storage device, it can also effectively reduce erase amplification and extend the life of the storage device.

[0035] See also Figure 1 , Figure 1 It is a flowchart of the first embodiment of the control method of the storage device of the present application.

[0036] like Figure 1 As shown, the control method of the storage device of the present application includes the following steps:

[0037] S11. In response to the data to be written sent by the host, the data to be written is written into the storage unit according to the target mode; wherein the target mode includes at least the first mode and / or the second mode, the first mode includes first storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to the second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit.

[0038] Among them, the host end can be a communication device that can send commands, such as a mobile phone, tablet, computer, etc.; the data to be written can be various types of data that need to be stored, such as text, numbers, images, audio, video, etc.

[0039] In some embodiments, the storage device may include multiple storage units, and a portion of the storage units may be storage units of the first type, and another portion of the storage units may be storage units of the second type; or a single storage unit may be a storage unit of the first type in one time period and a storage unit of the second type in another time period. The setting can be made according to actual conditions.

[0040] The first type of storage unit is used as a buffer area, and the second type of storage unit is used as a normal storage area.

[0041] In some embodiments, the target mode may include the first mode alone, the second mode alone, or both the first mode and the second mode.

[0042] See also Figure 2 , Figure 2 It is a flowchart of an embodiment of step S11.

[0043] like Figure 2 As shown, including:

[0044] S111. Obtain available space of a storage device.

[0045] The available space of the storage device includes the available space of the desired storage unit, and the available space corresponding to each storage unit is determined.

[0046] S112: In response to the available space of the storage device being greater than or equal to the preset space, write the data to be written into the storage device according to the first mode.

[0047] In order to ensure the normal operation of the first mode, a threshold needs to be set, that is, a preset space is set so that when the data to be written is written to the storage unit using the first mode, sufficient available space is used for caching and transfer.

[0048] Specifically, when it is detected that the available space of the storage device is greater than or equal to the set preset space, the data to be written can be written to the storage device according to the first mode, that is, the target mode can be a first mode alone. In the case of the first mode, the host sends the data to be written to the storage device. After the storage device receives the data to be written, in response to the action, the storage device stores the data to be written in a first type of storage unit, and when the device is idle or the available bandwidth is sufficient, the data cached in the first type of storage unit is moved to the second type of storage unit. The move can be done by directly writing to refresh the data cached in the first type of storage unit to the second type of storage unit. The relevant data of the first type of storage unit is invalid, so that the storage unit releases more space.

[0049] S113. In response to the available space of the storage device being smaller than the preset space, write the data to be written into the storage device according to the second mode.

[0050] Specifically, when it is detected that the available space of the storage device is less than the preset space, the data to be written can be written to the storage device according to the second mode, that is, the target mode can include the second mode alone. In the case of the second mode, the host sends the data to be written to the storage device. After the storage device receives the data to be written, in response to the action, the storage device stores the data to be written in a second type of storage unit, that is, directly stores the data to be written in a normal storage area.

[0051] In some embodiments, the target mode may include a first mode and a second mode. For example, in the early stage of the storage process, the available space of the storage device is greater than or equal to the preset space, and in the later stage of the storage process, the available space of the storage device is less than the preset space, that is, when a large amount of data needs to be stored in one storage process, a mixed mode of the first mode and the second mode is adopted. In the case of a mixture of the first mode and the second mode, the available space of the storage device obtained in real time is compared with the preset space. When the available space of the storage device is greater than or equal to the preset space, the first mode is adopted to write the data to be written into the storage device, and when the available space of the storage device is less than the preset space, the second mode is adopted to write the data to be written into the storage device.

[0052] S12, counting a target erasure number according to a target mode; wherein the target erasure number is less than the sum of an actual erasure number of the first type of storage unit and an actual erasure number of the second type of storage unit.

[0053] Among them, the number of erase and write times is the number of times the data to be written is erased and written when it is written into the storage unit, and the target number of erase and write times is the number of erase and write times corresponding to writing the data to be written into the storage unit according to the target mode; the actual number of erase and write times of the first type of storage unit is the number of erase and write times when the data to be written is stored in the first type of storage unit, and the actual number of erase and write times of the second type of storage unit is the number of erase and write times when the data to be written is stored in the second type of storage unit.

[0054] Specifically, after the data to be written is written into the storage unit according to the target mode, the target erase and write times corresponding to the target mode are counted, as well as the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit. Because the target erase and write times are less than the sum of the actual erase and write times of the two types of storage units, the erase amplification is effectively reduced and the life of the storage device is extended.

[0055] For example, the capacity of the first type of storage unit is 1GB, and the capacity of the second type of storage unit is 3GB. When the second mode is used to write 3GB of data to be written into the storage unit, a direct write method is used to write the 3GB of data to be written directly into the second type of storage unit. During the writing process, the second type of storage unit needs to be erased once, and its erase amplification factor is 1 / 1=1; and when the first mode is used to write 3GB of data to be written into the storage unit, the 3GB of data to be written needs to be written into three first type of storage units with a capacity of 1GB respectively, and the host side is quickly replied. When the system is idle or has sufficient bandwidth, the 3GB of data stored in the three first type of storage units is moved to the second type of storage unit with a capacity of 3GB. Storing data in the first type of storage unit can accelerate storage efficiency. When writing data, each first type of storage unit with a capacity of 1GB is erased once, and when it is moved to the second type of storage unit, the second type of storage unit is erased again. Therefore, the number of erases in the first mode is four times, and the erase amplification factor is 4 / 1=4. That is, the sum of the actual erasure times of the first type of storage unit and the actual erasure times of the second type of storage unit is: 3+1=4, and the current target erasure times counted is less than 4, thus effectively reducing the erase amplification and extending the life of the storage device.

[0056] S13: In response to the target erasure count being greater than the erasure count threshold, shutting down the first mode.

[0057] In order to determine whether the life of the storage unit is exhausted, it is necessary to set an erase and write count threshold.

[0058] Specifically, an erasure count threshold is determined based on the erasable number of times a storage unit in the storage device can be erased. After the data to be written is written into the storage unit according to the target mode and the corresponding target erasure count is counted, the target erasure count is compared with the erasure count threshold. When the target erasure count is greater than the erasure count threshold, it indicates that the life of the storage unit is exhausted. Therefore, the first mode needs to be turned off to end the erasure of the storage unit.

[0059] In this embodiment, the data to be written is written into the storage unit through a target mode including the first mode and / or the second mode, the corresponding target erase and write times are obtained, and the target erase and write times are set to be smaller than the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit, so as to reduce the erase amplification. That is, the writing mode is controlled based on the target erase and write times, which can improve the write performance of the storage device while effectively reducing the erase amplification and extending the life of the storage device.

[0060] In order to further reduce the erase magnification, it can also be set according to the wear coefficient.

[0061] See also Figure 3 , Figure 3 It is a flowchart of the second embodiment of the control method of the storage device in the present application.

[0062] like Figure 3 As shown, the following steps are included:

[0063] S21. In response to the data to be written sent by the host, the data to be written is written into the storage unit according to the target mode; wherein the target mode includes at least a first mode and / or a second mode, the first mode includes first storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in a second type of storage unit; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit.

[0064] The same parts as those of the first embodiment are not described in detail.

[0065] S22. Obtain a first wear coefficient, wherein the first wear coefficient is determined by a first number of error bits corresponding to the first type of storage unit and a second number of error bits corresponding to the second type of storage unit; wherein the first wear coefficient is a positive number less than 1.

[0066] Among them, the first wear coefficient is an internal operating parameter corresponding to the erasure of the first type of storage unit, which is used to manage the life of the storage device and can adjust the erase amplification; under the same erasure conditions, the number of error bits (Fail bit count, FBC) caused by the first type of storage unit is less than the number of error bits caused by the second type of storage unit.

[0067] In some embodiments, the first wear coefficient may be obtained in advance in the following manner.

[0068] Specifically, the first type of storage unit and the second type of storage unit are erased and written the same number of times, and a first error bit number corresponding to the first type of storage unit and a second error bit number corresponding to the second type of storage unit are obtained respectively, and then a first wear coefficient is determined according to the first error bit number and the second error bit number.

[0069] like Figure 4 As shown, Figure 4 It is a relationship diagram between the number of erasures and writes and the number of error bits corresponding to the first type of storage unit and the second type of storage unit.

[0070] like Figure 4 As shown, when the number of erasures is the same, the second error bit number corresponding to the second type of storage unit is twice the first error bit number corresponding to the first type of storage unit, so the first wear coefficient is 1 / 2=0.5.

[0071] S23, determining the product of the first wear coefficient and the actual erasure times of the first type of storage unit, and determining the sum of the product and the actual erasure times of the second type of storage unit as the target erasure times.

[0072] Here, the first wear coefficient needs to be brought into the calculation of the target erasing times.

[0073] Specifically, the first wear coefficient and the actual erasure times of the first type of storage unit are multiplied to obtain a product, and the product and the actual erasure times of the second type of storage unit are added, and the obtained sum is the target erasure times.

[0074] Then, the first wear coefficient is 0.5, the actual number of erase and write times of the first type of storage unit is k, the actual number of erase and write times of the second type of storage unit is m, and the target number of erase and write times is n, then: n=k*0.5+m; for example, the capacity of the first type of storage unit is 1GB, the capacity of the second type of storage unit is 3GB, the data to be written is 3GB, and when the first mode is used to write data, the actual number of erase and write times of the first type of storage unit is 3, and the actual number of erase and write times of the second type of storage unit is 1, then the target number of erase and write times n=3*0.5+1=2.5, which is less than the sum of the actual number of erase and write times of the first type of storage unit and the actual number of erase and write times of the second type of storage unit, which is 4; that is, the erase amplification is corrected from 4 to 2.5, which is 37.5% lower than the original 4 times erase amplification.

[0075] S24: In response to the target erasure count being greater than the erasure count threshold, shutting down the first mode.

[0076] The same parts as those of the first embodiment are not described in detail.

[0077] In this embodiment, the data to be written is written into the storage unit through a target mode including the first mode and / or the second mode, and the corresponding target erase and write times are obtained, and the first wear coefficient affecting the target erase and write times is obtained, so that the target erase and write times are less than the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit, so as to reduce the erase amplification, that is, the writing mode is controlled based on the target erase and write times, which can effectively reduce the erase amplification and extend the life of the storage device while improving the write performance of the storage device.

[0078] In order to further reduce the erase amplification, the wear coefficient may be set according to the erase state threshold voltage and the programming state threshold voltage, thereby reducing the erase amplification.

[0079] See also Figure 5 , Figure 5 It is a flowchart of the third embodiment of the control method of the storage device in the present application.

[0080] like Figure 5 As shown, the following steps are included:

[0081] S31. In response to the data to be written sent by the host end, the data to be written is written into the storage unit according to the first mode with a first erased state threshold voltage and / or a first programmed state threshold voltage; wherein the first erased state threshold voltage is greater than the second erased state threshold voltage corresponding to the first wear coefficient, and the first programmed state threshold voltage is less than the second programmed state threshold voltage corresponding to the first wear coefficient.

[0082] Among them, when determining the first wear coefficient, there is a corresponding second erased state threshold voltage and a second programmed state threshold voltage, the second erased state threshold voltage is the voltage of the erased state corresponding to the first wear coefficient, and the second programmed state threshold voltage is the voltage of the programmed state corresponding to the first wear coefficient.

[0083] The reason why the number of error bits increases with the number of erase and write cycles is because of electron tunneling, which in turn causes the tunneling oxide layer of the storage unit to degrade, and the degree of degradation depends on the electron tunneling rate.

[0084] See also Figure 6 and Figure 7 , Figure 6 is a schematic diagram of threshold voltages corresponding to a first type of memory cell and a second type of memory cell in the current technology; Figure 7 This is a schematic diagram of the threshold voltage corresponding to the first type of memory cell in the third embodiment of the present application.

[0085] like Figure 6 As shown, the threshold voltage of the programming state (L1-L7) of the first type of memory cell is relatively high, and the threshold voltage of the erased state (L0) is relatively low, so the electron tunneling amount is high, and the loss caused to the memory cell is also high; Figure 7 As shown, the threshold voltage corresponding to the first type of storage cell in the current technology is SLC, and the threshold voltage corresponding to the first type of storage cell in the third embodiment is the optimized SLC. Figure 7 It can be seen that the read window corresponding to the optimized SLC is smaller than the read window of the SLC.

[0086] In some embodiments, the first erased state threshold voltage is 0.2-0.3V higher than the second erased state threshold voltage, and the first programmed state threshold voltage is 0.2-0.3V lower than the second programmed state threshold voltage. For example, the second erased state threshold voltage ranges from 0-0.5V, the second programmed state threshold voltage ranges from 2.0-2.5V, the first erased state threshold voltage ranges from 0.2-0.8V, and the first programmed state threshold voltage ranges from 1.8-2.2V.

[0087] S32. Obtain a second wear coefficient, wherein the second wear coefficient is determined by the first erased state threshold voltage and / or the first programmed state threshold voltage, and wherein the second wear coefficient is smaller than the first wear coefficient.

[0088] Among them, the erased state threshold voltage is negatively correlated with the wear coefficient, and the programmed state threshold voltage is positively correlated with the wear coefficient; the first wear coefficient is determined by the first error bit number corresponding to the first type of storage cell and the second error bit number corresponding to the second type of storage cell; the first wear coefficient is a positive number less than 1.

[0089] Specifically, by providing a first erased state threshold voltage greater than the second erased state threshold voltage and / or a first programmed state threshold voltage less than the second programmed state threshold voltage, the goal of a lower electron tunneling amount can be achieved, so that the second wear coefficient corresponding to the first erased state threshold voltage and / or the first programmed state threshold voltage is less than the first wear coefficient, that is, the second wear coefficient is less than 0.5, thereby further reducing the erase amplification and improving the life of the storage device.

[0090] S33, determining the product of the second wear coefficient and the actual erasure number of the first type of storage unit, and determining the sum of the product and the actual erasure number of the second type of storage unit as the target erasure number.

[0091] S34: In response to the target erasure times being greater than the erasure times threshold, shutting down the first mode.

[0092] The same parts as those of the first embodiment and the second embodiment are not repeated here.

[0093] In this embodiment, by increasing the erase state threshold voltage and / or decreasing the programming state threshold voltage, the electron tunneling amount is reduced, and the corresponding second wear coefficient is also smaller than the first wear coefficient, thereby further reducing the erase amplification and increasing the life of the storage device.

[0094] In order to further reduce the erase amplification, the wear coefficient may be set according to the erase start voltage and the program start voltage, thereby reducing the erase amplification.

[0095] See also Figure 8 , Figure 8 It is a flowchart of the fourth embodiment of the control method of the storage device in the present application.

[0096] like Figure 8 As shown, the following steps are included:

[0097] S41. In response to the data to be written sent by the host end, the data to be written is written into the storage unit according to the first mode, based on the first erase start voltage and / or the first programming start voltage; wherein the first erase start voltage is less than the second erase start voltage corresponding to the first wear coefficient, and the first programming start voltage is less than the second programming start voltage corresponding to the first wear coefficient.

[0098] Among them, multiple pulses are required during the conversion process between the programming state and the erased state; when determining the first wear coefficient, there are corresponding second erased state threshold voltage, second programming state threshold voltage, second erase start voltage and second programming start voltage, the second erase start voltage is the starting voltage for converting from the programming state to the erased state corresponding to the first wear coefficient, and the second programming start voltage is the starting voltage for converting from the erased state to the programming state corresponding to the first wear coefficient.

[0099] A lower erase start voltage and / or programming start voltage can reduce the degradation rate of the memory cell tunneling oxide layer. The degradation rate depends on the electron tunneling rate. The higher the erase start voltage and programming start voltage, the higher the electron tunneling amount and the higher the loss to the memory cell.

[0100] S42. Obtain a third wear coefficient, wherein the third wear coefficient is determined by the first erase start voltage and / or the first program start voltage, and wherein the third wear coefficient is smaller than the first wear coefficient.

[0101] Among them, the erase start voltage is positively correlated with the wear coefficient, and the programming start voltage is positively correlated with the wear coefficient; the first wear coefficient is determined by the first error bit number corresponding to the first type of storage cell and the second error bit number corresponding to the second type of storage cell; the first wear coefficient is a positive number less than 1.

[0102] Therefore, by providing a first erase start voltage that is less than the second erase start voltage and / or a first programming start voltage that is less than the second programming start voltage, the goal of a lower electron tunneling amount can be achieved, so that the third wear coefficient corresponding to the first erase start voltage and / or the first programming start voltage is less than the first wear coefficient, that is, the third wear coefficient is less than 0.5, thereby further reducing the erase amplification and improving the life of the storage device.

[0103] S43, determining the product of the third wear coefficient and the actual erasure number of the first type of storage unit, and determining the sum of the product and the actual erasure number of the second type of storage unit as the target erasure number.

[0104] S44: In response to the target erasure count being greater than the erasure count threshold, shut down the first mode.

[0105] The same parts as those of the first embodiment and the second embodiment are not repeated here.

[0106] In some embodiments, while using the first erase start voltage and the first programming start voltage, the first erase state threshold voltage and the first programming state threshold voltage can also be used, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and improving the life of the storage device.

[0107] In this embodiment, by lowering the erase start voltage and / or the programming start voltage, the electron tunneling amount is reduced, and the corresponding third wear coefficient is also smaller than the first wear coefficient, which further reduces the erase amplification and increases the life of the storage device.

[0108] In order to further reduce the erase amplification, the wear coefficient may be set according to the erase step value and the programming step value, thereby reducing the erase amplification.

[0109] See also Fig. 9 , Fig. 9 It is a flowchart of the fifth embodiment of the control method of the storage device in the present application.

[0110] like Fig. 9 As shown, the following steps are included:

[0111] S51. In response to the data to be written sent by the host end, the data to be written is written into the storage unit according to the first mode with a first erase step value and / or a first programming step value; wherein the first erase step value is smaller than the second erase step value corresponding to the first wear coefficient, and the first programming step value is smaller than the second programming step value corresponding to the first wear coefficient.

[0112] Among them, multiple pulses are required during the conversion process between the programming state and the erased state; when determining the first wear coefficient, there are corresponding second erased state threshold voltage, second programming state threshold voltage, second erase start voltage, second programming start voltage, second erase step value and second programming step value, the second erase step value is the voltage difference between adjacent pulses corresponding to the first wear coefficient for converting from the programming state to the erased state, and the second programming step value is the voltage difference between adjacent pulses corresponding to the first wear coefficient for converting from the erased state to the programming state.

[0113] The degradation speed depends on the electron tunneling rate. When the erase step value and programming step value are high, the electron tunneling amount is high and the loss to the storage cell is also high. Lower erase step value and / or programming step value can reduce the degradation speed of the storage cell tunneling oxide layer.

[0114] S52. Obtain a fourth wear coefficient, wherein the fourth wear coefficient is determined by the first erase step value and / or the first programming step value, and wherein the fourth wear coefficient is smaller than the first wear coefficient.

[0115] Among them, the erase step value is positively correlated with the wear coefficient, and the programming step value is positively correlated with the wear coefficient; the first wear coefficient is determined by the first error bit number corresponding to the first type of storage unit and the second error bit number corresponding to the second type of storage unit; the first wear coefficient is a positive number less than 1.

[0116] Therefore, by giving a first erase step value that is smaller than the second erase step value and / or a first programming step value that is smaller than the second programming step value, the goal of a lower electron tunneling amount can be achieved, so that the fourth wear coefficient corresponding to the first erase step value and / or the first programming step value is smaller than the first wear coefficient, that is, the fourth wear coefficient is less than 0.5, thereby further reducing the erase amplification and improving the life of the storage device.

[0117] S53: Determine the product of the fourth wear coefficient and the actual erasure number of the first type of storage unit, and determine the sum of the product and the actual erasure number of the second type of storage unit as the target erasure number.

[0118] S54: In response to the target erasure count being greater than the erasure count threshold, shut down the first mode.

[0119] The same parts as those of the first embodiment and the second embodiment are not described in detail.

[0120] In some embodiments, the first erase state threshold voltage and the first programming state threshold voltage may be used together with the first erase step value and the first programming step value, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and improving the life of the storage device.

[0121] In other embodiments, the first erase start voltage and the first programming start voltage may be used together with the first erase step value and the first programming step value, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and increasing the life of the storage device.

[0122] In some further embodiments, while adopting the first erase step value and the first programming step value, the first erase start voltage, the first programming start voltage, the first erase state threshold voltage and the first programming state threshold voltage can be adopted, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and improving the life of the storage device.

[0123] In this embodiment, by reducing the erase step value and / or the programming step value, the electron tunneling amount is reduced, and the corresponding fourth wear coefficient is also smaller than the first wear coefficient, which further reduces the erase amplification and improves the life of the storage device.

[0124] In order to show the entire writing process, Fig.10 To express.

[0125] Fig.10 It is a principle flow chart of writing the data to be written into the storage unit in this application.

[0126] like Fig.10As shown, the target number of erase and write times is set to n, the total number of erase and write times of the storage device is N, the number of erase and write times of the first type of storage unit is k, the number of erase and write times of the second type of storage unit is m, and the wear coefficient is a; when starting to write data, Cycle n=0, SLC cycle k=0, TLC cycle m=0, and data is written to the entire disk of the storage device once. If the first mode is used for writing, that is, the SLC mode is used for writing, then k=K+1, m=m, and the target number of erase and write times is: n=k*a+m. When n is greater than N, the life of the flash memory block corresponding to the storage unit is exhausted, and the WriteBooster function is turned off, that is, the first mode is turned off; if the second mode is used for writing, then k=k, m=m+1, and the target number of erase and write times is: n=k*a+m.

[0127] See also Fig.11 , Fig.11 It is a structural diagram of an embodiment of a storage device of the present application.

[0128] like Fig.11 As shown, the storage device 600 includes a processor 610 and a storage unit 620. The processor 610 is coupled to the storage unit 620 and the host end, and executes instructions during operation to implement the above storage device control method.

[0129] See also Fig.12 , Fig.12 It is a structural schematic diagram of an embodiment of the electronic device of the present application.

[0130] like Fig.12 As shown, the electronic device 70 includes a processing device 71 and a storage device 600. The processor is coupled to the storage device 600 and executes instructions during operation to implement the above-mentioned storage device control method.

[0131] The above technical scheme provides a control method for a storage device, in response to the data to be written sent by the host end, the data to be written is written into the storage unit according to the target mode; wherein the target mode includes at least the first mode and / or the second mode, the first mode includes first storing in the first type of storage unit, and then migrating the data stored in the first type of storage unit to the second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the amount of storable data of each first type of storage unit is less than the amount of storable data of each second type of storage unit; according to the target mode, the target erase and write times are counted; wherein the target erase and write times are less than the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit; in response to the target erase and write times being greater than the erase and write times threshold, the first mode is turned off. That is, in the present application, the data to be written is written into the storage unit through a target mode including the first mode and / or the second mode, the corresponding target erase and write times are obtained, and the target erase and write times are set to be less than the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit, so as to reduce the erase amplification, that is, the writing mode is controlled based on the target erase and write times, which can improve the write performance of the storage device while effectively reducing the erase amplification and extending the life of the storage device.

[0132] In the several embodiments provided in the present application, it should be understood that the disclosed storage devices, electronic devices and methods can be implemented in other ways. For example, the embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0133] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for controlling a storage device, characterized in that: include: In response to the data to be written sent by the host, the data to be written is written into the storage unit according to the target mode; wherein the target mode includes at least a first mode and / or a second mode, the first mode includes firstly storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in a second type of storage unit; wherein the amount of data that can be stored in each of the first type of storage units is less than the amount of data that can be stored in each of the second type of storage units; Counting target erasure times according to the target mode; wherein the target erasure times are less than the sum of the actual erasure times of the first type of storage unit and the actual erasure times of the second type of storage unit; In response to the target erasure count being greater than an erasure count threshold, the first mode is turned off.

2. The control method according to claim 1, characterized in that: The counting of target erasing and writing times according to the target mode comprises: Obtaining a first wear coefficient, wherein the first wear coefficient is determined by a first number of error bits corresponding to a first type of storage unit and a second number of error bits corresponding to a second type of storage unit; wherein the first wear coefficient is a positive number less than 1; The product of the first wear coefficient and the actual number of erasures of the first type of storage unit is determined, and the sum of the product and the actual number of erasures of the second type of storage unit is determined as the target number of erasures.

3. The control method according to claim 2, characterized in that: The first wear coefficient is obtained by: Erasing and writing the first type of storage unit and the second type of storage unit the same number of times to obtain a first number of error bits corresponding to the first type of storage unit and a second number of error bits corresponding to the second type of storage unit; The first wear coefficient is determined according to the first number of error bits and the second number of error bits.

4. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: According to a first mode, the data to be written is written into a storage unit with a first erased state threshold voltage and / or a first programmed state threshold voltage; wherein the first erased state threshold voltage is greater than a second erased state threshold voltage corresponding to a first wear coefficient, and the first programmed state threshold voltage is less than a second programmed state threshold voltage corresponding to the first wear coefficient; The counting of target erasing and writing times according to the target mode comprises: Obtaining a second wear coefficient, wherein the second wear coefficient is determined by the first erased state threshold voltage and / or the first programmed state threshold voltage; wherein the second wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by a first error bit number corresponding to a first type of storage cell and a second error bit number corresponding to a second type of storage cell; the first wear coefficient is a positive number less than 1; The product of the second wear coefficient and the actual number of erasures of the first type of storage unit is determined, and the sum of the product and the actual number of erasures of the second type of storage unit is determined as the target number of erasures.

5. The control method according to claim 4, characterized in that: The first erased state threshold voltage is 0.2-0.3V higher than the second erased state threshold voltage, and the first programmed state threshold voltage is 0.2-0.3V lower than the second programmed state threshold voltage.

6. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: According to a first mode, the data to be written is written into a storage unit based on a first erase start voltage and / or a first programming start voltage; wherein the first erase start voltage is less than a second erase start voltage corresponding to a first wear coefficient, and the first programming start voltage is less than a second programming start voltage corresponding to the first wear coefficient; The counting of target erasing and writing times according to the target mode comprises: Obtaining a third wear coefficient, wherein the third wear coefficient is determined by the first erase start voltage and / or the first programming start voltage; wherein the third wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by a first error bit number corresponding to a first type of storage cell and a second error bit number corresponding to a second type of storage cell; and the first wear coefficient is a positive number less than 1; The product of the third wear coefficient and the actual number of erasures of the first type of storage unit is determined, and the sum of the product and the actual number of erasures of the second type of storage unit is determined as the target number of erasures.

7. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: According to a first mode, the data to be written is written into a storage unit with a first erase step value and / or a first programming step value; wherein the first erase step value is smaller than a second erase step value corresponding to a first wear coefficient, and the first programming step value is smaller than a second programming step value corresponding to the first wear coefficient; The counting of target erasing and writing times according to the target mode comprises: Obtaining a fourth wear coefficient, wherein the fourth wear coefficient is determined by the first erase step value and / or the first programming step value; wherein the fourth wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by a first error bit number corresponding to a first type of storage unit and a second error bit number corresponding to a second type of storage unit; the first wear coefficient is a positive number less than 1; The product of the fourth wear coefficient and the actual number of erasures of the first type of storage unit is determined, and the sum of the product and the actual number of erasures of the second type of storage unit is determined as the target number of erasures.

8. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: Acquire available space of the storage device, wherein the storage device includes a plurality of storage units; In response to the available space of the storage device being greater than or equal to the preset space, writing the data to be written into the storage device according to the first mode; or, In response to the available space of the storage device being less than the preset space, the data to be written is written into the storage device according to the second mode.

9. A storage device, characterized in that: The storage device includes a processor and a storage unit. The processor is coupled to the storage unit and a host end, and executes instructions when working to implement the control method described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The system comprises a processing device and a storage device, wherein the processing device is coupled to the storage device and executes instructions when working to implement the control method according to any one of claims 1 to 8.

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