Mode register update (MRUPD) mode

Abstract

A configuration register update mode may be implemented as an MRUPD (mode register update) mode for a DRAM (dynamic random access memory) device. In one example, the MRUPD may also be applied to update the RCD (register clock driver). In an update mode, a memory device (RCD or DRAM) may perform configuration of any number of configuration registers with in-band register writes. In-band register writes may be used to configure DFE (Decision Feedback Equalization) settings, as well as other configuration settings for non-DFE configurations of memory device interfaces.

Description

[0001] priority

[0002] This application is a non-provisional application of U.S. Provisional Application No. 63 / 596,257 filed on November 4, 2023, and claims priority to that provisional application. Technical Field

[0003] The specification relates generally to computer memory, and more particularly, the specification relates to memory interface training. Background Art

[0004] The memory controller can use MRW (Mode Register Write) to set the DRAM device configuration and perform some training. The memory controller traditionally needs to train the CA bus before commands such as MRW can be reliably sent to the DRAM devices. Therefore, programming the DRAM (Dynamic Random Access Memory) is performed using a sideband bus (e.g., SMBus (System Management Bus)) before training the CA (Command / Address) bus and the DQ (Data) bus. The sideband bus operates at a very low speed (approximately megahertz (MHz)) relative to the CA bus and the DQ bus (approximately gigahertz (GHz)). Using the sideband bus for training can cause significant delays in training.

[0005] Available DRAM devices have multiple training phases. Training is performed using MPC (Multi-Purpose Command) operations, which require an MPC opcode table. MPC commands can access a limited number of mode registers in the DRAM because there is not enough flexibility in the MPC commands to access all DRAM mode registers. Training with MPC is slow and is typically limited to training the DFE (Decision Feedback Equalization) registers. The use of MPC operations is expected to increase, which will increase the number of MPC opcodes required. The increase in MPC opcodes and training does not scale to all possible future training. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following description includes a discussion of the figures with descriptions given by way of examples of implementations. The accompanying drawings should be understood by way of example and not by way of limitation. As used herein, reference to one or more examples should be understood to describe a specific feature, structure or characteristic included in at least one implementation of the present invention. Phrases such as "in one example" or "in an alternative example" that appear herein provide examples of implementations of the present invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0007] Figure 1A is a block diagram of an example of a system having a memory module.

[0008] Figure 1B is a block diagram of an example of a system with unregistered memory modules.

[0009] Figure 2 is a block diagram of an example of a memory module with an RCD implementing an in-band configuration mode via an MRUPD.

[0010] Figure 3 is a block diagram of an example of a memory module having a memory device implementing an in-band configuration mode via MRUPD.

[0011] Figure 4A-4B is an example of a timing diagram for the MRUPD command timing.

[0012] Figure 5A is an example of a register field table for training mode available through MRUPD mode.

[0013] Figure 5B This is a first example of a command table for MRUPD based on seven CA pins.

[0014] Figure 5C This is a second example of a command table for MRUPD based on seven CA pins.

[0015] Figure 6 is a timing diagram for an example of a multi-cycle MRUPD command followed by a single-cycle MRUPD command.

[0016] Fig. 7A is an example of a command table for mode register access.

[0017] Figure 7B is an example of a timing diagram for a mode register access command.

[0018] Figure 8 is a flow chart for an example of the MRUPD process.

[0019] Fig. 9 is a state diagram of an example of MRUPD.

[0020] Fig.10 is a block diagram of an example of a memory subsystem in which an in-band configuration mode may be implemented.

[0021] Figures 11A-11B is a block diagram of an example of a CAMM system in which alarm signal testing may be implemented.

[0022] Fig.12 is a block diagram of an example of a computing system in which an in-band configuration mode may be implemented.

[0023] Fig.13is a block diagram of an example of a multi-node network in which an in-band configuration mode may be implemented.

[0024] What follows is a description of certain details and implementations, including non-limiting descriptions of the accompanying drawings, which may depict some or all examples, and other potential implementations. DETAILED DESCRIPTION

[0025] As described herein, a configuration register update mode may be implemented as an MRUPD (mode register update) mode for a DRAM (dynamic random access memory) device. In one example, the MRUPD may also be applied to update an RCD (register clock driver). In one example, the MRUPD may be applied to the RCD by selectively setting the RCD to a non-pass-through mode. In one example, the MRUPD may be applied to the RCD by setting a field in the command indicating whether the command is applied to the RCD or the DRAM. In update mode, a memory device (RCD or DRAM) may utilize in-band register writes to perform configuration of any number of configuration registers. In-band register writes may be used to configure DFE (decision feedback equalization) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

[0026] As described herein, in-band communication can be used to train any DRAM register or RCD register before training CS (chip select). Using the MRUPD mode can be used to update other registers, thereby avoiding the use of the SMBus (system management bus), thereby increasing training and setup speed. MRUPD extends the idea of ​​using in-band communication to update registers. The use of MRUPD can replace at least some MPC (multi-purpose command) operations. When the bus is not fully trained, the system can use in-band communication for training.

[0027] The present invention can be used for all training steps and is extended to MRUPD to speed up the training algorithm and allow any MR (mode register) to be updated through MRUPD mode. The following information describes an example of applying the MR update mode. After exiting MRUPD mode, the system can execute a conventional single-cycle MRW (mode register write) or MRUPD command to update any register. The ability to update registers using MRUPD simplifies host commands. Additionally, the system does not need to use different commands to adjust the mode register for different operations before or after training and at run time; instead, the same command can be used for all states, thereby simplifying the command operation of the host.

[0028] The described MRUPD mode can replace operations currently performed using MPC commands with MRUPD operations and mode register accesses. The ability to replace MPC operations with MRUPD operations can reduce the growing need for MPC opcodes; otherwise, the opcode table can be quickly exhausted. In one example, MRUPD operations can be used to set CA DFE (Command / Address Decision Feedback Equalization), CSDFE (Chip Select Decision Feedback Equalization), and CS / CA Vref (Chip Select / Command / Address Voltage Reference) scans. The Vref scan applies different values ​​of Vref settings to set the voltage that provides the best system performance.

[0029] In one example, MRUPD mode enables the system to de-gate registers that are only accessible via MRW (Mode Register Write). Adding access to registers improves the capabilities of subsequent DRAM architectures that are expected to have CA / CSDFE / Vref scans that require a large number of registers to be configured during the training phase. For example, with 8 mode registers, utilizing 10-20 CA DFE 1-tap settings times 10-20 Vref settings times 2 gain settings, the system can have approximately 800 register accesses as a starting point. CS Vref scans and CSDFE are expected to have similar significant register access sequences, which are currently predicted to significantly increase the MPC opcode table. With the ability to access registers via MRUPD, with faster access times compared to MPC operations, the time and efficiency of training can be significantly improved.

[0030] MRUPD mode can reduce the total number of commands required by the host system for the command truth table. For example, the ability to train through MRUPD can eliminate the need for commands such as Vref CA, Vref CS, and MPC. Removing these commands can save coding options for future commands. In one example, the functionality provided by the command can be moved to the MR register configuration so that the DRAM knows the exact operation that needs to be performed. In one example, the system has no restrictions on accessing the MR using MRUPD or MRW.

[0031] MRUPD mode can improve the time and efficiency of initialization and training. In one example, the host at runtime can implement ZQCAL (impedance calibration) through a single-cycle MRW instead of sending MPC. MRUPD is an in-band command, avoiding the use of sideband. In one example, the system can have default settings (e.g., DFE, ODT (on-die termination), Vref) to achieve higher speed operation in normal mode. The system can use MRUPD mode to write default settings to the mode register, optionally using the M3C (memory module management control) bus for debugging.

[0032] In one example, the system can apply MRUPD mode for DRAM to automatically perform any DFE or Vref scans using built-in logic. Currently, MRW cannot be used to access MPC bound registers, which refers to registers associated with access via MPC operations. By eliminating MPC operations for registers, registers can be accessed using MRW commands via MRUPD mode.

[0033] In one example, the system can combine RWUPD (Register Word Update) and MRUPD. The system can selectively apply the MRUPD command to RCD or DRAM based on the selection of the target device in the command (e.g., by using a bit in the command), without requiring a separate RWUPD for RCD. In one example, the system integrates MRUPD and MRW into a multi-cycle command during initialization and training, and after training, the system can use a single-cycle MRUPD command that also performs MRW work, thereby reducing the number of commands.

[0034] Figure 1A 1 is a block diagram of an example of a system with a memory module. System 102 includes a socket 110 coupled to a DIMM (dual in-line memory module) 120. Socket 110 represents a CPU (central processing unit) socket, and socket 110 may include a CPU 112 and a memory controller 114. DIMM 120 includes a plurality of DRAM devices. DIMM 120 represents any type of memory module, and the memory module may be a DIMM or a CAMM (compression attached memory module).

[0035] System 102 illustrates an example of a system having memory devices that share a control bus or command bus (CA (command / address) bus 126[0] for one channel and CA bus 126[1] for another channel) and a data bus (data bus 116[0] for one channel and data bus 116[1] for another channel). The memory devices are represented as DRAM (dynamic random access memory) devices. Each channel has N DRAM devices, DRAM 132[1:N] (collectively referred to as DRAM devices 132) for one channel, and DRAM 134[1:N] (collectively referred to as DRAM devices 134) for another channel, where N can be any integer. In one example, N includes one or more ECC (error checking and correction) DRAM devices in addition to the data devices. Each DRAM device 132 and each DRAM device 134 can represent a memory chip having a command bus interface to a memory controller 114, where the interface can be through RCD 128.

[0036] In one example, two separate channels share the CA bus 124 connection between the memory controller 114 and the RCD 128. In one example, separate channels will have separate CA buses. DRAM devices can be accessed individually using device specific commands, and can be accessed in parallel using parallel commands.

[0037] RCD (Registered Clock Driver) 128 (which may also be referred to as a registered clock driver) represents a controller for the DIMM 120. In one example, the RCD 128 receives information from the memory controller 114 and buffers the signals to the various DRAM devices. By buffering the incoming command signals from the memory controller 114, the controller only sees the load of the RCD 128 on the command / address (CA bus 124) and can then control the timing and signaling to the DRAM devices.

[0038] In one example, RCD 128 controls command signals to DRAM device 132 via CA bus 126[0] and controls signals to DRAM device 134 via CA bus 126[1]. In one example, RCD 128 has independent command ports for separate channels. In one example, DIMM 120 includes data buffers for buffering data bus signals between DRAM devices of DIMM 120 and memory controller 114.

[0039] Data bus 116[0] provides a data bus for DRAM device 132, which is buffered by DB (data buffer) 142[1:N] (collectively referred to as DB 142). Data bus 116[1] provides a data bus for DRAM device 134, which is buffered by DB 144[1:N] (collectively referred to as DB 144). System 102 shows a one-to-one relationship between data buffers and DRAM devices. In one example, the number of data buffers is less than the number of DRAM devices, and the DRAM devices share one data buffer.

[0040] CA bus 126[0] and CA bus 126[1] (collectively referred to as CA bus 126) are typically single-sided or unidirectional buses for communicating command and address information from memory controller 114 to DRAM devices. Thus, CA bus 126 may be a multi-drop bus. Data bus 116[0] and data bus 116[1] (collectively referred to as data bus 116) are conventionally bidirectional point-to-point buses.

[0041] In one example, the memory controller 114 includes one or more sideband bus connections, connected to other devices in the system 102. Sideband bus refers to a bus other than the CA bus 124 and the data bus 116. As shown, the memory controller 114 has an SMBus (system management bus, shown as "SMB" in the system 102 for simplicity) to connect to the RCD 128. In one example, the memory controller 114 has an SMBus connection or other SBB (sideband bus) to connect to the DRAM device. In one example, the SBB connection represents an M3C (memory module management control) bus. Both SMBus and SBB connections represent the sideband bus communication in the system 102.

[0042] The sideband bus enables the memory controller 114 to provide commands to the device over a connection other than the CA bus. Communications on the sideband bus are not in-band because the commands are not received on the CA bus. In one example, communications on the sideband bus enable the memory controller 114 to send a command to trigger the device to enter a pre-training update mode that uses in-band communications to perform configuration updates.

[0043] In one example, the DIMM 120 includes a PMIC (Power Management Integrated Circuit) 154 for managing power state and power usage for the memory. The power state may affect the use of the interface between the memory controller 114 and the DIMM 120.

[0044] In one example, DIMM 120 includes SPD (Serial Presence Detect) 152. SPD 152 provides information about components on DIMM 120. SPD 152 enables memory controller 114 to automatically access information about components. The system can adjust the configuration of components as needed to improve communication between memory controller 114 and memory devices.

[0045] In one example, the system 102 supports a RWUPD mode to configure the RCD interface to the CA bus 124. In one example, the system 102 supports an MRUPD mode to configure a DRAM device. The configuration of the DRAM device may include configuration of a data bus interface, configuration of a CA bus interface, or configuration of both a CA bus interface and a data bus interface. With the update mode, the system 102 supports writing configuration parameters in-band before training the CS (chip select).

[0046] In one example, utilizing the update mode, the system 102 can speed up back-end and front-end training for all parameter sweeps. With the increase of in-band commands to perform configuration, the system 102 can reduce the use of the sideband bus. Due to the significant speed difference between in-band communication and out-of-band communication (e.g., sideband bus usage), where in-band communication can be several orders of magnitude faster, using in-band communication for configuration updates can improve system boot time.

[0047] The CA bus 124 provides a link for the memory controller 114 to provide command and address information to identify the command to be executed and the address for executing the command. It will be appreciated that the interface of the command bus (e.g., CA bus 124) can be trained to recognize the preferred settings to ensure that the commands are properly received at the RCD 128. Training can include iterating through different configuration settings to determine the settings with the best performance, which settings can vary from system to system.

[0048] With the introduction of the DDR (Double Data Rate) mode of the command bus, the interface of the command bus may include a DFE (Decision Feedback Equalization) with multiple taps (e.g., 2 or 4 taps) to ensure the correct data eye on the CA signal line. DFE refers to a non-linear equalization circuit that uses information about previously received bits to determine the bit currently being received and processed. Other configuration settings may include reference voltage settings, current settings, and other configuration settings. Training setting parameters to ensure correct communication on the command bus.

[0049] In one example, when the system 102 supports the MRUPD mode, the update mode can reduce or eliminate the need to configure the multi-purpose command (MPC command). In one implementation, the system 102 can replace the MPC command, replace the voltage reference for the chip select (VrefCS) command, and replace the voltage reference for the command / address (VrefCA) command. Taking full advantage of the MRUPD mode for all training can remove the MPC encoded opcode table. Alternatively, the system can limit the opcode to a few commands. Removing and reducing both the MPC opcodes can save hardware logic within the DRAM device.

[0050] In one example, the MRUPD mode can be applied to DRAM or RCD. The RCD can receive a command and determine whether the command applies to the DRAM configuration or the RCD configuration. If the command applies to the RCD, the RCD can apply the command to its own configuration. If the command applies to the DRAM, the RCD can pass the command to the selected DRAM.

[0051] The described MRUPD mode can enable configuration for all possible training modes. In one example, enabling configuration for all training modes includes the following: triggering the device to enter update mode, issuing a configuration write operation using two commands, including one command for the register address and another command for the configuration data value. The register write operation is an in-band command, which speeds up the setting of the configuration.

[0052] The above can be used for the CA bus in double data rate DDR mode. If the DRAM defaults to MRUPD mode / state immediately after power-up, the system can perform MRUPD before CSTM (chip select training mode) and before CATM (command / address training mode). Such operations can set the termination and Vref values ​​through in-band commands instead of using sideband communication. Although MRUPD can utilize single cycle commands instead of MPC, it can require a multi-cycle chip select feature.

[0053] In one example, MRUPD can be applied to a DRAM device or an RCD. Thus, a system can use the MRUPD command where a RWUPD command is normally used. In one example, if a system includes an RCD, the memory controller can signal whether the MRUPD command is for the RCD or the DRAM. MRUPD can potentially replace the MRW (mode register write) and MRR (mode register read) commands. In this case, MRUPD with a single cycle can be used instead of the MRW command.

[0054] An MRUPD command with multiple cycles / phases can be used instead of an MPC (Multi-Purpose) command. In one example, a system with MRUPD enabled does not need to send multiple MPC commands to update configuration settings. Instead, the memory controller only needs to send MRUPDE to enter MRUPD mode and then continue to send data until MRUPDX is sent to exit MRUPD mode. In one example.

[0055] Figure 1B 1 is a block diagram of an example of a system with unregistered memory modules. System 104 includes many of the same components as described in system 102. Where system 102 includes RCD 128, and is therefore an RDIMM (registered DIMM), system 104 has DIMM 160, which is a UDIMM (unregistered DIMM) or CAMM.

[0056] In system 104, CA bus 124 connects memory controller 114 directly to DRAM devices. In one example, a single CA bus 124 is used, as shown, where different channels can use different time slices of the CA bus. In one example, the system can use separate system buses to separate channels instead of using a single CA bus.

[0057] Figure 2 is a block diagram of an example of a memory module with an RCD having an in-band configuration mode. System 200 illustrates a system according to an example of system 102 or system 104 .

[0058] The system 200 includes a dual in-line memory module (DIMM) 210, which represents a memory module having a module controller. The RCD 220 represents a module controller. The RCD 220 is connected to a host (not specifically shown) via a CA bus 224. The RCD 220 has an interface to the CA bus 224, which can be configured by setting the value of a register 222.

[0059] The register 222 may include, but is not limited to, DFE settings and terminal settings. Each register may include one or more configuration settings. The register 222 specifically shows DFE to indicate the configuration settings of the DFE of the CA bus 224, shows VREF to indicate the Vref configuration settings, and shows CA to indicate other settings, such as terminal settings or other configurations for the CA bus 224.

[0060] RCD 220 may be connected to DRAM device 232 via CA bus 244[0] and to DRAM device 234 via CA bus 244[1]. In one example, the configuration of register 222 is applied to the interface of CA bus 224, and the DRAM devices will have a different configuration for the CA bus interconnection than RCD 220.

[0061] Applying the MRUPD pattern to RCD 220 can enable system 200 to utilize the MRUPD pattern to complete DCSTM, and use in-band communication to set configuration. In one example, RCD 220 utilizes SMBus communication to enter MRUPD, and exits MRUPD in response to CS assertion. In one example, when RCD 220 is in MRUPD, system 200 has settings / configuration qualifiers. The qualifier can be, for example, chip selection (e.g., DCS0 / 1), wherein the assertion of chip selection can determine which channel is configured. In one example, each training mode can indicate which qualifier is used for specific training.

[0062] In one example, the host may send a register address (e.g., a RW address) and an opcode for a MRUPD operation and perform the update operation (e.g., using hardware acceleration) in an inner loop using the MRUPD qualifier. In one example, the system 200 triggers the RCD 220 to exit MRUPD by writing to the RCD register (RW32) or by an SMBus command. In one example, the register 222 may include a RW32 RCD register.

[0063] Figure 3 is a block diagram of an example of a memory module with a memory device having an in-band configuration mode. System 300 illustrates a system according to the example of system 102 or the example of system 200 .

[0064] The system 300 includes a dual in-line memory module (DIMM) 310, which represents a memory module having a module controller. The RCD 320 represents a module controller. The RCD 320 is connected to a host (not specifically shown). The RCD 320 can be connected to a DRAM device 332 via a CA bus 344[0], and can be connected to a DRAM device 334 via a CA bus 344[1].

[0065] In one example, DRAM device 332 includes register 336, and DRAM device 334 includes register 338. In one example, the configuration of register 336 applies to the interface of DRAM device 332 to CA bus 344[0]. In one example, the configuration of register 338 applies to the interface of DRAM device 334 to CA bus 344[1].

[0066] Registers 336 and 338 may include, but are not limited to, DFE settings and termination settings. Registers 336 and 338 specifically illustrate DFE to represent a DFE configuration register for storing one or more configuration settings for the DFE of the CA bus, VREF to represent a Vref configuration setting, and CA to represent other settings, such as termination settings or other configurations for the CA bus. In one example, MRUPD may be applied to all configuration settings in a DRAM device for the CA bus. MRUPD may provide a training mode for training all configuration registers for the CA bus. Thus, system 300 may include a DFE configuration register and a plurality of additional configuration registers for additional configuration settings.

[0067] The system 300 enables a DRAM mode register update (MRUPD) mode. In one example, the MRUPD mode has MRUPDE (MRUPD entry) and MRUPDX (MRUPD exit). In one example, MRUPD is applied to DDR6 (Double Data Rate Version 6). In one example, MRUPD is used in conjunction with an M3C bus. Application of the MRUPD mode can replace the MPC commands, VrefCA, and VrefCS commands. If there is no such command, the MPC opcode table is not required. Removing the table saves logic in the DRAM and allows access to the mode registers at any time and without any settings.

[0068] In one example, MRUPD in DRAM provides an update mode that DRAM is used for all training steps. With the proposed MRUPD, to scan any parameter, the system does not need to access through SMBus, which is significantly slower than in-band commands. Performing training through in-band access can speed up back-end training steps, such as CSTM, CATM, and DFE training algorithms, and improve system boot time.

[0069] In one example, the in-band register write is a MRW (Mode Register Write) based on a command on the command bus prior to executing CATM. In one example, the system 300 provides a first MPC to enter MRUPD mode. A second MPC may trigger exiting MRUPD mode.

[0070] Figure 4A Schematic 402 shows a timing diagram for MRUPD command timing. Schematic 402 shows various signals and example sequences over time. The bold dashed lines represent time breaks, indicating that the number of clock cycles involved in signal communication may be different than shown.

[0071] Signal 410 represents the host clock (CLK), which has CK_t (clock master) and CK_c (clock complementary) signals, which represent timing signals. Signal 420 represents command and address signal lines CA[6:0] (command / address bits 6 to 0), which represent commands sent by the host. Signal 430 represents an internal command signal CMD (command). The CMD signal represents a decoding operation performed internally on the DRAM device in response to a host command. Signal line 440 represents chip select. CS0_n (chip select 0, enumerated for each individual DRAM device) represents a chip select for a target DRAM device to be configured using MRUPD.

[0072] The CA signal shows MRUPD Command 0, MRUPD Command 1, and MRUPD Command 2 for the training sequence. After training, the CA signal can send any valid command. After training, the CMD can similarly generate any valid command and perform a single cycle CS assertion on the CS signal.

[0073] In a response to MRUPD command 0, CMD may be MRUPD ADDR (address, or MRA (MRUPD address)), and CS signal may assert CS signal for tMRUPD_CS time (for timing of CS signal in MRUPD mode). MRUPD command 0 may be an MRUPD mode command that triggers entry into MRUPD mode. In one example, there is tMRUPD_setup time (for setup time of MRUPD mode) before CS assertion, and tMRUPD_hold time (for hold time of MRUPD mode) after CS assertion.

[0074] In a response to MRUPD command 1, CMD can be MRUPD data 0, such as ZQCALS (impedance calibration start) or any other training pattern, and CS signal can assert CS signal for tMRUPD_CS. Similarly, in a response to MRUPD command 2, CMD can be MRUPD data 1, such as ZQCALS or any other training pattern, and CS signal can assert CS signal for tMRUPD_CS.

[0075] Schematic diagram 402 shows the use of multi-cycle CS used during MRUPD mode. Multi-cycle CS is used to allow the DRAM time to latch the signal because there is no Vref CS, no Vref CA or other training. After training, the CS0_n signal line shows a normal single-cycle CS. Using the multi-cycle CS signal, the system can clearly identify the DRAM in MRUPD mode (until CS / CA is trained) or normal mode.

[0076] In schematic 402, in one example, the host writes to the MR register field MRUPDX using MRUPD to exit. The DRAM can exit MRUPD to execute any valid single-cycle CS-based command (e.g., a read with tMRD (memory read time) timing) and MRUPD single-cycle command. Thus, the system can perform a configuration update for CS and can perform a configuration update for CA.

[0077] Figure 4BSchematic 404 shows another timing diagram for MRUPD exit timing. Schematic 404 shows various signals and example sequences over time. The bold dashed lines represent time breaks, indicating that the number of clock cycles involved in signal communication may be different than shown.

[0078] Signal 450 represents the host clock (CLK), which has CK_t (clock master) and CK_c (clock complementary) signals, which represent timing signals. Signal 460 represents command and address signal lines CA[6:0] (command / address bits 6 to 0), which represent commands sent by the host. Signal 470 represents the internal command signal CMD (command). The CMD signal represents a signal for a DRAM device. Signal line 480 represents chip select. CS0_n (chip select 0, enumerated for each individual DRAM device) represents the chip select of the target DRAM device to be configured using MRUPD.

[0079] The CA signal shows MRUPD Command 0, MRUPD Command 1, and MRUPD Command 2 for the training sequence. After training, the CA signal can send any valid command. After training, the CMD can similarly generate any valid command and perform a single cycle CS assertion on the CS signal. Schematic 402 shows the timing of the different stages of MRUPD, showing the timing of tMRUPD_PxDelay (timing between MRUPD commands) between MRUPD Command 0 and MRUPD Command 1.

[0080] In a response to MRUPD command 0, CMD may be MRUPD ADDR (address, or MRA (MRUPD address)), and CS signal may assert CS signal for tMRUPD_CS time (timing of CS signal in MRUPD mode). In one example, there is tMRUPD_setup time (setup time of MRUPD mode) before CS assertion, and tMRUPD_hold time (hold time of MRUPD mode) after CS assertion. Schematic diagram 404 shows the timing of MRUPD operation, showing the timing of tMRUPD_Delay from MRUPD command 0 to a valid command after training (timing of MRUPD mode).

[0081] In a response to MRUPD Command 1, CMD may be an MRUPD Exit command, shown as MRUPD Data 0, and the CS signal may assert the CS signal for tMRUPD_CS. Similarly, in a response to MRUPD Command 2, CMD may be MRUPD Data 1, which may be an extension of the Exit command, and the CS signal may assert the CS signal for tMRUPD_CS.

[0082] Schematic diagram 404 shows the use of multi-cycle CS used during MRUPD mode. Multi-cycle CS is used to allow the DRAM time to latch the signal because there is no Vref CS, no Vref CA or other training. After training, the CS0_n signal line shows a normal single-cycle CS. Using the multi-cycle CS signal, the system can clearly identify the DRAM in MRUPD mode (until CS / CA is trained) or normal mode.

[0083] In diagram 404, in one example, the host writes to the MR register field MRUPDX using MRUPD to exit. The DRAM can exit MRUPD to execute any valid single-cycle CS-based command (e.g., a read with tMRD (memory read time) timing) and MRUPD single-cycle command.

[0084] Figure 5A is an example of a register field table for a training mode available through MRUPD mode. Schematic 502 shows an example of a DRAM mode register field for an encoded MPC opcode. Rather than accessing the mode through an MPC operation, the mode can be triggered through an MR access using an MRUPD command.

[0085] Consider a register bit field with address or identifier MRxx 510, with row 512. Row 512 includes fields CSTME (chip select training mode entry), CSTMX (chip select training mode exit), CATME (command / address training mode entry), CATMX (command / address training mode exit), MRUPDE (mode register update entry), and MRUPDX (mode register update exit), as well as other bit fields for RFU (reserved for future use). These are examples only, and other mode combinations can be identified in the same mode register.

[0086] Consider register bit field MRyy 520, having row 522. Row 522 includes fields ZQCALS (impedance calibration start), ZQCALL (impedance calibration latch), 1N (referring to 1N mode, where the first half of a two cycle command is sampled on the clock that CS is asserted, and the second half of the command is sampled on the next clock edge), and 2N (referring to 2N mode, where the first half of a two cycle command is sampled on the clock that CS is asserted, and the second half of the command is sampled two clocks after the first half), DLL (delay locked loop) reset, and MECS, and RFU field.

[0087] In one example, MRUPDX provides an exit from MRUPD mode. MRUPD training can be characterized by a multi-cycle CS and 3-phase command, where the address and two data cycles represent 3 phases. The division of the MRUPD command into multi-cycle CS and 3 phases helps the DRAM sample the content reliably. In one example, MRUPD mode will start using the MR bit field of schematic 502, and other training modes can be triggered by MR.

[0088] Although not specifically illustrated, there may be a register identified as MRzz with RTT_CS (read terminal target for CS), RTT_CA (read terminal target for CA), RTT_CK (read terminal target for CK (clock)), RTT_PARK (read terminal target for park), and Vref settings. In one example, the MRUPD mode will begin using an MR bit field similar to the EXIT mode provided in schematic 502 to cause the DRAM to start in a different mode. In one example, the system samples the DRAM mode register field from the table instead of the encoded MPC opcode.

[0089] Figure 5B Schematic 504 shows table 530, which is a first example MRUPD 3-phase command table based on seven CA pins. If the number of CA pins is reduced, the number of commands can be increased to send them multiple times.

[0090] Row 532 shows the first phase, Phase 0. In one example, the first phase command sends MRP[4:0] (five bits of mode register paging) and MRA[7:6] (mode register address bits 7 and 6). Row 534 shows the second phase, Phase 1. The second phase command can send MRA[5:0] (the six least significant bits of the mode register address) and OP0 (the least significant opcode bit). Row 536 shows the third phase, Phase 2. The third phase command can send OP[7:1] (the most significant bit of the opcode). In one example, paging information can be passed via MRA[0:X], where X is an integer to save the UI for each command. The number of bits can be the number of bits shown in schematic 504, or it can be a different number, depending on the configuration of the system.

[0091] In one example, there may be 32 pages, 256 registers within each page, an 8-bit opcode (data bit in the command), and 128 directly addressable registers. Any of these values ​​may have variations, with different numbers of pages, registers per page, opcode sizes, and directly addressable registers. Different configurations may be used for different DRAM device implementations.

[0092] In one example, the RCD is placed in pass-through mode to allow commands to be passed to the DRAM. In one example, the RCD may be selectively placed in pass-through mode, and it passes the MRUPD commands to the DRAM. In one example, the RCD is selectively not placed in pass-through mode, and it receives the MRUPD commands as its configured RWUPD commands.

[0093] Figure 5C Schematic 506 shows table 540, which is an example MRUPD 3-phase command based on seven CA pins (CA[6:0]). If the number of CA pins is reduced, the number of commands can be increased to send them multiple times.

[0094] Row 542 shows the first phase, Phase 0. In one example, the first phase command sends MA[5:0] (six bits of the mode register address) and a valid bit (V). Row 544 shows the second phase, Phase 1. The second phase command can send MA[7:6] (the most significant mode register address bits) and OP[3:0] (the four least significant opcode bits). Row 546 shows the third phase, Phase 2. The third phase command can send OP[7:4] (the most significant bit of the opcode) and a valid bit. In one example, the page point is available in one of the MR bits, and a data integrity (per phase / step) check is added in place of the V.

[0095] In one example, there may be 32 pages, 256 registers within a page, 8-bit opcodes (data bits in commands), and 128 directly addressable registers. Any of these values ​​may have variations, with different numbers of pages, registers per page, opcode sizes, and directly addressable registers. Different configurations may be used for different DRAM device implementations.

[0096] In one example, the RCD is in pass-through mode to allow commands to be passed to the DRAM. In one example, the RCD may be selectively in pass-through mode, and it passes the MRUPD commands to the DRAM. In one example, the RCD is selectively not in pass-through mode, and it will receive the MRUPD commands as its configured RWUPD commands.

[0097] Figure 6 600 is a timing diagram of an example of a multi-cycle MRUPD command followed by a single-cycle MRUPD command. Schematic 600 shows another timing diagram of the MRUPD exit timing. Schematic 600 shows various signals and example sequences over time. The bold dashed lines represent time breaks, thus indicating that the number of clock cycles involved in the signal communication may be different than shown.

[0098] Signal 610 represents the host clock (CLK), which has CK_t (clock master) and CK_c (clock complementary) signals, which represent timing signals. Signal 620 represents command and address signal lines CA[6:0] (command / address bits 6 to 0), which represent commands sent by the host. Signal 630 represents the internal command signal CMD (command). CMD (command) represents a signal for a DRAM device. Signal line 640 represents chip select. CS0_n (chip select 0, enumerated for each individual DRAM device) represents the chip select of the target DRAM device to be configured using MRUPD.

[0099] The CA signal shows MRUPD Command 0, MRUPD Command 1, and MRUPD Command 2 for the training sequence. After training, the CA signal can send any valid command. After training, the CMD can similarly generate any valid command and perform a single cycle CS assertion on the CS signal. Schematic 600 shows the timing of the different phases of MRUPD, showing the timing of tMRUPD_PxDelay (timing between MRUPD commands) between MRUPD Command 0 and MRUPD Command 1.

[0100] In a response to MRUPD command 0, CMD may be MRUPD ADDR (address, or MRA (MRUPD address)), and CS signal may assert CS signal for tMRUPD_CS (timing of CS signal in MRUPD mode). In one example, there is tMRUPD_setup time (setup time of MRUPD mode) before CS assertion, and tMRUPD_hold time (hold time of MRUPD mode) after CS assertion. Schematic diagram 600 shows the timing of MRUPD operation, showing the timing of tMRUPD_Delay (timing of MRUPD mode), from MRUPD command 0 to a valid command after training.

[0101] In a response to MRUPD Command 1, CMD may be an MRUPD Exit command, shown as MRUPD Data 0, and the CS signal may assert the CS signal for tMRUPD_CS. Similarly, in a response to MRUPD Command 2, CMD may be MRUPD Data 1, MRUPD Data 1 may be an extension of the Exit command, and the CS signal may assert the CS signal for tMRUPD_CS.

[0102] Schematic diagram 600 shows the use of multi-cycle CS used during MRUPD mode. Multi-cycle CS is used to allow the DRAM time to latch the signal because there is no Vref CS, no Vref CA or other training. After training, the CS0_n signal line shows a normal single cycle CS.

[0103] In schematic 600, in one example, the host writes to the MR register field MRUPDX using MRUPD to exit. In one example, the DRAM can exit MRUPD to execute any single cycle MRUPD or MRW command. The MRUPD or MRW command can identify the address, causing a bit flip at the MRA. In one example, the timing from MRUPD command 2 to the single cycle command has timing tMRD (mode register delay timing).

[0104] In one example, by not sending two different commands, the system can align MRW with the single cycle MRUPD, simplifying the overall logic. In one example, the multi-cycle CS command can be part of the MRUPD mode until the DRAM is trained, thereby setting the DRAM VrefCA, VrefCS, CS, and CA.

[0105] In one example, after exiting MRUPD mode, the DRAM moves to single-cycle MRUPD mode, where it can send MRW from the host to the DRAM. In single-cycle MRUPD mode, MRUPD mode and MRW can be combined because both are single-cycle commands. Since the CA has limited pins, MRUPD or MRW may need to be sent with more than one command, as shown previously.

[0106] Fig. 7A is an example of a mode register access command table. Schematic 702 shows table 710, which is different from the options shown above. Table 710 shows an example of MRW / MRR (mode register write / mode register read) commands based on CA[6:0]. In an example, the system can have fewer command signal lines, such as four signal lines.

[0107] Table 710 shows MRW-1 in row 712 (rising edge R) and row 714 (falling edge F). Table 710 shows MRW-2 in row 716 (rising edge R) and row 718 (falling edge F). Table 710 shows MRR in row 720 (rising edge R) and row 722 (falling edge F). Rows 712, 716, and 720 show asserted chip selects, and rows 714, 718, and 722 show "don't care" chip selects.

[0108] MRW-1, where CA[6:0] or unshared CA[3:0] / CA[7:0] or shared CA[7:0] sends multiple MRW command encodings. As shown, MRW-1 has a low CS on the rising edge and a don't care CS on the falling edge. For CA[0:6] on the rising edge (row 712), these bits can be the encoding (H / L, H / L, H / L, H / L), TBD bit, and MA[0:1], respectively. For CA[0:6] on the falling edge (row 714), these bits can be MA[2:7] and valid bits. MRW-1 can have command encoding and address information.

[0109] As shown, MRW-2 has a low CS on the rising edge and a don't care CS on the falling edge. For CA[0:6] on the rising edge (row 716), the bits can be the encoding (H / L, H / L, H / L, H / L), the TBD bit, and OP[0:1], respectively. For CA[0:6] on the falling edge (row 718), the bits can be OP[2:7] and the valid bit. Thus, MRW-2 can have command encoding and opcode data.

[0110] As shown, the MRR has a low CS on the rising edge (row 720), and a don't care CS on the falling edge. For CA[0:6] on the rising edge, the bits can be the code (H / L, H / L, H / L, H / L), the TBD bit, and MA[0:1], respectively. For CA[0:6] on the falling edge (row 722), the bits can be MA[2:7] and the valid bit. Thus, the MRR can have a command code and a register address.

[0111] Figure 7B is an example of a timing diagram for a mode register access command. Timing diagram 704 shows various signals and example sequences over time. The bold dashed lines represent time breaks, indicating that the number of clock cycles involved in signal communication may be different than shown.

[0112] Signal 730 represents the host clock (CLK), which has CK_t (clock master) and CK_c (clock complementary) signals, which represent timing signals. Signal 740 represents chip select. CS0_n (chip select 0, enumerated for each individual DRAM device) represents the chip select of the target DRAM device to be configured using MRUPD. Signal 750 represents command and address signal lines CA[6:0] (command / address bits 6 to 0), which represent commands sent by the host. Signal line 760 represents the internal command signal CMD (command). The CMD signal represents a signal for a DRAM device.

[0113] Signal 740 shows chip select asserted at ta0R (time a0, rising edge), with a valid command on signal 750, and MRW-1 on signal 760. The signal continues at ta0F (time a0, falling edge). At time ta1R, signal 760 shows MRW-2. At time ta1F, signal 740 shows an edge transition of CS. Time ta2R shows CS deasserted, and a deselect command (DES) on signal 760.

[0114] At time tb0R, signal 760 shows a DES with CS deasserted. At time tb0F, signal 740 shows an edge transition of CS asserted, and another DES on signal 760. Time tb1R shows CS asserted, a valid command on signal 750, and MRW-1 on signal 760. Time tb1F shows CS asserted, a valid command on signal 750, and MRW-1 on signal 760.

[0115] 70. Time tb2R shows CS assertion, a valid command on signal 750, and MRW-2 on signal 760. Time tb2F shows an edge transition of CS, a valid command on signal 750, and MRW-2 on signal 760. CS de-assertion and DES on signal 760 are shown at time tb3R, time tb3F, time tb4R, tb4F, and tc0R. At time tc0F, signal 740 shows a CS transition with DES on signal 760. At time tc1R and time tc1F, signal 740 shows CS assertion, valid on signal 750, and any command (CMD) on signal 760.

[0116] Chip Select is asserted for the MRW command. The CA signal line only needs to be valid to enable the Mode Register command to be issued. The CMD signal line shows the MRW-1 and MRW-2 commands sent sequentially when CS is asserted. The time for MRW (tMRW) is from ta1R to tb2R, and the time for MRD (tMRD) is from tb2R to tc1R.

[0117] Figure 8 8 is a flow chart of an example of an MRUPD process. Process 800 represents a process flow for in-band DRAM configuration using MRUPD. After the system PON (power on), at 802, the host can initiate communication. In one example, the system powers on (PON) the DRAM and defaults to MRUPD mode, which can be part of a reset process. The system can optionally perform an M3C operation during debug to enter MRUPDE / MRUPDX to enter MRUPD mode.

[0118] At 804, the system may perform operations to read the SPD and power up the PMIC. At 806, the system may follow a standards-based initialization sequence, including starting the M3C bus, deasserting the Reset_n signal, and waiting for an initialization period (eg, tINIT3).

[0119] In one example, at 808, the system determines if there are strap pins. If there are strap pins, at 810, the YES branch, in one example, at 812, there are optional M3C RW (register word) updates for CS / CA and for ODT / Vref (e.g., for RCD, or for mode register updates for DRAM). If there are no strap pins, at 810, the NO branch, in one example, at 814, an M3C register write is required.

[0120] In one example, MRUPD mode follows three operations: MRUPD entry / idle, MRUPD operation (with address and data), and MRUPD exit to perform a regular MRW. At 816, the system can perform MRUPD idle. The system can send an MRUPD address command at 818, send an MRUPD command with a first portion of data at 820, and send a second MRUPD command with a second portion of data at 822.

[0121] The system can use MRUPD mode operation to set up the DLL and train ZQCal, ODT, and Vref. MRUPD mode operation can also be used for CSTM entry, CATM entry, and DFE training. In one example, after setting the parameters, at 824, the system determines whether there are more parameters to be set. If there are more parameters to be configured (YES branch at 826), at 816, the system can return to MRUPD idle. If there are no more parameters to be configured (NO branch at 826), at 828, the system can trigger MRUPD exit. At 830, after exiting MRUPD, the system supports regular MRW to set the configuration.

[0122] In one example, the system uses the same DRAM CS as the qualifier of MRUPD, using MRUPD to configure all required DRAM mode registers. In one example, the system applies a multi-cycle CS to cause MRUPD to enter CSTM training (write MR field), and exits CSTM using a CA of all zeros (0). Optionally, M3C can be used to initialize / debug the termination, Vref, and other parameters. M3C can initiate termination and Vref setup, and MRUPD in-band commands can be used for any parameter scans to be accelerated with the help of DRAM scan acceleration logic. The system can similarly use the identifier of RCD to set the RCD configuration register.

[0123] Fig. 9900 is a state diagram of an example of MRUPD. System 900 represents various states in an example MRUPD flow. In one example, in response to a power-on reset, the memory enters state MRUPD Idle 902, in which the memory can perform in-band training with MRUPD, but is idle because it currently has no operations to perform.

[0124] In one example, as an alternative to entering MRUPD IDLE at power-on reset, during debug time, a command is issued on the M3C bus (which may be a subset of the I3C basic bus). In one example, with a multi-cycle chip select (CS) assertion, the memory may move to state MRUPD ADDR 904. In response to the CS assertion, the selected memory device may check the MRUPD address for configuration updates. With another CS assertion (which may also be a multi-cycle assertion), the memory moves to state MRUPD DATA 906, where the memory device obtains data to be written to the address of the previous state.

[0125] In one example, the mode register update written may be an update to disable MRUPD mode. In response to such an update, the memory may enter state MRUPD EXIT 908 and exit MRUPD mode.

[0126] In one example, 902 and 906 may represent states for general mode register updates. Such general updates are not necessarily associated with enabling training mode. For example, updates may be for Vref configuration. If Vref is out of range, in one example, the system may recover using the M3C bus.

[0127] In one example, the MRUPD data 906 can be written with a mode register configuration to trigger CSTM entry 910 to enable CSTM. In one example, with all CA pins set high (e.g., set to a high logic state), CS asserts and the memory enters state CSTM 912 to perform chip select training. In one example, during CS training, the CA pins can remain high. In one example, during CSTM, no commands are supported. Alternatively, the DRAM device can be disabled from decoding any commands.

[0128] In one example, in response to CS assertion with all CA pins driven low, the memory may move to state CSTM EXIT 914. In response to exiting CSTM mode, the memory may return to state MRUPD IDLE 902.

[0129] In one example, the MRUPD data 906 can trigger CATM entry 920 with a mode register configuration write to enable CATM. In one example, using a CS assertion (e.g., CA code or CATM command) with the appropriate CA mode on the CA pin, the memory enters state CATM 922 to perform CA bus training. In one example, during CA bus training, the CA pin can be held at the CA code that triggers entry into CATM.

[0130] In one example, in response to a multi-cycle CS assertion with all CA pins driven high, the memory can move to state CATM EXIT 924. In response to exiting CATM mode, the memory can return to state MRUPD IDLE 902.

[0131] Fig.10 1 is a block diagram of an example of a memory subsystem that can implement an in-band configuration mode. System 1000 includes a processor in a computing device and elements of a memory subsystem. System 1000 represents a system having a memory subsystem according to the example of system 102 or the example of system 200 or the example of system 300.

[0132] In one example, system 1000 includes RCD 1072 in memory module 1070. Configuration of RCD 1072 may be programmed using in-band register writes according to any description herein. Memory device 1040 may represent a DRAM device, and DRAM device configuration may be programmed using in-band register writes according to any description herein.

[0133] Processor 1010 represents a processing unit of a computing platform that can execute an operating system (OS) and applications, which can be collectively referred to as a host or user of memory. The OS and applications perform operations that result in memory access. Processor 1010 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a main processor, such as a CPU (central processing unit), a peripheral processor, such as a GPU (graphics processing unit), or a combination. Memory access may also be initiated by devices such as a network controller or a hard disk controller. In some systems, such devices may be integrated with the processor or attached to the processor via a bus (e.g., PCI Express), or a combination. System 1000 may be implemented as a SOC (system on chip) or with separate components.

[0134] References to memory devices may apply to different memory types. Memory devices generally refer to volatile memory technologies. Volatile memory refers to memory whose state (and the data stored therein) is uncertain if power to the device is interrupted. Non-volatile memory refers to memory whose state remains certain even if power to the device is interrupted. Dynamic volatile memory requires that the data stored in the device be refreshed to maintain the state. An example of dynamic volatile memory includes DRAM (dynamic random access memory) or some variants such as synchronous DRAM (SDRAM). The memory subsystem described herein may be compatible with a variety of memory technologies, such as DDR4 (Double Data Rate Version 4, JESD79-4, originally released by JEDEC (Joint Electron Device Engineering Council, now JEDEC Solid State Technology Association) in September 2012), LPDDR4 (Low Power DDR Version 4, JESD209-4, originally released by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, originally released by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A, originally released by JEDEC in November 2015), DDR5 (DDR version 5, originally released by JEDEC in July 2020), LPDDR5 (LPDDR version 5, JESD209-5, originally released by JEDEC in February 2019), HBM2 (HBM version 2, JESD235C, originally released by JEDEC in January 2020), HBM3 (HBM version 3, JESD238, originally released by JEDEC in January 2022), DDR6 (DDR version 6, under discussion), GDDR7 (Graphics DDR version 7, under discussion), or other or a combination of multiple memory technologies, as well as derivative or extended technologies based on such specifications.

[0135] The memory controller 1020 represents one or more memory controller circuits or devices of the system 1000. In one example, the memory controller 1020 is located on the same semiconductor substrate as the processor 1010. The memory controller 1020 represents control logic that generates memory access commands in response to the processor 1010 performing operations. The memory controller 1020 accesses one or more memory devices 1040. The memory device 1040 can be a DRAM device that meets any of the above requirements. In one example, the memory device 1040 is organized and managed as different channels, wherein each channel is coupled to a bus and signal lines that are coupled to multiple memory devices in parallel. Each channel is independently operable. Therefore, each channel is independently accessed and controlled, and the timing, data transfer, command and address exchange, and other operations of each channel are independent. Coupling can refer to electrical coupling, communication coupling, physical coupling, or a combination of these. Physical coupling can include direct contact. Electrical coupling includes interfaces or interconnections that allow current flow between components or allow signal transmission between components or both. Communication coupling includes connections (including wired or wireless) that enable components to exchange data.

[0136] In one example, the settings for each channel are controlled by a separate mode register or other register setting. In one example, each memory controller 1020 manages a separate memory channel, although the system 1000 can be configured to have multiple channels managed by a single controller, or to have multiple controllers on a single channel. In one example, the memory controller 1020 is part of the host processor 1010, such as logic implemented on the same die as the processor or logic implemented in the same package space as the processor.

[0137] The memory controller 1020 includes an I / O interface logic 1022 to couple to a memory bus, such as a memory channel as described above. The I / O interface logic 1022 (and the I / O interface logic 1042 of the memory device 1040) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or a combination of these. The I / O interface logic 1022 may include a hardware interface. As shown, the I / O interface logic 1022 includes at least a driver / transceiver for a signal line. Typically, wires within an integrated circuit interface are coupled to pads, pins, or connectors to engage with signal lines or traces or other wires between devices. The I / O interface logic 1022 may include a driver, a receiver, a transceiver, or a terminal, or other circuit systems or combinations of circuit systems to exchange signals on signal lines between devices. Signal exchange includes at least one of sending or receiving. Although the I / O 1022 of the memory controller 1020 is shown coupled to the I / O 1042 of the memory devices 1040, it is understood that in implementations of the system 1000 where groups of memory devices 1040 are accessed in parallel, multiple memory devices may include an I / O interface to the same interface of the memory controller 1020. In implementations of the system 1000 that include one or more memory modules 1070, the I / O 1042 may include interface hardware for the memory modules in addition to the interface hardware on the memory devices themselves. Other memory controllers 1020 will include separate interfaces with other memory devices 1040.

[0138] The bus between the memory controller 1020 and the memory device 1040 can be implemented as a plurality of signal lines that couple the memory controller 1020 to the memory device 1040. The bus can typically include at least a clock (CLK) 1032, a command / address (CMD) 1034, a data (DQ) 1036, and zero or more other signal lines 1038. In one example, the bus or connection between the memory controller 1020 and the memory can be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal line of CMD can be referred to as a "C / A bus" (or an ADD / CMD bus, or some other name indicating the transmission of command (C or CMD) and address (A or ADD) information), and the signal line for writing and reading DQ can be referred to as a "data bus". In one example, independent channels have different clock signals, C / A buses, data buses, and other signal lines. Therefore, the system 1000 can be considered to have multiple "buses", that is, independent interface paths can be considered as separate buses. It is understood that, in addition to the lines clearly shown, the bus may also include at least one of a strobe signal line, an alarm line, an auxiliary line, or other signal lines, or a combination. It is also understood that serial bus technology may be used for the connection between the memory controller 1020 and the memory device 1040. An example of serial bus technology is to use an embedded clock to perform 8B10B encoding and transmit high-speed data in each direction through a single differential signal pair. In one example, CMD 1034 represents a signal line shared in parallel with a plurality of memory devices. In one example, a plurality of memory devices share the encoding command signal line of CMD 1034, and each memory device has a separate chip select (CS_n) signal line to select each memory device.

[0139] It should be understood that in the example of system 1000, the bus between the memory controller 1020 and the memory device 1040 includes an auxiliary command bus CMD 1034 and an auxiliary bus DQ 1036 for carrying write and read data. In one example, the data bus may include a bidirectional line for reading data and for writing / command data. In another example, the auxiliary bus DQ 1036 may include a unidirectional write signal line for writing and data from the host to the memory, and may include a unidirectional line for reading data from the memory to the host. Depending on the selected memory technology and system design, other signals 1038 may accompany the bus or sub-bus, such as a strobe line DQS. Based on the design of the system 1000, or if the design supports multiple implementations, the data bus may have more or less bandwidth for each memory device 1040 according to the implementation. For example, the data bus may support memory devices with x4 interfaces, x8 interfaces, x16 interfaces, or other interfaces. The convention "xW" refers to the number of signal lines that exchange data with the memory controller 1020, where W is an integer that refers to the interface size or interface width of the memory device 1040. The interface size of the memory device is a controlling factor regarding how many memory devices can be used simultaneously per channel in the system 1000 or how many memory devices can be coupled to the same signal line in parallel. In one example, a high bandwidth memory device, a wide interface device, or a stacked memory configuration, or a combination can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface, or other data bus interface widths.

[0140] In one example, the memory device 1040 and the memory controller 1020 exchange data through the data bus in a burst or continuous data transfer sequence. The burst corresponds to the number of transfer cycles, which is related to the bus frequency. In one example, the transfer cycle can be the entire clock cycle of the transfer that occurs on the same clock or selection signal edge (e.g., on the rising edge). In one example, each clock cycle (referring to the cycle of the system clock) is divided into a plurality of unit intervals (UIs), wherein each UI is a transfer cycle. For example, double data rate transmission is triggered on two edges (e.g., rising and falling edges) of the clock signal. The burst can be continuously configured for the number of UIs, which can be a configuration stored in a register, or triggered instantly. For example, a sequence of eight continuous transfer cycles can be regarded as a burst length of eight (BL8), and each memory device 1040 can transmit data on each UI. Therefore, an x8 memory device operating on BL8 can transmit 64 bits of data (8 data signal lines multiplied by 8 data bits transmitted by each line in the burst). It is understood that this simple example is only an illustration, not a limitation.

[0141] Memory devices 1040 represent memory resources of system 1000. In one example, each memory device 1040 is a separate memory die. In one example, each memory device 1040 can be coupled to multiple (e.g., 2) channels of each device or die. Each memory device 1040 includes I / O interface logic 1042, which has a bandwidth determined by the implementation of the device (e.g., x16 or x8 or some other interface bandwidth). I / O interface logic 1042 enables the memory device to be coupled to memory controller 1020. I / O interface logic 1042 may include a hardware interface and may be consistent with I / O 1022 of the memory controller, but at the memory device end. In one example, multiple memory devices 1040 are connected to the same command and data bus in parallel. In another example, multiple memory devices 1040 are connected to the same command bus in parallel and to different data buses. For example, the system 1000 may be configured with multiple memory devices 1040 coupled in parallel, each memory device responding to commands and accessing memory resources 1060 internal to each memory device. For a write operation, a single memory device 1040 may write a portion of an overall data word, and for a read operation, a single memory device 1040 may retrieve a portion of an overall data word. The remaining bits of the word will be provided or received in parallel by other memory devices.

[0142] In one example, the memory device 1040 is directly disposed on a motherboard or host system platform of the computing device (e.g., a PCB (printed circuit board) or substrate on which the processor 1010 is disposed). In one example, the memory device 1040 may be organized into a memory module 1070. In one example, the memory module 1070 represents a dual in-line memory module (DIMM). In one example, the memory module 1070 represents other organizations of multiple memory devices to share at least a portion of the access or control circuit system, which may be a circuit, a separate device, or a separate board from the host system platform. The memory module 1070 may include multiple memory devices 1040, and the memory module may include support for multiple separate channels of the included memory devices disposed thereon. In another example, the memory device 1040 may be incorporated into the same package as the memory controller 1020, for example, by technologies such as multi-chip modules (MCMs), package-on-package, through silicon vias (TSVs), or other technologies or combinations. Similarly, in one example, multiple memory devices 1040 can be incorporated into a memory module 1070, which itself can be incorporated into the same package as the memory controller 1020. It can be appreciated that for these and other implementations, the memory controller 1020 can be part of the host processor 1010.

[0143] Each memory device 1040 includes one or more memory arrays 1060. The memory array 1060 represents an addressable memory location or storage location of data. Typically, the memory array 1060 is managed as a data row, and access is controlled via word lines (rows) and bit lines (individual bits within a row). The memory array 1060 can be organized into separate memory channels, memory ranks, and banks. A channel can refer to an independent control path to a storage location within the memory device 1040. A column can refer to a common location across multiple memory devices in parallel (e.g., the same row address within different devices). A bank can refer to a sub-array of memory locations within the memory device 1040. In one example, a bank is divided into sub-banks, wherein the sub-banks have at least a portion of a shared circuit system (e.g., a driver, a signal line, a control logic), thereby allowing separate addressing and access. It can be understood that the channel, column, bank, sub-bank, bank group, or other organization of the memory location, and a combination of these organizations can overlap when applied to physical resources. For example, the same physical memory location as a specific bank can be accessed through a specific channel, which can also belong to a column. Therefore, the organization of memory resources is to be understood in an inclusive rather than exclusive manner.

[0144] In one example, the memory device 1040 includes one or more registers 1044. The register 1044 represents one or more storage devices or storage locations that provide configuration or settings for the operation of the memory device. In one example, the register 1044 can provide a storage location for the memory device 1040 to store data for access by the memory controller 1020 as part of a control or management operation. In one example, the register 1044 includes one or more mode registers. In one example, the register 1044 includes one or more multi-purpose registers. The location configuration within the register 1044 can configure the memory device 1040 to operate in different "modes", where command information can trigger different operations within the memory device 1040 based on the mode. Additionally or alternatively, different modes can also trigger different operations from address information or other signal lines based on the mode. The settings of the register 1044 can indicate the configuration of the I / O settings (e.g., timing, termination or ODT (on-die termination) 1046, driver configuration, or other I / O settings).

[0145] In one example, the memory device 1040 includes an ODT 1046 as part of the interface hardware associated with the I / O 1042. The ODT 1046 can be configured as described above and provides impedance settings for the interface to be applied to a specified signal line. In one example, the ODT 1046 is applied to the DQ signal line. In one example, the ODT 1046 is applied to the command signal line. In one example, the ODT 1046 is applied to the address signal line. In one example, the ODT 1046 can be applied to any combination of the foregoing. The ODT setting can be changed based on whether the memory device is the selected target or non-target device of the access operation. The ODT 1046 setting can affect the timing and reflection of the signaling on the terminal line. Careful control of the ODT 1046 can achieve higher speed operation while improving the matching of the applied impedance and load. The ODT 1046 can be applied to specific signal lines (e.g., ODT for DQ lines or ODT for CA lines) of the I / O interface 1042, 1022, and not necessarily to all signal lines.

[0146] The memory device 1040 includes a controller 1050, which represents the control logic within the memory device for controlling the internal operations within the memory device. For example, the controller 1050 decodes the command sent by the memory controller 1020 and generates internal operations to execute or satisfy the command. The controller 1050 can be called an internal controller and is separate from the memory controller 1020 of the host. The controller 1050 can determine which mode to select based on the register 1044, and configure the internal operation execution for accessing the memory resource 1060 or other operations based on the selected mode. The controller 1050 generates control signals to control the bit routing within the memory device 1040, thereby providing an appropriate interface for the selected mode and directing the command to the appropriate memory location or address. The controller 1050 includes a command logic 1052, which can decode the command encoding received on the command and address signal lines. Therefore, the command logic 1052 can be or include a command decoder. Using the command logic 1052, the memory device can identify the command and generate internal operations to execute the requested command.

[0147] Referring again to the memory controller 1020, the memory controller 1020 includes command (CMD) logic 1024, which represents logic or circuitry that generates commands to send to the memory device 1040. The generation of a command may refer to a command before scheduling, or a queued command that is ready to be sent. Typically, signaling in a memory subsystem includes address information within or accompanying a command to indicate or select one or more memory locations where the memory device should execute the command. In response to the transaction scheduling of the memory device 1040, the memory controller 1020 may issue a command via the I / O 1022 to cause the memory device 1040 to execute the command. In one example, the controller 1050 of the memory device 1040 receives and decodes the command and address information received from the memory controller 1020 via the I / O 1042. Based on the received command and address information, the controller 1050 may control the timing of operation of the logic and circuitry within the memory device 1040 to execute the command. The controller 1050 is responsible for compliance with standards or specifications, such as timing and signaling requirements, within the memory device 1040. The memory controller 1020 may implement compliance with standards or specifications through access scheduling and control.

[0148] The memory controller 1020 includes a scheduler 1030, which represents a logic or circuit system for generating transactions and ordering transactions to be sent to the memory device 1040. From one perspective, the main function of the memory controller 1020 can be said to be to schedule memory access and other transactions to the memory device 1040. Such scheduling may include generating the transaction itself to implement the processor 1010 request for data and maintain the integrity of the data (e.g., such as commands related to refresh). A transaction may include one or more commands and result in the transmission of commands or data or both within one or more timing cycles (e.g., clock cycles or unit intervals). Transactions may be used for access (e.g., read or write or related commands or combinations), and other transactions may include memory management commands for configuration, setup, data integrity, or other commands or combinations.

[0149] The memory controller 1020 typically includes logic such as a scheduler 1030 to allow transactions to be selected and ordered to improve the performance of the system 1000. Thus, the memory controller 1020 can select which outstanding transactions should be sent to the memory device 1040 in what order, which is typically achieved by logic that is much more complex than a simple first-in, first-out algorithm. The memory controller 1020 manages the transmission of transactions to the memory device 1040 and manages the timing associated with the transactions. In one example, the transactions have deterministic timing, which can be managed by the memory controller 1020 and used to determine how to schedule transactions using the scheduler 1030.

[0150] In one example, the memory controller 1020 includes refresh (REF) logic 1026. The refresh logic 1026 can be used for memory resources that are volatile and need to be refreshed to maintain a deterministic state. In one example, the refresh logic 1026 indicates the location of the refresh and the type of refresh to be performed. The refresh logic 1026 can trigger a self-refresh within the memory device 1040, or perform an external refresh (which can be referred to as an automatic refresh command) by sending a refresh command, or a combination. In one example, the controller 1050 within the memory device 1040 includes refresh logic 1054 to apply refresh within the memory device 1040. In one example, the refresh logic 1054 generates internal operations to perform refresh based on the external refresh received from the memory controller 1020. The refresh logic 1054 can determine whether the refresh is for the memory device 1040, and which memory resources 1060 to refresh in response to the command.

[0151] Figure 11A-11B is a block diagram of an example of a CAMM system in which alarm signal testing may be implemented.

[0152] refer to Fig.11A, system 1102 includes a memory stack architecture monitored by a memory fault tracker that can perform mirroring. System 1102 is an example of a system according to an example of system 102, system 200, or system 300.

[0153] Substrate 1110 shows a SOC package substrate or a mainboard or system board. Substrate 1110 includes contacts 1112, which represent contacts for connecting to a memory. CPU 1114 represents a processor or a central processing unit (CPU) chip or a graphics processing unit (GPU) chip to be arranged on substrate 1110. CPU 1114 performs computing operations in system 1102. In one example, CPU 1114 includes multiple cores (not specifically shown), and the cores can generate operations requesting to read data from a memory and write data to a memory. CPU 1114 may include a memory controller to manage access to a memory device.

[0154] Compression attached memory module (CAMM) 1130 represents a module with memory devices that are not specifically shown in system 1102. Substrate 1110 is coupled to CAMM 1130 and its memory devices via compression mounting technology (CMT) connector 1120. Connector 1120 includes contacts 1122, which are compression-based contacts. Compression-based contacts are compressible pins or devices whose shapes compress as pressure is applied to connector 1120. In one example, contact 1122 represents a C-shaped pin as shown. In one example, contact 1122 represents another compressible pin shape, such as a spring-shaped, S-shaped or pin with other compressible shapes.

[0155] CAMM 1130 includes contacts 1132 on one side of the CAMM board that engage with connector 1120. Contacts 1132 connect to memory devices on the CAMM board. Board 1140 represents a board or housing that provides a structure to apply pressure to compress contacts 1122 of connector 1120.

[0156] refer to Fig. 11B , system 1104 is a perspective view of a system according to system 1102. System 1104 shows a memory controller 1150, which is not specifically shown in system 1102. Memory controller 1150 can provide row hammer mitigation for DRAM 1136. DRAM 1136 can be connected to memory controller 1150 via an alert signal line. System 1104 enables DRAM 1136 to perform an alert signal test mode with memory controller 1150 according to any example herein.

[0157] CAMM 1130 is shown with memory chips or memory dies identified as DRAM 1136 on one or both sides of the PCB of CAMM 1130. DRAM 1136 is coupled to conductive contacts via conductive traces in or on the PCB, which is coupled to contacts 1132, which in turn are coupled to contacts 1122 of connector 1120.

[0158] System 1104 shows holes 1142 in plate 1140 for receiving fasteners, represented by screws 1144. There are corresponding holes in CAMM 1130, connector 1120, and substrate 1110. Screws 1144 can compressibly attach CAMM 1130 to substrate 1110 via connector 1120.

[0159] Fig.12 1 is a block diagram of an example of a computing system that can implement an in-band configuration mode. System 1200 represents a computing device according to any example herein, and can be a laptop computer, a desktop computer, a tablet computer, a server, a game or entertainment control system, an embedded computing device, or other electronic device. System 1200 represents a system with a storage device according to the example of system 102 or the example of system 200 or the example of system 300.

[0160] In one example, system 1200 includes a memory subsystem 1220, wherein RCD 1224 is located in a memory module. The configuration of RCD 1224 can be programmed using in-band register writes according to any description herein. Memory 1230 can represent a DRAM device, and RAM device configuration can be programmed using in-band register writes according to any description herein. In-band configuration (CONFIG) 1290 represents a component that enables the system to perform in-band register configuration updates in update mode.

[0161] The system 1200 includes a processor 1210, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or a combination thereof, to provide processing or execution of instructions for the system 1200. The processor 1210 may be a host processor device. The processor 1210 controls the overall operation of the system 1200 and may be or include one or more programmable general or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination of these devices.

[0162] System 1200 includes boot / configuration 1216, which represents a storage device for storing boot code (e.g., basic input / output system (BIOS)), configuration settings, security hardware (e.g., trusted platform module (TPM)), or other system-level hardware operating outside of the host OS. Boot / configuration 1216 may include a non-volatile storage device, such as a read-only memory (ROM), flash memory, or other memory device.

[0163] In one example, the system 1200 includes an interface 1212 coupled to the processor 1210, which may represent a higher speed interface or a high throughput interface for system components (e.g., the memory subsystem 1220 or the graphics interface component 1240) that require a higher bandwidth connection. The interface 1212 represents an interface circuit, which may be a separate component or integrated onto a processor chip. The interface 1212 may be integrated onto a processor die as a circuit or onto a system on a chip as a component. If present, the graphics interface 1240 is coupled to the graphics component to provide a visual display to a user of the system 1200. The graphics interface 1240 may be a separate component or integrated onto a processor die or onto a system on a chip. In one example, the graphics interface 1240 may drive a high definition (HD) display or an ultra high definition (UHD) display to provide output to a user. In one example, the display may include a touch screen display. In one example, the graphics interface 1240 generates a display based on data stored in the memory 1230 or based on operations performed by the processor 1210 or both.

[0164] Memory subsystem 1220 represents the main memory of system 1200 and provides storage for code executed by processor 1210 or data values ​​used when executing routines. Memory subsystem 1220 may include one or more random access memories (RAM), such as DRAM, 3DXP (three-dimensional crosspoint) or other memory devices, or a combination of these devices. Memory 1230 stores and hosts operating system (OS) 1232 and other components to provide a software platform for executing instructions in system 1200. Additionally, application 1234 can be executed on the software platform of OS1232 from memory 1130. Application 1234 represents a program that has its own operating logic to perform the operation of one or more functions. Process 1236 represents an agent or routine that provides auxiliary functions to OS1232 or one or more applications 1234 or a combination. OS1232, application 1234 and process 1236 provide software logic to provide the functions of system 1200. In one example, the memory subsystem 1220 includes a memory controller 1222, which is a memory controller for generating commands and issuing commands to the memory 1230. It is understood that the memory controller 1222 can be a physical part of the processor 1210 or a physical part of the interface 1212. For example, the memory controller 1222 can be an integrated memory controller integrated into a circuit with the processor 1210, such as integrated into a processor die or a system on a chip.

[0165] Although not specifically described, it is understood that the system 1200 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, etc. A bus or other signal line may couple components together in a communicative or electrical manner, or in a communicative and electrical manner. A bus may include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuit system or combination. For example, a bus may include one or more of a system bus, a peripheral component interconnect (PCI) bus, a hypertransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or other buses, or a combination.

[0166] In one example, system 1200 includes an interface 1214, which can be coupled to interface 1212. Interface 1214 can be an interface with a lower speed than interface 1212. In one example, interface 1214 represents an interface circuit, which can include independent components and integrated circuit systems. In one example, multiple user interface components or peripheral components or both are coupled to interface 1214. Network interface 1250 provides system 1200 with the ability to communicate with remote devices (e.g., servers or other computing devices) through one or more networks. Network interface 1250 can represent a network interface circuit (NIC) that allows connection to a remote device via a network connection. The network connection enabled by network interface 1250 can include an Ethernet adapter, a wireless interconnect component, a cellular network interconnect component, a USB (universal serial bus) or other wired or wireless standard or proprietary interface. Network interface 1250 can exchange data with a remote device, which can include sending data stored in a memory or receiving data to be stored in a memory.

[0167] In one example, the system 1200 includes one or more input / output (I / O) interfaces 1260. The I / O interfaces 1260 may include one or more interface components through which a user interacts with the system 1200 (e.g., audio, alphanumeric, tactile / touch, or other interfaces). The peripheral interfaces 1270 may include any hardware interfaces not explicitly mentioned above. Peripheral devices generally refer to devices that are dependently connected to the system 1200. A dependent connection refers to a connection in which the system 1200 provides a software platform or a hardware platform or both, operations are performed on it, and the user interacts with it.

[0168] In one example, system 1200 includes a storage subsystem 1280 for storing data in a non-volatile manner. In one example, in a particular system implementation, at least certain components of storage subsystem 1280 may overlap with components of memory subsystem 1220. Storage subsystem 1280 includes storage 1284, which may be or include any conventional media for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, NAND, 3DXP, or optical disks, or a combination. Storage 1284 holds code or instructions and data 1286 in a persistent state (i.e., the value is retained even if power to system 1200 is interrupted). Storage 1284 may be generally considered "memory," although memory 1230 is typically execution or operating memory for providing instructions to processor 1210. Although storage 1284 is non-volatile, memory 1230 may include volatile memory (i.e., if power to system 1200 is interrupted, the value or state of the data is indeterminate). In one example, storage subsystem 1280 includes controller 1282 for interfacing with storage 1284. In one example, controller 1282 is a physical part of interface 1214 or processor 1210, or may include circuitry or logic in both processor 1210 and interface 1214.

[0169] The power supply 1202 provides power to the components of the system 1200. More specifically, the power supply 1202 is typically coupled to one or more power supply devices 1204 in the system 1200 for providing power to the components of the system 1200. In one example, the power supply device 1204 includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. This AC power can be a renewable energy (e.g., solar) power supply 1202. In one example, the power supply 1202 includes a DC power source, such as an external AC to DC converter. In one example, the power supply 1202 or the power supply device 1204 includes wireless charging hardware for charging via proximity to a charging field. In one example, the power supply 1202 may include an internal battery or fuel cell source.

[0170] Fig.13 1300 is a block diagram of an example of a multi-node network that can implement an in-band configuration mode. System 1300 represents a network of nodes to which adaptive ECC can be applied. In one example, system 1300 represents a data center. In one example, system 1300 represents a server farm. In one example, system 1300 represents a data cloud or a processing cloud.

[0171] System 1300 represents a system with a storage device according to the example of system 102 or the example of system 200 or the example of system 300. In one example, memory node 1322 includes a memory module (not specifically shown) with an RCD. The configuration of the RCD can be programmed using in-band register writes according to any description herein, as represented by in-band configuration (CONFIG) 1392. System 1300 may include a memory device according to the contents described, and in-band configuration (CONFIG) 1390 represents the ability to program the RCD and / or memory device using in-band register writes according to any description herein.

[0172] One or more clients 1302 send requests to system 1300 via network 1304. Network 1304 represents one or more local networks, or wide area networks, or a combination. Client 1302 can be a human or machine client that generates a request for system 1300 to perform an operation. System 1300 performs the application or data computing task requested by client 1302.

[0173] In one example, system 1300 includes one or more racks, where a rack represents a structure and interconnection resource for housing and interconnecting multiple computing nodes. In one example, rack 1310 includes multiple nodes 1330. In one example, rack 1310 hosts multiple blade components, blade 1320[0], ..., blade 1320[N-1], collectively referred to as blade 1320. Hosting refers to providing power, structural or mechanical support, and interconnection. Blade 1320 can refer to a computing resource on a printed circuit board (PCB), where the PCB houses hardware components of one or more nodes 1330. In one example, blade 1320 does not include a chassis or housing or other "box" other than that provided by rack 1310. In one example, blade 1320 includes a housing with exposed connectors to connect to rack 1310. In one example, system 1300 does not include rack 1310, and each blade 1320 includes a chassis or housing that can be stacked or otherwise reside near other blades and allow nodes 1330 to be interconnected.

[0174] The system 1300 includes a fabric 1370, which represents one or more interconnects of the nodes 1330. In one example, the fabric 1370 includes a plurality of switches 1372 or routers or other hardware for routing signals between the nodes 1330. Additionally, the fabric 1370 can couple the system 1300 to a network 1304 for access by clients 1302. In addition to routing devices, the fabric 1370 can be considered to include cables or ports or other hardware devices to couple the nodes 1330 together. In one example, the fabric 1370 has one or more associated protocols for managing the routing of signals through the system 1300. In one example, the one or more protocols rely, at least in part, on the hardware devices used in the system 1300.

[0175] As shown, rack 1310 includes N blades 1320. In one example, in addition to rack 1310, system 1300 also includes rack 1350. As shown, rack 1350 includes M blade assemblies, blade 1360[0], ..., blade 1360[M-1], collectively referred to as blade 1360. M is not necessarily the same as N; therefore, it should be understood that a variety of different hardware device components can be used and coupled to system 1300 through structure 1370. Blade 1360 can be the same as or similar to blade 1320. Node 1330 can be any type of node, and is not necessarily all nodes of the same type. System 1300 is not limited to being homogeneous or non-homogeneous.

[0176] The nodes in the system 1300 may include computing nodes, memory nodes, storage nodes, accelerator nodes, or other nodes. Rack 1310 is represented by memory nodes 1322 and storage nodes 1324, which represent shared system memory resources and shared persistent storage, respectively. One or more nodes of rack 1350 may be memory nodes or storage nodes.

[0177] Node 1330 represents an example of a computing node. For simplicity, only the computing nodes in blade 1320[0] are shown in detail. However, other nodes in system 1300 can be the same or similar. At least some of nodes 1330 are computing nodes, having a processor (proc) 1332 and a memory 1340. A computing node refers to a node having processing resources (e.g., one or more processors) that executes an operating system and can receive and process one or more tasks. In one example, at least some of nodes 1330 are server nodes, where a server is a processing resource represented by processor 1332 and memory 1340.

[0178] Memory node 1322 represents an example of a memory node whose system memory is located outside the compute node. The memory node may include controller 1382, which represents a processor on the node for managing access to memory. The memory node includes memory 1384 as a memory resource to be shared between multiple compute nodes.

[0179] Storage node 1324 represents an example of a storage server, which refers to a node that has more storage resources than a computing node, and the storage server does not have a processor for performing tasks, but instead includes processing resources for managing access to the storage nodes within the storage server. The storage node may include a controller 1386 for managing access to the storage 1388 of the storage node.

[0180] In one example, node 1330 includes an interface controller 1334, which represents logic for controlling node 1330's access to structure 1370. The logic may include hardware resources for interconnecting to physical interconnect hardware. The logic may include software or firmware logic for managing interconnections. In one example, interface controller 1334 is or includes a host fabric interface, which may be a fabric interface according to any example described herein. Interface controllers for memory node 1322 and storage device node 1324 are not explicitly shown.

[0181] Processor 1332 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a main processor, such as a CPU (central processing unit), a peripheral processor, such as a GPU (graphics processing unit), or a combination. Memory 1340 may be or include a memory device represented by memory 1340 and a memory controller represented by controller 1342.

[0182] In general, with respect to the description herein, in one aspect, a device includes: a hardware interface for interfacing with a command bus, the hardware interface for receiving a mode register update (MRUPD) mode command to trigger entry into MRUPD mode; a decision feedback equalization (DFE) configuration register for storing a first configuration setting for the hardware interface to the command bus; and a second configuration register for configuration settings other than the DFE, the second configuration register for storing a second configuration setting for the hardware interface to the command bus; wherein the device is configured to update the second configuration register in the MRUPD mode using a mode register write (MRW) command.

[0183] In one example of the apparatus, the hardware interface comprises a hardware interface of a dynamic random access memory (DRAM) device, wherein the MRUPD mode is used to update the configuration of the DRAM device. According to any previous example of the apparatus, in one example, the hardware interface comprises a hardware interface of a registered clock driver (RCD), wherein the MRUPD mode is used to update the configuration of the RCD. According to any previous example of the apparatus, in one example, the apparatus is used to update a second configuration register in the MRUPD mode to store a configuration setting for an on-die terminal (ODT). According to any previous example of the apparatus, in one example, the apparatus is used to update a second configuration register in the MRUPD mode to store a configuration setting for a voltage reference (Vref). According to any of the previous examples of the apparatus, in one example, the second configuration register comprises a plurality of additional configuration registers for a plurality of additional configuration settings, wherein the apparatus is used to sequentially update the plurality of additional configuration registers in the MRUPD mode to store the plurality of additional configuration settings, and then exit the MRUPD mode. According to any of the previous examples of the apparatus, in one example, the apparatus is used to sequentially update a configuration for a chip select (CS) and a configuration for a command and address (CA). According to any of the preceding examples of the apparatus, in one example, the apparatus is used to update the DFE configuration register in the MRUPD mode. According to any of the preceding examples of the apparatus, in one example, the apparatus is used to update the second configuration register using a mode register write (MRW) command in the MRUPD mode.

[0184] In general, with respect to the description herein, in one aspect, a computer system includes: a memory controller coupled to a command bus; and a memory chip coupled to the command bus via a command bus interface, the memory chip being used to receive an MRUPD mode command from the memory controller to trigger the memory chip to enter MRUPD mode, the memory chip including: a decision feedback equalization (DFE) configuration register for storing a first configuration setting of the command bus interface; and a second configuration register for configuration settings other than the DFE, the second configuration register being used to store a second configuration setting of the command bus interface; wherein the memory chip is used to update the second configuration register in the MRUPD mode using a write command.

[0185] In one example of a computer system, in one example, the memory chip includes a dynamic random access memory (DRAM) device, wherein the MRUPD mode is used to update a configuration for the DRAM device. According to any of the foregoing examples of the computer system, in one example, the memory chip includes a registered clock driver (RCD), wherein the MRUPD mode is used to update the configuration of the RCD. According to any of the foregoing examples of the computer system, in one example, the memory chip is used to update a second configuration register in the MRUPD mode to store a configuration setting for an on-die terminal (ODT). According to any of the foregoing examples of the computer system, in one example, the memory chip is used to update the second configuration register in the MRUPD mode to store a configuration setting for a voltage reference (Vref). According to any of the foregoing examples of the computer system, in one example, the second configuration register includes a plurality of additional configuration registers for a plurality of additional configuration settings, wherein the memory chip is used to sequentially update the plurality of additional configuration registers in the MRUPD mode to store the plurality of additional configuration settings, and then exit the MRUPD mode. According to any of the foregoing examples of the computer system, in one example, the memory chip is used to sequentially update a configuration for a chip select (CS) and a configuration for a command and address (CA). According to any of the foregoing examples of computer systems, in one example, a memory chip is used to update a DFE configuration register in MRUPD mode. According to any of the foregoing examples of computer systems, in one example, the computer system includes a multi-core processor device coupled to a memory controller. According to any of the foregoing examples of computer systems, in one example, the computer system includes a display communicatively coupled to the processor device. According to any of the foregoing examples of computer systems, in one example, the computer system includes a battery for powering the system. According to any of the foregoing examples of computer systems, in one example, the computer system includes a network interface circuit for coupling with a remote device via a network connection.

[0186] In general, with respect to the description herein, in one aspect, a method for setting a configuration includes: receiving a mode register update (MRUPD) mode command to trigger entry into MRUPD mode; updating a decision feedback equalization (DFE) configuration register in the MRUPD mode; and updating a second configuration register for configuration settings other than DFE in the MRUPD mode.

[0187] In one example of the method, receiving the MRUPD mode command includes receiving the MRUPD command at a dynamic random access memory (DRAM) device, wherein the MRUPD mode is used to update the configuration of the DRAM device. According to any of the previous examples of the method, in one example, receiving the MRUPD mode command includes receiving the MRUPD command at a registered clock driver (RCD), wherein the MRUPD mode is used to update the configuration of the RCD. According to any of the previous examples of the method, in one example, updating the second configuration register includes storing a configuration setting for an on-die terminal (ODT) in the MRUPD mode. According to any of the previous examples of the method, in one example, storing a configuration setting for a voltage reference (Vref) in the MRUPD mode. According to any of the previous examples of the method, in one example, the second configuration register includes a plurality of additional configuration registers for a plurality of additional configuration settings, wherein updating the second configuration register includes sequentially storing the plurality of additional configuration settings in the MRUPD mode, and then exiting the MRUPD mode. According to any of the previous examples of the method, in one example, updating the second configuration includes sequentially updating a configuration for a chip select (CS) and a configuration for a command and address (CA). According to any of the foregoing examples of the method, in one example, updating the second configuration includes updating a DFE configuration register in MRUPD mode. According to any of the foregoing examples of the method, in one example, updating the second configuration includes updating the second configuration register using a mode register write (MRW) command in MRUPD mode.

[0188] The flowcharts as shown in this article provide examples of sequences of various process actions. The flowchart may indicate operations to be performed by software or firmware routines as well as physical operations. The flowchart may illustrate examples of implementations of the states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although displayed in a particular sequence or order, the order of the actions may be modified unless otherwise specified. Therefore, the illustrated figures should be understood only as examples, and the processes may be performed in different orders, and some actions may be performed in parallel. Additionally, one or more actions may be omitted; therefore, not all implementations will perform all actions.

[0189] To the extent that various operations or functions described herein are concerned, they may be described or defined as software code, instructions, configurations, and / or data. Content may be directly executable ("object" or "executable" form), source code, or differential code ("incremental" or "patch" code). The software content described herein may be provided via a manufactured product storing content, or via a method of operating a communication interface to send data via a communication interface. A machine-readable storage medium may enable a machine to perform the functions or operations, and includes any mechanism for storing information in a form accessible to a machine (e.g., a computing device, an electronic system, etc.), such as a recordable / unrecordable medium (e.g., a read-only memory (ROM), a random access memory (RAM), a disk storage medium, an optical storage medium, a flash memory device, etc.). A communication interface includes any mechanism for engaging with any hardwired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface may be configured by providing configuration parameters and / or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface may be accessed via one or more commands or signals sent to the communication interface.

[0190] The various components described herein may be units for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of the two. The components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hard-wired circuit systems, etc.

[0191] In addition to what is described herein, various modifications may be made to the disclosed content and implementation of the present invention without departing from its scope. Therefore, the description and examples herein should be understood in an illustrative rather than a restrictive sense. The scope of the present invention should be measured only with reference to the appended claims.

Claims

1. An apparatus for setting a memory configuration, comprising: a hardware interface for interfacing with a command bus, the hardware interface for receiving a mode register update (MRUPD) mode command to trigger entry into the MRUPD mode; a decision feedback equalization (DFE) configuration register to store a first configuration setting for the hardware interface to the command bus; as well as a second configuration register for configuration settings other than the DFE, the second configuration register for storing second configuration settings for the hardware interface to the command bus; The device is used to update the second configuration register using a mode register write (MRW) command in the MRUPD mode.

2. The device according to claim 1, wherein: The hardware interface comprises a hardware interface of a dynamic random access memory (DRAM) device, wherein the MRUPD mode is used to update a configuration for the DRAM device.

3. The device according to claim 1, wherein: The hardware interface includes a hardware interface of a registered clock driver (RCD), wherein the MRUPD mode is used to update a configuration for the RCD.

4. The device according to claim 1, wherein: The apparatus is configured to update the second configuration register in the MRUPD mode to store configuration settings for an on-die termination (ODT).

5. The device according to claim 1, wherein: The apparatus is for updating the second configuration register in the MRUPD mode to store configuration settings for a voltage reference (Vref).

6. The device according to claim 1, wherein: The second configuration registers include: a plurality of additional configuration registers for a plurality of additional configuration settings, wherein the apparatus is configured to sequentially update the plurality of additional configuration registers in the MRUPD mode to store the plurality of additional configuration settings, and then exit the MRUPD mode.

7. The device according to claim 6, wherein: The device is used to sequentially update a configuration for a chip select (CS) and a configuration for a command and address (CA).

8. The device according to claim 1, wherein: The apparatus is configured to update the DFE configuration register in the MRUPD mode.

9. The device according to claim 1, wherein: The apparatus is configured to update the second configuration register using a mode register write (MRW) command in the MRUPD mode.

10. A computer system for setting a memory configuration, comprising: a memory controller coupled to the command bus; as well as A memory chip, wherein the memory chip is coupled to the command bus using a command bus interface, and the memory chip is used to receive an MRUPD mode command from the memory controller to trigger the memory chip to enter the MRUPD mode, and the memory chip comprises: a decision feedback equalization (DFE) configuration register for storing a first configuration setting for the command bus interface; and a second configuration register for configuration settings other than the DFE, the second configuration register being used to store second configuration settings for the command bus interface; The memory chip is used to update the second configuration register using a write command in the MRUPD mode.

11. The computer system according to claim 10, wherein: The memory chip includes a dynamic random access memory (DRAM) device, wherein the MRUPD mode is used to update the configuration for the DRAM device, or wherein the memory chip includes a registered clock driver (RCD), wherein the MRUPD mode is used to update the configuration for the RCD.

12. The computer system according to claim 10, wherein: The memory chip is used to update the second configuration register in the MRUPD mode to store configuration settings for an on-die terminal (ODT), or wherein the memory chip is used to update the second configuration register in the MRUPD mode to store configuration settings for a voltage reference (Vref).

13. The computer system according to claim 10, wherein: The second configuration registers include: a plurality of additional configuration registers for a plurality of additional configuration settings, wherein the memory chip is used to sequentially update the plurality of additional configuration registers in the MRUPD mode to store the plurality of additional configuration settings, and then exit the MRUPD mode.

14. The computer system of claim 13, wherein: The memory chip is used to sequentially update a configuration for a chip select (CS) and a configuration for a command and address (CA).

15. The computer system according to claim 10, wherein: The memory chip is used to update the DFE configuration register in the MRUPD mode.

16. The computer system of claim 10, further comprising: a multi-core processor device coupled to the memory controller; a display communicatively coupled to the processor device; A battery, the battery being used to power the system; or A network interface circuit is used to couple with a remote device through a network connection.

17. A method for setting a memory configuration, comprising: Receive a mode register update (MRUPD) mode command to trigger entry into MRUPD mode; updating a decision feedback equalization (DFE) configuration register in the MRUPD mode; as well as A second configuration register for configuration settings other than the DFE is updated in the MRUPD mode.

18. The method according to claim 17, wherein: Receiving the MRUPD mode command includes: receiving the MRUPD command at a dynamic random access memory (DRAM) device, wherein the MRUPD mode is used to update the configuration for the DRAM device, or wherein receiving the MRUPD mode command includes: receiving the MRUPD command at a registered clock driver (RCD), wherein the MRUPD mode is used to update the configuration for the RCD.

19. The method according to claim 17, wherein: Updating the second configuration register includes storing configuration settings for an on-die termination (ODT) in the MRUPD mode or storing configuration settings for a voltage reference (Vref) in the MRUPD mode.

20. The method according to claim 17, wherein: The second configuration registers include a plurality of additional configuration registers for a plurality of additional configuration settings, wherein updating the second configuration registers includes sequentially storing the plurality of additional configuration settings in the MRUPD mode and then exiting the MRUPD mode.

21. An article of manufacture comprising a computer-readable storage medium having stored thereon content, the content, when executed, causing a machine to perform a method for setting a memory configuration, the method comprising: Receive a mode register update (MRUPD) mode command to trigger entry into MRUPD mode; updating a decision feedback equalization (DFE) configuration register in the MRUPD mode; as well as A second configuration register for configuration settings other than the DFE is updated in the MRUPD mode.

22. The article of manufacture according to claim 21, wherein Receiving the MRUPD mode command includes: receiving the MRUPD command at a dynamic random access memory (DRAM) device, wherein the MRUPD mode is used to update the configuration for the DRAM device, or wherein receiving the MRUPD mode command includes: receiving the MRUPD command at a registered clock driver (RCD), wherein the MRUPD mode is used to update the configuration for the RCD.

23. The article of manufacture according to claim 21, wherein: Updating the second configuration register includes storing configuration settings for an on-die termination (ODT) in the MRUPD mode or storing configuration settings for a voltage reference (Vref) in the MRUPD mode.

24. The article of manufacture according to claim 21, wherein: The second configuration registers include a plurality of additional configuration registers for a plurality of additional configuration settings, wherein updating the second configuration registers includes sequentially storing the plurality of additional configuration settings in the MRUPD mode and then exiting the MRUPD mode.

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